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INTERFACING THE ADS1210 WITH AN
8xC51 MICROCONTROLLER
By Miaochen Wu
The ADS1210 is a 24-bit delta-sigma analog-to-digital converter. This application bulletin provides examples of how
to interface the ADS1210 with an Intel 8xC51
microcontroller. The converter can be operated with the
serial data clock SCLK, generated by itself or provided
externally, such as by an 8xC51. The ADS1210 supports SPI
(Serial Peripheral Interface) interfacing and SSI (Synchronized Serial Interface) interfacing. This bulletin focuses on
interfacing the ADS1210 to an 8xC51, which provides the
synchronous SCLK signal. The schematic and 8xC51 assembly code are provided for both of the interface protocols.
The INSR data is the code to instruct the ADS1210 what to do
in the next operation. Typical instruction codes are the following:
INSR = C0H
Read 3 bytes of the Data Output Register of
the ADS1210
INSR = 64H
Write 4 bytes of the Command Register of
the ADS1210
INSR = E4H
Read 4 bytes of the Command Register of
the ADS1210
This data structure is implemented in the following assembly code:
MSB
1 Byte
LSB
B16
DOR 2
B23
B8
DOR 1
B15
B0
DOR 0
B7
B7
INSR
B0
B24
CMR 3
B31
B16
CMR 2
B23
B8
CMR 1
B15
B0
CMR 0
B7
B16
OCR 2
B23
B8
OCR 1
B15
B0
OCR 0
B7
; The ADS1210 Instruction Register code
RD_DATA
EQU
0C0H ; INSR = Read 3 Bytes Data
WR_CMR
EQU
064H
; INSR = Write 4 Bytes CMR
RD_CMR
EQU
0E4H ; INSR = Read 4 Bytes CMR
RRD_DATA
EQU
003H
; INSR = Read 3 Bytes Data Reversed
RRD_DLSB
EQU
043H
; INSR = Read 3 Bytes Data Reversed
; with LSByte first
; Definition for delays
D1210A
EQU
8
; 256 XIN clocks with XIN=10MHz
D1210B
EQU
15
; 512 XIN clocks
D1210C
EQU
30
; 1024 XIN clocks
DSYNCD
EQU
100
; _DSYNC=L for 120µs
; Pin connections to the ADS1210
DSYNC_
BIT
P2.5
;
CS_
BIT
P2.4
;
M_SDIO
BIT
P3.0
;
M_SCLK
BIT
P3.1
;
06EH
FCR 2
B23
B8
FCR 1
B15
B0
FCR 0
B7
the ADS1210 _DSYNC PIN
the ADS1210 _CS PIN
SDIO by MC51
SCLK by MC51
; Definition for flags
DRDYINT
BIT
LSByte
BIT
SLEEP
BIT
003H
004H
005H
; _DRDY interrupt flag
; LSbyte flag
; SLEEP flag
; Address for variables
AOFS
DATA
ABIT
DATA
NBYTE
DATA
NADDR
DATA
05AH
05BH
05CH
05DH
;
;
;
;
Address offset
Address bit
INSR BYTE
INSR ADDR
; Address for storing the ADS1210 register data
DOR2
DATA
060H
; DATA REG BYTE2
DOR1
DATA
061H
; DATA REG BYTE1
DOR0
DATA
062H
; DATA REG BYTE0
INSR
DATA
063H
; INSTRUCTION REG
CMR3
DATA
064H
; COMMAND REG BYTE3
CMR2
DATA
065H
; COMMAND REG BYTE2
CMR1
DATA
066H
; COMMAND REG BYTE1
CMR0
DATA
067H
; COMMAND REG BYTE0
OCR2
DATA
068H
; OFFSET COEF REG BYTE2
OCR1
DATA
069H
; OFFSET COEF REG BYTE1
OCR0
DATA
06AH ; OFFSET COEF REG BYTE0
FCR2
DATA
06CH ; GAIN COEF REG BYTE2
FCR1
DATA
06DH ; GAIN COEF REG BYTE1
FCR0
DATA
06EH ; GAIN COEF REG BYTE0
RESERVED
B16
TABLE I. The Memory Organization Used to Map the
ADS1210 to the 8xC51.
TABLE II. 8xC51 Assembly Listing—Constants and
Definitions.
©
1997 Burr-Brown Corporation
3
DATA STRUCTURE
DATA STRUCTURE
The ADS1210 has five internal registers; the 24-bit Data
Output Register (DOR), 8-bit Instruction Register (INSR),
32-bit Command Register (CMR), 24-bit Offset Calibration
Register (OCR) and 24-bit Full-Scale Calibration Register
(FCR). In the 8xC51, memory address from 060H to 06EH
are used to duplicate these registers. This part of memory is
called the ADS memory. The data stored in the ADS
memory are from LSB (Least Significant Bit) to MSB (Most
Significant Bit) for all the registers except INSR. Table I
shows the organization of the ADS memory.
060H
1
AB-112
1
Printed in U.S.A. March, 1997
4
SPI-COMPATIBLE INTERFACE DESIGN
A typical configuration using SPI type interfacing is shown
in Figure 1. In the schematic, the SCLK pin of the ADS1210
is connected to pin TXD of the 8xC51, SDIO is connected
to RXD, and DRDY to INT1. The CS pin is hardwired to
digital ground in this operating mode. The connection for
DSYNC pin is optional. For simplicity, assume that the
ADS1210 XIN pin is at FXIN = 10MHz frequency and 8xC51
XTAL1 pin is at FXTAL = 10MHz frequency.
There are basically five routines that can be used to interface
and control the ADS1210 (see Table IV). The routine
SPISCWR performs writing the one byte INSR code followed by the writing operation defined in the INSR code.
For example, with INSR=64H, SPISCWR will write 64H to
the ADS1210 Instruction Register followed by writing four
bytes of CMR data indexed by R1 into the ADS1210
Command Register.
The routine SPISCRD performs writing the one byte INSR
code followed by the reading operation defined in the INSR
code. For example, with INSR=E4H, SPISCRD will write
E4H to the ADS1210 INSR followed by reading four bytes
of CMR from the ADS1210. This data is placed into the
ADS memory as indexed by R1.
The routine PSCONVT performs the basic data acquisition
function. It writes the one byte INSR code C0H into the
ADS1210 and reads back three bytes of data from the Data
Output Register. This data is put into the ADS memory as
indexed by R1.
Two routines, EWRITE and EREAD, are the core for the
above operations. In EWRITE, the INSR content is copied
to R5. The data to be written into the ADS1210 is indexed
by R1. R3 controls the number of bytes sent to the ADS1210.
In EREAD, R5 carries the INSR code. The data to be read
back from the ADS1210 is put to the address indexed by R1.
To be compatible with the approach described in the section
Increasing Interface Speed, EWRITE and EREAD transmit
data with LSB first. The reader can easily make it MSB first.
In such a case, supporting routines BITINSR and REVINSR
are not needed. The SCLK clock rate using these two
routines is about 119kHz (FXTAL/84).
The routine PCSYNC performs the synchronization function as defined in the ADS1210 data sheet. The pin DSYNC
will be held LOW, approximately 120µs, and then returned
HIGH. The routine PCRESET generates a pre-defined clock
pattern at the SCLK pin to trigger a serial reset operation on
the ADS1210. The main routine SPISC is just an example
showing how to use the routines described above.
INITIALIZATION
After power on, the I/O pins and internal memory of the
8xC51 defined in Table II are initialized. The memory for
CMR, OCR and FCR are initialized from LSB to MSB, based
on the register definition from the ADS1210 data sheet. The
memory for INSR is initialized from MSB to LSB with the
value C0H. Port P3 of the 8xC51 is used for input and output
of the 8xC51. The ADS1210 pins DSYNC, CS, SDIO and
SCLK are connected to the 8xC51 pins P2.5, P2.4, P3.0 and
P3.1 (see Figures 1 through 3). AOFS is for INSR address
offset with a value of 01100000B. ABIT is for masking the
address bits of INSR with a value of 00001111B. R7 holds
the INSR data. R1 and R3 in register bank 00 and 01 are
assigned with 60H and 02H. Register R1 is used to index the
ADS memory, and R3 stores the number of bytes for each
register in the ADS memory. For example, when reading the
three bytes of the Data Output Register, R1 = 03H.
INITIALIZATION
; Interrupt Vectors
ORG
0
AJMP
RESET
ORG
13H
CLR
DRDYINT
RETI
; MC51 Initialization
RESET:
MOV
IE,#00000101B
MOV
CCON,#00H
MOV
PSW,#00H
MOV
SP,#30H
MOV
8EH,#01H
MOV
A,#11111111B
MOV
P0,A
MOV
P1,A
MOV
P2,A
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
A,#10111111B
P3,A
AOFS,#01100000B
ABIT,#00001111B
R7,#RD_DATA
IP,#00H
TCON,#00000101B
SCON,#00000000B
; The ADS1210 Initialization
START:
SETB
DRDYINT
CLR
LSByte
CLR
SLEEP
MOV
INSR,#RD_DATA
MOV
CMR3,#10000010B
MOV
CMR2,#00H
MOV
CMR1,#00H
MOV
CMR0,#01101000B
MOV
OCR2,#00H
MOV
OCR1,#00H
MOV
OCR0,#00H
MOV
FCR2,#01H
MOV
FCR1,#00H
MOV
FCR0,#00H
MOV
R1,#60H
MOV
R3,#02H
SETB
PSW.3
MOV
R1,#60H
MOV
R3,#02H
CLR
PSW.3
; Reset vector.
; External interrupt 1
; _DRDY=L
; Disable all interrupts
; Disable PCA
; Select Bank0
; Stack pointer
; EMI flag
; ACC=FFH
; P0 input
; P1 output H
; P2 input
; {NA,NA,DSYNC_,CS_,NA,NA,NA,NA}
; ACC=BFH
; P3 inout
; INSR address offset
; INSR address bits
; R7 gets INSR data
; INT priority
; EX0/1 edge trigger
; serial port mode 0
; 000REN00TIRI
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
_DRDY=H
LSByte=L
SLEEP=L
INSR=C0H
CMR3=R41H
CMR2=R00H
CMR1=R00H
CMR0=R16H
OCR2=R00H
OCR1=R00H
OCR0=R00H
FCR2=R80H
FCR1=R00H
FCR0=R00H
ADDR=60H
NBYTE=02H
Rbank=01
ADDR=60H
NBYTE=02H
Rbank=00
The information provided herein is believed to be reliable; however, BURRBROWN assumes no responsibility for inaccuracies or omissions. BURRBROWN assumes no responsibility for the use of this information, and all use of
such information shall be entirely at the user’s own risk. Prices and specifications
are subject to change without notice. No patent rights or licenses to any of the
circuits described herein are implied or granted to any third party. BURRBROWN does not authorize or warrant any BURR-BROWN product for use in life
support devices and/or systems.
TABLE III. 8xC51 Assembly Listing—ADS1210 Initialization.
2
DVDD
8xC51
U3
AIN4P
AIN4N
AIN3P
+
10pF
U1
AIN3N
AIN3N
AIN3P
AIN2P
AIN2P
AIN4N
AIN2N
AIN2N
AIN4P
AINP
AINP
REFIN
AINN
AINN
REFOUT
AGND
ADS1211
U2
+
12pF
+
AVDD
VBIAS
MODE
CS
DRDY
DSYNC
1.0µF
+
8.2kΩ
VDD
0.1µF
SDOUT
XIN
SDIO
XOUT
SCLK
DGND
DVDD
12pF
+
+
DVDD
10kΩ
0.1µF
U4
+
= Digital Ground
= Analog Ground
FIGURE 1. SPI Compatible Interface.
3
24pF
+
24pF
P1.0
VCC
P1.1
P0.0
P1.2
P0.1
P1.3
P0.2
P1.4
P0.3
P1.5
P0.4
P1.6
P0.5
P1.7
P0.6
RST
P0.7
RXD
EA/VDD
TXD
ALE PROG
INT0
PSEN
INT1
P2.7
T0
P2.6
T1
P2.5
WR
P2.4
RD
P2.3
XTAL2
P2.2
XTAL1
P2.1
VSS
P2.0
DVDD
U3
AIN4P
AIN4N
+
AIN3P
10pF
U1
AIN3N
AIN3N
AIN3P
AIN2P
AIN2P
AIN4N
AIN2N
AIN2N
AIN4P
AINP
AINP
REFIN
AINN
AINN
REFOUT
AGND
ADS1211
U2
+
12pF
+
12pF
1.0µF
AVDD
VBIAS
MODE
CS
DRDY
DSYNC
+
+
8.2kΩ
VDD
0.1µF
SDOUT
XIN
SDIO
XOUT
SCLK
DGND
DVDD
+
DVDD
10kΩ
0.1µF
U4
+
= Digital Ground
= Analog Ground
FIGURE 2. SSI Interface.
4
24pF
+
24pF
8xC51
P1.0
VCC
P1.1
P0.0
P1.2
P0.1
P1.3
P0.2
P1.4
P0.3
P1.5
P0.4
P1.6
P0.5
P1.7
P0.6
RST
P0.7
RXD
EA/VDD
TXD
ALE PROG
INT0
PSEN
INT1
P2.7
T0
P2.6
T1
P2.5
WR
P2.4
RD
P2.3
XTAL2
P2.2
XTAL1
P2.1
VSS
P2.0
DVDD
8xC51
U3
AIN4P
AIN4N
AIN3P
+
10pF
U1
AIN3N
AIN3N
AIN3P
AIN2P
AIN2P
AIN4N
AIN2N
AIN2N
AIN4P
AINP
AINP
REFIN
AINN
AINN
REFOUT
AGND
AVDD
ADS1211
VBIAS
MODE
CS
DRDY
DSYNC
U2
+
12pF
+
+
1.0µF
+
8.2kΩ
VDD
0.1µF
SDOUT
XIN
SDIO
XOUT
SCLK
DGND
DVDD
12pF
+
DVDD
U5
10kΩ
0.1µF
U4
+
= Digital Ground
= Analog Ground
FIGURE 3. Increasing the Interface Speed.
5
24pF
+
24pF
P1.0
VCC
P1.1
P0.0
P1.2
P0.1
P1.3
P0.2
P1.4
P0.3
P1.5
P0.4
P1.6
P0.5
P1.7
P0.6
RST
P0.7
RXD
EA/VDD
TXD
ALE PROG
INT0
PSEN
INT1
P2.7
T0
P2.6
T1
P2.5
WR
P2.4
RD
P2.3
XTAL2
P2.2
XTAL1
P2.1
VSS
P2.0
6
serial write
get CMR3
get LSByte
save LSByte
mask CMR2
get sleep mode
not sleep
SLEEP=H
;
;
;
;
;
;
;
;
;
;
;
;
;
read 3 bytes
DOR2 address
get RRD_DATA
goto EDINS2
get RRD_DLSB
; sense _DRDY
; serial read
; get ADDR NBYTE
; reverse INSR
; sense _DRDY
get ADDR NBYTE
reverse INSR
not sleep
SLEEP=L
wakeup
sense _DRDY
;
;
;
;
;
;
get WR_CMR
Write the ADS1210 CMR
get RD_CMR
Read back the ADS1210 CMR
get the ADS1210 Data
Sync the ADS1210 via _DSYNC Pin
Reset the ADS1210 via SCLK
R6,LOOPC
M_SCLK
;
;
;
;
get INSR
output 8 bits
if not 0, more output
output last one
; SCLK=L
; SCLK=H
; delays
; SCLK=L
R6,LOOPB
M_SCLK
M_SCLK
R6,#D1210C
; SCLK=H
; delays
; SCLK=L
R6,LOOPA
M_SCLK
M_SCLK
R6,#D1210B
; SCLK=L
; SCLK=H
; delays
; _DSYNC=H
; _DSYNC=L
; delays
; read data
; MC writes data to RAM
M_SCLK
M_SCLK
R6,#D1210A
; Routine for serial port external clock write
EWRITE:
MOV
A,R5
ACALL
TXBIT
ETION:
CJNE
R3,#00H,EWMORE
MOV
A,@R1
ACALL
TXBIT
SJMP
EWEND
; Routine for PCRESET
PCRESET:
CLR
SETB
MOV
LOOPA:
NOP
DJNZ
CLR
NOP
NOP
NOP
NOP
SETB
MOV
LOOPB:
NOP
DJNZ
CLR
NOP
NOP
NOP
NOP
SETB
MOV
LOOPC:
NOP
DJNZ
CLR
RET
DSYNC_
R6,#DSYNCD
R6,LOOP
DSYNC_
EREAD
MCWRITE
SPI-COMPATIBLE INTERFACE DESIGN (cont)
ACALL
ACALL
RET
; Routine for PCSYNC
PCSYNC:
CLR
MOV
LOOP:
DJNZ
SETB
RET
EDINS2:
;
EPSCON:
TABLE IV. 8xC51 Assembly Listing—Core ADS1210 Communication Functions (SPI Interface).
; Routine for SPISC data converting
PSCONVT:
JB
DRDYINT,EPSCON
SETB
DRDYINT
MOV
R3,#02H
MOV
R1,#60H
MOV
R5,#RRD_DATA
JNB
LSByte,EDINS2
MOV
R5,#RRD_DLSB
; Routine for SPISC read the ADS1210
SPISCRD:
ACALL
BITINSR
ACALL
REVINSR
PSDRH:
JB
DRDYINT,PSDRH
SETB
DRDYINT
ACALL
EREAD
RET
; Routine for SPISC write the ADS1210
SPISCWR:
ACALL
BITINSR
ACALL
REVINSR
JNB
SLEEP,PSDWH
CLR
SLEEP
JMP
PSWKUP
PSDWH:
JB
DRDYINT,PSDWH
SETB
DRDYINT
PSWKUP:
ACALL
EWRITE
MOV
B,CMR3
MOV
C,B.4
MOV
LSByte,C
MOV
A,#00000011B
ANL
A,CMR2
CJNE
A,#00000011B,PSEND
SETB
SLEEP
PSEND:
RET
;
;
;
;
;
;
;
SPI-COMPATIBLE INTERFACE DESIGN
; Routines for SPISC protocol
SPISC:
MOV
INSR,#WR_CMR
ACALL
SPISCWR
MOV
INSR,#RD_CMR
ACALL
SPISCRD
ACALL
PSCONVT
ACALL
PCSYNC
ACALL
PCRESET
RET
7
;
;
;
;
;
;
;
;
;
;
;
;
R6,#08H
A
M_SCLK
M_SDIO,C
M_SCLK
R6,TXLOOP
R6,#08H
M_SCLK
C,M_SDIO
M_SCLK
A
R6,RXLOOP
;
;
;
;
;
;
get NBYTE
mask bits
swap A
rotate right A
save NBYTE
get ADDR
store data
ADDR+1
NBYTE-1
more read
ANL
ORL
MOV
MOV
MOV
SETB
MOV
MOV
CLR
RET
A,ABIT
A,AOFS
R1,A
NBYTE,R3
NADDR,R1
PSW.3
R3,NBYTE
R1,NADDR
PSW.3
mask bits
offset ADDR
save read ADDR
save NBYTE
save NADDR
Rbank=01
save NBYTE
save NADDR
Rbank=00
; save to R5
; bit0
; bit1
; bit2
; bit3
; bit4
; bit5
; bit6
; INSR to A
; rotate bit7
;
;
;
;
;
;
;
;
;
SPI-COMPATIBLE INTERFACE DESIGN (cont)
; Routine for reverse INSR
REVINSR:
MOV
A,INSR
RLC
A
MOV
B.0,C
RLC
A
MOV
B.1,C
RLC
A
MOV
B.2,C
RLC
A
MOV
B.3,C
RLC
A
MOV
B.4,C
RLC
A
MOV
B.5,C
RLC
A
MOV
B.6,C
RLC
A
MOV
B.7,C
MOV
R5,B
RET
TABLE IV (cont). 8xC51 Assembly Listing—Core ADS1210 Communication Functions (SPI Interface).
; Routine to get INSR bits for NBYTE and ADDR
BITINSR:
MOV
A,INSR
ANL
A,AOFS
SWAP
A
RR
A
MOV
R3,A
MOV
A,INSR
;
;
;
;
; goto end
; if not 0, more output
; get INSR
8 bit
SCLK=H
get data
SCLK=L
get LSB into A, can be modified MSB first
8 bit in
8 bits
get LSB, can be modified MSB first
SCLK=H
output LSB
SCLK=L
8 bits out
; ADDR+1
; NBYTE-1
; TI send
; output byte 1,2,3
A,@R1
TXBIT
R1
R3
ETION
; Routine for serial port external clock read
EREAD:
MOV
A,R5
ACALL
TXBIT
ERISSI:
CJNE
R3,#00H,ERMORE
ACALL
RXBIT
MOV
@R1,A
SJMP
EREND
ERMORE:
ACALL
RXBIT
MOV
@R1,A
INC
R1
DEC
R3
SJMP
ERISSI
EREND:
RET
MOV
ACALL
INC
DEC
SJMP
EWEND:
RET
; Routine for TX data
TXBIT:
MOV
TXLOOP:
RRC
SETB
MOV
CLR
DJNZ
RET
; Routine for RX data
RXBIT:
MOV
RXLOOP:
SETB
MOV
CLR
RRC
DJNZ
RET
EWMORE:
SPI-COMPATIBLE INTERFACE DESIGN
SSI INTERFACE DESIGN
A typical configuration using SSI interfacing is shown in
Figure 2. The difference between Figure 1 and Figure 2 is
the CS pin is connected to P2.4. In this interface protocol,
communication starts when CS is toggles from HIGH to
LOW. This means that the communication is synchronized
by the CS signal.
There are three routines for basic SSI interface operation:
The routine SSIECWR performs writing one byte INSR
code followed by the writing operation defined in the INSR
code. The routine SSIECRD performs writing one byte
INSR code followed by the reading operation defined in the
INSR code. However, SSIECRD is also used to read Data
Output Register from the ADS1210. If a single data point is
collected from the ADS1210, SSIECRD will do the job.
The ADS1210 design supports continuous reading of the
Data Output Register without issuing the INSR data for each
read. The routine SECONVT performs this function. Once
SSIECRD is executed to read back a single data point and
CS pin stays LOW and is not toggled, SECONVT will
SSI INTERFACE DESIGN
; Routine for SSIEC protocol
SSIEC:
MOV
ACALL
MOV
ACALL
ACALL
ACALL
ACALL
RET
INSR,#WR_CMR
SSIECWR
INSR,#RD_CMR
SSIECRD
SECONVT
PCSYNC
PCRESET
; Routine for SSIEC write the ADS1210
SSIECWR:
SETB
CS_
ACALL
BITINSR
ACALL
REVINSR
JNB
SLEEP,SEDWH
CLR
SLEEP
JMP
SEWKUP
SEDWH:
JB
DRDYINT,SEDWH
SETB
DRDYINT
SEWKUP:
CLR
CS_
ACALL
EWRITE
SETB
CS_
MOV
A,#00000011B
ANL
A,CMR2
CJNE
A,#00000011B,SEEND
SETB
SLEEP
SEEND:
RET
; Routine for SSIEC read the ADS1210
SSIECRD:
SETB
CS_
ACALL
BITINSR
ACALL
REVINSR
SEDRH:
JB
DRDYINT,SEDRH
SETB
DRDYINT
CLR
CS_
ACALL
EREAD
CJNE
R5,#03H,ESERD3
JMP
ESERD2
ESERD3:
CJNE
R5,#43H,ESERD
JMP
ESERD2
ESERD:
SETB
CS_
ESERD2:
RET
; Routine for SSIEC data converting
SECONVT:
JB
SETB
JB
MOV
MOV
ACALL
;
ACALL
ESECON:
RET
DRDYINT,ESECON
DRDYINT
CS_,ESECON
R3,#02H
R1,#60H
ERISSI
MCWRITE
;
;
;
;
;
;
;
get WR_CMR
Write the ADS1210 CMR
get RD_CMR
Read back the ADS1210 CMR
get the ADS1210 Data
Sync the ADS1210 via DSYNC_ Pin
Reset the ADS1210 via SCLK
;
;
;
;
;
;
;
_CS=H
get ADDR NBYTE
reverse INSR
no sleep
SLEEP=L
wakeup
sense _DRDY
;
;
;
;
;
;
;
_CS=L
serial write
_CS=H
mask CMR2
get sleep mode
not sleep
SLEEP=H
;
;
;
;
_CS=H
get ADDR NBYTE
reverse INSR
sense _DRDY
;
;
;
;
;
;
;
_CS=L
serial read
not SSI read
SSI read
not SSI read
SSI read
_CS=H
; sense _DRDY
;
;
;
;
;
_CS=H
read 3 bytes
DOR2 address
read data
MC writes data to RAM
TABLE V. 8xC51 Assembly Listing—Core ADS1210 Communication Functions (SSI Interface).
8
continuously read back three bytes data from the ADS1210.
The data is put in the ADS memory indexed by R1. Routine
MCWRITE (not shown in the code listing) can be inserted
to copy the data from DOR2-DOR0 address to external
memory.
Two routines, EWRITE and EREAD used in the SPIcompatible interface, are shared for the SSI interface. The
routines PCSYNC and PCRESET can be modified by
adding CS toggling to perform synchronization and serial
reset operation for SSI operation. The main routine SSIEC
is an example of how to use the routines described in
Tables IV and V.
Interface Mode 0. The clock frequency at the TXD pin is
FXTAL/12 in Mode 0. For example, with FXTAL = 24MHz, the
SCLK frequency is 2MHz.
A typical configuration using the 8xC51 Standard Serial
Interface Mode 0 is shown in Figure 3. As TXD stays HIGH
during idle, an inverter is required between SCLK and TXD.
In Mode 0, serial data is transmitted/received with LSB first.
Two core routines, EWRITE and EREAD, are modified and
listed in Table VI. The data structure described at the
beginning still supports these two new routines. Of course,
the interrupt register IE should be set properly to enable the
interrupt.
INCREASING THE INTERFACE SPEED
SUMMARY
In the SPI-Compatible Design and SSI Interface Design
sections of this application bulletin, the clock frequency in
SCLK is approximately 119kHz or FXTAL/84. The ADS1210
supports a maximum 2MHz or FXIN/5 MHz SCLK clock
frequency. One way to increase the interface speed is to
increase the 8xC51 crystal frequency, FXTAL. For example,
with FXTAL = 40MHz, the SCLK frequency is 476kHz.
However, in order to have a 2MHz SCLK clock frequency,
FXTAL would have to be 168MHz! Another way to increase
the interface speed is to use the 8xC51 Standard Serial
This application bulletin discusses how to interface the
ADS1210 with an 8xC51 microcontroller using either SPIcompatible interface or SSI interface. The routines for writing/reading the ADS1210 internal registers are provided. A
modified version is given to increase the interface speed. The
schematic for the different protocols are presented. The
reader can customize the data structure and the writing/
reading routines for the application. The routines, EWRITE
and EREAD in the sections SPI-Compatible Interface Design
and Increasing Interface Speed, serve for general purpose.
INCREASING THE INTERFACE SPEED
; Routine for serial port external clock write
EWRITE:
MOV
SCON,#00000000B
MOV
SBUF,R5
ETION:
JNB
SCON.1,ETION
CLR
SCON.1
CJNE
R3,#00H,EWMORE
MOV
SBUF,@R1
ETION2:
JB
SCON.1,EWEND
SJMP
ETION2
EWMORE: MOV
SBUF,@R1
INC
R1
DEC
R3
JMP
ETION
EWEND:
RET
; Routine for serial port external clock read
EREAD:
MOV
SCON,#00000000B
MOV
SBUF,R5
ETION3:
NB
SCON.1,ETION3
ERISSI:
OV
SCON,#00010001B
ERIUSE:
JNE
R3,#00H,ERMORE
CLR
SCON.0
ERION:
NB
SCON.0,ERION
MOV
@R1,SBUF
SJMP
EREND
ERMORE: CLR
SCON.0
ERION2:
NB
SCON.0,ERION2
MOV
@R1,SBUF
INC
R1
DEC
R3
SJMP
ERIUSE
EREND:
RET
;
;
;
;
;
;
;
serial mode=0
output INSR
TI is done ?
clear TI
if not 0, more output
output last one
goto end
;
;
;
;
output byte 1,2,3
ADDR+1
NBYTE-1
TI send
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
serial mode=0
output INSR
TI is done ?
serial mode=0
if not 0, more output
clear RI
RI is done ?
input last one
goto end
clear RI
RI is done ?
input byte 1,2,3
ADDR+1
NBYTE-1
more read
TABLE VI. 8xC51 Assembly Listing—Mode 0 Interface
Routines.
9