FINAL Am27C2048 2 Megabit (131,072 x 16-Bit) CMOS EPROM DISTINCTIVE CHARACTERISTICS ■ ±10% power supply tolerance standard ■ Fast access time ■ 100% Flashrite programming — 55 ns maximum access time ■ Low power consumption — Typical programming time of 16 seconds — 100 µA maximum CMOS standby current ■ JEDEC-approved pinout — Plug-in upgrade of 1 Mbit EPROM — 40-pin DIP/PDIP — 44-pin PLCC ■ Single +5 V power supply ■ Latch-up protected to 100 mA from -1 V to VCC + 1 V ■ Versatile features for simple interfacing — Both CMOS and TTL input/output compatibility — Two line control functions ■ High noise immunity GENERAL DESCRIPTION The Am27C2048 is a 2 Mbit, ultraviolet erasable programmable read-only memory. It is organized as 128K words by 16 bits per word, operates from a single +5 V supply, has a static standby mode, and features fast single address location programming. The Am27C2048 is ideal for use in 16-bit microprocessor systems. Products are available in windowed ceramic DIP packages as well as plastic one time programmable (OTP) PDIP and PLCC packages. Typically, any byte can be accessed in less than 70 ns, allowing operation with high-performance microprocessors without any WAIT states. The Am27C2048 offers separate Output Enable (OE) and Chip Enable (CE) controls, thus eliminating bus contention in a multiple bus microprocessor system. AMD’s CMOS process technology provides high speed, low power, and high noise immunity.Typical power consumption is only 125 mW in active mode, and 100 µW in standby mode. All signals are TTL levels, including programming signals. Bit locations may be programmed singly, in blocks, or at random. The Am27C2048 supports AMD’s Flashrite programming algorithm (100 µs pulses) resulting in typical programming time of 16 seconds. BLOCK DIAGRAM VCC VSS VPP OE CE PGM A0–A16 Address Inputs Data Outputs DQ0–DQ15 Output Enable Chip Enable and Prog Logic Output Buffers Y Decoder Y Gating X Decoder 2,097,152 Bit Cell Matrix 11407F-1 Publication# 11407 Rev: F Amendment/+2 Issue Date: July 1997 PRODUCT SELECTOR GUIDE Family Part No. Am27C2048 Ordering Part No: VCC = 5.0 V ± 5% -55 VCC = 5.0 V ± 10% -255 -55 -70 -90 -120 -150 -200 Max Access Time (ns) 55 70 90 120 150 200 250 CE (E) Access (ns) 55 70 90 120 150 200 250 OE (G) Access (ns) 40 40 40 50 65 75 75 CONNECTION DIAGRAMS Top View A15 DQ13 5 36 A14 DQ12 6 35 A13 DQ11 7 34 A12 DQ10 8 33 DQ9 DQ8 VSS 9 10 11 32 31 30 A11 A10 A9 VSS 6 5 4 3 2 1 44 43 42 41 40 A14 NC 37 A15 38 4 A16 3 DQ14 PMG (P) DQ15 VCC PMG (P) DU (Note 2) VCC 39 VPP 40 2 CE (E) 1 DQ15 VPP CE (E) DQ14 PLCC DQ13 DIP DQ12 7 39 A13 DQ11 8 38 A12 DQ10 9 37 A11 DQ9 10 36 A10 DQ8 11 35 A9 VSS 12 34 VSS 13 33 NC 27 A6 DQ6 15 31 A7 15 26 A5 DQ5 16 30 A6 DQ3 16 25 A4 DQ4 A5 DQ2 17 24 A3 29 17 18 19 20 21 22 23 24 25 26 27 28 DQ1 18 23 A2 DQ0 19 22 A1 OE (G) 20 21 A0 11407F-2 A4 14 DQ4 A3 DQ5 A2 A8 A1 32 A0 14 DU (Note 2) DQ7 OE (G) A7 DQ0 A8 28 DQ1 29 13 DQ2 12 DQ6 DQ3 DQ7 NC 11407F-3 Notes: 1. JEDEC nomenclature is in parenthesis. 2. Don’t use (DU) for PLCC. PIN DESIGNATIONS A0–A16 = Address Inputs CE (E) = Chip Enable Input LOGIC SYMBOL 17 DQ0–DQ15 = Data Input/Outputs 16 A0–A16 OE (G) = Output Enable Input PGM (P) = Program Enable Input VCC = VCC Supply Voltage PMG (P) VPP = Program Voltage Input OE (G) VSS = Ground DQ0–DQ15 CE (E) 11407F-4 2 Am27C2048 ORDERING INFORMATION UV EPROM Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: AM27C2048 -55 D C 5 B OPTIONAL PROCESSING Blank = Standard Processing B = Burn-In VOLTAGE TOLERANCE 5 = VCC ± 5%, 55 ns only See Product Selector Guide and Valid Combinations TEMPERATURE RANGE C = Commercial (0°C to +70°C) I = Industrial (–40°C to +85°C) E = Extended (–55°C to +125°C) PACKAGE TYPE D = 40-Pin Ceramic DIP (CDV040) SPEED OPTION See Product Selector Guide and Valid Combinations DEVICE NUMBER/DESCRIPTION Am27C2048 2 Megabit (131,072 x 16-Bit) CMOS UV EPROM Valid Combinations Valid Combinations AM27C2048-55 VCC = 5.0 V ± 5% Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. DC5, DC5B, DI5, DI5B AM27C2048-55 VCC = 5.0 V ± 10% AM27C2048-70 DC, DCB, DI, DIB AM27C2048-90 AM27C2048-120 AM27C2048-150 DC, DCB, DE, DEB, DI, DIB AM27C2048-200 AM27C2048-255 VCC = 5.0 V ± 5% DC, DCB, DI, DIB Am27C2048 3 ORDERING INFORMATION OTP EPROM Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: AM27C2048 -55 J C 5 OPTIONAL PROCESSING Blank = Standard Processing VOLTAGE TOLERANCE 5 = VCC ± 5%, -55 ns only See Product Selector Guide and Valid Combinations TEMPERATURE RANGE C = Commercial (0°C to +70°C) I = Industrial (–40°C to +85°C) PACKAGE TYPE P = 40-Pin Plastic DIP (PD 040) J = 44-Pin Square Plastic Leaded Chip Carrier (PL 044) SPEED OPTION See Product Selector Guide and Valid Combinations DEVICE NUMBER/DESCRIPTION Am27C2048 2 Megabit (131,072 x 16-Bit) CMOS OTP EPROM Valid Combinations Valid Combinations AM27C2048-55 VCC = 5.0 V ± 5% PC5, PI5, JC5, JI5 AM27C2048-55 VCC = 5.0 V ± 10% Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. AM27C2048-70 AM27C2048-90 AM27C2048-120 PC, PI, JC, JI AM27C2048-150 AM27C2048-200 AM27C2048-255 VCC = 5.0 V ± 5% 4 Am27C2048 FUNCTIONAL DESCRIPTION Erasing the Am27C2048 In order to clear all locations of their programmed contents, it is necessary to expose the Am27C2048 to an ultraviolet light source. A dosage of 15 W seconds/cm2 is required to completely erase an Am27C2048. This dosage can be obtained by exposure to an ultraviolet lamp—wavelength of 2537 Å—with intensity of 12,000 µW/cm2 for 15 to 20 minutes. The Am27C2048 should be directly under and about one inch from the source and all filters should be removed from the UV light source prior to erasure. It is important to note that the Am27C2048, and similar devices, will erase with light sources having wavelengths shorter than 4000 Å. Although erasure times will be much longer than with UV sources at 2537 Å, nevertheless the exposure to fluorescent light and sunlight will eventually erase the Am27C2048 and exposure to them should be prevented to realize maximum system reliability. If used in such an environment, the package window should be covered by an opaque label or substance. Programming the Am27C2048 Upon delivery, or after each erasure, the Am27C2048 has all 2,097,152 bits in the “ONE”, or HIGH state. “ZEROs” are loaded into the Am27C2048 through the procedure of programming. The programming mode is entered when 12.75 V ± 0.25 V is applied to the VPP pin, and CE and PGM are at VIL. For programming, the data to be programmed is applied 16 bits in parallel to the data pins. The flowchart (Figure 2) shows AMD’s Flashrite algorithm. The Flashrite algorithm reduces programming time by using 100 µs programming pulse and by giving each address only as many pulses as are necessary in order to reliably program the data. After each pulse is applied to a given address, the data in that address is verified. If the data does not verify, additional pulses are given until it verifies or the maximum is reached. This process is repeated while sequencing through each address of the Am27C2048. This part of the algorithm is done at VCC = 6.25 V to assure that each EPROM bit is programmed to a sufficiently high threshold voltage. After the final address is completed, the entire EPROM memory is verified at VCC = VPP = 5.25 V. Please refer to Section 6 for programming flow chart and characteristics. Program Inhibit Programming of multiple Am27C2048s in parallel with different data is also easily accomplished. Except for CE, all like inputs of the parallel Am27C2048 may be common. A TTL low-level program pulse applied to an Am27C2048 CE input with VPP = 12.75 V ± 0.25 V and PGM LOW will program that Am27C2048. A high-level CE input inhibits the other Am27C2048 devices from being programmed. Program Verify A verify should be performed on the programmed bits to determine that they were correctly programmed. The verify should be performed with OE and CE, at VIL, PGM at VIH, and VPP between 12.5 V and 13.0 V. Auto Select Mode The auto select mode allows the reading out of a binary code from an EPROM that will identify its manufacturer and type. This mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional in the 25°C ± 5°C ambient temperature range that is required when programming the Am27C2048. To activate this mode, the programming equipment must force 12.0 V ± 0.5 V on address line A9 of the Am27C2048. Two identifier bytes may then be sequenced from the device outputs by toggling address line A0 from VIL to VIH. All other address lines must be held at VIL during auto select mode. Byte 0 (A0 = VIL) represents the manufacturer code, and Byte 1 (A0 = VIH), the device identifier code. For the Am27C2048, these two identifier bytes are given in the Mode Select table. All identifiers for manufacturer and device codes will possess odd parity, with the MSB (DQ7) defined as the parity bit. Read Mode The Am27C2048 has two control functions, both of which must be logically satisfied in order to obtain data at the outputs. Chip Enable (CE) is the power control and should be used for device selection. Output Enable (OE) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that addresses are stable, address access time (tACC) is equal to the delay from CE to output (tCE). Data is available at the outputs tOE after the falling edge of OE, assuming that CE has been LOW and addresses have been stable for at least tACC–tOE. Standby Mode The Am27C2048 has a CMOS standby mode which reduces the maximum VCC current to 100 µA. It is placed in CMOS-standby when CE is at V CC ± 0.3 V. The Am27C2048 also has a TTL-standby mode which reduce the maximum VCC current to 1.0 mA. It is placed in TTL-standby when CE is at VIH. When in standby mode, the outputs are in a high-impedance state, independent of the OE input. Am27C2048 5 Output OR-Tieing System Applications To accommodate multiple memory connections, a two-line control function is provided to allow for: During the switch between active and standby conditions, transient current peaks are produced on the rising and falling edges of Chip Enable. The magnitude of these transient current peaks is dependent on the output capacitance loading of the device. At a minimum, a 0.1 µF ceramic capacitor (high frequency, low inherent inductance) should be used on each device between VCC and VSS to minimize transient effects. In addition, to overcome the voltage drop caused by the inductive effects of the printed circuit board traces on EPROM arrays, a 4.7 µF bulk electrolytic capacitor should be used between VCC and VSS for each eight devices. The location of the capacitor should be close to where the power supply is connected to the array. ■ Low memory power dissipation, and ■ Assurance that output bus contention will not occur It is recommended that CE be decoded and used as the primary device-selecting function, while OE be made a common connection to all devices in the array and connected to the READ line from the system control bus. This assures that all deselected memory devices are in their low-power standby mode and that the output pins are only active when data is desired from a particular memory device. MODE SELECT TABLE Pins Mode CE OE PGM A0 A9 VPP Outputs Read VIL VIL X X X X DOUT Output Disable VIL VIH X X X X High Z Standby (TTL) VIH X X X X X High Z VCC ± 0.3 V X X X X X High Z Program VIL X VIL X X VPP DIN Program Verify VIL VIL VIH X X VPP DOUT Program Inhibit VIH X X X X VPP High Z Auto Select Manufacturer Code (Note 3) Device Code VIL VIL X VIL VH X 01H VIL VIL X VIH VH X 98H Standby (CMOS) Notes: 1. VH = 12.0 V ± 0.5 V. 2. X = Either VIH or VIL. 3. A1–A8 = A10-16 = VIL. 4. See DC Programming Characteristics for VPP voltage during programming. 6 Am27C2048 ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature OTP Products. . . . . . . . . . . . . . . . . . –65°C to +125°C All Other Products . . . . . . . . . . . . . . –65°C to +150°C Commercial (C) Devices Ambient Temperature with Power Applied. . . . . . . . . . . . . . –55°C to +125°C Ambient Temperature (TA). . . . . . . . . . . .0°C to +70°C Industrial (I) Devices Ambient Temperature (TA). . . . . . . . . .–40°C to +85°C Voltage with Respect to VSS All pins except A9, VPP, VCC . . . .–0.6 V to VCC + 0.6 V Extended (E) Devices A9 and VPP (Note 2). . . . . . . . . . . . . . –0.6 V to 13.5 V Supply Read Voltages VCC (Note 1). . . . . . . . . . . . . . . . . . . . . –0.6 V to 7.0 V VCC for Am27C2048-55, 255 . . . . +4.75 V to +5.25 V VCC for Am27C2048 (All Others) . +4.50 V to +5.50 V Notes: 1. Minimum DC voltage on input or I/O pins –0.5 V. During voltage transitions, the input may overshoot VSS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on input and I/O pins is VCC + 5 V. During voltage transitions, input and I/O pins may overshoot to VCC + 2.0 V for periods up to 20ns. Ambient Temperature (TA). . . . . . . . .–55°C to +125°C Operating ranges define those limits between which the functionality of the device is guaranteed. 2. Minimum DC input voltage on A9 is –0.5 V. During voltage transitions, A9 and VPP may overshoot VSS to –2.0 V for periods of up to 20 ns. A9 and VPP must not exceed+13.5 V at any time. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure of the device to absolute maximum ratings for extended periods may affect device reliability. Am27C2048 7 DC CHARACTERISTICS over operating range unless otherwise specified (Notes 1, 2, and 4) Parameter Symbol Parameter Description Test Conditions Min 2.4 VOH Output HIGH Voltage IOH = –400 µA VOL Output LOW Voltage IOL = 2.1 mA VIH Input HIGH Voltage VIL Input LOW Voltage ILI Input Load Current ILO Output Leakage Current ICC1 VCC Active Current (Note 3) ICC2 VCC TTL Standby Current ICC3 VCC CMOS Standby Current IPP1 VPP Supply Current (Read) VIN = 0 V to VCC Unit V 0.45 V 2.0 VCC + 0.5 V -0.5 +0.8 V C/I Devices 1.0 µA E Devices 5.0 VOUT = 0 V to VCC CE = VIL, f = 5 MHz, IOUT = 0 mA Max µA 5.0 C/I Devices 50 E Devices 60 mA CE = VIH 1.0 mA CE = VCC ± 0.3 V 100 µA CE = OE = VIL, VPP = VCC 100 µA Notes: 1. VCC must be applied simultaneously or before VPP, and removed simultaneously or after VPP. 2. Caution: The Am27C2048 must not be removed from (or inserted into) a socket when VCC or VPP is applied. 3. ICC1 is tested with OE = VIH to simulate open outputs. 4. Minimum DC Input Voltage is –0.5 V. During transitions, the inputs may overshoot to –2.0 V for periods less than 20 ns. Maximum DC Voltage on output pins is VCC + 0.5 V, which may overshoot to VCC + 2.0 V for periods less than 20 ns. 8 Am27C2048 35 30 30 Supply Current in mA Supply Current in mA 35 25 20 2 3 4 5 6 7 Frequency in MHz 8 9 20 15 –75 –50 –55 0 25 50 75 100 125 150 Temperature in °C 15 1 25 10 11407F-6 11407F-5 Figure 1. Typical Supply Current vs. Frequency VCC = 5.5 V, T = 25°C Figure 2. Typical Supply Current vs. Temperature VCC = 5.5 V, f = 5 MHz CAPACITANCE Parameter Symbol CIN COUT Parameter Description CDV040 Test Conditions PD 040 PL 044 Typ Max Typ Max Typ Max Unit Input Capacitance VIN = 0 10 12 10 12 7 10 pF Output Capacitance VOUT = 0 12 15 12 15 12 14 pF Notes: 1. This parameter is only sampled and not 100% tested. 2. TA = +25°C, f = 1 MHz. Am27C2048 9 AC CHARACTERISTICS Parameter Symbols Am27C2048 JEDEC Standard Description Test Setup -55 -70 -90 -120 -150 -200 -255 Unit tAVQV tACC Address to Output Delay CE, OE = VIL Max 55 70 90 120 150 200 250 ns tELQV tCE Chip Enable to Output Delay OE = VIL Max 55 70 90 120 150 200 250 ns tGLQV tOE Output Enable to Output Delay CE = VIL Max 40 40 40 50 65 75 75 ns tEHQZ tGHQZ tDF (Note 3) Chip Enable to Output High Z or Output Enable to Output High Z to Output Float, Whichever Occurs First Max 25 25 25 30 30 40 60 ns tAXQX tOH Output Hold Time from Addresses, CE or OE, Whichever Occurs First Min 0 0 0 0 0 0 0 ns Notes: 1. Caution: Do not remove the Am27C2048 from (or insert it into) a socket or board that has VPP or VCC applied. 2. VCC must be applied simultaneously or before VPP, and removed simultaneously or after VPP. 3. This parameter is sampled and not 100% tested. 4. Switching characteristics are over operating range, unless otherwise specified. 5. Test Conditions for Am27C2048-55: Output Load: 1 TTL gate and CL = 30 pF Input rise and fall times: 20 ns Input pulse levels: 0.0 V to 3.0 V Timing measurement reference level Inputs and Outputs: 1.5 V Test Conditions for all others: Output Load: 1 TTL gate and CL = 100 pF Input rise and fall times: 20 ns Input pulse levels: 0.45 V to 2.4 V Timing measurement reference level Inputs and Outputs: 0.8 and 2.0 V 10 Am27C2048 SWITCHING TEST CIRCUIT 5.0 V IN3064 or Equivalent Device Under Test CL 2.7 kΩ 6.2 kΩ Diodes = IN3064 or Equivalent Notes: For -55: CL = 30 pF including jig capacitance For all others: CL = 100 pF including jig capacitance 11407F-7 SWITCHING TEST WAVEFORM 3V 2.4 V 2.0 V 2.0 V Test Points 1.5 V Test Points 1.5 V 0.8 V 0V 0.8 V 0.45 V Input Output Input AC Testing for -55 devices: Inputs are driven at 3.0 V for a logic “1” and 0 V for a logic “0”. Input pulse rise and fall times are ≤20 ns. Output AC Testing (except for -55 devices): Inputs are driven at 2.4 V for a logic “1” and 0.45 V for a logic “0”. Input pulse rise and fall times are ≤20 ns. 11407F-8 Am27C2048 11 KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS OUTPUTS Must be Steady Will be Steady May Change from H to L Will be Changing from H to L May Change from L to H Will be Changing from L to H Don’t Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is HighImpedance “Off” State KS000010-PAL SWITCHING WAVEFORMS 2.4 Addresses 0.45 2.0 0.8 2.0 0.8 Addresses Valid CE tCE OE tOE Output High Z tACC (Note 1) tOH Valid Output tDF (Note 2) High Z 11407F-9 Trademarks Copyright © 1997 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc. Flashrite is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. 12 Am27C2048 Valid Combinations: Added the 55 ns speed grade to the table. REVISION SUMMARY FOR AM27C2048 Distinctive Characteristics: The fastest speed grade available is now 55 ns. Operating Ranges: Product Selector Guide: Changed Supply Read Voltages listings to match those in the Product Selector Guide. Added 55 ns column. AC Characteristics: Ordering Information, UV EPROM Products: The 55 ns part number is now listed in the example. The nomenclature now has a method of clearly designating the voltage operating range and speed grade. Ordering Information, OTP EPROM Products: Changed the part number example from -70 to -55. The nomenclature now has a method of clearly designating the voltage operating range and speed grade. Added column for 55 ns speed grade, rearranged notes, moved text from table title to Note 4, renamed table. Switching Test Circuit: Added 55 ns to the CL note on 30 pF test condition. Switching Test Waveform: Added the 3 V test waveform. Am27C2048 13