ETC AT29C040A-12JC

Features
• Fast Read Access Time – 120 ns
• 5-volt Only Reprogramming
• Sector Program Operation
•
•
•
•
•
•
•
•
•
– Single Cycle Reprogram (Erase and Program)
– 2048 Sectors (256 bytes/sector)
– Internal Address and Data Latches for 256 Bytes
Internal Program Control and Timer
Hardware and Software Data Protection
Two 16 KB Boot Blocks with Lockout
Fast Sector Program Cycle Time - 10 ms
DATA Polling for End of Program Detection
Low Power Dissipation
– 40 mA Active Current
– 100 µA CMOS Standby Current
Typical Endurance > 10,000 Cycles
Single 5V ± 10% Supply
CMOS and TTL Compatible Inputs and Outputs
4-megabit
(512K x 8)
5-volt Only
256-byte Sector
Flash Memory
Description
The AT29C040A is a 5-volt only in-system Flash Programmable and Erasable Read
Only Memory (PEROM). Its 4 megabits of memory is organized as 524,288 words by
8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS EEPROM technology,
the device offers access times up to 120 ns, and a low 220 mW power dissipation.
When the device is deselected, the CMOS standby current is less than 100 µA. The
device endurance is such that any sector can typically be written to in excess of
10,000 times. The programming algorithm is compatible with other devices in Atmel’s
(continued)
5-volt only Flash family.
PLCC Top View
CE
Chip Enable
OE
Output Enable
WE
Write Enable
I/O0 - I/O7
Data Inputs/Outputs
NC
No Connect
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
TSOP Top View
Type 1
DIP Top View
A18
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
4
3
2
1
32
31
30
Addresses
14
15
16
17
18
19
20
A0 - A18
I/O1
I/O2
GND
I/O3
I/O4
I/O5
I/O6
Function
A12
A15
A16
A18
VCC
WE
A17
Pin Configurations
Pin Name
AT29C040A
VCC
WE
A17
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
A11
A9
A8
A13
A14
A17
WE
VCC
A18
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
Rev. 0333G–03/01
1
To allow for simple in-system reprogrammability, the
AT29C040A does not require high input voltages for programming. Five-volt-only commands determine the operation of the device. Reading data out of the device is similar
to reading from an EPROM. Reprogramming the
AT29C040A is performed on a sector basis; 256 bytes of
data are loaded into the device and then simultaneously
programmed.
During a reprogram cycle, the address locations and 256
bytes of data are internally latched, freeing the address and
data bus for other operations. Following the initiation of a
program cycle, the device will automatically erase the sector and then program the latched data using an internal
control timer. The end of a program cycle can be detected
by DATA polling of I/O7. Once the end of a program cycle
has been detected, a new access for a read or program
can begin.
Block Diagram
Device Operation
READ: The AT29C040A is accessed like an EPROM.
When CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state whenever CE or OE is high. This dual-line
control gives designers flexibility in preventing bus contention.
BYTE LOAD: Byte loads are used to enter the 256 bytes
of a sector to be programmed or the software codes for
data protection. A byte load is performed by applying a low
pulse on the WE or CE input with CE or WE low (respectively) and OE high. The address is latched on the falling
edge of CE or WE, whichever occurs last. The data is
latched by the first rising edge of CE or WE.
PROGRAM: The device is reprogrammed on a sector
basis. If a byte of data within a sector is to be changed,
data for the entire sector must be loaded into the device.
Any byte that is not loaded during the programming of its
sector will be erased to read FFH. Once the bytes of a sector are loaded into the device, they are simultaneously programmed during the internal programming period. After the
2
AT29C040A
first data byte has been loaded into the device, successive
bytes are entered in the same manner. Each new byte to
be programmed must have its high to low transition on WE
(or CE) within 150 µs of the low to high transition of WE (or
CE) of the preceding byte. If a high to low transition is not
detected within 150 µs of the last low to high transition, the
load period will end and the internal programming period
will start. A8 to A18 specify the sector address. The sector
address must be valid during each high to low transition of
WE (or CE). A0 to A7 specify the byte address within the
sector. The bytes may be loaded in any order; sequential
loading is not required. Once a programming operation has
been initiated, and for the duration of tWC, a read operation
will effectively be a polling operation.
SOFTWARE DATA PROTECTION: A software controll ed data pr otec tion feature is av ailable on the
AT29C040A. Once the software protection is enabled a
software algorithm must be issued to the device before a
program may be performed. The software protection feature may be enabled or disabled by the user; when shipped
from Atmel, the software data protection feature is disabled. To enable the software data protection, a series of
three program commands to specific addresses with specific data must be performed. After the software data protection is enabled the same three program commands
must begin each program cycle in order for the programs to
occur. All software program commands must obey the sector program timing specifications. The SDP feature protects
all sectors, not just a single sector. Once set, the software
data protection feature remains active unless its disable
command is issued. Power transitions will not reset the
software data protection feature, however the software feature will guard against inadvertent program cycles during
power transitions.
After setting SDP, any attempt to write to the device without
the three-byte command sequence will start the internal
write timers. No data will be written to the device; however,
for the duration of tWC, a read operation will effectively be a
polling operation.
After the software data protection’s 3-byte command code
is given, a byte load is performed by applying a low pulse
on the WE or CE input with CE or WE low (respectively)
and OE high. The address is latched on the falling edge of
CE or WE, whichever occurs last. The data is latched by
the first rising edge of CE or WE. The 256 bytes of data
must be loaded into each sector by the same procedure as
outlined in the program section under device operation.
HARDWARE DATA PROTECTION: Hardware features
protect against inadvertent programs to the AT29C040A in
the following ways: (a) V CC sense—if V CC is below 3.8V
(typical), the program function is inhibited; (b) VCC power on
delay—once V CC has reached the V CC sense level, the
device will automatically time out 5 ms (typical) before programming; (c) Program inhibit—holding any one of OE low,
AT29C040A
CE high or WE high inhibits program cycles; and (d) Noise
filter—pulses of less than 15 ns (typical) on the WE or CE
inputs will not initiate a program cycle.
PRODUCT IDENTIFICATION: The product identification
mode identifies the device and manufacturer as Atmel. It
may be accessed by hardware or software operation. The
hardware operation mode can be used by an external programmer to identify the correct programming algorithm for
the Atmel product. In addition, users may wish to use the
software product identification mode to identify the part (i.e.
using the device code), and have the system software use
the appropriate sector size for program operations. In this
manner, the user can have a common board design for
256K to 4-megabit densities and, with each density’s sector
size in a memory map, have the system software apply the
appropriate sector size.
For details, see Operating Modes (for hardware operation)
or Software Product Identification. The manufacturer and
device code is the same for both modes.
DATA POLLING: The AT29C040A features DATA polling to indicate the end of a program cycle. During a program cycle an attempted read of the last byte loaded will
result in the complement of the loaded data on I/O7. Once
the program cycle has been completed, true data is valid
on all outputs and the next cycle may begin. DATA polling
may begin at any time during the program cycle.
TOGGLE BIT: In addition to DATA polling the
AT29C040A provides another method for determining the
end of a program or erase cycle. During a program or erase
operation, successive attempts to read data from the
device will result in I/O6 toggling between one and zero.
Once the program cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit
may begin at any time during a program cycle.
OPTIONAL CHIP ERASE MODE: The entire device can
be erased by using a 6-byte software code. Please see
Software Chip Erase application note for details.
BO OT BLOCK PROGRAMMING LOCKO UT: The
AT29C040A has two designated memory blocks that have
a programming lockout feature. This feature prevents programming of data in the designated block once the feature
has been enabled. Each of these blocks consists of 16K
bytes; the programming lockout feature can be set independently for either block. While the lockout feature does
not have to be activated, it can be activated for either or
both blocks.
These two 16K memory sections are referred to as boot
blocks. Secure code which will bring up a system can be
contained in a boot block. The AT29C040A blocks are
located in the first 16K bytes of memory and the last 16K
bytes of memory. The boot block programming lockout feature can therefore support systems that boot from the lower
addresses of memory or the higher addresses. Once the
programming lockout feature has been activated, the data
in that block can no longer be erased or programmed; data
in other memory locations can still be changed through the
regular programming methods. To activate the lockout feature, a series of seven program commands to specific
addresses with specific data must be performed. Please
see Boot Block Lockout Feature Enable Algorithm.
If the boot block lockout feature has been activated on
either block, the chip erase function will be disabled.
BOOT BLOCK LOCKOUT DETECTION: A software
method is available to determine whether programming of
either boot block section is locked out. See Software Product Identification Entry and Exit sections. When the device
is in the software product identification mode, a read from
location 00002H will show if programming the lower
address boot block is locked out while reading location
FFFF2H will do so for the upper boot block. If the data is
FE, the corresponding block can be programmed; if the
data is FF, the program lockout feature has been activated
and the corresponding block cannot be programmed. The
software product identification exit mode should be used to
return to standard operation.
Absolute Maximum Ratings*
Temperature Under Bias................................ -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
All Input Voltages (including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to VCC + 0.6V
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Voltage on OE
with Respect to Ground ...................................-0.6V to +13.5V
3
DC and AC Operating Range
AT29C040A-12
AT29C040A-15
AT29C040A-20
0°C - 70°C
0°C - 70°C
0°C - 70°C
-40°C - 85°C
-40°C - 85°C
-40°C - 85°C
5V ± 10%
5V ± 10%
5V ± 10%
Com.
Operating
Temperature (Case)
Ind.
VCC Power Supply
Operating Modes
Mode
CE
OE
WE
Ai
I/O
VIL
VIL
VIH
Ai
DOUT
VIL
VIH
VIL
Ai
DIN
VIH
X(1)
X
X
High Z
Program Inhibit
X
X
VIH
Program Inhibit
X
VIL
X
Output Disable
X
VIH
X
VIL
VIL
VIH
Read
Program
(2)
Standby/Write Inhibit
High Z
Product Identification
Hardware
A1 - A18 = VIL, A9 = VH,(3) A0 = VIL
Manufacturer Code(4)
A1 - A18 = VIL, A9 = VH,(3) A0 = VIH
Device Code(4)
Software(5)
Notes:
A0 = VIL
Manufacturer Code(4)
A0 = VIH
Device Code(4)
1. X can be VIL or VIH.
2. Refer to AC Programming Waveforms.
3. VH = 12.0V ± 0.5V.
4. Manufacturer Code: 1F, Device Code: A4.
5. See details under Software Product Identification Entry/Exit.
DC Characteristics
Symbol
Parameter
Condition
ILI
Input Load Current
ILO
Max
Units
VIN = 0V to VCC
10
µA
Output Leakage Current
VI/O = 0V to VCC
10
µA
Com.
100
µA
ISB1
VCC Standby Current CMOS
CE = VCC - 0.3V to VCC
Ind.
300
µA
ISB2
VCC Standby Current TTL
CE = 2.0V to VCC
3
mA
ICC
VCC Active Current
f = 5 MHz; IOUT = 0 mA
40
mA
VIL
Input Low Voltage
0.8
V
VIH
Input High Voltage
VOL
Output Low Voltage
IOL = 2.1 mA
VOH1
Output High Voltage
IOH = -400 µA
2.4
V
VOH2
Output High Voltage CMOS
IOH = -100 µA; VCC = 4.5V
4.2
V
4
Min
2.0
AT29C040A
V
0.45
V
AT29C040A
AC Read Characteristics
Symbol
Parameter
tACC
AT29C040A-12
AT29C040A-15
AT29C040A-20
Min
Min
Min
Max
Max
Max
Units
Address to Output Delay
120
150
200
ns
(1)
CE to Output Delay
120
150
200
ns
(2)
OE to Output Delay
0
50
0
70
0
80
ns
tDF(3)(4)
CE or OE to Output Float
0
30
0
40
0
50
ns
tOH
Output Hold from OE, CE or
Address, whichever occurred first
0
tCE
tOE
0
0
ns
AC Read Waveforms(1)(2)(3)(4)
Notes:
1.
CE may be delayed up to tACC - tCE after the address transition without impact on tACC.
2.
OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC.
3.
tDF is specified from OE or CE whichever occurs first (CL = 5 pF).
4.
This parameter is characterized and is not 100% tested.
Input Test Waveforms and
Measurement Level
Output Test Load
tR, tF < 5 ns
Pin Capacitance
f = 1 MHz, T = 25°C(1)
Symbol
CIN
COUT
Note:
Typ
Max
Units
Conditions
4
6
pF
VIN = 0V
pF
VOUT = 0V
8
12
1. This parameter is characterized and is not 100% tested.
5
AC Byte Load Characteristics
Symbol
Parameter
Min
Max
Units
tAS, tOES
Address, OE Setup Time
10
ns
tAH
Address Hold Time
50
ns
tCS
Chip Select Setup Time
0
ns
tCH
Chip Select Hold Time
0
ns
tWP
Write Pulse Width (WE or CE)
90
ns
tDS
Data Setup Time
50
ns
tDH, tOEH
Data, OE Hold Time
10
ns
tWPH
Write Pulse Width High
100
ns
AC Byte Load Waveforms(1)
WE Controlled
CE Controlled
Note:
6
1.
A complete sector (256 bytes) should be loaded using the waveforms shown in these byte load waveform diagrams.
AT29C040A
AT29C040A
Program Cycle Characteristics
Symbol
Parameter
Min
Max
Units
tWC
Write Cycle Time
10
ms
tAS
Address Setup Time
10
ns
tAH
Address Hold Time
50
ns
tDS
Data Setup Time
50
ns
tDH
Data Hold Time
10
ns
tWP
Write Pulse Width
90
ns
tBLC
Byte Load Cycle Time
tWPH
Write Pulse Width High
150
100
µs
ns
Program Cycle Waveforms(1)(2)(3)
Notes:
1.
A8 through A18 must specify the sector address during each high to low transition of WE (or CE).
2.
OE must be high only when WE and CE are both low.
3.
All bytes that are not loaded within the sector being programmed will be indeterminate.
7
Software Data Protection
Enable Algorithm(1)
Software Data Protection
Disable Algorithm(1)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA A0
TO
ADDRESS 5555
WRITES ENABLED
LOAD DATA 80
TO
ADDRESS 5555
LOAD DATA
TO
PAGE (256 BYTES)(4)
ENTER DATA
PROTECT STATE(2)
LOAD DATA AA
TO
ADDRESS 5555
Notes for software program code:
1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. Data Protect state will be activated at end of program
cycle.
3. Data Protect state will be deactivated at end of program
period.
4. 256 bytes of data MUST BE loaded.
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 20
TO
ADDRESS 5555
EXIT DATA
PROTECT STATE(3)
LOAD DATA
TO
PAGE (256 BYTES)(4)
Software Protected Program Cycle Waveform(1)(2)(3)
Notes:
8
1.
A8 through A18 must specify the sector address during each high to low transition of WE (or CE) after the software code
has been entered.
2.
OE must be high when WE and CE are both low.
3.
All bytes that are not loaded within the sector being programmed will be indeterminate.
AT29C040A
AT29C040A
Data Polling Characteristics(1)
Symbol
Parameter
Min
tDH
Data Hold Time
10
ns
tOEH
OE Hold Time
10
ns
Max
(2)
tOE
tWR
Notes:
Typ
OE to Output Delay
Write Recovery Time
1. These parameters are characterized and not 100% tested.
Units
ns
0
ns
2. See tOE spec in AC Read Characteristics.
Data Polling Waveforms
Toggle Bit Characteristics(1)
Symbol
Parameter
Min
tDH
Data Hold Time
10
ns
tOEH
OE Hold Time
10
ns
(2)
tOE
OE to Output Delay
tOEHP
OE High Pulse
tWR
Notes:
Write Recovery Time
1. These parameters are characterized and not 100% tested.
Typ
Max
Units
ns
150
ns
0
ns
2. See tOE spec in AC Read Characteristics.
Toggle Bit Waveforms(1)(2)(3)
Notes:
1.
Toggling either OE or CE or both OE and CE will operate toggle bit. The tOEHP specification must be met by the toggling
input(s).
2.
Beginning and ending state of I/O6 will vary.
3.
Any address location may be used but the address should not vary.
9
Software Product Identification Entry(1)
LOAD DATA AA
TO
ADDRESS 5555
Boot Block Lockout
Feature Enable Algorithm(1)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 90
TO
ADDRESS 5555
PAUSE 10 mS
LOAD DATA 80
TO
ADDRESS 5555
ENTER PRODUCT
IDENTIFICATION
MODE(2)(3)(5)
LOAD DATA AA
TO
ADDRESS 5555
Software Product Identification Exit(1)
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 40
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA F0
TO
ADDRESS 5555
PAUSE 10 mS
EXIT PRODUCT
IDENTIFICATION
MODE(4)
Notes for software product identification:
1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. A1 - A18 = VIL.
Manufacturer Code is read for A0 = VIL;
Device Code is read for A0 = VIH.
3. The device does not remain in identification mode if
powered down.
4. The device returns to standard operation mode.
5. Manufacturer Code is 1F. The Device Code is A4.
10
AT29C040A
LOAD DATA 00
TO
ADDRESS 00000H(2)
LOAD DATA FF
TO
ADDRESS FFFFFH(3)
PAUSE 10 mS
PAUSE 10 mS
Notes for boot block lockout feature enable:
1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. Lockout feature set on lower address boot block.
3. Lockout feature set on higher address boot block.
AT29C040A
Ordering Information
ICC (mA)
tACC
(ns)
Active
Standby
Ordering Code
Package
120
40
0.1
AT29C040A-12JC
AT29C040A-12PC
AT29C040A-12TC
32J
32P6
32T
Commercial
(0° to 70°C)
40
0.3
AT29C040A-12JI
AT29C040A-12PI
AT29C040A-12TI
32J
32P6
32T
Industrial
(-40° to 85°C)
40
0.1
AT29C040A-15JC
AT29C040A-15PC
AT29C040A-15TC
32J
32P6
32T
Commercial
(0° to 70°C)
40
0.3
AT29C040A-15JI
AT29C040A-15PI
AT29C040A-15TI
32J
32P6
32T
Industrial
(-40° to 85°C)
40
0.1
AT29C040A-20JC
AT29C040A-20PC
AT29C040A-20TC
32J
32P6
32T
Commercial
(0° to 70°C)
40
0.3
AT29C040A-20JI
AT29C040A-20PI
AT29C040A-20TI
32J
32P6
32T
Industrial
(-40° to 85°C)
150
200
Operation Range
Package Type
32J
32-lead, Plastic J-leaded Chip Carrier (PLCC)
32P6
32-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)
32T
32-lead, Thin Small Outline Package (TSOP)
11
Packaging Information
32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC)
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-016 AE
.045(1.14) X 45˚
PIN NO. 1
IDENTIFY
.050(1.27) TYP
.300(7.62) REF
.430(10.9)
.390(9.90)
AT CONTACT
POINTS
.030(.762)
.015(.381)
.095(2.41)
.060(1.52)
.140(3.56)
.120(3.05)
JEDEC OUTLINE MO-142 BD
INDEX
MARK
20.2(.795)
19.8(.780)
0.25(.010)
0.15(.006)
8.20(.323)
7.80(.307)
1.20(.047) MAX
0.15(.006)
0.05(.002)
0
5 REF
0.20(.008)
0.10(.004)
0.70(.028)
0.50(.020)
*Controlling dimension: millimeters
12
AT29C040A
.090(2.29)
MAX
1.500(38.10) REF
.220(5.59)
MAX
.005(.127)
MIN
SEATING
PLANE
.065(1.65)
.015(.381)
.022(.559)
.014(.356)
.161(4.09)
.125(3.18)
.110(2.79)
.090(2.29)
.012(.305)
.008(.203)
32T, 32-lead, Plastic Thin Small Outline Package
(TSOP)
Dimensions in Millimeters and (Inches)*
7.50(.295)
REF
.566(14.4)
.530(13.5)
.021(.533)
.013(.330)
.453(11.5)
.447(11.4)
.495(12.6)
.485(12.3)
18.5(.728)
18.3(.720)
PIN
1
.530(13.5)
.490(12.4)
.022(.559) X 45˚ MAX (3X)
0.50(.020)
BSC
1.67(42.4)
1.64(41.7)
.025(.635) X 30˚ - 45˚
.012(.305)
.008(.203)
.553(14.0)
.547(13.9)
.595(15.1)
.585(14.9)
.032(.813)
.026(.660)
32P6, 32-lead, 0.600” Wide, Plastic Dual Inline
Package (PDIP)
Dimensions in Inches and (Millimeters)
.065(1.65)
.041(1.04)
.630(16.0)
.590(15.0)
0 REF
15
.690(17.5)
.610(15.5)
Atmel Headquarters
Atmel Operations
Corporate Headquarters
Atmel Colorado Springs
2325 Orchard Parkway
San Jose, CA 95131
TEL (408) 441-0311
FAX (408) 487-2600
Europe
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Atmel Smart Card ICs
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© Atmel Corporation 2001.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
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not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted
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