ETC AT49BV1614-11CI

Features
• 2.7V to 3.3V Read/Write
• Access Time – 90 ns
• Sector Erase Architecture
•
•
•
•
•
•
•
•
•
•
•
– Thirty 32K Word (64K Byte) Sectors with Individual Write Lockout
– Eight 4K Word (8K Byte) Sectors with Individual Write Lockout
– Two 16K Word (32K Byte) Sectors with Individual Write Lockout
Fast Word Program Time – 20 µs
Fast Sector Erase Time – 200 ms
Dual-plane Organization, Permitting Concurrent Read while Program/Erase
Memory Plane A: Eight 4K Word, Two 16K Word and Six 32K Word Sectors
Memory Plane B: Twenty-four 32K Word Sectors
Erase Suspend Capability
– Supports Reading/Programming Data from Any Sector by Suspending Erase of
Any Different Sector
Low-power Operation
– 25 mA Active
– 10 µA Standby
Data Polling, Toggle Bit, Ready/Busy for End of Program Detection
Optional VPP Pin for Fast Programming
RESET Input for Device Initialization
Sector Program Unlock Command
TSOP, CBGA and µBGA Package Options
Top or Bottom Boot Block Configuration Available
Description
The AT49BV16X4(T) is a 2.7- to 3.3-volt 16-megabit Flash memory organized as
1,048,576 words of 16 bits each or 2,097,152 bytes of 8 bits each. The x16 data
appears on I/O0 - I/O15; the x8 data appears on I/O0 - I/O7. The memory is divided
into 40 sectors for erase operations. The device is offered in 48-lead TSOP and
48-ball µBGA packages. The device has CE and OE control signals to avoid any bus
(continued)
Pin Configurations
Pin Name
16-megabit
(1M x 16/2M x 8)
3-volt Only
Flash Memory
AT49BV1604
AT49BV1604T
AT49BV1614
AT49BV1614T
Recommend Using
AT49BV160(T)/161(T)
for New Designs
Function
A0 - A19
Addresses
CE
Chip Enable
OE
Output Enable
WE
Write Enable
RESET
Reset
RDY/BUSY
READY/BUSY Output
VPP
Optional Power Supply for Faster
Program/Erase Operations
I/O0 - I/O14
Data Inputs/Outputs
I/O15 (A-1)
I/O15 (Data Input/Output, Word Mode)
A-1 (LSB Address Input, Byte Mode)
BYTE
Selects Byte or Word Mode
NC
No Connect
VCCQ
Output Power Supply
DC
Don’t Connect
Rev. 0925K–09/00
1
AT49BV1604(T)
µBGA Top View (Ball Down)
6
7
8
A19
A7
A4
A17
A5
A2
A6
A3
A1
I/O2
I/O8
CE
A0
I/O12
I/O3
I/O9
I/O0
GND
I/O4
VCC
I/O10
I/O1
OE
1
2
3
4
A13
A11
A8
VPP
A14
A10
WE
RST
A15
A12
A9
A16
I/O14
I/O5
I/O11
VCCQ I/O15
I/O6
I/O7
I/O13
5
A
B
A18
C
D
E
F
GND
CBGA Top View
TSOP Top View
Type 1
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
WE
RESET
VPP
NC
RDY/BUSY
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE
GND
I/O15/A-1
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
VCC
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
OE
GND
CE
A0
2
A3
3
4
5
6
A7 RDY/BUSY WE
A9
A13
A4
A17
NC
RESET
A8
A12
A2
A6
A18
VPP
A10
A14
A1
A5
NC
A19
A11
A15
A0
I/O0
I/O2
I/O5
I/O7
A16
CE
I/O8
I/O10
I/O12
I/O14
BYTE
OE
I/O9
I/O11
VCC
I/O13
I/O15
/A-1
VSS
I/O1
I/O3
I/O4
I/O6
VSS
A
B
C
D
E
AT49BV1614(T)
contention. This device can be read or reprogrammed
using a single 2.7V power supply, making it ideally suited
for in-system programming.
The device powers on in the read mode. Command
sequences are used to place the device in other operation
modes such as program and erase. The device has the
capability to protect the data in any sector. Once the data
protection for a given sector is enabled, the data in that
sector cannot be changed using input levels between
ground and VCC.
The device is segmented into two memory planes. Reads
from memory plane B may be performed even while
2
1
F
G
H
program or erase functions are being executed in memory
plane A and vice versa. This operation allows improved
system performance by not requiring the system to wait for
a program or erase operation to complete before a read is
performed. To further increase the flexibility of the device, it
contains an Erase Suspend feature. This feature will put
the erase on hold for any amount of time and let the user
read data from or program data to any of the remaining
sectors within the same memory plane. There is no reason
to suspend the erase operation if the data to be read is in
the other memory plane. The end of a program or an erase
cycle is detected by the Ready/Busy pin, Data Polling or by
the toggle bit.
AT49BV1604(T)/1614(T)
AT49BV1604(T)/1614(T)
A VPP pin is provided to improve program/erase times.
This pin can be tied to V CC. To take advantage of faster
programming and erasing, the pin should supply 4.5 to 5.5
volts during program and erase operations.
A six-byte command (Bypass Unlock) sequence to remove
the requirement of entering the three-byte program
sequence is offered to further improve programming time.
After entering the six-byte code, only single pulses on the
write control lines are required for writing into the device.
This mode (Single Pulse Byte/Word Program) is exited by
powering down the device, or by pulsing the RESET pin
low for a minimum of 50 ns and then bringing it back to VCC.
Erase and Erase Suspend/Resume commands will not
work while in this mode; if entered they will result in data
being programmed into the device. It is not recommended
that the six-byte code reside in the software of the final
product but only exist in external programming code.
For the AT49BV1614(T), the BYTE pin controls whether
the device data I/O pins operate in the byte or word configuration. If the BYTE pin is set at logic “1”, the device is in
word configuration, I/O0 - I/O15 are active and controlled
by CE and OE.
If the BYTE pin is set at logic “0”, the device is in byte configuration, and only data I/O pins I/O0 - I/O7 are active and
controlled by CE and OE. The data I/O pins I/O8 - I/O14
are tri-stated, and the I/O15 pin is used as an input for the
LSB (A-1) address function.
Block Diagram
I/O0 - I/O15/A-1
INPUT
BUFFER
INPUT
BUFFER
IDENTIFIER
REGISTER
STATUS
REGISTER
DATA
REGISTER
A0 - A19
OUTPUT
MULTIPLEXER
OUTPUT
BUFFER
CE
WE
OE
RESET
BYTE
COMMAND
REGISTER
ADDRESS
LATCH
DATA
COMPARATOR
Y-DECODER
Y-GATING
RDY/BUSY
WRITE STATE
MACHINE
PROGRAM/ERASE
VOLTAGE SWITCH
VPP
VCC
GND
X-DECODER
PLANE B
SECTORS
PLANE A SECTORS
Device Operation
READ: The AT49BV16X4(T) is accessed like an EPROM.
When CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins are
asserted on the outputs. The outputs are put in the highimpedance state whenever CE or OE is high. This dual-line
control gives designers flexibility in preventing bus
contention.
COMMAND SEQUENCES: When the device is first powered on, it will be reset to the read or standby mode,
depending upon the state of the control line inputs. In order
to perform other device functions, a series of command
sequences are entered into the device. The command
sequences are shown in the Command Definitions table
(I/O8 - I/O15 are don’t care inputs for the command codes).
3
The command sequences are written by applying a low
pulse on the WE or CE input with CE or WE low (respectively) and OE high. The address is latched on the falling
edge of CE or WE, whichever occurs last. The data is
latched by the first rising edge of CE or WE. Standard
microprocessor write timings are used. The address locations used in the command sequences are not affected by
entering the command sequences.
RESET: A RESET input pin is provided to ease some system applications. When RESET is at a logic high level, the
device is in its standard operating mode. A low level on the
RESET input halts the present device operation and puts
the outputs of the device in a high-impedance state. When
a high level is reasserted on the RESET pin, the device
returns to the read or standby mode, depending upon the
state of the control inputs. By applying a 12V ± 0.5V input
signal to the RESET pin, any sector can be reprogrammed
even if the sector lockout feature has been enabled (see
Sector Programming Lockout Override section).
ERASURE: Before a byte/word can be reprogrammed, it
must be erased. The erased state of memory bits is a logical “1”. The entire device can be erased by using the Chip
Erase command or individual sectors can be erased by
using the Sector Erase command.
CHIP ERASE: The entire device can be erased at one time
by using the six-byte chip erase software code. After the
chip erase has been initiated, the device will internally time
the erase operation so that no external clocks are required.
The maximum time to erase the chip is tEC.
If the sector lockout has been enabled, the chip erase will
not erase the data in the sector that has been locked; it will
erase only the unprotected sectors. After the chip erase,
the device will return to the read or standby mode.
SECTOR ERASE: As an alternative to a full chip erase, the
device is organized into 40 sectors (SA0 - SA39) that can
be individually erased. The Sector Erase command is a sixbus cycle operation. The sector address is latched on the
falling WE edge of the sixth cycle while the 30H data input
command is latched on the rising edge of WE. The sector
erase starts after the rising edge of WE of the sixth cycle.
The erase operation is internally controlled; it will automatically time to completion. The maximum time to erase a
section is tSEC. When the sector programming lockout feature is not enabled, the sector will erase (from the same
Sector Erase command). Once a sector has been protected, data in the protected sectors cannot be changed
unless the RESET pin is taken to 12V ± 0.5V. An attempt to
erase a sector that has been protected will result in the
operation terminating in 2 µs.
BYTE/WORD PROGRAMMING: Once a memory block is
erased, it is programmed (to a logical “0”) on a byte-by-byte
or on a word-by-word basis. Programming is accomplished
4
via the internal device command register and is a four-bus
cycle operation. The device will automatically generate the
required internal program pulses.
Any commands written to the chip during the embedded
programming cycle will be ignored. If a hardware reset happens during programming, the data at the location being
programmed will be corrupted. Please note that a data “0”
cannot be programmed back to a “1”; only erase operations
can convert “0”s to “1”s. Programming is completed after
the specified tBP cycle time. The Data Polling feature or the
Toggle Bit feature may be used to indicate the end of a program cycle.
SECTOR PROGRAMMING LOCKOUT: Each sector has a
programming lockout feature. This feature prevents programming of data in the designated sectors once the
feature has been enabled. These sectors can contain
secure code that is used to bring up the system. Enabling
the lockout feature will allow the boot code to stay in the
device while data in the rest of the device is updated. This
feature does not have to be activated; any sector’s usage
as a write-protected region is optional to the user.
Once the feature is enabled, the data in the protected sectors can no longer be erased or programmed when input
levels of 5.5V or less are used. Data in the remaining sectors can still be changed through the regular programming
method. To activate the lockout feature, a series of six program commands to specific addresses with specific data
must be performed. Please refer to the Command Definitions table.
SECTOR LOCKOUT DETECTION: A software method is
available to determine if programming of a sector is locked
out. When the device is in the software product identification mode (see Software Product Identification Entry and
Exit sections) a read from address location 00002H within a
sector will show if programming the sector is locked out. If
the data on I/O0 is low, the sector can be programmed; if
the data on I/O0 is high, the program lockout feature has
been enabled and the sector cannot be programmed. The
software product identification exit code should be used to
return to standard operation.
SECTOR PROGRAMMING LOCKOUT OVERRIDE: The
user can override the sector programming lockout by taking
the RESET pin to 12V ± 0.5V. By doing this, protected data
can be altered through a chip erase, sector erase or
byte/word programming. When the RESET pin is brought
back to TTL levels, the sector programming lockout feature
is again active.
ERASE SUSPEND/ERASE RESUME: The Erase Suspend command allows the system to interrupt a sector
erase operation and then program or read data from a different sector within the same plane. Since this device has a
dual-plane architecture, there is no need to use the Erase
AT49BV1604(T)/1614(T)
AT49BV1604(T)/1614(T)
Suspend feature while erasing a sector when you want to
read data from a sector in the other plane. After the Erase
Suspend command is given, the device requires a maximum time of 15 µs to suspend the erase operation. After
the erase operation has been suspended, the plane that
contains the suspended sector enters the erase-suspendread mode. The system can then read data or program
data to any other sector within the device. An address is
not required during the Erase Suspend command. During a
sector erase suspend, another sector cannot be erased. To
resume the sector erase operation, the system must write
the Erase Resume command. The Erase Resume command is a one-bus cycle command, which does require the
plane address (determined by A18 and A19). The device
also supports an erase suspend during a complete chip
erase. While the chip erase is suspended, the user can
read from any sector within the memory that is protected.
The command sequence for a chip erase suspend and a
sector erase suspend are the same.
PRODUCT IDENTIFICATION: The product identification
mode identifies the device and manufacturer as Atmel. It
may be accessed by hardware or software operation. The
hardware operation mode can be used by an external programmer to identify the correct programming algorithm for
the Atmel product.
For details, see “Operating Modes” on page 9 (for hardware operation) or “Software Product Identification
Entry/Exit” on page 14. The manufacturer and device code
is the same for both modes.
DATA POLLING: The AT49BV16X4(T) features Data Polling to indicate the end of a program cycle. During a
program cycle an attempted read of the last byte/word
loaded will result in the complement of the loaded data on
I/O7. Once the program cycle has been completed, true
data is valid on all outputs and the next cycle may begin.
During a chip or sector erase operation, an attempt to read
the device will give a “0” on I/O7. Once the program or
erase cycle has completed, true data will be read from the
device. Data Polling may begin at any time during the program cycle. Please see “Status Bit Table” on page 15 for
more details.
TOGGLE BIT: In addition to Data Polling, the
AT49BV16X4(T) provides another method for determining
the end of a program or erase cycle. During a program or
erase operation, successive attempts to read data from the
same memory plane will result in I/O6 toggling between
one and zero. Once the program cycle has completed, I/O6
will stop toggling and valid data will be read. Examining the
toggle bit may begin at any time during a program cycle.
An additional toggle bit is available on I/O2, which can be
used in conjunction with the toggle bit that is available on
I/O6. While a sector is erase suspended, a read or a program operation from the suspended sector will result in the
I/O2 bit toggling. Please see “Status Bit Table” on page 15
for more details.
RDY/BUSY: An open drain Ready/Busy output pin provides another method of detecting the end of a program or
erase operation. RDY/BUSY is actively pulled low during
the internal program and erase cycles and is released at
the completion of the cycle. The open drain connection
allows for OR-tying of several devices to the same
RDY/BUSY line.
HARDWARE DATA PROTECTION: The Hardware Data
Protection feature protects against inadvertent programs to
the AT49BV16X4(T) in the following ways: (a) VCC sense: if
VCC is below 1.8V (typical), the program function is inhibited. (b) V CC power-on delay: once V CC has reached the
V CC sense level, the device will automatically time out
10 ms (typical) before programming. (c) Program inhibit:
holding any one of OE low, CE high or WE high inhibits
program cycles. (d) Noise filter: pulses of less than 15 ns
(typical) on the WE or CE inputs will not initiate a program
cycle.
INPUT LEVELS: While operating with a 2.7V to 3.6V
power supply, the address inputs and control inputs (OE,
CE and WE) may be driven from 0 to 5.5V without
adversely affecting the operation of the device. The I/O
lines can only be driven from 0 to VCC + 0.6V.
OUTPUT LEVELS: For the 49BV1604(T), output high
levels (VOH) are equal to VCCQ - 0.2V (not VCC). For 2.7V 3.6V output levels, V CCQ must be tied to VCC . For 1.8V 2.2V output levels, VCCQ must be regulated to 2.0V ± 10%,
while VCC must be regulated to 2.7V - 3.0V (for minimum
power).
5
Command Definition in Hex(1)
Command
Sequence
1st Bus
Cycle
Bus
Cycles
Addr
Data
Read
1
Addr
DOUT
Chip Erase
6
5555
AA
2nd Bus
Cycle
3rd Bus
Cycle
4th Bus
Cycle
6th Bus
Cycle
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
2AAA
55
5555
80
5555
AA
2AAA
55
5555
10
Sector Erase
6
5555
AA
2AAA
55
5555
80
5555
AA
Byte/Word Program
4
5555
AA
2AAA
55
5555
A0
Addr
DIN
Bypass Unlock
6
5555
AA
2AAA
55
5555
80
5555
Single Pulse
Byte/Word Program
1
Addr
DIN
Sector Lockout
6
5555
AA
2AAA
55
5555
80
5555
Erase Suspend
1
xxxx
B0
Erase Resume
1
PA(5)
30
Product ID Entry
3
5555
AA
2AAA
55
5555
90
(2)
3
5555
AA
2AAA
55
5555
F0
Product ID Exit
5th Bus
Cycle
SA
(3)(4)
2AAA
55
AA
2AAA
55
5555
A0
AA
2AAA
55
SA(3)(4)
40
30
(2)
Product ID Exit
1
xxxx
F0
Notes: 1. The DATA FORMAT in each bus cycle is as follows: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex).
The ADDRESS FORMAT in each bus cycle is as follows: A15 - A0 (Hex), A-1, A14 - A19 (Don’t Care).
2. Either one of the Product ID Exit commands can be used.
3. SA = sector address. Any byte/word address within a sector can be used to designate the sector address (see next two
pages for details).
4. When the sector programming lockout feature is not enabled, the sector will erase (from the same Sector Erase command).
Once the sector has been protected, data in the protected sectors cannot be changed unless the RESET pin is taken to
12V ± 0.5V.
5. PA is the plane address (A19 - A18).
Absolute Maximum Ratings*
Temperature under Bias ................................ -55°C to +125°C
*NOTICE:
Storage Temperature ..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to VCC + 0.6V
Voltage on OE
with Respect to Ground ...................................-0.6V to +13.5V
6
AT49BV1604(T)/1614(T)
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
AT49BV1604(T)/1614(T)
AT49BV1604/1614 – Sector Address Table
Plane
Sector
Size (Bytes/Words)
x8
Address Range (A19 - A-1)
x16
Address Range (A19 - A0)
A
SA0
8K/4K
000000 - 001FFF
00000 - 00FFF
A
SA1
8K/4K
002000 - 003FFF
01000 - 01FFF
A
SA2
8K/4K
004000 - 005FFF
02000 - 02FFF
A
SA3
8K/4K
006000 - 007FFF
03000 - 03FFF
A
SA4
8K/4K
008000 - 009FFF
04000 - 04FFF
A
SA5
8K/4K
00A000 - 00BFFF
05000 - 05FFF
A
SA6
8K/4K
00C000 - 00DFFF
06000 - 06FFF
A
SA7
8K/4K
00E000 - 00FFFF
07000 - 07FFF
A
SA8
32K/16K
010000 - 017FFF
08000 - 0BFFF
A
SA9
32K/16K
018000 - 01FFFF
0C000 - 0FFFF
A
SA10
64K/32K
020000 - 02FFFF
10000 - 17FFF
A
SA11
64K/32K
030000 - 03FFFF
18000 - 1FFFF
A
SA12
64K/32K
040000 - 04FFFF
20000 - 27FFF
A
SA13
64K/32K
050000 - 05FFFF
28000 - 2FFFF
A
SA14
64K/32K
060000 - 06FFFF
30000 - 37FFF
A
SA15
64K/32K
070000 - 07FFFF
38000 - 3FFFF
B
SA16
64K/32K
080000 - 08FFFF
40000 - 47FFF
B
SA17
64K/32K
090000 - 09FFFF
48000 - 4FFFF
B
SA18
64K/32K
0A0000 - 0AFFFF
50000 - 57FFF
B
SA19
64K/32K
0B0000 - 0BFFFF
58000 - 5FFFF
B
SA20
64K/32K
0C0000 - 0CFFFF
60000 - 67FFF
B
SA21
64K/32K
0D0000 - 0DFFFF
68000 - 6FFFF
B
SA22
64K/32K
0E0000 - 0EFFFF
70000 - 77FFF
B
SA23
64K/32K
0F0000 - 0FFFFF
78000 - 7FFFF
B
SA24
64K/32K
100000 - 10FFFF
80000 - 87FFF
B
SA25
64K/32K
110000 - 11FFFF
88000 - 8FFFF
B
SA26
64K/32K
120000 - 12FFFF
90000 - 97FFF
B
SA27
64K/32K
130000 - 13FFFF
98000 - 9FFFF
B
SA28
64K/32K
140000 - 14FFFF
A0000 - A7FFF
B
SA29
64K/32K
150000 - 15FFFF
A8000 - AFFFF
B
SA30
64K/32K
160000 - 16FFFF
B0000 - B7FFF
B
SA31
64K/32K
170000 - 17FFFF
B8000 - BFFFF
B
SA32
64K/32K
180000 - 18FFFF
C0000 - C7FFF
B
SA33
64K/32K
190000 - 19FFFF
C8000 - CFFFF
B
SA34
64K/32K
1A0000 - 1AFFFF
D0000 - D7FFF
B
SA35
64K/32K
1B0000 - 1BFFFF
D8000 - DFFFF
B
SA36
64K/32K
1C0000 - 1CFFFF
E0000 - E7FFF
B
SA37
64K/32K
1D0000 - 1DFFFF
E8000 - EFFFF
B
SA38
64K/32K
1E0000 - 1EFFFF
F0000 - F7FFF
B
SA39
64K/32K
1F0000 - 1FFFFF
F8000 - FFFFF
7
AT49BV1604T/1614T – Sector Address Table
Plane
8
Sector
Size (Bytes/Words)
x8
Address Range (A19 - A-1)
x16
Address Range (A19 - A0)
B
SA0
64K/32K
000000 - 00FFFF
00000 - 07FFF
B
SA1
64K/32K
010000 - 01FFFF
08000 - 0FFFF
B
SA2
64K/32K
020000 - 02FFFF
10000 - 17FFF
B
SA3
64K/32K
030000 - 03FFFF
18000 - 1FFFF
B
SA4
64K/32K
040000 - 04FFFF
20000 - 27FFF
B
SA5
64K/32K
050000 - 05FFFF
28000 - 2FFFF
B
SA6
64K/32K
060000 - 06FFFF
30000 - 37FFF
B
SA7
64K/32K
070000 - 07FFFF
38000 - 3FFFF
B
SA8
64K/32K
080000 - 08FFFF
40000 - 47FFF
B
SA9
64K/32K
090000 - 09FFFF
48000 - 4FFFF
B
SA10
64K/32K
0A0000 - 0AFFFF
50000 - 57FFF
B
SA11
64K/32K
0B0000 - 0BFFFF
58000 - 5FFFF
B
SA12
64K/32K
0C0000 - 0CFFFF
60000 - 67FFF
B
SA13
64K/32K
0D0000 - 0DFFFF
68000 - 6FFFF
B
SA14
64K/32K
0E0000 - 0EFFFF
70000 - 77FFF
B
SA15
64K/32K
0F0000 - 0FFFFF
78000 - 7FFFF
B
SA16
64K/32K
100000 - 10FFFF
80000 - 87FFF
B
SA17
64K/32K
110000 - 11FFFF
88000 - 8FFFF
B
SA18
64K/32K
120000 - 12FFFF
90000 - 97FFF
B
SA19
64K/32K
130000 - 13FFFF
98000 - 9FFFF
B
SA20
64K/32K
140000 - 14FFFF
A0000 - A7FFF
B
SA21
64K/32K
150000 - 15FFFF
A8000 - AFFFF
B
SA22
64K/32K
160000 - 16FFFF
B0000 - B7FFF
B
SA23
64K/32K
170000 - 17FFFF
B8000 - BFFFF
A
SA24
64K/32K
180000 - 18FFFF
C0000 - C7FFF
A
SA25
64K/32K
190000 - 19FFFF
C8000 - CFFFF
A
SA26
64K/32K
1A0000 - 1AFFFF
D0000 - D7FFF
A
SA27
64K/32K
1B0000 - 1BFFFF
D8000 - DFFFF
A
SA28
64K/32K
1C0000 - 1CFFFF
E0000 - E7FFF
A
SA29
64K/32K
1D0000 - 1DFFFF
E8000 - EFFFF
A
SA30
32K/16K
1E0000 - 1E7FFF
F0000 - F3FFF
A
SA31
32K/16K
1E8000 - 1EFFFF
F4000 - F7FFF
A
SA32
8K/4K
1F0000 - 1F1FFF
F8000 - F8FFF
A
SA33
8K/4K
1F2000 - 1F3FFF
F9000 - F9FFF
A
SA34
8K/4K
1F4000 - 1F5FFF
FA000 - FAFFF
A
SA35
8K/4K
1F6000 - 1F7FFF
FB000 - FBFFF
A
SA36
8K/4K
1F8000 - 1F9FFF
FC000 - FCFFF
A
SA37
8K/4K
1FA000 - 1FBFFF
FD000 - FDFFF
A
SA38
8K/4K
1FC000 - 1FDFFF
FE000 - FEFFF
A
SA39
8K/4K
1FE000 - 1FFFFF
FF000 - FFFFF
AT49BV1604(T)/1614(T)
AT49BV1604(T)/1614(T)
DC and AC Operating Range
AT49LV16X4(T)-90
Com.
Operating
Temperature (Case)
AT49BV16X4(T)-11
0°C - 70°C
Ind.
-40°C - 85°C
VCC Power Supply
3.0V to 3.6V
2.7V to 3.3V
Operating Modes
Mode
CE
OE
WE
RESET
VPP(6)
Ai
I/O
Read
VIL
VIL
VIH
VIH
X
Ai
DOUT
Program/Erase(2)
VIL
VIH
VIL
VIH
VCC
Ai
DIN
Standby/Program Inhibit
VIH
X(1)
X
VIH
X
X
High-Z
Program Inhibit
X
X
VIH
VIH
X
Program Inhibit
X
VIL
X
VIH
X
Output Disable
X
VIH
X
VIH
X
Reset
X
X
X
VIL
X
VIL
VIL
VIH
VIH
High-Z
X
High-Z
Product Identification
Hardware
Software(5)
Notes:
A1 - A19 = VIL, A9 = VH(3), A0 = VIL
Manufacturer Code(4)
A1 - A19 = VIL, A9 = VH(3), A0 = VIH
Device Code(4)
VIH
A0 = VIL, A1 - A19 = VIL
Manufacturer Code(4)
A0 = VIH, A1 - A19 = VIL
Device Code(4)
1.
2.
3.
4.
X can be VIL or VIH.
Refer to AC programming waveforms.
VH = 12.0V ± 0.5V.
Manufacturer Code: 1FH (x8); 001FH (x16), Device Code: C0H (x8)-AT49BV16X4; 00C0H (x16)-AT49BV16X4;
C2H (x8)-AT49BV16X4T; 00C2H (x16)-AT49BV16X4T.
5. See details under “Software Product Identification Entry/Exit” on page 14.
6. For faster program/erase operations, VPP = 5V ± 10%.
DC Characteristics
Symbol
Parameter
Condition
ILI
Input Load Current
ILO
Max
Units
VIN = 0V to VCC
10
µA
Output Leakage Current
VI/O = 0V to VCC
10
µA
ISB1
VCC Standby Current CMOS
CE = VCC - 0.3V to VCC
10
µA
ISB2
VCC Standby Current TTL
CE = 2.0V to VCC
1
mA
ICC(1)
VCC Active Current
f = 5 MHz; IOUT = 0 mA
35
mA
ICCRW
VCC Read While Write Current
f = 5 MHz; IOUT = 0 mA
50
mA
VIL
Input Low Voltage
0.8
V
VIH
Input High Voltage
VOL
Output Low Voltage
IOL = 2.1 mA
IOH = -400 µA
VCCQ < 2.6V
VCCQ - 0.2 [AT49BV1604(T)]
V
VOH
Output High Voltage
IOH = -400 µA
VCCQ ≥ 2.6V
2.4 [AT49BV1604(T)]
V
2.4 (AT49BV1614)
V
2.0
IOH = -400 µA
Note:
Min
V
0.45
V
1. In the erase mode, ICC is 50 mA.
9
AC Read Characteristics
AT49LV16X4(T)-90
AT49BV16X4(T)-11
Min
Min
Symbol
Parameter
Max
Max
Units
tACC
Address to Output Delay
tCE(1)
90
110
ns
CE to Output Delay
tOE(2)
90
110
ns
OE to Output Delay
0
40
tDF(3)(4)
0
45
ns
CE or OE to Output Float
0
25
0
30
ns
tOH
Output Hold from OE, CE or Address, whichever occurred
first
0
tRO
RESET to Output Delay
0
800
ns
800
ns
AC Read Waveforms(1)(2)(3)(4)
ADDRESS
ADDRESS VALID
CE
tCE
tOE
OE
tDF
tOH
tACC
tRO
RESET
OUTPUT
Notes:
HIGH Z
OUTPUT
VALID
1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC.
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC.
3. tDF is specified from OE or CE, whichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
Input Test Waveforms and
Measurement Level
Output Test Load
tR, tF < 5 ns
Pin Capacitance
f = 1 MHz, T = 25°C(1)
Symbol
CIN
COUT
Note:
10
Typ
Max
Units
Conditions
4
6
pF
VIN = 0V
8
12
pF
VOUT = 0V
1. This parameter is characterized and is not 100% tested.
AT49BV1604(T)/1614(T)
AT49BV1604(T)/1614(T)
AC Byte/Word Load Characteristics
Symbol
Parameter
tAS, tOES
Address, OE Setup Time
tAH
Address Hold Time
tCS
Min
Max
Units
0
ns
100
ns
Chip Select Setup Time
0
ns
tCH
Chip Select Hold Time
0
ns
tWP
Write Pulse Width (WE or CE)
100
ns
tDS
Data Setup Time
100
ns
tDH, tOEH
Data, OE Hold Time
10
ns
tWPH
Write Pulse Width High
50
ns
AC Byte/Word Load Waveforms
WE Controlled
CE Controlled
11
Program Cycle Characteristics
Symbol
Parameter
Min
Typ
Max
Units
tBP
Byte/Word Programming Time
20
50
µs
tAS
Address Setup Time
0
ns
tAH
Address Hold Time
100
ns
tDS
Data Setup Time
100
ns
tDH
Data Hold Time
10
ns
tWP
Write Pulse Width
100
ns
tWPH
Write Pulse Width High
50
ns
tEC
Chip Erase Cycle Time
tSEC
Sector Erase Cycle Time
10
seconds
200
ms
Program Cycle Waveforms
PROGRAM CYCLE
OE
CE
tWP
tBP
tWPH
WE
tAS
A0 -A19
tAH
tDH
5555
5555
2AAA
5555
ADDRESS
tDS
DATA
55
AA
INPUT
DATA
A0
AA
Sector or Chip Erase Cycle Waveforms
OE
(1)
(4)
CE
tWP
tWPH
(4)
WE
tAS
A0-A19
tAH
tDH
5555
5555
5555
2AAA
Note 2
2AAA
tEC
tDS
DATA
Notes:
AA
55
80
AA
55
Note 3
WORD 0
WORD 1
WORD 2
WORD 3
WORD 4
WORD 5
1. OE must be high only when WE and CE are both low.
2. For chip erase, the address should be 5555. For sector erase, the address depends on what sector is to be erased.
(See note 3 under Command Definitions.)
3. For chip erase, the data should be 10H, and for sector erase, the data should be 30H.
4. The tWPH time between the 5th and 6th bus cycle should be a minimum of 150 ns.
12
AT49BV1604(T)/1614(T)
AT49BV1604(T)/1614(T)
Data Polling Characteristics(1)
Symbol
Parameter
Min
tDH
Data Hold Time
10
ns
tOEH
OE Hold Time
10
ns
Max
(2)
tOE
tWR
Notes:
Typ
OE to Output Delay
Write Recovery Time
1. These parameters are characterized and not 100% tested.
2. See tOE spec in “AC Read Characteristics” on page 10.
Units
ns
0
ns
Data Polling Waveforms
Toggle Bit Characteristics(1)
Symbol
Parameter
Min
tDH
Data Hold Time
10
ns
tOEH
OE Hold Time
10
ns
(2)
tOE
OE to Output Delay
tOEHP
OE High Pulse
tWR
Notes:
Write Recovery Time
1. These parameters are characterized and not 100% tested.
2. See tOE spec in “AC Read Characteristics” on page 10.
Typ
Max
Units
ns
150
ns
0
ns
Toggle Bit Waveforms(1)(2)(3)
Notes:
1. Toggling either OE or CE or both OE and CE will operate toggle bit.
The tOEHP specification must be met by the toggling input(s).
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.
13
Software Product Identification Entry(1)
Sector Lockout Enable Algorithm(1)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 80
TO
ADDRESS 5555
LOAD DATA 90
TO
ADDRESS 5555
LOAD DATA AA
TO
ADDRESS 5555
ENTER PRODUCT
IDENTIFICATION
MODE(2)(3)(5)
LOAD DATA 55
TO
ADDRESS 2AAA
Software Product Identification Exit(1)(6)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
OR
LOAD DATA F0
TO
ANY ADDRESS
LOAD DATA 40
TO
ADDRESS 5555
EXIT PRODUCT
IDENTIFICATION
MODE(4)
PAUSE 200 µs(2)
LOAD DATA F0
TO
ADDRESS 5555
Notes:
Address Format: A15 - A0 (Hex), A-1, and A15 - A19
(Don’t Care).
2. Sector Lockout feature enabled.
EXIT PRODUCT
IDENTIFICATION
MODE(4)
Notes:
1. Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex)
2.
3.
4.
5.
6.
14
1. Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex)
Address Format: A15 - A0 (Hex), A-1, and A15 - A19
(Don’t Care).
A1 - A19 = VIL.
Manufacturer Code is read for A0 = VIL;
Device Code is read for A0 = VIH.
The device does not remain in identification mode if
powered down.
The device returns to standard operation mode.
Manufacturer Code: 1FH(x8); 001FH(x16)
Device Code: C0H (x8)-AT49BV16X4;
00C0H (x16)-AT49BV16X4;
C2H (x8)-AT49BV16X4T;
00C2H (x16)-AT49BV16X4T.
Either one of the Product ID Exit commands can be used.
AT49BV1604(T)/1614(T)
AT49BV1604(T)/1614(T)
Status Bit Table
Status Bit
I/O7
Read Address In
I/O6
I/O2
Plane A
Plane B
Plane A
Plane B
Plane A
Plane B
Programming in Plane A
I/O7
DATA
TOGGLE
DATA
1
DATA
Programming in Plane B
DATA
I/O7
DATA
TOGGLE
DATA
1
Erasing in Plane A
0
DATA
TOGGLE
DATA
TOGGLE
DATA
Erasing in Plane B
DATA
0
DATA
TOGGLE
DATA
TOGGLE
Erase Suspended & Read
Erasing Sector
1
1
1
1
TOGGLE
TOGGLE
Erase Suspended & Read
Non-erasing Sector
DATA
DATA
DATA
DATA
DATA
DATA
1
1
1
1
TOGGLE
TOGGLE
Erase Suspended &
Program Non-erasing Sector
in Plane A
I/O7
DATA
TOGGLE
DATA
TOGGLE
DATA
Erase Suspended &
Program Non-erasing Sector
in Plane B
DATA
I/O7
DATA
TOGGLE
DATA
TOGGLE
While
Erase Suspended &
Program Erasing Sector
15
AT49BV1604(T)/1614(T) Ordering Information
ICC (mA)
tACC
(ns)
Active
Standby
90
25
110
25
Ordering Code
Package
0.01
AT49LV1614-90TC
48T
Commercial
(0° to 70°C)
0.01
AT49BV1604-11UI
48U
AT49BV1614-11CI
AT49BV1614-11TI
48C2
48T
Industrial
(-40° to 85°C)
90
25
0.01
AT49LV1614T-90TC
48T
Commercial
(0° to 70°C)
110
25
0.01
AT49BV1604T-11UI
48U
AT49BV1614T-11CI
AT49BV1614T-11TI
48C2
48T
Industrial
(-40° to 85°C)
Package Type
48C2
48-ball, Plastic Chip-size Ball Grid Array Package (CBGA)
48T
48-lead, Thin Small Outline Package (TSOP)
48U
48-ball, Micro Ball Grid Array Package (µBGA)
16
Operation Range
AT49BV1604(T)/1614(T)
AT49BV1604(T)/1614(T)
Packaging Information
48C2, 48-ball, Plastic Chip-size Ball Grid Array
Package (CBGA)
Dimensions in Millimeters and (Inches)*
48T, 48-lead, Plastic Thin Small Outline Package
(TSOP) Dimensions in Millimeters and (Inches)*
JEDEC OUTLINE MO-142 DD
8.2 (0.322)
7.8 (0.307)
10.2 (0.401)
9.8 (0.386)
1.20 (0.047)
1.00 (0.039)
2.12 (0.083)
1.86 (0.073)
0.30 (0.012)
4.0 (0.157)
6
5
4
3
2
1
2.32 (0.091)
2.06 (0.081)
A
B
C
D
5.6 (0.220)
E
F
G
H
0.40 (0.016)
DIA BALL TYP
0.80 (0.031) BSC
NON-ACCUMULATIVE
*Controlling dimension: millimeters
*Controlling dimension: millimeters
48U, 48-ball, Micro Ball Grid Array Package (µBGA)
Dimensions in Millimeters
6.97
6.63
8.60
8.36
0.30
0.15 MIN.
1.03
0.82
5.25
8
7
6
5
4
3
2
0.73
0.63
1
A
B
C
D
3.75
E
F
0.75 TYP
NON-ACCUMULATIVE
0.35 DIA TYP
17
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© Atmel Corporation 2000.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for
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