BF1009SW Silicon N-Channel MOSFET Tetrode 3 For low noise, high gain controlled 4 input stages up to 1GHz Operating voltage 9V Integrated bias network Drain AGC HF Input G2 G1 2 HF Output + DC GND 1 VPS05605 EHA07215 ESD: Electrostatic discharge sensitive device, observe handling precaution! Type Marking BF1009SW JLs Pin Configuration 1=D 2=S 3 = G1 Package 4 = G2 SOT343 Maximum Ratings Parameter Symbol Drain-source voltage VDS 12 V Continuos drain current ID 25 mA Gate 1/gate 2 peak source current ±IG1/2SM 10 Gate 1 (external biasing) +VG1SE 3 Total power dissipation, TS 76 °C Ptot 200 Storage temperature Tstg -55 ... 150 Channel temperature Tch 150 Value Unit V mW °C Thermal Resistance Channel - soldering point1) Rthchs 280 K/W 1For calculation of R thJA please refer to Application Note Thermal Resistance Note: It is not recommended to apply external DC-voltage on Gate 1 in active mode. 1 Jun-28-2001 BF1009SW Electrical Characteristics at T A = 25°C, unless otherwise specified. Symbol Values Parameter Unit min. typ. max. V(BR)DS 16 - - +V (BR)G1SS 8 - 12 ±V (BR)G2SS 10 - 16 +I G1SS - - 60 µA ±I G2SS - - 50 nA Drain current I DSS - - 500 µA VDS = 9 V, V G1S = 0 , V G2S = 6 V Operating current (selfbiased) I DSO 10 14 19 mA - 0.9 - V 26 30 - mS Cg1ss - 2.1 2.7 pF Cdss - 0.9 - Gps 18 22 - F800 - 1.4 - Gps 40 50 - DC characteristics Drain-source breakdown voltage V I D = 300 µA, V G1S = 0 V, V G2S = 0 V Gate 1 - source breakdown voltage +I G1S = 10 mA, VG2S = 0 V, V DS = 0 V Gate 2 source breakdown voltage ±I G2S = 10 mA, VG1S = 0 V, V DS = 0 V Gate 1 source current VG1S = 6 V, V G2S = 0 V Gate 2 source leakage current ±V G2S = 8 V, VG1S = 0 V, V DS = 0 V VDS = 9 V, V G2S = 6 V Gate 2-source pinch-off voltage VG2S(p) VDS = 9 V, ID = 100 µA AC characteristics Forward transconductance (self biased) gfs VDS = 9 V, VG2S = 6 V Gate 1-input capacitance (self biased) VDS = 9 V, VG2S = 6 V, f = 1 MHz Output capacitance (self biased) VDS = 9 V, VG2S = 6 V, f = 1 MHz Power gain (self biased) dB VDS = 9 V, VG2S = 6 V, f = 800 MHz Noise figure (self biased) VDS = 9 V, VG2S = 6 V, f = 800 MHz Gain control range (self biased) VDS = 9 V, VG2S = 6 ... 0V, f = 800 MHz 2 Jun-28-2001 BF1009SW Total power dissipation Ptot = f (TS ) Drain current ID = f (VG2S) 300 15 mA mW 12 200 10 ID P tot 11 9 8 150 7 6 100 5 4 3 50 2 1 0 0 20 40 60 80 100 120 °C 0 0.0 150 1.0 2.0 3.0 4.0 V TS VG2S Insertion power gain Forward transfer admittance | S21 | 2 = f (VG2S ) | Y 21 | = f (V G2S) 10 28 mS 0 24 -5 22 -10 20 |Y21| | S21 |2 dB -15 18 -20 16 -25 14 -30 12 -35 10 -40 8 -45 6 -50 4 -55 2 -60 0.0 6.0 1.0 2.0 3.0 4.0 V 0 0.0 6.0 VG2S 1.0 2.0 3.0 4.0 V 6.0 VG2S 3 Jun-28-2001 BF1009SW f = 200MHz f = 200MHz 3.0 pF 3.0 pF 2.4 2.4 2.2 2.2 Cdss Output capacitance C dss = f (V G2S) Cg1ss Gate 1 input capacitance Cg1ss = f (Vg2s) 2.0 1.8 2.0 1.8 1.6 1.6 1.4 1.4 1.2 1.2 1.0 1.0 0.8 0.8 0.6 0.6 0.4 0.4 0.2 0.2 0.0 0.0 1.0 2.0 3.0 4.0 V 0.0 0.0 6.0 VG2S 1.0 2.0 3.0 4.0 V 6.0 VG2S 4 Jun-28-2001