ETC CDCVF2505PW

CDCVF2505
3.3-V CLOCK PHASE-LOCK LOOP CLOCK DRIVER
SCAS640C – JULY 2000 – REVISED JUNE 2002
D
D
D
D
D
D
D
D
D
D
D
D
Phase-Lock Loop Clock Driver for
Synchronous DRAM and General-Purpose
Applications
Spread Spectrum Clock Compatible
Operating Frequency: 24 MHz to 200 MHz
Low Jitter (Cycle-cycle): <|150 ps| Over the
Range 66 MHz–200 MHz
Distributes One Clock Input to One Bank of
Five Outputs (CLKOUT Is Used to Tune the
Input-Output Delay)
Three-States Outputs When There Is no
Input Clock
Operates From Single 3.3-V Supply
Available in 8-Pin TSSOP and 8-Pin SOIC
Packages
Consumes Less Than 100-µA (Typically) in
Power Down Mode
Internal Feedback Loop Is Used to
Synchronize the Outputs to the Input Clock
25-Ω On-Chip Series Damping Resistors
Integrated RC PLL Loop Filter Eliminates
the Need for External Components
D OR PW PACKAGE
(TOP VIEW)
CLKIN
1Y1
1Y0
GND
1
8
2
7
3
6
4
5
CLKOUT
1Y3
VDD 3.3 V
1Y2
description
The CDCVF2505 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL
to precisely align, in both frequency and phase, the output clocks (1Y[0–3] and CLKOUT) to the input clock
signal (CLKIN). The CDCVF2505 operates at 3.3 V. It also provides integrated series-damping resistors that
make it ideal for driving point-to-point loads.
One bank of five outputs provides low-skew, low-jitter copies of CLKIN. Output duty cycles are adjusted to 50
percent, independent of duty cycle at CLKIN. The device automatically goes in power-down mode when no input
signal is applied to CLKIN.
Unlike many products containing PLLs, the CDCVF2505 does not require an external RC network. The loop
filter for the PLLs is included on-chip, minimizing component count, space, and cost.
Because it is based on the PLL circuitry, the CDCVF2505 requires a stabilization time to achieve phase lock
of the feedback signal to the reference signal. This stabilization is required following power up and application
of a fixed-frequency, fixed-phase signal at CLKIN, and following any changes to the PLL reference.
The CDCVF2505 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
CDCVF2505
3.3-V CLOCK PHASE-LOCK LOOP CLOCK DRIVER
SCAS640C – JULY 2000 – REVISED JUNE 2002
FUNCTION TABLE
OUTPUTS
INPUT
CLKIN
1Y (0:3)
CLKOUT
L
H
<10 MHz†
L
H
Z
L
H
Z
† Typically, below 2 MHz the device goes in power-down mode in
which the PLL is turned off and the outputs enter into Hi-Z mode. If
a >10 MHz signal is applied at CLKIN the PLL turns on, reacquires
lock and stabilizes after approximately 100 µs. The outputs will then
be enabled.
functional block diagram
8
CLKIN
1
PLL
25 Ω
3
25 Ω
2
Power Down
25 Ω
5
25 Ω
7
25 Ω
Edge Detect
Typical < 10 MHz
2
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CLKOUT
1Y0
1Y1
1Y2
1Y3
CDCVF2505
3.3-V CLOCK PHASE-LOCK LOOP CLOCK DRIVER
SCAS640C – JULY 2000 – REVISED JUNE 2002
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
1Y[0–3]
2, 3, 5, 7
O
Clock outputs. These outputs are low-skew copies of CLKIN. Each output has an integrated 25-Ω
series damping resistor.
CLKIN
1
I
Clock input. CLKIN provides the clock signal to be distributed by the CDCVF2505 clock driver.
CLKIN is used to provide the reference signal to the integrated PLL that generates the clock output
signals. CLKIN must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once
the circuit is powered up and a valid signal is applied, a stabilization time (100 µs) is required for the
PLL to phase lock the feedback signal to CLKIN.
CLKOUT
8
O
Feedback output. CLKOUT completes the internal feedback loop of the PLL. This connection is
made inside the chip and an external feedback loop should NOT be connected. CLKOUT can be
loaded with a capacitor to achieve zero delay between CLKIN and the Y outputs.
GND
4
Power
Ground
VDD3.3V
6
Power
3.3-V Supply
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.3 V
Input voltage range, VI (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V
Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Output clamp current, IOK (VO < 0 or VO > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous total output current, IO (VO = 0 to VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165.5°C/W
PWR package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230.5°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This value is limited to 4.3 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions
Supply voltage, VDD
High-level input voltage, VIH
MIN
NOM
MAX
3
3.3
3.6
0.7 VDD
Low-level input voltage, VIL
0
High-level output current, IOH
Low-level output current, IOL
Operating free-air temperature, TA
–40
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V
V
0.3 VDD
Input voltage, VI
UNIT
V
VDD
–12
mA
V
12
mA
85
°C
3
CDCVF2505
3.3-V CLOCK PHASE-LOCK LOOP CLOCK DRIVER
SCAS640C – JULY 2000 – REVISED JUNE 2002
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
MIN
fclk
Clock frequency
NOM
24
Input clock duty cycle
40%
50%
Stabilization time (see Note 4)
MAX
UNIT
200
MHz
60%
100
µs
NOTE 4: Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be
obtained, a fixed-frequency, fixed-phase reference signal must be present at CLKIN. Until phase lock is obtained, the specifications for
propagation delay, skew, and jitter parameters given in the switching characteristics table are not applicable. This parameter does not
apply for input modulation under SSC application.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VOH
VOL
IOH
TEST CONDITIONS
Input voltage
II = –18 mA
IOH = –100 µA
High-level output voltage
Low-level output voltage
High level output current
High-level
VDD
3V
MIN to MAX
IOH = –12 mA
IOH = –6 mA
3V
VDD–0.2
2.1
3V
2.4
IOL = 100 µA
IOL = 12 mA
MIN to MAX
MAX
UNIT
–1.2
V
V
0.2
3V
0.8
3V
0.55
VO = 1.65 V
VO = 2 V
3.3 V
3.3 V
40
4.2
3V
3V
Low level output current
Low-level
II
Ci
Input current
VO = 1.65 V
VI = 0 V or VDD
Input capacitance
VI = 0 V or VDD
3.3 V
Co
Output
capacitance
Out
ut ca
acitance
VI = 0 V or VDD
33V
3.3
CLKOUT
TYP†
IOL = 6 mA
VO = 1 V
IOL
Yn
MIN
V
–27
–36
27
±5
µA
pF
2.8
pF
F
5.2
† All typical values are at respective nominal VDD and 25°C.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 25 pF, VDD = 3.3 V ± 0.3 V (see Note 5)
PARAMETER
TEST CONDITIOINS
tpd
tsk(o)
Propagation delay (normalized (see Figure 3)
CLKIN to Yn, f= 66 MHz to 200 MHz
Output skew (see Note 6)
Yn to Yn
tc(jit_cc)
(jit
)
Jitter (cycle to cycle) (see Figure 5)
odc
Output duty cycle (see Figure 4)
TYP†
–150
MAX
UNIT
150
ps
150
ps
f = 66 MHz to 200 MHz
70
150
f = 24 MHz to 50 MHz
200
400
f = 24 MHz to 200 MHz at 50% VDD
tr
Rise time
VO = 0.4 V to 2 V
tf
Fall time
VO = 2 V to 0.4 V
† All typical values are at respective nominal VDD and 25°C.
NOTE 5: The tsk(o) specification is only valid for equal loading of all outputs.
4
MIN
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ps
45%
55%
0.5
2.0
ns
0.5
2.0
ns
CDCVF2505
3.3-V CLOCK PHASE-LOCK LOOP CLOCK DRIVER
SCAS640C – JULY 2000 – REVISED JUNE 2002
ESD information
ESD MODELS
LIMIT
Human Body Model (HBM)
2.0 kV
Machine Model (MM)
300 V
Charge Device Model (CDM)
1.0 kV
thermal information
THERMAL AIR FLOW (CFM)
PIN SOIC
CDCVF2505 8
8-PIN
0
150
250
500
UNIT
RθJA
High K
97
87
83
77
°C/W
RθJA
Low K
165
126
113
97
°C/W
RθJC
High K
39
°C/W
RθJC
Low K
42
°C/W
THERMAL AIR FLOW (CFM)
CDCVF2505 8-PIN
8 PIN TSSOP
0
150
250
500
UNIT
RθJA
High K
149
142
138
132
°C/W
RθJA
Low K
230
185
170
150
°C/W
RθJC
High K
65
°C/W
RθJC
Low K
69
°C/W
TYPICAL CHARACTERISTICS
tpd, PROPAGATION DELAY TIME
vs
DELTA LOAD (TYPICAL VALUES @ 3.3 V, 25°C)
tpd, PROPAGATION DELAY TIME
vs
FREQUENCY (TYPICAL VALUES @ 3.3 V, 25°C)
500
1400
Load: CLKOUT = 12 pF || 500 Ω,
Yn = 25 pF || 500 Ω
t pd – Propagation Delay Time – ps
t pd– Propagation Delay Time – ps
1050
700
350
0
–350
–700
Load: CLKOUT = 12 pF || 500 Ω,
Yn = 25 pF || 500 Ω
400
300
200
100
–1050
–1400
–30
–20
–10
0
10
Delta Load – pF
20
30
0
25
50
75
100
125
150
f – Frequency – MHz
175
200
Figure 2
Figure 1
NOTE: Delta Load = CLKOUT Load – Yn Load
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CDCVF2505
3.3-V CLOCK PHASE-LOCK LOOP CLOCK DRIVER
SCAS640C – JULY 2000 – REVISED JUNE 2002
TYPICAL CHARACTERISTICS
tpd, TYPICAL PROPAGATION DELAY TIME
vs
FREQUENCY(TUNED FOR MINIMUM DELAY)
DUTY CYCLE
vs
FREQUENCY
55
Load: CLKOUT = 12 pF || 500 Ω,
Yn = 25 pF || 500 Ω
Load: CLKOUT = 21 pF || 500 Ω,
Yn = 25 pF || 500 Ω
100
52.5
Duty Cycle – %
t pd – Propagation Delay Time – ps
150
50
0
50
–50
47.5
–100
45
25
–150
0
50
150
100
200
50
75
100
125
150
f – Frequency – MHz
f – Frequency – MHz
Figure 3
ICC, SUPPLY CURRENT
vs
FREQUENCY
500
120
Typical Values @ 3.3 V,
TA = 25°C
Worst Case @ VCC = 3.6 V, TA = 85°C,
Load: Y and CLKOUT = 25 pF || 500 Ω
100
400
I CC – Supply Current – mA
t c(jit_CC) – Cycle–Cycle Jitter – ps
200
Figure 4
CYCLE–CYCLE JITTER
vs
FREQUENCY
300
200
100
80
60
40
20
0
25
50
75
100
125
150
f – Frequency – MHz
175
200
0
0
20
Figure 5
6
175
40
60 80 100 120 140 160 180 200
f – Frequency – MHz
Figure 6
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CDCVF2505
3.3-V CLOCK PHASE-LOCK LOOP CLOCK DRIVER
SCAS640C – JULY 2000 – REVISED JUNE 2002
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
500 Ω
Yn = 25 pF || 500 Ω
CLKOUT = 12 pF || 500 Ω
Figure 7. Test Load Circuit
3V
50% VDD
CLKIN
0V
tpd
1Y0 – 1Y3
2V
0.4 V
50% VDD
tr
VOH
2V
0.4 V
VOL
tf
Figure 8. Voltage Threshold for Measurements, Propagation Delay (tpd)
Any Y
50 % VDD
tsk(o)
Any Y
50 % VDD
Figure 9. Output Skew
tc1
tc2
tc(jit_CC) = tc1 – tc2
Figure 10. Cycle-to-Cycle Jitter
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CDCVF2505
3.3-V CLOCK PHASE-LOCK LOOP CLOCK DRIVER
SCAS640C – JULY 2000 – REVISED JUNE 2002
MECHANICAL DATA
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0.050 (1,27)
0.020 (0,51)
0.014 (0,35)
14
0.010 (0,25) M
8
0.008 (0,20) NOM
0.244 (6,20)
0.228 (5,80)
0.157 (4,00)
0.150 (3,81)
Gage Plane
0.010 (0,25)
1
7
0°– 8°
A
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.069 (1,75) MAX
0.010 (0,25)
0.004 (0,10)
PINS **
0.004 (0,10)
8
14
16
A MAX
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
A MIN
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
DIM
4040047 / D 10/96
NOTES: A.
B.
C.
D.
8
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
Falls within JEDEC MS-012
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CDCVF2505
3.3-V CLOCK PHASE-LOCK LOOP CLOCK DRIVER
SCAS640C – JULY 2000 – REVISED JUNE 2002
MECHANICAL DATA
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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9
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Copyright  2002, Texas Instruments Incorporated