ETC CS5160GD16

The CS5160 is a 5–bit synchronous dual N–Channel buck
controllers designed to provide unprecedented transient response for
today’s demanding high–density, high–speed logic. It operates using a
proprietary control method which allows a 100 ns response time to
load transients. The CS5160 is designed to operate over a 9–16 V
range (VCC) using 12 V to power the IC and 5.0 V as the main supply
for conversion.
The CS5160 is specifically designed to power Pentium III
processors and other high performance core logic. They include the
following features: on board 5–bit DAC, short circuit protection, 1.0%
output tolerance, VCC monitor, and programmable Soft Start
capability. The CS5160 is available in a 16 pin surface mount package.
Features
Dual N–Channel Design
Excess of 1.0 MHz Operation
100 ns Transient Response
5–Bit DAC
Backward Compatible with CS515X Family
30 ns Gate Rise/Fall Times
0.8% DAC Accuracy for the 01111 DAC Code
5.0 V & 12 V Operation
Remote Sense
Programmable Soft Start
Lossless Short Circuit Protection
VCC Monitor
V2 Control Topology
Overvoltage Protection
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 Semiconductor Components Industries, LLC, 2001
April, 2001 – Rev. 5
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MARKING
DIAGRAMS
16
SOIC–16
D SUFFIX
CASE 751B
CS5160
AWLYWW
1
A
WL, L
YY, Y
WW, W
= Assembly Location
= Wafer Lot
= Year
= Work Week
PIN CONNECTIONS
VID0
VID1
VID2
VID3
SS
VID4
COFF
VFFB
VFB
COMP
LGnd
VCC1
VGATE(L)
PGnd
VGATE(H)
VCC2
1
ORDERING INFORMATION
Device
1
Package
Shipping
CS5160GD16
SO–16
48 Units/Rail
CS5160GDR16
SO–16
2500 Tape & Reel
Publication Order Number:
CS5160/D
CS5160
5V
12 V
1.0 µH
1200 µF/10 V × 6.0
Sanyo GX
0.1 µF
VCC1
SILICONIX
SUD50NO3–10P
VCC2
VGATE(H)
1.8 µH
VID0
VID0
VID1
VID1
VID2
VID2
VID3
VID3
VID4
VID4
VOUT
SILICONIX
SUD50NO3–07
VGATE(L)
CS5160
MBRS140T3
COFF
PGnd
680 pF
SS
VFB
0.1 µF
COMP
LGnd
1200 µF/10 V × 8.0
Sanyo GX
VFFB
0.33 µF
1.3 k
Figure 1. Application Diagram, 5.0 V to 1.5 V/15 A Core Logic Converter with 12 V Bias
ABSOLUTE MAXIMUM RATINGS*
Rating
Value
Unit
0 to 150
°C
230 peak
°C
–65 to +150
°C
2.0
kV
Operating Junction Temperature, TJ
Lead Temperature Soldering:
Reflow: (SMD styles only) (Note 1.)
Storage Temperature Range, TS
ESD Susceptibility (Human Body Model)
1. 60 second maximum above 183°C.
*The maximum package power dissipation must be observed.
ABSOLUTE MAXIMUM RATINGS
Pin Name
Max Operating Voltage
Max Current
VCC1
16 V/–0.3 V
100 mA DC/1.5 A peak
VCC2
18 V/–0.3 V
100 mA DC/1.5 A peak
SS
6.0 V/–0.3 V
–100 µA
COMP
6.0 V/–0.3 V
200 µA
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CS5160
ABSOLUTE MAXIMUM RATINGS (continued)
Pin Name
Max Operating Voltage
Max Current
VFB
6.0 V/–0.3 V
–0.2 µA
COFF
6.0 V/–0.3 V
–0.2 µA
VFFB
6.0 V/–0.3 V
–0.2 µA
VID0 – VID4
6.0 V/–0.3 V
–50 µA
VGATE(H)
18 V/–0.3 V
100 mA DC/1.5 A peak
VGATE(L)
16 V/–0.3 V
100 mA DC/1.5 A peak
LGnd
0V
25 mA
PGnd
0V
100 mA DC/1.5 A peak
ELECTRICAL CHARACTERISTICS (0°C < TA < +70°C; 0°C < TJ < +85°C; 9.5 V < VCC1 < 14 V; 5.0 V < VCC2 < 16 V; DAC
Code: VID4 = VID2 = VID1 = VID0 =1; VID3 = 0; CVGATE(L) and CVGATE(H) = 1.0 nF; COFF = 330 pF; CSS = 0.1 µF, unless otherwise specified.)
Test Conditions
Characteristic
Min
Typ
Max
Unit
Error Amplifier
VFB Bias Current
VFB = 0 V
–
0.3
1.0
µA
Open Loop Gain
1.25 V < VCOMP , 4.0 V; CCOMP = 0.1 µF;
Note 2.
–
80
–
dB
Unity Gain Bandwidth
CCOMP = 0.1 µF; Note 2.
–
50
–
kHz
COMP SINK Current
VCOMP = 1.5 V; VFB = 3.0 V; VSS > 2.0 V
30
60
120
µA
COMP SOURCE Current
VCOMP = 1.2 V; VFB = 2.7 V; VSS = 5.0 V
15
30
60
µA
COMP CLAMP Current
VCOMP = 0 V; VFB = 2.7 V
0.4
1.0
1.6
mA
COMP High Voltage
VFB = 2.7 V; VSS = 5.0 V
4.0
4.3
5.0
V
COMP Low Voltage
VFB = 3.0 V
–
1.00
1.15
V
PSRR
8.0 V < VCC1 < 14 V @ 1.0 kHz;
CCOMP = 0.1 µF; Note 2.
–
70
–
dB
–
33
–
mmho
Transconductance
–
VCC1 Monitor
Start Threshold
Output switching
8.60
8.95
9.30
V
Stop Threshold
Output not switching
8.45
8.80
9.15
V
Hysteresis
Start–Stop
–
150
–
mV
Soft Start (SS)
Charge Time
–
1.6
3.3
5.0
ms
Pulse Period
–
25
100
200
ms
Duty Cycle
(Charge Time /Pulse Period) × 100
1.0
3.3
6.0
%
COMP Clamp Voltage
VFB = 0 V; VSS = 0
0.50
0.95
1.10
V
VFFB SS Fault Disable
VGATE(H) = Low; VGATE(L) = Low
0.9
1.0
1.1
V
–
2.5
3.0
V
High Threshold
–
2. Guaranteed by design, not 100% tested in production.
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CS5160
ELECTRICAL CHARACTERISTICS (continued) (0°C < TA < +70°C; 0°C < TJ < +85°C; 9.5 V < VCC1 < 14 V; 5.0 V < VCC2 < 16 V; DAC
Code: VID4 = VID2 = VID1 = VID0 =1; VID3 = 0; CVGATE(L) and CVGATE(H) = 1.0 nF; COFF = 330 pF; CSS = 0.1 µF, unless otherwise specified.)
Characteristic
Test Conditions
Min
Typ
Max
Unit
Transient Response
VFFB = 0 to 5.0 V to VGATE(H) = 9.0 V to 1.0 V;
VCC1 = VCC2 = 12 V
–
100
125
ns
VFFB Bias Current
VFFB = 0 V
–
0.3
–
µA
PWM Comparator
DAC
Input Threshold
VID0, VID1, VID2, VID3, VID4
1.00
1.25
2.40
V
Input Pull Up Resistance
VID0, VID1, VID2, VID3, VID4
25
50
110
kΩ
4.85
5.00
5.15
V
–
–
1.0
%
Pull Up Voltage
–
Accuracy (all codes except 11111,
10110, 10101, 10100, 10011,
10010, 10001, 10000, and 01111)
Measure VFB = COMP,
CS5160: 25°C ≤ TJ ≤ 85°C
VID4
VID3
VID2
VID1
VID0
0
1
1
1
1
–
1.2896
1.3000
1.3104
V
0
1
1
1
0
–
1.3365
1.3500
1.3635
V
0
1
1
0
1
–
1.3860
1.4000
1.4140
V
0
1
1
0
0
–
1.4355
1.4500
1.4645
V
0
1
0
1
1
–
1.4850
1.5000
1.5150
V
0
1
0
1
0
–
1.5345
1.5500
1.5655
V
0
1
0
0
1
–
1.5840
1.6000
1.6160
V
0
1
0
0
0
–
1.6335
1.6500
1.6665
V
0
0
1
1
1
–
1.6830
1.7000
1.7170
V
0
0
1
1
0
–
1.7325
1.7500
1.7675
V
0
0
1
0
1
–
1.7820
1.8000
1.8180
V
0
0
1
0
0
–
1.8315
1.8500
1.8685
V
0
0
0
1
1
–
1.8810
1.9000
1.9190
V
0
0
0
1
0
–
1.9305
1.9500
1.9695
V
0
0
0
0
1
–
1.9800
2.0000
2.0200
V
0
0
0
0
0
–
2.0295
2.0500
2.0705
V
1
1
1
1
1
–
1.2191
1.2440
1.2689
V
1
1
1
1
0
–
2.0790
2.1000
2.1210
V
1
1
1
0
1
–
2.1780
2.2000
2.2220
V
1
1
1
0
0
–
2.2770
2.3000
2.3230
V
1
1
0
1
1
–
2.3760
2.4000
2.4240
V
1
1
0
1
0
–
2.4750
2.5000
2.5250
V
1
1
0
0
1
–
2.5740
2.6000
2.6260
V
1
1
0
0
0
–
2.6730
2.7000
2.7270
V
1
0
1
1
1
–
2.7720
2.8000
2.8280
V
1
0
1
1
0
–
2.8420
2.9000
2.9580
V
1
0
1
0
1
–
2.9400
3.0000
3.0600
V
1
0
1
0
0
–
3.0380
3.1000
3.1620
V
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CS5160
ELECTRICAL CHARACTERISTICS (continued) (0°C < TA < +70°C; 0°C < TJ < +85°C; 9.5 V < VCC1 < 14 V; 5.0 V < VCC2 < 16 V; DAC
Code: VID4 = VID2 = VID1 = VID0 =1; VID3 = 0; CVGATE(L) and CVGATE(H) = 1.0 nF; COFF = 330 pF; CSS = 0.1 µF, unless otherwise specified.)
Characteristic
Test Conditions
Min
Typ
Max
Unit
DAC
1
0
0
1
1
–
3.1360
3.2000
3.2640
V
1
0
0
1
0
–
3.2340
3.3000
3.3660
V
1
0
0
0
1
–
3.3320
3.4000
3.4680
V
1
0
0
0
0
–
3.4300
3.5000
3.5700
V
VGATE(H) and VGATE(L)
Out SOURCE Sat at 100 mA
Measure VCC1 – VGATE(L); VCC2 – VGATE(H)
–
1.2
2.0
V
Out SINK Sat at 100 mA
Measure VGATE(H) – VPGnd; VGATE(L) – VPGnd
–
1.0
1.5
V
Out Rise Time
1.0 V < VGATE(H) < 9.0 V; 1.0 V < VGATE(L)
< 9.0 V; VCC1 = VCC2 = 12 V
–
30
50
ns
Out Fall Time
9.0 V < VGATE(H) > 1.0 V; 9.0 V > VGATE(L)
> 1.0 V; VCC1 = VCC2 = 12 V
–
30
50
ns
Delay VGATE(H) to VGATE(L)
VGATE(H) falling to 1.0 V; VCC1 = VCC2 = 8.0 V
CVGATE(H) = 3.3 nF; VGATE(L) rising to 1.0 V
45
70
95
ns
Delay VGATE(L) to VGATE(H)
VGATE(L) falling to 1.0 V; VCC1 = VCC2 = 8.0 V
CVGATE(H) = 3.3 nF; VGATE(H) rising to 1.0 V
45
70
95
ns
VGATE(H), VGATE(L) Resistance
Resistor to LGnd. Note 3.
20
50
100
kΩ
VGATE(H), VGATE(L) Schottky
LGnd to VGATE(H) @ 10 mA;
LGnd to VGATE(L) @ 10 mA
–
600
800
mV
Supply Current
ICC1 No Switching
–
–
9.5
14.5
mA
ICC2 No Switching
–
–
2.0
3.5
mA
Operating ICC1
VFB = COMP = VFFB
–
9.0
14
mA
Operating ICC2
VFB = COMP = VFFB
–
2.5
5.5
mA
COFF
Normal Charge Time
VFFB = 1.5 V; VSS = 5.0 V
1.0
1.6
2.2
µs
Discharge Current
COFF to 5.0 V; VFB > 1.0 V
5.0
–
–
mA
Time Out Time
VFB = VCOMP; VFFB = 2.0 V;
Record VGATE(H) Pulse High Duration
10
30
65
µs
Fault Mode Duty Cycle
VFFB = 0V
35
50
70
%
Time Out Timer
3. Guaranteed by design, not 100% tested in production.
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CS5160
PACKAGE PIN DESCRIPTION
PACKAGE PIN #
PIN SYMBOL
FUNCTION
1, 2, 3, 4, 6
VID0–VID4
Voltage ID DAC input pins. These pins are internally pulled
up to 5.0 V providing logic ones if left open. VID4 selects the
DAC range. When VID4 is High (logic one), the DAC range
is 2.10 V to 3.50 V with 100 mV increments. When VID4 is
Low (logic zero), the DAC range is 1.30 V to 2.05 V with
50 mV increments. VID0 – VID4 select the desired DAC output voltage. Leaving all 5 DAC input pins open results in a
DAC output voltage of 1.2440 V, allowing for adjustable
output voltage, using a traditional resistor divider.
5
SS
Soft Start Pin. A capacitor from this pin to LGnd in conjunction with internal 60 µA current source provides Soft Start
function for the controller. This pin disables fault detect function during Soft Start. When a fault is detected, the Soft Start
capacitor is slowly discharged by internal 2.0 µA current
source setting the time out before trying to restart the IC.
Charge/discharge current ratio of 30 sets the duty cycle for
the IC when the regulator output is shorted.
7
COFF
A capacitor from this pin to ground sets the time duration for
the on board one shot, which is used for the constant off time
architecture.
8
VFFB
Fast feedback connection to the PWM comparator. This pin
is connected to the regulator output. The inner feedback loop
terminates on time.
9
VCC2
Boosted power for the high side gate driver.
10
VGATE(H)
High FET driver pin capable of 1.5 A peak switching current.
Internal circuit prevents VGATE(H) and VGATE(L) from being in
high state simultaneously.
11
PGnd
High current ground for the IC. The MOSFET drivers are
referenced to this pin. Input capacitor ground and the source
of lower FET should be tied to this pin.
12
VGATE(L)
Low FET driver pin capable of 1.5 A peak switching current.
13
VCC1
Input power for the IC and low side gate driver.
14
LGnd
Signal ground for the IC. All control circuits are referenced to
this pin.
15
COMP
Error amplifier compensation pin. A capacitor to ground
should be provided externally to compensate the amplifier.
16
VFB
16 Lead SO Narrow
Error amplifier DC feedback input. This is the master voltage
feedback which sets the output voltage. This pin can be connected directly to the output or a remote sense trace.
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6
CS5160
VCC2
VCC1
–
VCC1 Monitor
Comparator
5.0 V
+
–
9.05 V
8.90V
VGATE(H)
SS Low
Comparator
R
60 µA
Q
S
FAULT
Latch
0.7 V
SS
+
2.0 µA
VID2
PGnd
FAULT
VCC1
–
VID0
VID1
SS High
Comparator
FAULT
Q
+
5 BIT
DAC
VID3
Error
Amplifier
+
–
VGATE(L)
2.5 V
PGnd
PWM
Comparator
VID4
–
VFB
Maximum
On–Time
Timeout
+
Slow Feedback
Normal
Off–Time
Timeout
Extended
Off–Time
Timeout
COMP
VFFB
Fast Feedback
–
+
LGnd
1.0 V
R
Q
S
Q
PMW
Latch
GATE(H) = ON
GATE(H) = OFF
COFF
One Shot
R
Off–Time
Timeout
COFF
Q
S
VFFB Low
Comparator
Time–Out
Timer
(30 µs)
Edge Triggered
Figure 2. Block Diagram
APPLICATIONS INFORMATION
THEORY OF OPERATION
PWM
Comparator
+
VGATE(H)
C
VGATE(L)
V2 Control Method
The V2 method of control uses a ramp signal that is
generated by the ESR of the output capacitors. This ramp is
proportional to the AC current through the main inductor
and is offset by the value of the DC output voltage. This
control scheme inherently compensates for variation in
either line or load conditions, since the ramp signal is
generated from the output voltage itself. This control
scheme differs from traditional techniques such as voltage
mode, which generates an artificial ramp, and current mode,
which generates a ramp from inductor current.
–
Ramp
Signal
VFFB
VFB
Error
Amplifier
COMP
Error
Signal
Output
Voltage
Feedback
–
E
+
Figure 3. V2 Control Diagram
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7
Reference
Voltage
CS5160
The V2 control method is illustrated in Figure 3. The
output voltage is used to generate both the error signal and
the ramp signal. Since the ramp signal is simply the output
voltage, it is affected by any change in the output regardless
of the origin of that change. The ramp signal also contains
the DC portion of the output voltage, which allows the
control circuit to drive the main switch to 0% or 100% duty
cycle as required.
A change in line voltage changes the current ramp in the
inductor, affecting the ramp signal, which causes the V2
control scheme to compensate the duty cycle. Since the
change in inductor current modifies the ramp signal, as in
current mode control, the V2 control scheme has the same
advantages in line transient response.
A change in load current will have an affect on the output
voltage, altering the ramp signal. A load step immediately
changes the state of the comparator output, which controls
the main switch. Load transient response is determined only
by the comparator response time and the transition speed of
the main switch. The reaction time to an output load step has
no relation to the crossover frequency of the error signal
loop, as in traditional control methods.
The error signal loop can have a low crossover frequency,
since transient response is handled by the ramp signal loop.
The main purpose of this ‘slow’ feedback loop is to provide
DC accuracy. Noise immunity is significantly improved,
since the error amplifier bandwidth can be rolled off at a low
frequency. Enhanced noise immunity improves remote
sensing of the output voltage, since the noise associated with
long feedback traces can be effectively filtered.
Line and load regulation are drastically improved because
there are two independent voltage loops. A voltage mode
controller relies on a change in the error signal to
compensate for a deviation in either line or load voltage.
This change in the error signal causes the output voltage to
change corresponding to the gain of the error amplifier,
which is normally specified as line and load regulation. A
current mode controller maintains fixed error signal under
deviation in the line voltage, since the slope of the ramp
signal changes, but still relies on a change in the error signal
for a deviation in load. The V2 method of control maintains
a fixed error signal for both line and load variation, since the
ramp signal is affected by both line and load.
Constant off time provides a number of advantages.
Switch duty cycle can be adjusted from 0 to 100% on a pulse
by pulse basis when responding to transient conditions. Both
0% and 100% duty cycle operation can be maintained for
extended periods of time in response to load or line
transients. PWM slope compensation to avoid
sub–harmonic oscillations at high duty cycles is avoided.
Switch on time is limited by an internal 30 µs timer,
minimizing stress to the power components.
Programmable Output
The CS5160 is designed to provide two methods for
programming the output voltage of the power supply. A five
bit on board digital to analog converter (DAC) is used to
program the output voltage within two different ranges. The
first range is 2.10 V to 3.50 V in 100 mV steps, the second
is 1.30 V to 2.05 V in 50 mV steps, depending on the digital
input code. If all five bits are left open, the CS5160 enters
adjust mode. In adjust mode, the designer can choose any
output voltage by using resistor divider feedback to the VFB
and VFFB pins, as in traditional controllers.
Start Up
Until the voltage on the VCC1 supply pin exceeds the
9.05 V monitor threshold, the Soft Start and gate pins are
held low. The FAULT latch is reset (no Fault condition). The
output of the error amplifier (COMP) is pulled up to 1.0 V
by the comparator clamp. When the VCC1 pin exceeds the
monitor threshold, the GATE(H) output is activated, and the
Soft Start capacitor begins charging. The GATE(H) output
will remain on, enabling the NFET switch, until terminated
by either the PWM comparator, or the maximum on time
timer.
If the maximum on time is exceeded before the regulator
output voltage achieves the 1.0 V level, the pulse is
terminated. The GATE(H) pin drives low, and the GATE(L)
pin drives high for the duration of the extended off time. This
time is set by the time out timer and is approximately equal
to the maximum on time, resulting in a 50% duty cycle. The
GATE(L) pin will then drive low, the GATE(H) pin will
drive high, and the cycle repeats.
When regulator output voltage achieves the 1.0 V level
present at the COMP pin, regulation has been achieved and
normal off time will ensue. The PWM comparator
terminates the switch on time, with off time set by the COFF
capacitor. The V2 control loop will adjust switch duty cycle
as required to ensure the regulator output voltage tracks the
output of the error amplifier.
The Soft Start and COMP capacitors will charge to their
final levels, providing a controlled turn on of the regulator
output. Regulator turn on time is determined by the COMP
capacitor charging to its final value. Its voltage is limited by
Constant Off Time
To maximize transient response, the CS5160 uses a
constant off time method to control the rate of output pulses.
During normal operation, the off time of the high side switch
is terminated after a fixed period, set by the COFF capacitor.
To maintain regulation, the V2 control loop varies switch on
time. The PWM comparator monitors the output voltage
ramp, and terminates the switch on time.
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8
CS5160
the Soft Start COMP clamp and the voltage on the Soft Start
pin (see Figures 4 and 5).
M 10.0 µs
M 250 µs
Trace 1– Regulator Output Voltage (5.0 V/div.)
Trace 2– Inductor Switching Node (5.0 V/div.)
Trace 1– Regulator Output Voltage (1.0 V/div.)
Trace 2– Inductor Switching Node (2.0 V/div.)
Trace 3– 12 V Input (VCC1 and VCC2) (5.0 V/div.)
Figure 6. CS5160 Enable Startup Waveforms
Trace 4– 5.0 V Input (1.0 V/div.)
Normal Operation
Figure 4. CS5160 Startup in Response to Increasing
12 V and 5.0 V Input Voltages. Extended Off Time is
Followed by Normal Off Time Operation when Output
Voltage Achieves Regulation to the Error Amplifier
Output
During normal operation, switch off time is constant and
set by the COFF capacitor. Switch on time is adjusted by the
V2 control loop to maintain regulation. This results in
changes in regulator switching frequency, duty cycle, and
output ripple in response to changes in load and line. Output
voltage ripple will be determined by inductor ripple current
working into the ESR of the output capacitors (see Figures
7 and 8).
M 2.50 ms
Trace 1– Regulator Output Voltage (1.0 V/div.)
Trace 3– COMP PIn (error amplifier output) (1.0 V/div.)
Trace 4– Soft Start Pin (2.0 V/div.)
Figure 5. CS5160 Startup Waveforms
M 1.00 µs
If the input voltage rises quickly, or the regulator output
is enabled externally, output voltage will increase to the
level set by the error amplifier output more rapidly, usually
within a couple of cycles (see Figure 6).
Trace 1– Regulator Output Voltage (10 mV/div.)
Trace 2– Inductor Switching Node (5.0 V/div.)
Figure 7. CS5160 Peak–to–Peak Ripple on VOUT = 2.8 V,
IOUT = 0.5 A (Light Load)
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CS5160
10 µs/div.
M 1.00 µs
Trace 1– Inductor Switching Node (5.0 V/div.)
Trace 2– Regulator Output Voltage (output set for 1.55 V, 20 mV/div.)
Trace 1– Regulator Output Voltage (10 mV/div.)
Figure 10. CS5160 Pentium III Converter Output
Voltage Response to a 0 to 12 A Load Increase
Trace 2– Inductor Switching Node (5.0 V/div.)
Figure 8. CS5160 Peak–to–Peak Ripple on VOUT = 2.8 V,
IOUT = 13 A (Heavy Load)
Transient Response
The CS5160 V2 control loop’s 100 ns reaction time
provides unprecedented transient response to changes in
input voltage or output current. Pulse by pulse adjustment of
duty cycle is provided to quickly ramp the inductor current
to the required level. Since the inductor current cannot be
changed instantaneously, regulation is maintained by the
output capacitor(s) during the time required to slew the
inductor current.
For best transient response, a combination of a number of
high frequency and bulk output capacitors are usually used.
If the maximum on time is exceeded while responding to
a sudden increase in load current, a normal off time occurs
to prevent saturation of the output inductor.
Trace 1– Inductor Switching Node (5 V/div.)
10 µs/div.
Trace 2– Regulator Output Voltage (output set for 1.55 V, 20 mV/div.)
Figure 11. CS5160 Pentium III Converter Output
Voltage Response to a 12 to 0 A Load Decrease
PROTECTION AND MONITORING FEATURES
VCC1 Monitor
To maintain predictable startup and shutdown
characteristics an internal VCC1 monitor circuit is used to
prevent the part from operating below 8.95 V minimum
startup. The VCC1 monitor comparator provides hysteresis
and guarantees a 8.80 V minimum shutdown threshold.
Short Circuit Protection
100 µs/div.
A lossless hiccup mode short circuit protection feature is
provided, requiring only the Soft Start capacitor to
implement. If a short circuit condition occurs
(VFFB < 1.0 V), the VFFB low comparator sets the FAULT
Trace 2– Regulator Output Voltage (output set for 1.55 V, 20 mV/div.)
Figure 9. CS5160 Pentium III Converter Output
Voltage Response to a 12 A Load Pulse
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CS5160
latch. This causes the top MOSFET to shut off,
disconnecting the regulator from it’s input voltage. The Soft
Start capacitor is then slowly discharged by a 2.0 µA current
source until it reaches it’s lower 0.7 V threshold. The
regulator will then attempt to restart normally, operating in
it’s extended off time mode with a 50% duty cycle, while the
Soft Start capacitor is charged with a 60 µA charge current.
If the short circuit condition persists, the regulator output
will not achieve the 1.0 V low VFFB comparator threshold
before the Soft Start capacitor is charged to it’s upper 2.5 V
threshold. If this happens the cycle will repeat itself until the
short is removed. The Soft Start charge/discharge current
ratio sets the duty cycle for the pulses
(2.0 µA/60 µA = 3.3%), while actual duty cycle is half that
due to the extended off time mode (1.65%).
This protection feature results in less stress to the
regulator components, input power supply, and PC board
traces than occurs with constant current limit protection (see
Figures 12 and 13).
If the short circuit condition is removed, output voltage
will rise above the 1.0 V level, preventing the FAULT latch
from being set, allowing normal operation to resume.
M 50.0 µs
Trace 4– 5.0 V from PC Power Supply (2.0 V/div.)
Trace 2– Inductor Switching Node (2.0 V/div.)
Figure 13. CS5160 Startup with Regulator
Output Shorted
Overvoltage Protection
Overvoltage protection (OVP) is provided as result of the
normal operation of the V2 control topology and requires no
additional external components. The control loop responds
to an overvoltage condition within 100 ns, causing the top
MOSFET to shut off, disconnecting the regulator from it’s
input voltage. The bottom MOSFET is then activated,
resulting in a “crowbar” action to clamp the output voltage
and prevent damage to the load (see Figures 14 and 15). The
regulator will remain in this state until the overvoltage
condition ceases or the input voltage is pulled low. The
bottom FET and board trace must be properly designed to
implement the OVP function.
M 25.0 ms
Trace 4– 5.0 V Supply Voltage (2.0 V/div.)
Trace 3– Soft Start Timing Capacitor (1.0 V/div.)
Trace 2– Inductor Switching Node (2.0 V/div.)
Figure 12. CS5160 Hiccup Mode Short Circuit
Protection. Gate Pulses are Delivered While the Soft
Start Capacitor Charges, and Cease During Discharge
M 10.0 µs
Trace 4– 5.0 V from PC Power Supply (5.0 V/div.)
Trace 1– Regulator Output Voltage (1.0 V/div.)
Trace 2– Inductor Switching Node 5.0 V/div.)
Figure 14. CS5160 OVP Response to an
Input–to–Output Short Circuit by Immediately
Providing 0% Duty Cycle, Crow–Barring the Input
Voltage to Ground
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CS5160
5.0 V
R3
10 k
VOUT
R1
10 k
CS5160
PN3904
Power Good
PN3904
R2
6.2 k
Figure 17. Implementing Power Good
with the CS5160
M 5.00 ms
Trace 4– 5.0 V from PC Power Supply (5.0 V/div.)
Trace 1– Regulator Output Voltage (1.0 V/div.)
Figure 15. CS5160 OVP Response to an
Input–to–Output Short Circuit by Pulling the Input
Voltage to Ground
External Output Enable Circuit
On/off control of the regulator can be implemented
through the addition of two additional discrete components
(see Figure 14). This circuit operates by pulling the Soft
Start pin high, and the VFFB pin low, emulating a short
circuit condition.
M 2.50 ms
5.0 V
Trace 3 – 12 V Input (VCC1) and (VCC2) (10 V/div.)
Trace 4– 5.0 V Input (2.0 V/div.)
Trace 1– Regulator Output Voltage (1.0 V/div.)
Trace 2– Power Good Signal (2.0 V/div.)
Figure 18. CS5160 During Power Up. Power
Good Signal is Activated when Output
Voltage Reaches 1.70 V
MMUN2111T1 (SOT–23)
5 SS
8 V
FFB
Slope Compensation
The V2 control method uses a ramp signal, generated by
the ESR of the output capacitors, that is proportional to the
ripple current through the inductor. To maintain regulation,
the V2 control loop monitors this ramp signal, through the
PWM comparator, and terminates the switch on–time.
The stringent load transient requirements of modern
microprocessors require the output capacitors to have very
low ESR. The resulting shallow slope presented to the PWM
comparator, due to the very low ESR, can lead to pulse width
jitter and variation caused by both random or synchronous
noise.
Adding slope compensation to the control loop, avoids
erratic operation of the PWM circuit, particularly at lower
duty cycles and higher frequencies, where there is not
enough ramp signal, and provides a more stable switchpoint.
The scheme that prevents that switching noise
prematurely triggers the PWM circuit consists of adding a
positive voltage slope to the output of the Error Amplifier
(COMP pin) during an off–time cycle.
CS5160
IN4148
Shutdown
Input
Figure 16. Implementing Shutdown
with the CS5160
External Power Good Circuit
An optional Power Good signal can be generated through
the use of four additional external components (see Figure
17). The threshold voltage of the Power Good signal can be
adjusted per the following equation:
VPower Good +
(R1 ) R2) 0.65 V
R2
This circuit provides an open collector output that drives
the Power Good output to ground for regulator voltages less
than VPower Good.
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CS5160
The circuit that implements this function is shown in
Figure 19.
16
COMP
CCOMP
CS5160
VOUT
R2
C1
R1
12
GATE(L)
To Synchronous
FET
M 1.00 µs
Figure 19. Small RC Filter Provides the
Proper Voltage Ramp at the Beginning of
each On–Time Cycle
Trace 3 = VGATE(H) (10 V/div.)
Math 1 = VGATE(H) – 5.0 VIN
Trace 4 = VGATE(L) (10 V/div.)
The ramp waveform is generated through a small RC filter
that provides the proper voltage ramp at the beginning of
each on–time cycle. The resistors R1 and R2 in the circuit of
Figure 14 form a voltage divider from the GATE(L) output,
superimposing a small artificial ramp on the output of the
error amplifier. It is important that the series combination
R1/R2 is high enough in resistance not to load down and
negatively affect the slew rate on the GATE(L) pin.
Trace 2= Inductor Switching Nodes (5.0 V/div.)
Figure 20. CS5160 Gate Drive Waveforms Depicting
Rail to Rail Swing
The most important aspect of MOSFET performance is
RDSON, which effects regulator efficiency and MOSFET
thermal management requirements.
The power dissipated by the MOSFETs may be estimated
as follows;
Switching MOSFET:
Selecting External Components
The CS5160 can be used with a wide range of external
power components to optimize the cost and performance of
a particular design. The following information can be used
as general guidelines to assist in their selection.
Power + ILOAD2
RDSON
duty cycle
Synchronous MOSFET:
Power + ILOAD2
NFET Power Transistors
RDSON
(1 * duty cycle)
Duty Cycle =
Both logic level and standard MOSFETs can be used. The
reference designs derive gate drive from the 12 V supply
which is generally available in most computer systems and
utilize logic level MOSFETs. Multiple MOSFETs may be
paralleled to reduce losses and improve efficiency and
thermal management.
Voltage applied to the MOSFET gates depends on the
application circuit used. Both upper and lower gate driver
outputs are specified to drive to within 1.5 V of ground when
in the low state and to within 2.0 V of their respective bias
supplies when in the high state. In practice, the MOSFET
gates will be driven rail to rail due to overshoot caused by the
capacitive load they present to the controller IC. For the
typical application where VCC1 = VCC2 = 12 V and 5.0 V is
used as the source for the regulator output current, the
following gate drive is provided;
VOUT ) (ILOAD
ƪ
RDSON OF SYNCH FET)
VIN)(ILOAD RDSON OF SYNCH FET)
* (ILOAD RDSON OF SWITCH FET)
ƫ
Off Time Capacitor (COFF)
The COFF timing capacitor sets the regulator off time:
TOFF + COFF
4848.5
The preceding equations for duty cycle can also be used
to calculate the regulator switching frequency and select the
COFF timing capacitor:
COFF +
Perioid
(1 * duty cycle)
4848.5
where:
VGATE(H) + 12 V * 5.0 V + 7.0 V, VGATE(L) + 12 V
Period +
(see Figure 20.)
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1
switching frequency
CS5160
Schottky Diode for Synchronous MOSFET
A heatsink may be added to TO–220 components to
reduce their thermal impedance. A number of PC board
layout techniques such as thermal vias and additional copper
foil area can be used to improve the power handling
capability of surface mount components.
A Schottky diode may be placed in parallel with the
synchronous MOSFET to conduct the inductor current upon
turn off of the switching MOSFET to improve efficiency.
For a design operating at 200 kHz or so, the low non–overlap
time combined with Schottky forward recovery time may
make the benefits of this device not worth the additional
expense (see Figure 8, channel 2). The power dissipation in
the synchronous MOSFET due to body diode conduction
can be estimated by the following equation:
Power + VBD
ILOAD
conduction time
EMI Management
As a consequence of large currents being turned on and off
at high frequency, switching regulators generate noise as a
consequence of their normal operation. When designing for
compliance with EMI/EMC regulations, additional
components may be added to reduce noise emissions. These
components are not required for regulator operation and
experimental results may allow them to be eliminated. The
input filter inductor may not be required because bulk filter
and bypass capacitors, as well as other loads located on the
board will tend to reduce regulator di/dt effects on the circuit
board and input power supply. Placement of the power
component to minimize routing distance will also help to
reduce emissions.
switching frequency
Where VBD = the forward drop of the MOSFET body
diode. For the CS5160 demonstration board as shown in
Figure 8;
Power + 1.6 V
13 A
100 ns
233 kHz + 0.48 W
This is only 1.3% of the 36.4 W being delivered to the
load.
Input and Output Capacitors
These components must be selected and placed carefully
to yield optimal results. Capacitors should be chosen to
provide acceptable ripple on the input supply lines and
regulator output voltage. Key specifications for input
capacitors are their ripple rating, while ESR is important for
output capacitors. For best transient response, a combination
of low value/high frequency and bulk capacitors placed
close to the load will be required.
2.0 µH
33 Ω
1000 pF
Output Inductor
The inductor should be selected based on its inductance,
current capability, and DC resistance. Increasing the
inductor value will decrease output voltage ripple, but
degrade transient response.
Figure 21. Filter Components
2.0 µH
THERMAL MANAGEMENT
+
1200 pF × 3.0/16 V
Thermal Considerations for Power
MOSFETs and Diodes
In order to maintain good reliability, the junction
temperature of the semiconductor components should be
kept to a maximum of 150°C or lower. The thermal
impedance (junction to ambient) required to meet this
requirement can be calculated as follows:
Thermal Impedance +
Figure 22. Input Filter
TJUNCTION(MAX) * TAMBIENT
Power
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CS5160
Layout Guidelines
1.
2.
3.
4.
5.
6.
7.
To the negative terminal
of the input capacitors
VCC
0.1 µF
Place 12 V filter capacitor next to the IC and connect
capacitor ground to pin 11 (PGnd).
Connect pin 11 (PGnd) with a separate trace to the
ground terminals of the 5.0 V input capacitors.
Place fast feedback filter capacitor next to pin 8 (VFFB)
and connect it’s ground terminal with a separate, wide
trace directly to pin 14 (LGnd).
Connect the ground terminals of the Compensation
capacitor directly to the ground of the fast feedback
filter capacitor to prevent common mode noise from
effecting the PWM comparator.
Place the output filter capacitor(s) as close to the load
as possible and connect the ground terminal to pin 14
(LGnd).
Connect the VFB pin directly to the load with a separate
trace (remote sense).
Place 5.0 V input capacitors close to the switching
MOSFET and synchronous MOSFET.
Route gate drive signals VGATE(H) (pin 10) and
VGATE(L) (pin 12 when used) with traces that are a
minimum of 0.025 inches wide.
15
11
1.0 µF
VCOMP
8
5
100 pF
VFFB
SOFT START
OFF TIME
To the negative terminal of the output capacitors
Figure 23. Layout Guidelines
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CS5160
ADDITIONAL APPLICATION DIAGRAMS
3.3 V
12 V
33 µF/25 V × 3.0
Tantalum
1.0 µF
VCC2
VCC1
5.0 µH
Si9410
VGATE(H)
2.5 V/7.0 A
VID0
VID1
VGATE(L)
VID2
100 µF/10 V × 2.0
Tantalum
VID3
VID4
CS5160
Si9410
PGnd
COFF
330 pF
MBRS140T3
SS
0.1 µF
VFB
3.3 k
COMP
VFFB
LGnd
100 pF
0.33 µF
Figure 24. 3.3 V to 2.5 V/7.0 A Converter with 12 V Bias
5.0 V
12 V
1.0 µH
0.1 µF
VCC1
SILICONIX
SUD50NO3–10P
VCC2
VGATE(H)
VID0
VID0
VID1
VID1
VID2
VID2
VID3
VID3
VID4
VID4
1200 µF/10 V × 6.0
Sanyo GX
1.8 µH
SILICONIX
SUD50NO3–07
VGATE(L)
10 k
CS5160
VOUT
MBRS140T3
30 nF
COFF
680 pF
PGnd
SS
VFB
0.1 µF
COMP
LGnd
500 k
VFFB
1200 µF/10 V × 8.0
Sanyo GX
1.0 µF
00.1 µF
10 k
100
Figure 25. PentiumIII Converter with Slope Compensation and Adaptive Voltage Positioning
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CS5160
PACKAGE DIMENSIONS
SO–16
D SUFFIX
CASE 751B–05
ISSUE J
–A–
16
!
" # $ ! % # 9
–B–
1
P
8 PL
&!
8
G
R
K
F
X 45 _
C
–T–
SEATING
PLANE
J
M
D
16 PL
&!
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
$
$&
&&_
$&&_
PACKAGE THERMAL DATA
Parameter
16 Lead SO Narrow
Unit
RΘJC
Typical
28
°C/W
RΘJA
Typical
115
°C/W
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INCHES
MIN
MAX
$
&
&&_
$&&_
CS5160
Notes
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CS5160
Notes
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CS5160
V2 is a trademark of Switch Power, Inc.
Pentium is a registered trademark of Intel Corporation.
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
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SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or
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attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
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CS5160/D