CY24202 PRELIMINARY 27-MHz Clock Generator with Serial Programming Interface Features Benefits • Integrated phase-locked loop High-performance PLL tailored for multimedia applications • Low jitter, high accuracy outputs Meets critical timing requirements in complex system designs • Serial Programming Interface (SPI) Dynamic Digital VCXO control • 3.3V Operation Enables application compatibility in low power systems Part Number CY24202 Outputs Input Frequency Range Output Frequencies 2 13.5-MHz pullable crystal input per Cypress Specification 2 copies of 27 MHz Logic Block Diagram 13.5 XIN OSC OUTPUT DIVIDERS Φ Q XOUT VCO CLK2 CLK1 P PLL SCLK SDAT Digital VCXO Serial Programming Interface VDD VSS Pin Configuration CY24202 8-pin SOIC Cypress Semiconductor Corporation Document #: 38-07198 Rev. *A • XIN 1 8 XOUT VDD SDAT 2 7 3 6 CLK2 CLK1 VSS 4 5 SCLK 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised December 14, 2002 CY24202 PRELIMINARY Summary Name Pin Number Description XIN 1 Reference Crystal Input VDD 2 Voltage Supply SDAT 3 Digital VCXO Serial Data Input VSS 4 Ground SCLK 5 Digital VCXO Serial Clock Input CLK1 6 Clock Output 1 @ 27 MHz CLK2 7 Clock Output 2 @ 27 MHz 8 Reference Crystal Output XOUT [1] Pullable Crystal Specifications Parameter CRload Description Min. Crystal Load Capacitance Typ. Max. 14 C0/C1 Unit pF 240 ESR Equivalent Series Resistance Ω 35 To Operating Temperature 70 °C Crystal Accuracy Crystal Accuracy 0 ±20 ppm TTs Stability over temperature and aging ±50 ppm Absolute Maximum Conditions Parameter Description Min. Max. Unit VDD Supply Voltage –0.5 7.0 V TS Storage Temperature[2] –65 125 °C TJ Junction Temperature 125 °C Digital Inputs VSS – 0.3 VDD + 0.3 V Digital Outputs referred to VDD VSS – 0.3 VDD + 0.3 Electro-Static Discharge 2 V kV Recommended Operating Conditions Parameter Description VDD Operating Voltage TA Ambient Temperature CLOAD Max. Load Capacitance fREF Reference Frequency tPU Power-up time for all VDD's to reach minimum specified voltage (power ramps must be monotonic) Min. Typ. Max. 3.135 3.3 3.465 V 70 °C 0 15 13.5 0.05 Unit pF MHz 500 ms Notes: 1. Float XOUT if XIN is externally driven. 2. Rated for 10 years. Document #: 38-07198 Rev. *A Page 2 of 6 CY24202 PRELIMINARY DC Electrical Characteristics Parameter Description Conditions Min. Typ. Max. Unit IOH Output High Current VOH = VDD – 0.5, VDD = 3.3V 12 24 mA IOL Output Low Current VOL = 0.5, VDD = 3.3V 12 24 mA CIN Input Capacitance IIZ Input Leakage Current 5 IVDD Supply Current 20 7 pF µA 30 mA AC Electrical Characteristics (VDD = 3.3V) Parameter[3] Name Description Min Typ Max Unit Duty Cycle is defined in Figure 4, 50% of VDD 45 50 55 % DC Output Duty Cycle t3 Rising Edge Slew Rate Output Clock Rise Time, 20% - 80% of VDD 0.8 1.4 V/ns t4 Falling Edge Slew Rate Output Clock Fall Time, 80% - 20% of VDD 0.8 1.4 V/ns t9 Clock Jitter Peak to Peak period jitter t10 PLL Lock Time Note: 3. Not 100% tested. ps 3 ms Start Sequence Serial Programmable Interface Protocol The CY24202 utilizes a 2-wire interface SDAT and SCLK that operates up to 400 kbits/sec in Read or Write mode. The basic Write serial format is as follows: Start Bit; 7-bit Device Address (DA); R/W Bit; Slave Clock Acknowledge (ACK); 8-bit Memory Address (MA); ACK; 8-bit Data; ACK; 8-bit Data in MA+1 if desired; ACK; 8-bit Data in MA+2; ACK; etc. until STOP Bit, as illustrated in Figure 1. SDA Write 175 1 Bit 1 Bit Slave R/W = 0 ACK 7 Bit Device Address 1 Bit Slave ACK 8 Bit Register Address Start Signal 1 Bit Slave ACK 8 Bit Register Data Stop Signal Figure 1. Data Frame Architecture Start Frame is indicated by SDAT going LOW when SCLK is HIGH. Every time a start signal is given the next 8-bit data must be the device address (7 bits) and a R/W bit (0 for write), followed by register address (8 bits) and register data (8 bits). See Figure 3. Stop Sequence Stop Frame is indicated by SDAT going high when SCLK is high. A Stop Frame frees the bus for writing to another part on the same bus or writing to another random register address. See Figure 3. Acknowledge Pulse During Write Mode the CY24202 will respond with an Acknowledge pulse after every 8 bits. This is accomplished by pulling the SDAT line low during the next clock cycle after the 8th bit is shifted in. Device Address The 7 bit device address is 1101001. Data Valid Data is valid when the Clock is HIGH, and may only be transitioned when the clock is LOW as illustrated in Figure 2. Register Address The 8 bit address for the VCXO register is 00010011. Data Frame Register Data Every new data frame is indicated by a start and stop sequence, as illustrated in Figure 3. The register data can be any value between 00H - FFH. As you increase the value, the capacitance on the XIN and XOUT pins will increase, thereby decreasing the xtal frequency. Document #: 38-07198 Rev. *A Page 3 of 6 CY24202 PRELIMINARY Data Valid Transition to next Bit SDAT tDH tSU CLKHIGH VIH SCLK CLKLOW VIL Figure 2. Data Valid and Data Transition Periods SDAT SCLK Transition to next Bit START STOP Figure 3. Start and Stop Frame Serial Programming Interface Timing Specifications Parameter fSCL Description Min. Frequency of SCLK Max. Unit 400 kHz Start Mode Time from SDAT LOW to SCLK LOW 0.6 µs CLKLOW SCLK LOW Period 1.3 µs CLKHIGH SCLK HIGH Period 0.6 µs tSU Data Transition to SCLK HIGH 100 ns tDH Data Hold (SCLK LOW to Data Transition) 0 ns Rise Time of SCLK and SDAT 300 ns Fall Time of SCLK and SDAT 300 ns Stop Mode Time from SCLK HIGH to SDA HIGH 0.6 µs Stop Mode to Start Mode 1.3 µs Document #: 38-07198 Rev. *A Page 4 of 6 CY24202 PRELIMINARY Test Circuit VDD CLK out 0.1 µF CLOAD OUTPUTS GND t1 t3 t2 CLK t4 80% 50% 50% CLK Figure 4. Duty Cycle Definition; DC = t2/t1 20% Figure 5. Rise and Fall Time Definitions Ordering Information Ordering Code Package Name Package Type Operating Range Operating Voltage CY24202SC S8 8-Pin SOIC Commercial 3.3V Package Diagram 8-Lead (150-Mil) SOIC S8 51-85066-A Document #: 38-07198 Rev. *A Page 5 of 6 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. PRELIMINARY CY24202 Document Title: CY24202 27-MHz Clock Generator with Serial Programming Interface Document Number: 38-07198 ECN NO. Issue Date Orig. of Change ** 111424 02/27/02 CKN New data sheet *A 121876 12/14/02 RBI Power up requirements added to Operating Conditions Information REV. Document #: 38-07198 Rev. *A Description of Change Page 6 of 6 CY24202 PRELIMINARY 27-MHz Clock Generator with Serial Programming Interface Features Benefits • Integrated phase-locked loop High-performance PLL tailored for multimedia applications • Low jitter, high accuracy outputs Meets critical timing requirements in complex system designs • Serial Programming Interface (SPI) Dynamic Digital VCXO control • 3.3V Operation Enables application compatibility in low power systems Part Number CY24202 Outputs Input Frequency Range Output Frequencies 2 13.5-MHz pullable crystal input per Cypress Specification 2 copies of 27 MHz Logic Block Diagram 13.5 XIN OSC OUTPUT DIVIDERS Φ Q XOUT VCO CLK2 CLK1 P PLL SCLK SDAT Digital VCXO Serial Programming Interface VDD VSS Pin Configuration CY24202 8-pin SOIC Cypress Semiconductor Corporation Document #: 38-07198 Rev. *A • XIN 1 8 XOUT VDD SDAT 2 7 3 6 CLK2 CLK1 VSS 4 5 SCLK 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised December 14, 2002 CY24202 PRELIMINARY Summary Name Pin Number Description XIN 1 Reference Crystal Input VDD 2 Voltage Supply SDAT 3 Digital VCXO Serial Data Input VSS 4 Ground SCLK 5 Digital VCXO Serial Clock Input CLK1 6 Clock Output 1 @ 27 MHz CLK2 7 Clock Output 2 @ 27 MHz 8 Reference Crystal Output XOUT [1] Pullable Crystal Specifications Parameter CRload Description Min. Crystal Load Capacitance Typ. Max. 14 C0/C1 Unit pF 240 ESR Equivalent Series Resistance Ω 35 To Operating Temperature 70 °C Crystal Accuracy Crystal Accuracy 0 ±20 ppm TTs Stability over temperature and aging ±50 ppm Absolute Maximum Conditions Parameter Description Min. Max. Unit VDD Supply Voltage –0.5 7.0 V TS Storage Temperature[2] –65 125 °C TJ Junction Temperature 125 °C Digital Inputs VSS – 0.3 VDD + 0.3 V Digital Outputs referred to VDD VSS – 0.3 VDD + 0.3 Electro-Static Discharge 2 V kV Recommended Operating Conditions Parameter Description VDD Operating Voltage TA Ambient Temperature CLOAD Max. Load Capacitance fREF Reference Frequency tPU Power-up time for all VDD's to reach minimum specified voltage (power ramps must be monotonic) Min. Typ. Max. 3.135 3.3 3.465 V 70 °C 0 15 13.5 0.05 Unit pF MHz 500 ms Notes: 1. Float XOUT if XIN is externally driven. 2. Rated for 10 years. Document #: 38-07198 Rev. *A Page 2 of 6 CY24202 PRELIMINARY DC Electrical Characteristics Parameter Description Conditions Min. Typ. Max. Unit IOH Output High Current VOH = VDD – 0.5, VDD = 3.3V 12 24 mA IOL Output Low Current VOL = 0.5, VDD = 3.3V 12 24 mA CIN Input Capacitance IIZ Input Leakage Current 5 IVDD Supply Current 20 7 pF µA 30 mA AC Electrical Characteristics (VDD = 3.3V) Parameter[3] Name Description Min Typ Max Unit Duty Cycle is defined in Figure 4, 50% of VDD 45 50 55 % DC Output Duty Cycle t3 Rising Edge Slew Rate Output Clock Rise Time, 20% - 80% of VDD 0.8 1.4 V/ns t4 Falling Edge Slew Rate Output Clock Fall Time, 80% - 20% of VDD 0.8 1.4 V/ns t9 Clock Jitter Peak to Peak period jitter t10 PLL Lock Time Note: 3. Not 100% tested. ps 3 ms Start Sequence Serial Programmable Interface Protocol The CY24202 utilizes a 2-wire interface SDAT and SCLK that operates up to 400 kbits/sec in Read or Write mode. The basic Write serial format is as follows: Start Bit; 7-bit Device Address (DA); R/W Bit; Slave Clock Acknowledge (ACK); 8-bit Memory Address (MA); ACK; 8-bit Data; ACK; 8-bit Data in MA+1 if desired; ACK; 8-bit Data in MA+2; ACK; etc. until STOP Bit, as illustrated in Figure 1. SDA Write 175 1 Bit 1 Bit Slave R/W = 0 ACK 7 Bit Device Address 1 Bit Slave ACK 8 Bit Register Address Start Signal 1 Bit Slave ACK 8 Bit Register Data Stop Signal Figure 1. Data Frame Architecture Start Frame is indicated by SDAT going LOW when SCLK is HIGH. Every time a start signal is given the next 8-bit data must be the device address (7 bits) and a R/W bit (0 for write), followed by register address (8 bits) and register data (8 bits). See Figure 3. Stop Sequence Stop Frame is indicated by SDAT going high when SCLK is high. A Stop Frame frees the bus for writing to another part on the same bus or writing to another random register address. See Figure 3. Acknowledge Pulse During Write Mode the CY24202 will respond with an Acknowledge pulse after every 8 bits. This is accomplished by pulling the SDAT line low during the next clock cycle after the 8th bit is shifted in. Device Address The 7 bit device address is 1101001. Data Valid Data is valid when the Clock is HIGH, and may only be transitioned when the clock is LOW as illustrated in Figure 2. Register Address The 8 bit address for the VCXO register is 00010011. Data Frame Register Data Every new data frame is indicated by a start and stop sequence, as illustrated in Figure 3. The register data can be any value between 00H - FFH. As you increase the value, the capacitance on the XIN and XOUT pins will increase, thereby decreasing the xtal frequency. Document #: 38-07198 Rev. *A Page 3 of 6 CY24202 PRELIMINARY Data Valid Transition to next Bit SDAT tDH tSU CLKHIGH VIH SCLK CLKLOW VIL Figure 2. Data Valid and Data Transition Periods SDAT SCLK Transition to next Bit START STOP Figure 3. Start and Stop Frame Serial Programming Interface Timing Specifications Parameter fSCL Description Min. Frequency of SCLK Max. Unit 400 kHz Start Mode Time from SDAT LOW to SCLK LOW 0.6 µs CLKLOW SCLK LOW Period 1.3 µs CLKHIGH SCLK HIGH Period 0.6 µs tSU Data Transition to SCLK HIGH 100 ns tDH Data Hold (SCLK LOW to Data Transition) 0 ns Rise Time of SCLK and SDAT 300 ns Fall Time of SCLK and SDAT 300 ns Stop Mode Time from SCLK HIGH to SDA HIGH 0.6 µs Stop Mode to Start Mode 1.3 µs Document #: 38-07198 Rev. *A Page 4 of 6 CY24202 PRELIMINARY Test Circuit VDD CLK out 0.1 µF CLOAD OUTPUTS GND t1 t3 t2 CLK t4 80% 50% 50% CLK Figure 4. Duty Cycle Definition; DC = t2/t1 20% Figure 5. Rise and Fall Time Definitions Ordering Information Ordering Code Package Name Package Type Operating Range Operating Voltage CY24202SC S8 8-Pin SOIC Commercial 3.3V Package Diagram 8-Lead (150-Mil) SOIC S8 51-85066-A Document #: 38-07198 Rev. *A Page 5 of 6 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. PRELIMINARY CY24202 Document Title: CY24202 27-MHz Clock Generator with Serial Programming Interface Document Number: 38-07198 ECN NO. Issue Date Orig. of Change ** 111424 02/27/02 CKN New data sheet *A 121876 12/14/02 RBI Power up requirements added to Operating Conditions Information REV. Document #: 38-07198 Rev. *A Description of Change Page 6 of 6