CY26210 PRELIMINARY PacketClock™ T1/E1 to 19.44 MHz Clock Translator Features Benefits • Integrated phase-locked loop High performance PLL tailored for T1/E1 clock generation • Low jitter, high accuracy outputs Meets critical timing requirements in complex system designs • 3.3V Operation Enables application compatibility Part Number Outputs Input Frequency Range Output Frequencies CY26210 1 1.544 or 2.048 MHz 19.44 MHz Logic Block Diagram Q Fref Φ VCO OUTPUT DIVIDERS CLK1 P PLL FS AVDD AVSS VDD VSS Pin Configuration CY26210 8-pin SOIC Table 1. CY26210 Frequency Select Option Fref 1 8 NC AVDD FS 2 7 3 6 VSS CLK1 AVSS 4 5 VDD Cypress Semiconductor Corporation Document #: 38-07446 Rev. *A • Frequency Select Input CLK1 Unit 0 1.544 19.44 MHz 1 2.048 19.44 MHz 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised December 14, 2002 CY26210 Pin Description Name Pin Number Description Fref 1 1.544 MHz/2.048 MHz Reference Input AVDD 2 Analog Voltage Supply FS 3 Frequency Select – See Table 1 AVSS 4 Analog Ground VDD 5 Voltage Supply CLK1 6 19.44 MHz Clock Output VSS 7 Ground NC 8 Leave floating No Connect Absolute Maximum Conditions Parameter VDD Description Supply Voltage [1] TS Storage Temperature TJ Junction Temperature Min. Max. Unit –0.5 7.0 V –65 125 °C 125 °C Digital Inputs VSS – 0.3 VDD + 0.3 V Digital Outputs referred to VDD VSS – 0.3 VDD + 0.3 V Electro-Static Discharge 2000 V Recommended Operating Conditions Parameter Description VDD/AVDD Operating Voltage TA Ambient Temperature (Commercial) CLOAD Max. Load Capacitance fREF tPU Min. Typ. Max. 3.135 3.3 Unit 3.465 V 0 70 °C 15 pF Reference Frequency 1.544 2.048 MHz Power-up time for all VDD's to reach minimum specified voltage (power ramps must be monotonic) 0.05 500 ms DC Electrical Specifications (Commercial) Min. Typ. IOH Parameter Output High Current Name VOH = VDD – 0.5, VDD = 3.3V Description 12 24 IOL Output Low Current VOL = 0.5, VDD = 3.3V 12 24 CIN Input Capacitance IIZ Input Current IDD Supply Current Sum of Core and Output Current VIH Input High Voltage CMOS levels, 70% of VDD VIL Input Low Voltage CMOS levels, 30% of VDD Max. Unit mA mA 7 pF 20 mA µA 5 0.7VDD V 0.3VDD V AC Electrical Specifications (VDD = 3.3V) Parameter[2] Description Min Typ Max Unit DC Output Duty Cycle Name Duty Cycle is defined in Figure 1, 50% of VDD 45 50 55 % ERO Rising Edge Rate Output Clock Edge Rate, Measured from 20% to 80% of VDD, CLOAD = 15pF See Figure 2. 0.8 1.4 V/ns EFO Falling Edge Rate Output Clock Edge Rate, Measured from 80% to 20% of VDD, CLOAD = 15pF See Figure 2. 0.8 1.4 V/ns t9 Clock Jitter Peak to Peak Period Jitter t10 PLL Lock Time Document #: 38-07446 Rev. *A 200 ps 3 ms Page 2 of 5 CY26210 AC Electrical Specifications (VDD = 3.3V) Parameter[2] Name Description Min Typ Max Unit Note: 1. Rated for 10 years 2. Not 100% tested Test and Measurement Set-up VDD CLK out 0.1 µF CLOAD OUTPUTS GND Voltage and Timing Definitions t1 t2 CLK 50% 50% Figure 1. Duty Cycle Definition; DC = t2/t1 t3 t4 80% CLK 20% Figure 2. Rise and Fall Time Definitions: ER = 0.6 x VDD / t3, EF = 0.6 x VDD / t4 Ordering Information Ordering Code Package Name Package Type Operating Range Operating Voltage CY26210SC S8 8-Pin SOIC Commercial 3.3V CY26210SCT S8 8-Pin SOIC - Tape and Reel Commercial 3.3V Document #: 38-07446 Rev. *A Page 3 of 5 PRELIMINARY CY26210 Package Drawing and Dimensions 8-Lead (150-Mil) SOIC S8 51-85066-A Document #: 38-07446 Rev. *A Page 4 of 5 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY26210 Document History Page Document Title: CY26210 PacketClock™ T1/E1 to 19.44 MHz Clock Translator Document Number: 38-07446 REV. ECN NO. Issue Date Orig. of Change ** 116739 09/12/02 CKN New data sheet *A 121904 12/14/02 RBI Power up requirements added to Operating Conditions Information Document #: 38-07446 Rev. *A Description of Change Page 5 of 5