CYM8301BV33 512K x 24 Static RAM Module Features • • • • • • • High-density 12-Megabit SRAM module Access time: 10 ns Single 3.3V power supply Low active power(1000 W max.) TTL-compatible inputs and outputs Available in standard 119-ball BGA Interface to Motorola digital signal processor (DSP) and analog devices Functional Description The CYM8301BV33 is a 3.3V high-performance 12-Megabit static RAM organized as a 512K words by 24 bits. This module is constructed from three 512K × 8 SRAM dice mounted on a multi layer laminate substrate combined to form a 24 bit SRAM. CYM8301BV33 is a ideal single-chip solution for Motorola’s DSP5630X or a two chip solution to Analog Devices ADSP2106XL. Each data byte is separately controlled by the individual chip selects(CE0,CE1,CE2). CE0 controls I/O0–7. CE1 controls I/O7–15. CE2 controls I/O16–23. Writing the data bytes into the SRAM is accomplished when the chip select (CSx) controlling that byte is LOW and Write Enable (WE) is LOW.Data on the respective input/output pins (I/O) is then written into the memory location specified on the address pins (A0 through A18). Asserting all the (CSx) LOW and (WE) LOW will write the entire data (I/O0–23) into the memory. Output Enable (OE) is a don’t care in a write mode. Reading a byte is accomplished when the chip select (CSx) controlling that byte is LOW and Write Enable (WE) is LOW while the Output Enable (OE) is LOW.Under these conditions the contents of the memory location specified on the address pins will all appear on the specified data input/output pins (I/O). Asserting all the (CSx) LOW and (WE) LOW with Output Enable (OE) LOW will read the entire data (I/O0-23) from the memory. The data input/output pins (I/O0–23) are placed in a high-impedance state when the device is deselected (CE) HIGH, the outputs are disabled (OE) HIGH or during a Write operation (CE LOW, and WE LOW). For further details on Read and Write conditions, please see the truth table on page 7 of this data sheet. Functional Block Diagram A[18:0] CE WE OE CE0 A[18:0] I/O0–7 I/O0–7 8 A[18:0] CE1 WE OE CE WE OE I/O8–15 8 A[18:0] CE WE OE CE2 I/O0–23 I/O0–7 I/O16–23 I/O0–7 8 Selection Guide CYM8301BV33-10 CYM8301BV33-12 CYM8301BV33-15 Unit Maximum Access Time Maximum Operating Current Commercial Maximum Standby Current 10 12 15 ns mA 300 270 255 Industrial 330 300 285 Commercial/Industrial 30 30 30 Cypress Semiconductor Corporation Document #: 38-05294 Rev. ** • 3901 North First Street • San Jose • mA CA 95134 • 408-943-2600 Revised May 13, 2002 CYM8301BV33 Pin Configurations 119 BGA Top View 1 2 3 4 5 6 7 A NC A A A A A NC B NC A A CE0 A A NC C I/O12 NC CE1 NC CE2 NC I/O0 D I/O13 VDD VSS VSS VSS VDD I/O1 E I/O14 VSS VDD VSS VDD VSS I/O2 F I/O15 VDD VSS VSS VSS VDD I/03 G I/O16 VSS VDD VSS VDD VSS I/04 H I/O17 VDD VSS VSS VSS VDD I/O5 J NC VSS VDD VSS VDD VSS NC K I/O18 VDD VSS VSS VSS VDD I/O6 L I/O19 VSS VDD VSS VDD VSS I/O7 M I/O20 VDD VSS VSS VSS VDD I/O8 N I/O21 VSS VDD VSS VDD VSS I/09 P I/O22 VDD VSS VSS VSS VDD I/O10 R I/O23 A NC NC NC A I/O11 T NC A A WE A A NC U NC A A OE A A NC Document #: 38-05294 Rev. ** Page 2 of 9 CYM8301BV33 Current into Outputs (LOW)......................................... 20 mA Maximum Ratings Static Discharge Voltage .......................................... > 2001V (per MIL-STD-883, Method 3015) (Above which the useful life may be impaired. For user guidelines, not tested.) Latch-up Current..................................................... > 200 mA Storage Temperature .................................–65°C to +150°C Operating Range Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage on VCC to Relative GND[1] ...... –0.5V to 4.6V Range DC Voltage Applied to Outputs in High-Z State[1] ....................................–0.5V to VCC + 0.5V Commercial Industrial DC Input Voltage[1].................................–0.5V to VCC + 0.5V Ambient Temperature VCC 0°C to +70°C 3.3V ± 5% –40°C to +85°C 3.3V ± 5% Electrical Characteristics Over the Operating Range CYM8301BV33-10 CYM8301BV33-12/15 Parameter Description Test Conditions[2] VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA VIH Input HIGH Voltage VIL Input LOW Voltage[1] IIX Input Load Current GND < VI < VCC IOZ Output Leakage Current GND < VI < VCC, Output Disabled ICC VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC ISB1 Automatic CE Power-down Current —TTL Inputs ISB2 Automatic CE Power-down Current —CMOS Inputs Min. Max. 2.4 Min. Max. Unit 2.4 0.4 V 0.4 V VCC + 0.3 V VCC + 0.3 2.2 –0.5 0.8 –0.5 0.8 V –10 +10 –10 +10 µA –10 +10 –10 +10 µA 300 300 mA Max. VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX 150 150 mA Max. VCC, CE > VCC – 0.3V, VIN > VCC – 0.3V, or VIN < 0.3V, f = 0 30 30 mA 2.2 Capacitance[3] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 3.3V Max. Unit 8 pF 8 pF Notes: 1. VIL (min.) = –2.0V for pulse durations of less than 20 ns. 2. CE is a combination of CE1, CE2 and CE3. 3. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05294 Rev. ** Page 3 of 9 CYM8301BV33 AC Test Loads and Waveforms R1 317 Ω OUTPUT ALL INPUT PULSES 3.3V Z0 = 50Ω OUTPUT RL = 50Ω VTH = 1.5V 3.0V 90% R2 351Ω 5 pF GND 10% ≤ 3 ns INCLUDING JIG AND SCOPE (b) (a) 90% 10% ≤ 3 ns Switching Characteristics[4] Over the Operating Range Description[2] Parameter CYM8301BV-10 CYM8301BV-12 CYM8301BV-15 Min. Min. Min. Max. Max. Max. Unit Read Cycle tRC Read Cycle Time tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE active to Data Valid 10 12 15 ns tDOE OE LOW to Data Valid 7 7.5 8.5 ns tLZOE OE LOW to Low-Z tHZOE OE HIGH to High-Z[5, 6] tLZCE CE Active to Low-Z 10 [6] 3 3 CE Active to Power-up CE Inactive to Power-down 3 0 10 ns 7 6 ns ns 7 0 12 ns ns 0 3 0 15 6 5 ns 3 0 3 tPU 15 12 5 [5, 6] CE Inactive to High-Z Write 10 0 tHZCE tPD 12 ns ns 15 ns Cycle[7, 8] tWC Write Cycle Time 10 12 15 ns tSCE CE active to Write End 9 9 9 ns tAW Address Set-up to Write End 9 9 10 ns tHA Address Hold from Write End 0 0 0 ns tSA Address Set-up to Write Start 0 0 0 ns tPWE WE Pulse Width 8 10 11 ns tSD Data Set-up to Write End 6 6 7 ns tHD Data Hold from Write End 0 0 0 ns 3 3 3 ns tLZWE tHZWE [6] WE HIGH to Low-Z [5, 6] WE LOW to High-Z 5 6 7 ns Notes: 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH. 5. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 500 mV from steady-state voltage. 6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 7. The internal Write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of any of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write. 8. The minimum Write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 38-05294 Rev. ** Page 4 of 9 CYM8301BV33 Switching Waveforms Read Cycle No. 1[9, 10] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (OE Controlled)[2, 10, 11] ADDRESS tRC CE tACE OE tHZOE tDOE DATA OUT tHZCE tLZOE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT HIGH IMPEDANCE tPD tPU ICC 50% 50% ISB Write Cycle No. 1 (CE Controlled)[2, 12, 13] tWC ADDRESS tSCE CE tSA tSCE tHA tAW tPWE WE tSD DATA I/O tHD DATA VALID Notes: 9. Device is continuously selected. OE, CE = VIL. 10. WE is HIGH for Read cycle. 11. Address valid prior to or coincident with CE transition LOW. 12. Data I/O is high impedance if OE = VIH. 13. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Document #: 38-05294 Rev. ** Page 5 of 9 CYM8301BV33 Switching Waveforms (continued) Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[12, 13] tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE OE tSD DATA I/O tHD DATAIN VALID NOTE 14 tHZOE Write Cycle No. 3 (WE Controlled, OE LOW)[2, 13] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE tSD DATA I/O NOTE 14 tHD DATA VALID tHZWE tLZWE Note: 14. During this period the I/Os are in the output state and input signals should not be applied. Document #: 38-05294 Rev. ** Page 6 of 9 CYM8301BV33 Truth Table CE1 CE2 CE3 WE OE H H H X X High-Z I/O0–I/O23 Deselect/Power-down Mode L L L H L Data Out (I/O0–23) Read L L L H H I/O High-Z Power-down L H H H L Data Out (I/O0–7) I/O8-23 in High-Z Read H L H H L Data Out (I/O8–15) I/O0–7 in High-Z I/O16–23 in High-Z Read H H L H L Data Out (I/O16–23) I/O0–15 in High-Z Read L L L L X Data In (I/O0–23) Write L H H L X Data In (I/O0–7) Write H L H L X Data In (I/O8–15) Write H H L L X Data In (I/O16–23) Write Ordering Information Speed (ns) Ordering Code Package Name Package Type Operating Range 10 CYM8301BV33 - 10BGC BG119 119-ball BGA CYM8301BV33 - 10BGI BG119 119-ball BGA Industrial 12 CYM8301BV33 - 12BGC BG119 119-ball BGA Commercial 15 Commercial CYM8301BV33 - 12BGI BG119 119-ball BGA Industrial CYM8301BV33 - 15BGC BG119 119-ball BGA Commercial CYM8301BV33 - 15BGI BG119 119-ball BGA Industrial Document #: 38-05294 Rev. ** Page 7 of 9 CYM8301BV33 Package Diagram 119-ball PBGA (14 x 22 x 2.4 mm) BG119 51-85115-*A All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05294 Rev. ** Page 8 of 9 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CYM8301BV33 Document Title: CYM8301BV33 512K x 24 Static RAM Module Document Number: 38-05294 REV. ECN NO. ISSUE DATE ORIG. OF CHANGE ** 114945 05/20/02 DFP Document #: 38-05294 Rev. ** DESCRIPTION OF CHANGE New Data Sheet Page 9 of 9