Technical Data DSP56311/D Rev. 2, 1/2002 24-Bit Digital Signal Processor 3 16 6 6 Memory Expansion Area EFCOP Peripheral Expansion Area Program RAM 32 K × 24 bits or 31 K × 24 bits and Instruction Cache 1024 × 24 bits Address Generation Unit Six Channel DMA Unit X Data RAM 48 K × 24 bits YAB XAB PAB DAB Y Data RAM 48 K × 24 bits YM_EB ESSI XM_EB PIO_EB The DSP56311 is intended for applications requiring a large amount of on-chip memory, such as networking and wireless infrastructure applications. The EFCOP can accelerate general filtering applications, such as echo-cancellation applications, correlation, and general-purpose convolution-based algorithms. HI08 PM_EB Triple Timer SCI 24-Bit DSP56300 Core Bootstrap ROM External Address Bus Switch External Bus Interface and I - Cache Control 18 Address 13 Control DDB YDB XDB PDB GDB Internal Data Bus Switch Clock PLL Generator EXTAL XTAL RESET PINIT/NMI Program Interrupt Controller Program Decode Controller Program Address Generator Data ALU 24 × 24 + 56 → 56-bit MAC Two 56-bit Accumulators 56-bit Barrel Shifter External Data Bus Switch Power Management 24 Data 5 JTAG OnCE™ DE PCAP MODA/IRQA MODB/IRQB MODC/IRQC MODD/IRQD Figure 1. DSP56311 Block Diagram The Motorola DSP56311, a member of the DSP56300 Digital Signal Processor (DSP) family, supports network applications with general filtering operations. The Enhanced Filter Coprocessor (EFCOP) executes filter algorithms in parallel with core operations enhancing signal quality with no impact on channel throughput or total channels supported. The result is increased overall performance. Like the other DSP56300 family members, the DSP56311 uses a high-performance, single-clock-cycle-perinstruction engine (DSP56000 code-compatible), a barrel shifter, 24-bit addressing, an instruction cache, and a direct memory access (DMA) controller (see Figure 1). The DSP56311 performs at 150 million instructions per second (MIPS), attaining 270 MIPS when the EFCOP is in use. It operates with an internal 150 MHz clock with a 1.8 volt core and independent 3.3 volt input/output (I/O) power. Table of Contents DSP56311 Features ............................................................................................................................................ iii Target Applications ..............................................................................................................................................v Product Documentation........................................................................................................................................v Chapter 1 Signal/ Connection Descriptions 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 1.10 1.11 1.12 1.13 Chapter 2 Specifications 2.1 2.2 2.3 2.4 2.5 Chapter 3 Pin-Out and Package ........................................................................................................................................ 3-1 MAP-BGA Package Description ..................................................................................................................... 3-2 MAP-BGA Package Mechanical Drawing .................................................................................................... 3-10 Design Considerations 4.1 4.2 4.3 4.4 4.5 Appendix A Introduction ...................................................................................................................................................... 2-1 Maximum Ratings............................................................................................................................................ 2-1 Thermal Characteristics ................................................................................................................................... 2-2 DC Electrical Characteristics ........................................................................................................................... 2-3 AC Electrical Characteristics ........................................................................................................................... 2-4 Packaging 3.1 3.2 3.3 Chapter 4 Signal Groupings.............................................................................................................................................. 1-1 Power................................................................................................................................................................ 1-3 Ground.............................................................................................................................................................. 1-3 Clock ................................................................................................................................................................ 1-4 PLL................................................................................................................................................................... 1-4 External Memory Expansion Port (Port A)...................................................................................................... 1-5 Interrupt and Mode Control ............................................................................................................................. 1-8 Host Interface (HI08) ....................................................................................................................................... 1-9 Enhanced Synchronous Serial Interface 0 (ESSI0)........................................................................................ 1-13 Enhanced Synchronous Serial Interface 1 (ESSI1)........................................................................................ 1-14 Serial Communication Interface (SCI)........................................................................................................... 1-16 Timers............................................................................................................................................................. 1-17 JTAG and OnCE Interface ............................................................................................................................. 1-18 Thermal Design Considerations....................................................................................................................... 4-1 Electrical Design Considerations ..................................................................................................................... 4-2 Power Consumption Considerations ................................................................................................................ 4-4 PLL Performance Issues .................................................................................................................................. 4-5 Input (EXTAL) Jitter Requirements................................................................................................................. 4-5 Power Consumption Benchmark Index Data Sheet Conventions OVERBAR “asserted” “deasserted” Examples: Used to indicate a signal that is active when pulled low (For example, the RESET pin is active when low.) Means that a high true (active high) signal is high or that a low true (active low) signal is low Means that a high true (active high) signal is low or that a low true (active low) signal is high Signal/Symbol Logic State Signal State Voltage PIN True Asserted VIL/VOL PIN False Deasserted VIH/VOH PIN True Asserted VIH/VOH PIN False Deasserted VIL/VOL Note: Values for VIL, VOL, VIH, and VOH are defined by individual product specifications. ii DSP56311 Features High-Performance DSP56300 Core • 150 million instructions per second (MIPS) (270 MIPS using the EFCOP in filtering applications) with a 150 MHz clock at 1.8 V core and 3.3 V I/O • Object code compatible with the DSP56000 core with highly parallel instruction set • Data Arithmetic Logic Unit (Data ALU) with fully pipelined 24 × 24-bit parallel Multiplier-Accumulator (MAC), 56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and parsing), conditional ALU instructions, and 24-bit or 16-bit arithmetic support under software control • Program Control Unit (PCU) with Position Independent Code (PIC) support, addressing modes optimized for DSP applications (including immediate offsets), on-chip instruction cache controller, on-chip memory-expandable hardware stack, nested hardware DO loops, and fast auto-return interrupts • Direct Memory Access (DMA) with six DMA channels supporting internal and external accesses; one-, two-, and three-dimensional transfers (including circular buffering); end-of-block-transfer interrupts; and triggering from interrupt lines and all peripherals • Phase Lock Loop (PLL) allows change of low-power Divide Factor (DF) without loss of lock and output clock with skew elimination • Hardware debugging support including On-Chip Emulation (OnCE) module, Joint Test Action Group (JTAG) Test Access Port (TAP) Enhanced Filtering Coprocessor (EFCOP) • On-chip 24 × 24-bit filtering and echo-cancellation coprocessor that runs in parallel to the DSP core • Operation at the same frequency as the core (up to 150 MHz) • Support for a variety of filter modes, some of which are optimized for cellular base station applications: — Real Finite Impulse Response (FIR) with real taps — Complex FIR with complex taps — Complex FIR generating pure real or pure imaginary outputs alternately — A 4-bit decimation factor in FIR filters, thus providing a decimation ratio up to 16 — Direct form 1 (DFI) Infinite Impulse Response (IIR) filter — Direct form 2 (DFII) IIR filter — Four scaling factors (1, 4, 8, 16) for IIR output — Adaptive FIR filter with true least mean square (LMS) coefficient updates — Adaptive FIR filter with delayed LMS coefficient updates On-Chip Peripherals • Enhanced DSP56000-like 8-bit parallel host interface (HI08) supports a variety of buses (for example, ISA) and provides glueless connection to a number of industry-standard microcomputers, microprocessors, and DSPs • Two enhanced synchronous serial interfaces (ESSI), each with one receiver and three transmitters (allows six-channel home theater) • Serial communications interface (SCI) with baud rate generator • Triple timer module • Up to 34 programmable general-purpose input/output (GPIO) pins, depending on which peripherals are enabled iii On-Chip Memories • 192 × 24-bit bootstrap ROM • 128 K RAM total • Program RAM, Instruction Cache, X data RAM, and Y data RAM sizes are programmable: Program RAM Size Instruction Cache Size X Data RAM Size* Y Data RAM Size* Instruction Cache Switch Mode MSW1 MSW0 32 K × 24-bit 0 48 K × 24-bit 48 K × 24-bit disabled disabled 0/1 0/1 31 K × 24-bit 1024 × 24-bit 48 K × 24-bit 48 K × 24-bit enabled disabled 0/1 0/1 96 K × 24-bit 0 16 K × 24-bit 16 K × 24-bit disabled enabled 0 0 95 K × 24-bit 1024 × 24-bit 16 K × 24-bit 16 K × 24-bit enabled enabled 0 0 80 K × 24-bit 0 24 K × 24-bit 24 K × 24-bit disabled enabled 0 1 79 K × 24-bit 1024 × 24-bit 24 K × 24-bit 24 K × 24-bit enabled enabled 0 1 64 K × 24-bit 0 32 K × 24-bit 32 K × 24-bit disabled enabled 1 0 63 K × 24-bit 1024 × 24-bit 32 K × 24-bit 32 K × 24-bit enabled enabled 1 0 48 K × 24-bit 0 40 K × 24-bit 40 K × 24-bit disabled enabled 1 1 47 K × 24-bit 1024 × 24-bit 40 K × 24-bit 40 K × 24-bit enabled enabled 1 1 *Includes 10 K × 24-bit shared memory (that is, memory shared by the core and the EFCOP) Off-Chip Memory Expansion • Data memory expansion to two 256 K × 24-bit word memory spaces using the standard external address lines • Program memory expansion to one 256 K × 24-bit words memory space using the standard external address lines • External memory expansion port • Chip Select Logic for glueless interface to static random access memory (SRAMs) • On-chip DRAM Controller for glueless interface to dynamic random access memory (DRAMs) up to 100 MHz operating frequency Reduced Power Dissipation • • • • Very low-power CMOS design Wait and Stop low-power standby modes Fully static design specified to operate down to 0 Hz (dc) Optimized power management circuitry (instruction-dependent, peripheral-dependent, and mode-dependent) Packaging The DSP56311 is available in a 196-pin MAP-BGA package. iv Target Applications • • • • • Wireless and wireline infrastructure applications Multi-channel wireless local loop systems DSP resource boards High-speed modem banks Packet telephony Product Documentation The three documents listed in the following table are required for a complete description of the DSP56311 and are necessary to design properly with the part. Documentation is available from the following sources. (See the back cover for details.) • • • • A local Motorola distributor A Motorola semiconductor sales office A Motorola Literature Distribution Center The World Wide Web (WWW) Table 1. DSP56311 Name Documentation Description Order Number DSP56300 Family Manual Detailed description of the DSP56300 family processor core and instruction set DSP56300FM/AD DSP56311 User’s Manual Detailed functional description of the DSP56311 memory configuration, operation, and register programming DSP56311UM/D DSP56311 Technical Data DSP56311 features list and physical, electrical, timing, and package specifications DSP56311/D v vi Chapter 1 Signal/ Connection Descriptions 1.1 Signal Groupings The DSP56311 input and output signals are organized into functional groups as shown in Table 1-1. Figure 1-1 diagrams the DSP56311 signals by functional group. The remainder of this chapter describes the signal pins in each functional group. Table 1-1. DSP56311 Functional Signal Groupings Number of Signals Functional Group Power (VCC) 20 Ground (GND) 66 Clock 2 PLL 3 18 Address bus Port A1 Data bus Bus control 13 Interrupt and mode control Host interface (HI08) Enhanced synchronous serial interface (ESSI) Serial communication interface (SCI) Timer 1. 2. 3. 4. 5. Note: 5 Port B 2 Ports C and D3 4 Port E 16 12 3 3 OnCE/JTAG Port Notes: 24 6 Port A signals define the external memory interface port, including the external address bus, data bus, and control signals. Port B signals are the HI08 port signals multiplexed with the GPIO signals. Port C and D signals are the two ESSI port signals multiplexed with the GPIO signals. Port E signals are the SCI port signals multiplexed with the GPIO signals. There are 5 signal connections that are not used. These are designated as no connect (NC) in the package description (see Chapter 3). The Clock Output (CLKOUT), BCLK, BCLK, CAS, and RAS[0–3] signals used by other DSP56300 family members are supported by the DSP56311 at operating frequencies up to 100 MHz. Therefore, above 100 MHz, you must enable bus arbitration by setting the Asynchronous Bus Arbitration Enable Bit (ABE) in the operating mode register. When set, the ABE bit eliminates the required set-up and hold times for BB and BG with respect to CLKOUT. In addition, DRAM access is not supported above 100 MHz. 1-1 Signal Groupings DSP56311 VCCP VCCQL VCCQH VCCA VCCD VCCC VCCH VCCS GNDP GNDP1 GND 4 3 3 4 2 2 64 EXTAL XTAL During Reset PINIT Power Inputs: PLL Core Logic I/O Address Bus Data Bus Bus Control HI08 ESSI/SCI/Timer Grounds: PLL PLL Ground plane Clock CLKOUT4 PCAP After Reset NMI Interrupt/ Mode Control 8 Host Interface (HI08) Port1 Enhanced Synchronous Serial Interface Port 0 (ESSI0)2 3 Enhanced Synchronous Serial Interface Port 1 (ESSI1)2 3 During Reset MODA MODB MODC MODD RESET After Reset IRQA IRQB IRQC IRQD RESET Non-Multiplexed Bus H[0–7] HA0 HA1 HA2 HCS/HCS Single DS HRW HDS/HDS Single HR HREQ/HREQ HACK/HACK Multiplexed Bus HAD[0–7] HAS/HAS HA8 HA9 HA10 Double DS HRD/HRD HWR/HWR Double HR HTRQ/HTRQ HRRQ/HRRQ SC0[0–2] SCK0 SRD0 STD0 Port C GPIO PC[0–2] PC3 PC4 PC5 SC1[0–2] SCK1 SRD1 STD1 Port D GPIO PD[0–2] PD3 PD4 PD5 RXD TXD SCLK Port E GPIO PE0 PE1 PE2 PLL Port B GPIO PB[0–7] PB8 PB9 PB10 PB13 PB11 PB12 PB14 PB15 Port A A[0–17] D[0–23] AA0/RAS0– AA3/RAS34 RD WR TA BR BG BB CAS4 BCLK4 BCLK4 Notes: 1. 2. 3. 4. 18 24 4 External Address Bus External Data Bus External Bus Control Serial Communications Interface (SCI) Port2 Timers3 TIO0 TIO1 TIO2 TCK TDI TDO TMS TRST DE The HI08 port supports a non-multiplexed or a multiplexed bus, single or double Data Strobe (DS), and single or double Host Request (HR) configurations. Since each of these modes is configured independently, any combination of these modes is possible. These HI08 signals can also be configured alternatively as GPIO signals (PB[0–15]). Signals with dual designations (for example, HAS/HAS) have configurable polarity. The ESSI0, ESSI1, and SCI signals are multiplexed with the Port C GPIO signals (PC[0–5]), Port D GPIO signals (PD[0–5]), and Port E GPIO signals (PE[0–2]), respectively. TIO[0–2] can be configured as GPIO signals. CLKOUT, BCLK, BCLK, CAS, and RAS[0–3] are valid only for operating frequencies ≤ 100 MHz. OnCE/ JTAG Port Figure 1-1. Signals Identified by Functional Group 1-2 Timer GPIO TIO0 TIO1 TIO2 Power 1.2 Power Table 1-2. Power Inputs Power Name Description VCCP PLL Power—VCC dedicated for PLL use. The voltage should be well-regulated and the input should be provided with an extremely low impedance path to the VCC power rail. VCCQL Quiet Core (Low) Power—An isolated power for the core processing logic. This input must be isolated externally from all other chip power inputs. VCCQH Quiet External (High) Power—A quiet power source for I/O lines. This input must be tied externally to all other chip power inputs, except VCCQL. VCCA Address Bus Power—An isolated power for sections of the address bus I/O drivers. This input must be tied externally to all other chip power inputs, except VCCQL. VCCD Data Bus Power—An isolated power for sections of the data bus I/O drivers. This input must be tied externally to all other chip power inputs, except VCCQL. VCCC Bus Control Power—An isolated power for the bus control I/O drivers. This input must be tied externally to all other chip power inputs, except VCCQL. VCCH Host Power—An isolated power for the HI08 I/O drivers. This input must be tied externally to all other chip power inputs, except VCCQL. VCCS ESSI, SCI, and Timer Power—An isolated power for the ESSI, SCI, and timer I/O drivers. This input must be tied externally to all other chip power inputs, except VCCQL. Note: The user must provide adequate external decoupling capacitors for all power connections. 1.3 Ground Table 1-3. Grounds Ground Name Description GNDP PLL Ground—Ground-dedicated for PLL use. The connection should be provided with an extremely low-impedance path to ground. VCCP should be bypassed to GNDP by a 0.47 µF capacitor located as close as possible to the chip package. GNDP1 PLL Ground 1—Ground-dedicated for PLL use. The connection should be provided with an extremely low-impedance path to ground. GND Ground—Connected to an internal device ground plane. Note: The user must provide adequate external decoupling capacitors for all GND connections. 1-3 Clock 1.4 Clock Table 1-4. Clock Signals Signal Name State During Reset Type Signal Description EXTAL Input Input External Clock/Crystal Input—Interfaces the internal crystal oscillator input to an external crystal or an external clock. XTAL Output Chip-driven Crystal Output—Connects the internal crystal oscillator output to an external crystal. If an external clock is used, leave XTAL unconnected. 1.5 PLL Table 1-5. Phase-Locked Loop Signals Signal Name CLKOUT Type Output State During Reset Chip-driven Signal Description Clock Output—Provides an output clock synchronized to the internal core clock phase. If the PLL is enabled and both the multiplication and division factors equal one, then CLKOUT is also synchronized to EXTAL. If the PLL is disabled, the CLKOUT frequency is half the frequency of EXTAL. Note: At operating frequencies above 100 MHz, this signal produces a low-amplitude waveform that is not usable externally by other devices. Above 100 MHz, you can use the asynchronous bus arbitration option that is enabled by the Asynchronous Bus Arbitration Enable (ABE) bit in the Operating Mode Register. When set, the DSP enters the Asynchronous Arbitration mode, which eliminates the BB and BG set-up and hold time requirements with respect to CLKOUT. PCAP Input Input PLL Capacitor—An input connecting an off-chip capacitor to the PLL filter. Connect one capacitor terminal to PCAP and the other terminal to VCCP. If the PLL is not used, PCAP can be tied to VCC, GND, or left floating. 1-4 PINIT Input NMI Input Input PLL Initial—During assertion of RESET, the value of PINIT is written into the PLL enable (PEN) bit of the PLL control (PCTL) register, determining whether the PLL is enabled or disabled. Nonmaskable Interrupt—After RESET deassertion and during normal instruction processing, this Schmitt-trigger input is the negative-edge-triggered NMI request internally synchronized to CLKOUT. External Memory Expansion Port (Port A) 1.6 External Memory Expansion Port (Port A) Note: When the DSP56311 enters a low-power standby mode (stop or wait), it releases bus mastership and tri-states the relevant Port A signals: A[0–17], D[0–23], AA0/RAS0–AA3/RAS3, RD, WR, BB, CAS. 1.6.1 External Address Bus Table 1-6. External Address Bus Signals Signal Name A[0–17] Type Output State During Reset, Stop, or Wait Tri-stated Signal Description Address Bus—When the DSP is the bus master, A[0–17] are active-high outputs that specify the address for external program and data memory accesses. Otherwise, the signals are tri-stated. To minimize power dissipation, A[0–17] do not change state when external memory spaces are not being accessed. 1.6.2 External Data Bus Table 1-7. External Data Bus Signals Signal Name D[0–23] Type Input/ Output State During Reset Ignored Input State During Stop or Wait Last state: Input: Ignored Output: Last value Signal Description Data Bus—When the DSP is the bus master, D[0–23] are active-high, bidirectional input/outputs that provide the bidirectional data bus for external program and data memory accesses. Otherwise, D[0–23] drivers are tri-stated. If the last state is output, these lines have weak keepers to maintain the last output state if all drivers are tri-stated. 1-5 External Memory Expansion Port (Port A) 1.6.3 External Bus Control Table 1-8. External Bus Control Signals Signal Name AA[0–3] Type Output State During Reset, Stop, or Wait Tri-stated Signal Description Address Attribute—When defined as AA, these signals can be used as chip selects or additional address lines. The default use defines a priority scheme under which only one AA signal can be asserted at a time. Setting the AA priority disable (APD) bit (Bit 14) of the Operating Mode Register, the priority mechanism is disabled and the lines can be used together as four external lines that can be decoded externally into 16 chip select signals. Row Address Strobe—When defined as RAS, these signals can be used as RAS for DRAM interface. These signals are tri-statable outputs with programmable polarity. RAS[0–3] Output Note: DRAM access is not supported above 100 MHz. RD Output Tri-stated Read Enable—When the DSP is the bus master, RD is an active-low output that is asserted to read external memory on the data bus (D[0–23]). Otherwise, RD is tri-stated. WR Output Tri-stated Write Enable—When the DSP is the bus master, WR is an active-low output that is asserted to write external memory on the data bus (D[0–23]). Otherwise, the signals are tri-stated. TA Input Ignored Input Transfer Acknowledge—If the DSP56311 is the bus master and there is no external bus activity, or the DSP56311 is not the bus master, the TA input is ignored. The TA input is a data transfer acknowledge (DTACK) function that can extend an external bus cycle indefinitely. Any number of wait states (1, 2. . .infinity) can be added to the wait states inserted by the bus control register (BCR) by keeping TA deasserted. In typical operation, TA is deasserted at the start of a bus cycle, is asserted to enable completion of the bus cycle, and is deasserted before the next bus cycle. The current bus cycle completes one clock period after TA is asserted synchronous to CLKOUT. The number of wait states is determined by the TA input or by the BCR, whichever is longer. The BCR can be used to set the minimum number of wait states in external bus cycles. To use the TA functionality, the BCR must be programmed to at least one wait state. A zero wait state access cannot be extended by TA deassertion; otherwise, improper operation may result. TA can operate synchronously or asynchronously depending on the setting of the TAS bit in the Operating Mode Register. TA functionality cannot be used during DRAM type accesses; otherwise improper operation may result. BR Output Reset: Output (deasserted) State during Stop/Wait depends on BRH bit setting: • BRH = 0: Output, deasserted • BRH = 1: Maintains last state (that is, if asserted, remains asserted) 1-6 Bus Request—Asserted when the DSP requests bus mastership. BR is deasserted when the DSP no longer needs the bus. BR may be asserted or deasserted independently of whether the DSP56311 is a bus master or a bus slave. Bus “parking” allows BR to be deasserted even though the DSP56311 is the bus master. (See the description of bus “parking” in the BB signal description.) The bus request hold (BRH) bit in the BCR allows BR to be asserted under software control even though the DSP does not need the bus. BR is typically sent to an external bus arbitrator that controls the priority, parking, and tenure of each master on the same external bus. BR is affected only by DSP requests for the external bus, never for the internal bus. During hardware reset, BR is deasserted and the arbitration is reset to the bus slave state. External Memory Expansion Port (Port A) Table 1-8. External Bus Control Signals (Continued) Signal Name BG Type Input State During Reset, Stop, or Wait Ignored Input Signal Description Bus Grant—Asserted by an external bus arbitration circuit when the DSP56311 becomes the next bus master. When BG is asserted, the DSP56311 must wait until BB is deasserted before taking bus mastership. When BG is deasserted, bus mastership is typically given up at the end of the current bus cycle. This may occur in the middle of an instruction that requires more than one external bus cycle for execution. The default operation of this bit requires a set-up and hold time as specified in Chapter 2. An alternate mode can be invoked: set the asynchronous bus arbitration enable (ABE) bit (Bit 13) in the Operating Mode Register. When this bit is set, BG and BB are synchronized internally. This eliminates the respective set-up and hold time requirements but adds a required delay between the deassertion of an initial BG input and the assertion of a subsequent BG input. BB Input/ Output Ignored Input Bus Busy—Indicates that the bus is active. Only after BB is deasserted can the pending bus master become the bus master (and then assert the signal again). The bus master may keep BB asserted after ceasing bus activity regardless of whether BR is asserted or deasserted. Called “bus parking,” this allows the current bus master to reuse the bus without rearbitration until another device requires the bus. BB is deasserted by an “active pull-up” method (that is, BB is driven high and then released and held high by an external pull-up resistor). The default operation of this signal requires a set-up and hold time as specified in Chapter 2. An alternative mode can be invoked by setting the ABE bit (Bit 13) in the Operating Mode Register. When this bit is set, BG and BB are synchronized internally. See BG for additional information. Note: BB requires an external pull-up resistor. CAS Output Tri-stated Column Address Strobe—When the DSP is the bus master, CAS is an active-low output used by DRAM to strobe the column address. Otherwise, if the Bus Mastership Enable (BME) bit in the DRAM control register is cleared, the signal is tri-stated. Note: DRAM access is not supported above 100 MHz. BCLK Output Tri-stated Bus Clock When the DSP is the bus master, BCLK is active when the ATE bit in the Operating Mode Register is set. When BCLK is active and synchronized to CLKOUT by the internal PLL, BCLK precedes CLKOUT by one-fourth of a clock cycle. Note: At operating frequencies above 100 MHz, this signal produces a low-amplitude waveform that is not usable externally by other devices. BCLK Output Tri-stated Bus Clock Not When the DSP is the bus master, BCLK is the inverse of the BCLK signal. Otherwise, the signal is tri-stated. Note: At operating frequencies above 100 MHz, this signal produces a low-amplitude waveform that is not usable externally by other devices. 1-7 Interrupt and Mode Control 1.7 Interrupt and Mode Control The interrupt and mode control signals select the chip operating mode as it comes out of hardware reset. After RESET is deasserted, these inputs are hardware interrupt request lines. Table 1-9. Interrupt and Mode Control Signal Name 1-8 Type MODA Input IRQA Input MODB Input IRQB Input MODC Input IRQC Input MODD Input IRQD Input RESET Input State During Reset Schmitt-trigger Input Signal Description Mode Select A—MODA, MODB, MODC, and MODD select one of 16 initial chip operating modes, latched into the Operating Mode Register when the RESET signal is deasserted. External Interrupt Request A—After reset, this input becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. If the processor is in the STOP or WAIT standby state and IRQA is asserted, the processor exits the STOP or WAIT state. Schmitt-trigger Input Mode Select B—MODA, MODB, MODC, and MODD select one of 16 initial chip operating modes, latched into the Operating Mode Register when the RESET signal is deasserted. External Interrupt Request B—After reset, this input becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. If the processor is in the WAIT standby state and IRQB is asserted, the processor exits the WAIT state. Schmitt-trigger Input Mode Select C—MODA, MODB, MODC, and MODD select one of 16 initial chip operating modes, latched into the Operating Mode Register when the RESET signal is deasserted. External Interrupt Request C—After reset, this input becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. If the processor is in the WAIT standby state and IRQC is asserted, the processor exits the WAIT state. Schmitt-trigger Input Mode Select D—MODA, MODB, MODC, and MODD select one of 16 initial chip operating modes, latched into the Operating Mode Register when the RESET signal is deasserted. External Interrupt Request D—After reset, this input becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. If the processor is in the WAIT standby state and IRQD is asserted, the processor exits the WAIT state. Schmitt-trigger Input Reset—Places the chip in the Reset state and resets the internal phase generator. The Schmitt-trigger input allows a slowly rising input (such as a capacitor charging) to reset the chip reliably. When the RESET signal is deasserted, the initial chip operating mode is latched from the MODA, MODB, MODC, and MODD inputs. The RESET signal must be asserted after powerup. Host Interface (HI08) 1.8 Host Interface (HI08) The HI08 provides a fast, 8-bit, parallel data port that connects directly to the host bus. The HI08 supports a variety of standard buses and connects directly to a number of industry-standard microcomputers, microprocessors, DSPs, and DMA hardware. 1.8.4 Host Port Usage Considerations Careful synchronization is required when the system reads multiple-bit registers that are written by another asynchronous system. This is a common problem when two asynchronous systems are connected (as they are in the Host port). The considerations for proper operation are discussed in Table 1-10. Table 1-10. Host Port Usage Considerations Action Description Asynchronous read of receive byte registers When reading the receive byte registers, Receive register High (RXH), Receive register Middle (RXM), or Receive register Low (RXL), the host interface programmer should use interrupts or poll the Receive register Data Full (RXDF) flag that indicates data is available. This assures that the data in the receive byte registers is valid. Asynchronous write to transmit byte registers The host interface programmer should not write to the transmit byte registers, Transmit register High (TXH), Transmit register Middle (TXM), or Transmit register Low (TXL), unless the Transmit register Data Empty (TXDE) bit is set indicating that the transmit byte registers are empty. This guarantees that the transmit byte registers transfer valid data to the Host Receive (HRX) register. Asynchronous write to host vector The host interface programmer must change the Host Vector (HV) register only when the Host Command bit (HC) is clear. This practice guarantees that the DSP interrupt control logic receives a stable vector. 1.8.5 Host Port Configuration HI08 signal functions vary according to the programmed configuration of the interface as determined by the 16 bits in the HI08 Port Control Register. Refer to the DSP56311 User’s Manual for details on HI08 configuration registers. Table 1-11. Host Interface Type State During Reset1,2 H[0–7] Input/Output Ignored Input HAD[0–7] Input/Output Host Address—When the HI08 is programmed to interface with a multiplexed host bus and the host interface function is selected, these signals are lines 0–7 of the bidirectional multiplexed Address/Data bus. Input or Output Port B 0–7—When the HI08 is configured as GPIO through the HI08 Port Control Register, these signals are individually through the HI08 Data Direction Register programmed as inputs or outputs. Signal Name PB[0–7] Signal Description Host Data—When the HI08 is programmed to interface with a non-multiplexed host bus and the host interface function is selected, these signals are lines 0–7 of the bidirectional Data bus. 1-9 Host Interface (HI08) Table 1-11. Host Interface (Continued) 1-10 Signal Name Type State During Reset1,2 HA0 Input Ignored Input HAS/HAS Input Host Address Strobe—When the HI08 is programmed to interface with a multiplexed host bus and the host interface function is selected, this signal is the host address strobe (HAS) Schmitt-trigger input. The polarity of the address strobe is programmable but is configured active-low (HAS) following reset. PB8 Input or Output Port B 8—When the HI08 is configured as GPIO through the HI08 Port Control Register, this signal is individually programmed through the HI08 Data Direction Register as an input or output. HA1 Input HA8 Input Host Address 8—When the HI08 is programmed to interface with a multiplexed host bus and the host interface function is selected, this signal is line 8 of the host address (HA8) input bus. PB9 Input or Output Port B 9—When the HI08 is configured as GPIO through the HI08 Port Control Register, this signal is individually programmed through the HI08 Data Direction Register as an input or output. HA2 Input HA9 Input Host Address 9—When the HI08 is programmed to interface with a multiplexed host bus and the host interface function is selected, this signal is line 9 of the host address (HA9) input bus. PB10 Input or Output Port B 10—When the HI08 is configured as GPIO through the HI08 Port Control Register, this signal is individually programmed through the HI08 Data Direction Register as an input or output. HCS/HCS Input HA10 Input PB13 Input or Output Ignored Input Ignored Input Ignored Input Signal Description Host Address Input 0—When the HI08 is programmed to interface with a nonmultiplexed host bus and the host interface function is selected, this signal is line 0 of the host address input bus. Host Address Input 1—When the HI08 is programmed to interface with a nonmultiplexed host bus and the host interface function is selected, this signal is line 1 of the host address (HA1) input bus. Host Address Input 2—When the HI08 is programmed to interface with a nonmultiplexed host bus and the host interface function is selected, this signal is line 2 of the host address (HA2) input bus. Host Chip Select—When the HI08 is programmed to interface with a nonmultiplexed host bus and the host interface function is selected, this signal is the host chip select (HCS) input. The polarity of the chip select is programmable but is configured active-low (HCS) after reset. Host Address 10—When the HI08 is programmed to interface with a multiplexed host bus and the host interface function is selected, this signal is line 10 of the host address (HA10) input bus. Port B 13—When the HI08 is configured as GPIO through the HI08 Port Control Register, this signal is individually programmed through the HI08 Data Direction Register as an input or output. Host Interface (HI08) Table 1-11. Host Interface (Continued) Signal Name Type State During Reset1,2 HRW Input Ignored Input HRD/HRD Input Host Read Data—When the HI08 is programmed to interface with a double-data-strobe host bus and the host interface function is selected, this signal is the HRD strobe Schmitt-trigger input. The polarity of the data strobe is programmable but is configured as active-low (HRD) after reset. Input or Output Port B 11—When the HI08 is configured as GPIO through the HI08 Port Control Register, this signal is individually programmed through the HI08 Data Direction Register as an input or output. PB11 Host Read/Write—When the HI08 is programmed to interface with a single-data-strobe host bus and the host interface function is selected, this signal is the Host Read/Write (HRW) input. HDS/HDS Input HWR/HWR Input Host Write Data—When the HI08 is programmed to interface with a double-data-strobe host bus and the host interface function is selected, this signal is the host write data strobe (HWR) Schmitt-trigger input. The polarity of the data strobe is programmable but is configured as active-low (HWR) following reset. Input or Output Port B 12—When the HI08 is configured as GPIO through the HI08 Port Control Register, this signal is individually programmed through the HI08 Data Direction Register as an input or output. PB12 HREQ/HREQ Output HTRQ/HTRQ Output PB14 Input or Output Ignored Input Signal Description Ignored Input Host Data Strobe—When the HI08 is programmed to interface with a single-data-strobe host bus and the host interface function is selected, this signal is the host data strobe (HDS) Schmitt-trigger input. The polarity of the data strobe is programmable but is configured as active-low (HDS) following reset. Host Request—When the HI08 is programmed to interface with a single host request host bus and the host interface function is selected, this signal is the host request (HREQ) output. The polarity of the host request is programmable but is configured as active-low (HREQ) following reset. The host request may be programmed as a driven or open-drain output. Transmit Host Request—When the HI08 is programmed to interface with a double host request host bus and the host interface function is selected, this signal is the transmit host request (HTRQ) output. The polarity of the host request is programmable but is configured as active-low (HTRQ) following reset. The host request may be programmed as a driven or open-drain output. Port B 14—When the HI08 is configured as GPIO through the HI08 Port Control Register, this signal is individually programmed through the HI08 Data Direction Register as an input or output. 1-11 Host Interface (HI08) Table 1-11. Host Interface (Continued) Signal Name Type State During Reset1,2 HACK/HACK Input Ignored Input HRRQ/HRRQ Output PB15 Signal Description Host Acknowledge—When the HI08 is programmed to interface with a single host request host bus and the host interface function is selected, this signal is the host acknowledge (HACK) Schmitt-trigger input. The polarity of the host acknowledge is programmable but is configured as active-low (HACK) after reset. Receive Host Request—When the HI08 is programmed to interface with a double host request host bus and the host interface function is selected, this signal is the receive host request (HRRQ) output. The polarity of the host request is programmable but is configured as active-low (HRRQ) after reset. The host request may be programmed as a driven or open-drain output. Input or Output Port B 15—When the HI08 is configured as GPIO through the HI08 Port Control Register, this signal is individually programmed through the HI08 Data Direction Register as an input or output. Notes: 1. 2. 1-12 In the Stop state, the signal maintains the last state as follows: • If the last state is input, the signal is an ignored input. • If the last state is output, these lines have weak keepers that maintain the last output state even if the drivers are tri-stated. The Wait processing state does not affect the signal state. Enhanced Synchronous Serial Interface 0 (ESSI0) 1.9 Enhanced Synchronous Serial Interface 0 (ESSI0) Two synchronous serial interfaces (ESSI0 and ESSI1) provide a full-duplex serial port for serial communication with a variety of serial devices, including one or more industry-standard codecs, other DSPs, microprocessors, and peripherals that implement the Motorola serial peripheral interface (SPI). Table 1-12. Enhanced Synchronous Serial Interface 0 Type State During Reset1,2 SC00 Input or Output Ignored Input PC0 Input or Output SC01 Input/Output PC1 Input or Output SC02 Input/Output PC2 Input or Output SCK0 Input/Output Signal Name Signal Description Serial Control 0—For asynchronous mode, this signal is used for the receive clock I/O (Schmitt-trigger input). For synchronous mode, this signal is used either for transmitter 1 output or for serial I/O flag 0. Port C 0—The default configuration following reset is GPIO input PC0. When configured as PC0, signal direction is controlled through the Port C Direction Register. The signal can be configured as ESSI signal SC00 through the Port C Control Register . Ignored Input Serial Control 1—For asynchronous mode, this signal is the receiver frame sync I/O. For synchronous mode, this signal is used either for transmitter 2 output or for serial I/O flag 1. Port C 1—The default configuration following reset is GPIO input PC1. When configured as PC1, signal direction is controlled through the Port C Direction Register. The signal can be configured as an ESSI signal SC01 through the Port C Control Register. Ignored Input Serial Control Signal 2—The frame sync for both the transmitter and receiver in synchronous mode, and for the transmitter only in asynchronous mode. When configured as an output, this signal is the internally generated frame sync signal. When configured as an input, this signal receives an external frame sync signal for the transmitter (and the receiver in synchronous operation). Port C 2—The default configuration following reset is GPIO input PC2. When configured as PC2, signal direction is controlled through the Port C Direction Register. The signal can be configured as an ESSI signal SC02 through the Port C Control Register. Ignored Input Serial Clock—Provides the serial bit rate clock for the ESSI. The SCK0 is a clock input or output, used by both the transmitter and receiver in synchronous modes or by the transmitter in asynchronous modes. Although an external serial clock can be independent of and asynchronous to the DSP system clock, it must exceed the minimum clock cycle time of 6T (that is, the system clock frequency must be at least three times the external ESSI clock frequency). The ESSI needs at least three DSP phases inside each half of the serial clock. PC3 Input or Output Port C 3—The default configuration following reset is GPIO input PC3. When configured as PC3, signal direction is controlled through the Port C Direction Register. The signal can be configured as an ESSI signal SCK0 through the Port C Control Register. 1-13 Enhanced Synchronous Serial Interface 1 (ESSI1) Table 1-12. Enhanced Synchronous Serial Interface 0 (Continued) Signal Name Type SRD0 Input PC4 Input or Output STD0 Output PC5 Input or Output Notes: 1. 2. State During Reset1,2 Ignored Input Signal Description Serial Receive Data—Receives serial data and transfers the data to the ESSI receive shift register. SRD0 is an input when data is received. Port C 4—The default configuration following reset is GPIO input PC4. When configured as PC4, signal direction is controlled through the Port C Direction Register. The signal can be configured as an ESSI signal SRD0 through the Port C Control Register. Ignored Input Serial Transmit Data—Transmits data from the serial transmit shift register. STD0 is an output when data is transmitted. Port C 5—The default configuration following reset is GPIO input PC5. When configured as PC5, signal direction is controlled through the Port C Direction Register. The signal can be configured as an ESSI signal STD0 through the Port C Control Register. In the Stop state, the signal maintains the last state as follows: • If the last state is input, the signal is an ignored input. • If the last state is output, these lines have weak keepers that maintain the last output state even if the drivers are tri-stated. The Wait processing state does not affect the signal state. 1.10 Enhanced Synchronous Serial Interface 1 (ESSI1) Table 1-13. Enhanced Serial Synchronous Interface 1 Type State During Reset1,2 SC10 Input or Output Ignored Input PD0 Input or Output SC11 Input/Output PD1 Input or Output Signal Name 1-14 Signal Description Serial Control 0—For asynchronous mode, this signal is used for the receive clock I/O (Schmitt-trigger input). For synchronous mode, this signal is used either for transmitter 1 output or for serial I/O flag 0. Port D 0—The default configuration following reset is GPIO input PD0. When configured as PD0, signal direction is controlled through the Port D Direction Register. The signal can be configured as an ESSI signal SC10 through the Port D Control Register. Ignored Input Serial Control 1—For asynchronous mode, this signal is the receiver frame sync I/O. For synchronous mode, this signal is used either for Transmitter 2 output or for Serial I/O Flag 1. Port D 1—The default configuration following reset is GPIO input PD1. When configured as PD1, signal direction is controlled through the Port D Direction Register. The signal can be configured as an ESSI signal SC11 through the Port D Control Register. Enhanced Synchronous Serial Interface 1 (ESSI1) Table 1-13. Enhanced Serial Synchronous Interface 1 (Continued) Signal Name Type SC12 Input/Output PD2 Input or Output SCK1 Input/Output State During Reset1,2 Ignored Input Signal Description Serial Control Signal 2—The frame sync for both the transmitter and receiver in synchronous mode and for the transmitter only in asynchronous mode. When configured as an output, this signal is the internally generated frame sync signal. When configured as an input, this signal receives an external frame sync signal for the transmitter (and the receiver in synchronous operation). Port D 2—The default configuration following reset is GPIO input PD2. When configured as PD2, signal direction is controlled through the Port D Direction Register. The signal can be configured as an ESSI signal SC12 through the Port D Control Register. Ignored Input Serial Clock—Provides the serial bit rate clock for the ESSI. The SCK1 is a clock input or output used by both the transmitter and receiver in synchronous modes or by the transmitter in asynchronous modes. Although an external serial clock can be independent of and asynchronous to the DSP system clock, it must exceed the minimum clock cycle time of 6T (that is, the system clock frequency must be at least three times the external ESSI clock frequency). The ESSI needs at least three DSP phases inside each half of the serial clock. PD3 Input or Output SRD1 Input PD4 Input or Output STD1 Output PD5 Input or Output Notes: 1. 2. Port D 3—The default configuration following reset is GPIO input PD3. When configured as PD3, signal direction is controlled through the Port D Direction Register. The signal can be configured as an ESSI signal SCK1 through the Port D Control Register. Ignored Input Serial Receive Data—Receives serial data and transfers the data to the ESSI receive shift register. SRD1 is an input when data is being received. Port D 4—The default configuration following reset is GPIO input PD4. When configured as PD4, signal direction is controlled through the Port D Direction Register. The signal can be configured as an ESSI signal SRD1 through the Port D Control Register. Ignored Input Serial Transmit Data—Transmits data from the serial transmit shift register. STD1 is an output when data is being transmitted. Port D 5—The default configuration following reset is GPIO input PD5. When configured as PD5, signal direction is controlled through the Port D Direction Register. The signal can be configured as an ESSI signal STD1 through the Port D Control Register. In the Stop state, the signal maintains the last state as follows: • If the last state is input, the signal is an ignored input. • If the last state is output, these lines have weak keepers that maintain the last output state even if the drivers are tri-stated. The Wait processing state does not affect the signal state. 1-15 Serial Communication Interface (SCI) 1.11 Serial Communication Interface (SCI) The SCI provides a full duplex port for serial communication with other DSPs, microprocessors, or peripherals such as modems. Table 1-14. Serial Communication Interface Signal Name RXD Input PE0 Input or Output TXD Output PE1 Input or Output SCLK Input/Output PE2 Input or Output Notes: 1. 2. 1-16 Type State During Reset1,2 Ignored Input Signal Description Serial Receive Data—Receives byte-oriented serial data and transfers it to the SCI receive shift register. Port E 0—The default configuration following reset is GPIO input PE0. When configured as PE0, signal direction is controlled through the Port E Direction Register. The signal can be configured as an SCI signal RXD through the Port E Control Register. Ignored Input Serial Transmit Data—Transmits data from the SCI transmit data register. Port E 1—The default configuration following reset is GPIO input PE1. When configured as PE1, signal direction is controlled through the Port E Direction Register. The signal can be configured as an SCI signal TXD through the Port E Control Register. Ignored Input Serial Clock—Provides the input or output clock used by the transmitter and/or the receiver. Port E 2—The default configuration following reset is GPIO input PE2. When configured as PE2, signal direction is controlled through the Port E Direction Register. The signal can be configured as an SCI signal SCLK through the Port E Control Register. In the Stop state, the signal maintains the last state as follows: • If the last state is input, the signal is an ignored input. • If the last state is output, these lines have weak keepers that maintain the last output state even if the drivers are tri-stated. The Wait processing state does not affect the signal state. Timers 1.12 Timers The DSP56311 has three identical and independent timers. Each timer can use internal or external clocking and can either interrupt the DSP56311 after a specified number of events (clocks) or signal an external device after counting a specific number of internal events. Table 1-15. Triple Timer Signals Signal Name TIO0 Type State During Reset1,2 Input or Output Ignored Input Signal Description Timer 0 Schmitt-Trigger Input/Output— When Timer 0 functions as an external event counter or in measurement mode, TIO0 is used as input. When Timer 0 functions in watchdog, timer, or pulse modulation mode, TIO0 is used as output. The default mode after reset is GPIO input. TIO0 can be changed to output or configured as a timer I/O through the Timer 0 Control/Status Register. TIO1 Input or Output Ignored Input Timer 1 Schmitt-Trigger Input/Output— When Timer 1 functions as an external event counter or in measurement mode, TIO1 is used as input. When Timer 1 functions in watchdog, timer, or pulse modulation mode, TIO1 is used as output. The default mode after reset is GPIO input. TIO1 can be changed to output or configured as a timer I/O through the Timer 1 Control/Status Register. TIO2 Input or Output Ignored Input Timer 2 Schmitt-Trigger Input/Output— When Timer 2 functions as an external event counter or in measurement mode, TIO2 is used as input. When Timer 2 functions in watchdog, timer, or pulse modulation mode, TIO2 is used as output. The default mode after reset is GPIO input. TIO2 can be changed to output or configured as a timer I/O through the Timer 2 Control/Status Register. Notes: 1. 2. In the Stop state, the signal maintains the last state as follows: • If the last state is input, the signal is an ignored input. • If the last state is output, these lines have weak keepers that maintain the last output state even if the drivers are tri-stated. The Wait processing state does not affect the signal state. 1-17 JTAG and OnCE Interface 1.13 JTAG and OnCE Interface The DSP56300 family and in particular the DSP56311 support circuit-board test strategies based on the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture, the industry standard developed under the sponsorship of the Test Technology Committee of IEEE and the JTAG. The OnCE module provides a means to interface nonintrusively with the DSP56300 core and its peripherals so that you can examine registers, memory, or on-chip peripherals. Functions of the OnCE module are provided through the JTAG TAP signals. For programming models, see the chapter on debugging support in the DSP56300 Family Manual. Table 1-16. JTAG/OnCE Interface Type State During Reset TCK Input Input Test Clock—A test clock input signal to synchronize the JTAG test logic. TDI Input Input Test Data Input—A test data serial input signal for test instructions and data. TDI is sampled on the rising edge of TCK and has an internal pull-up resistor. TDO Output Tri-stated Test Data Output—A test data serial output signal for test instructions and data. TDO is actively driven in the shift-IR and shift-DR controller states. TDO changes on the falling edge of TCK. TMS Input Input Test Mode Select—Sequences the test controller’s state machine. TMS is sampled on the rising edge of TCK and has an internal pull-up resistor. TRST Input Input Test Reset—Initializes the test controller asynchronously. TRST has an internal pull-up resistor. TRST must be asserted after powerup. Input/ Output (open-drain) Input Debug Event—As an input, initiates the debug mode of operation from an external command controller, and, as an open-drain output, acknowledges that the chip has entered Debug mode. As an input, DE causes the DSP56300 core to finish executing the current instruction, save the instruction pipeline information, enter Debug mode, and wait for commands to be entered from the debug serial input line. This signal is asserted as an output for three clock cycles when the chip enters Debug mode as a result of a debug request or as a result of meeting a breakpoint condition. The DE has an internal pull-up resistor. Signal Name DE Signal Description This signal is not a standard part of the JTAG TAP controller. The signal connects directly to the OnCE module to initiate debug mode directly or to provide a direct external indication that the chip has entered Debug mode. All other interface with the OnCE module must occur through the JTAG port. 1-18 Chapter 2 Specifications 2.1 Introduction The DSP56311 is fabricated in high-density CMOS with Transistor-Transistor Logic (TTL) compatible inputs and outputs. 2.2 Maximum Ratings CAUTION This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, normal precautions should be taken to avoid exceeding maximum voltage ratings. Reliability is enhanced if unused inputs are tied to an appropriate logic voltage level (for example, either GND or VCC). Note: In the calculation of timing requirements, adding a maximum value of one specification to a minimum value of another specification does not yield a reasonable sum. A maximum specification is calculated using a worst case variation of process parameter values in one direction. The minimum specification is calculated using the worst case for the same parameters in the opposite direction. Therefore, a “maximum” value for a specification never occurs in the same device that has a “minimum” value for another specification; adding a maximum to a minimum represents a condition that can never exist. 2-1 Thermal Characteristics Table 2-1. Absolute Maximum Ratings Rating1 Supply Voltage Input/Output Supply Voltage Symbol Value1, 2 Unit VCC –0.1 to 2.0 V VCCQH –0.3 to 4.0 V VIN GND – 0.3 to VCCQH + 0.3 V I 10 mA TJ –40 to +100 °C TSTG –55 to +150 °C All input voltages Current drain per pin excluding VCC and GND Operating temperature range Storage temperature Notes: 1. 2. 3. GND = 0 V, VCC = 1.8 V ± 0.1 V, VCCQH = 3.3 V ± 0.3 V, TJ = –40°C to +100°C, CL = 50 pF Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond the maximum rating may affect device reliability or cause permanent damage to the device. Power-up sequence: During power-up, and throughout the DSP56311 operation, VCCQH voltage must always be higher or equal to VCC voltage. 2.3 Thermal Characteristics Table 2-2. Thermal Characteristics Symbol MAP-BGA Value RθJA 49 RθJMA 26 Junction-to-ambient, @200 ft/min air flow, single layer board (1s) RθJMA 39 Junction-to-ambient, @200 ft/min air flow, four-layer board (2s2p)1,3 RθJMA 22 RθJB 14 RθJC 5 Junction-to-package-top, natural convection ΨJT 2 Junction-to-package-top, @200 ft/min air flow6 ΨJT 2 Characteristic Junction-to-ambient, natural convection, single-layer board (1s)1,2 Junction-to-ambient, natural convection, four-layer board (2s2p)1,3 1,3 Junction-to-board4 Junction-to-case thermal resistance 5 6 Notes: 1. 2. 3. 4. 5. 6. 2-2 Unit °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal. Per JEDEC JESD51-6 with the board horizontal. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. DC Electrical Characteristics 2.4 DC Electrical Characteristics Table 2-3. DC Electrical Characteristics Characteristics Symbol Min Typ Max Unit 1.7 3.0 1.8 3.3 1.9 3.6 V V VIH VIHP 2.0 2.0 — — VCCQH + 0.3 VCCQH + 0.3 V V VIHX 0.8 × VCCQH — VCCQH V VIL VILP VILX –0.3 –0.3 –0.3 — — — 0.8 0.8 0.2 × VCCQH V V V Input leakage current IIN –10 — 10 µA High impedance (off-state) input current (@ 2.4 V / 0.4 V) ITSI –10 — 10 µA Output high voltage • TTL (IOH = –0.4 mA)5,7 • CMOS (IOH = –10 µA)5 VOH 2.4 VCC – 0.01 — — — — V V Output low voltage • TTL (IOL = 3.0 mA, open-drain pins IOL = 6.7 mA)5,7 • CMOS (IOL = 10 µA)5 VOL — — — — 0.4 0.01 V V ICCI ICCW ICCS — — — 150 7. 5 100 — — — mA mA µA — 1 2.5 mA CIN — — 10 pF Supply voltage: • Core (VCCQL) and PLL (VCCP) • I/O (VCCQH, VCCA, VCCD, VCCC, VCCH, and VCCS) Input high voltage • D[0–23], BG, BB, TA • MOD/IRQ1, RESET, PINIT/NMI and all JTAG/ESSI/SCI/Timer/HI08 pins • EXTAL8 Input low voltage • D[0–23], BG, BB, TA, MOD/IRQ1, RESET, PINIT • All JTAG/ESSI/SCI/Timer/HI08 pins • EXTAL8 Internal supply current2: • In Normal mode • In Wait mode3 • In Stop mode4 PLL supply current Input capacitance5 Notes: 1. 2. 3. 4. 5. 6. 7. 8. Refers to MODA/IRQA, MODB/IRQB, MODC/IRQC, and MODD/IRQD pins. Section 4.3 provides a formula to compute the estimated current requirements in Normal mode. To obtain these results, all inputs must be terminated (that is, not allowed to float). Measurements are based on synthetic intensive DSP benchmarks (see Appendix A). The power consumption numbers in this specification are 90 percent of the measured results of this benchmark. This reflects typical DSP applications. Typical internal supply current is measured with VCCQP = 3.3 V, VCC = 1.8 V at TJ = 100°C. To obtain these results, all inputs must be terminated (that is, not allowed to float). PLL and XTAL signals are disabled during Stop state. DC current in Stop mode is evaluated based on measurements. To obtain these results, all inputs not disconnected at Stop mode must be terminated (that is, not allowed to float). Periodically sampled and not 100 percent tested. VCCQH = 3.3 V ± 0.3 V, VCC = 1.8 V ± 0.1 V; TJ = –40°C to +100 °C, CL = 50 pF This characteristic does not apply to XTAL and PCAP. Driving EXTAL to the low VIHX or the high VILX value may cause additional power consumption (DC current). To minimize power consumption, the minimum VIHX should be no lower than 0.9 × VCCQH and the maximum VILX should be no higher than 0.1 × VCCQH. 2-3 AC Electrical Characteristics 2.5 AC Electrical Characteristics The timing waveforms shown in the AC electrical characteristics section are tested with a VIL maximum of 0.3 V and a VIH minimum of 2.4 V for all pins except EXTAL, which is tested using the input levels shown in Note 6 of Table 2-2. AC timing specifications, which are referenced to a device input signal, are measured in production with respect to the 50 percent point of the respective input signal’s transition. DSP56311 output levels are measured with the production test machine VOL and VOH reference levels set at 0.4 V and 2.4 V, respectively. Note: Although the minimum value for the frequency of EXTAL is 0 MHz, the device AC test conditions are 15 MHz and rated speed. 2.5.1 Internal Clocks Table 2-4. Internal Clocks Expression1, 2 Characteristics Min Typ Max Internal operation frequency with PLL enabled f — (Ef × MF)/ (PDF × DF) — Internal operation frequency with PLL disabled f — Ef/2 — TH — 0.49 × ETC × PDF × DF/MF 0.47 × ETC × PDF × DF/MF ETC — — 0.51 × ETC × PDF × DF/MF 0.53 × ETC × PDF × DF/MF — 0.49 × ETC × PDF × DF/MF 0.47 × ETC × PDF × DF/MF ETC — Internal clock high period • With PLL disabled • With PLL enabled and MF ≤ 4 • With PLL enabled and MF > 4 Internal clock low period • With PLL disabled • With PLL enabled and MF ≤ 4 • With PLL enabled and MF > 4 TL — — — 0.51 × ETC × PDF × DF/MF 0.53 × ETC × PDF × DF/MF Internal clock cycle time with PLL enabled TC — ETC × PDF × DF/MF — Internal clock cycle time with PLL disabled TC — 2 × ETC — ICYC — TC — Instruction cycle time Notes: 1. 2. 2-4 Symbol DF = Division Factor; Ef = External frequency; ETC = External clock cycle; MF = Multiplication Factor; PDF = Predivision Factor; TC = internal clock cycle. See the PLL and Clock Generation section in the DSP56300 Family Manual for a details on the PLL. AC Electrical Characteristics 2.5.2 External Clock Operation The DSP56311 system clock is derived from the on-chip oscillator or is externally supplied. To use the on-chip oscillator, connect a crystal and associated resistor/capacitor components to EXTAL and XTAL; examples are shown in Figure 2-1. EXTAL XTAL EXTAL XTAL R R2 R1 C C XTAL1 Note: Ensure that in the PCTL Register: ■ XTLD (bit 16) = 0 ■ If fOSC ≤ 200 kHz, XTLR (bit 15) = 1 Fundamental Frequency Fork Crystal Oscillator XTAL1 C Note: Make sure that in the PCTL Register: ■ XTLD (bit 16) = 0 ■ If fOSC > 200 kHz, XTLR (bit 15) = 0 C Fundamental Frequency Crystal Oscillator Suggested Component Values: Suggested Component Values: fOSC = 32.768 kHz R1 = 3.9 MΩ ± 10% C = 22 pF ± 20% R2 = 200 kΩ ± 10% fOSC = 4 MHz R = 680 kΩ ± 10% C = 56 pF ± 20% Calculations are for a 32.768 kHz crystal with the following parameters: ■ load capacitance (CL) of 12.5 pF, ■ shunt capacitance (C0) of 1.8 pF, ■ series resistance of 40 kΩ, and ■ drive level of 1 µW. fOSC = 20 MHz R = 680 kΩ ± 10% C = 22 pF ± 20% Calculations are for a 4/20 MHz crystal with the following parameters: ■ CLof 30/20 pF, ■ C0 of 7/6 pF, ■ series resistance of 100/20 Ω, and ■ drive level of 2 mW. Figure 2-1. Crystal Oscillator Circuits If an externally-supplied square wave voltage source is used, disable the internal oscillator circuit during bootup by setting XTLD (PCTL Register bit 16 = 1—see the DSP56311 User’s Manual). The external square wave source connects to EXTAL; XTAL is not physically connected to the board or socket. Figure 2-2 shows the relationship between the EXTAL input and the internal clock and CLKOUT. Midpoint EXTAL VILX ETH VIHX ETL 2 3 4 5 Note: ETC The midpoint is 0.5 (VIHX + VILX). 5 CLKOUT with PLL disabled 7 CLKOUT with PLL enabled 6a 6b 7 Figure 2-2. External Clock Timing 2-5 AC Electrical Characteristics Table 2-5. Clock Operation 150 MHz No. Characteristics Symbol Min Max Ef 0 150.0 1 Frequency of EXTAL (EXTAL Pin Frequency) The rise and fall time of this external clock should be 3 ns maximum. 2 EXTAL input high1, 2 • With PLL disabled (46.7%–53.3% duty cycle6) • With PLL enabled (42.5%–57.5% duty cycle6) ETH 3.11 ns 2.83 ns 157.0 µs EXTAL input low1, 2 • With PLL disabled (46.7%–53.3% duty cycle6) • With PLL enabled (42.5%–57.5% duty cycle6) ETL 3.11 ns 2.83 ns 157.0 µs EXTAL cycle time2 • With PLL disabled • With PLL enabled ETC 6.67 ns 6.67 ns 273.1 µs 11.0 ns 3 4 5 Internal clock change from EXTAL fall with PLL disabled 4.3 ns 6 a.Internal clock rising edge from EXTAL rising edge with PLL enabled (MF = 1 or 2 or 4, PDF = 1, Ef > 15 MHz)3,5 0.0 ns b. Internal clock falling edge from EXTAL falling edge with PLL enabled (MF ≤ 4, PDF ≠ 1, Ef / PDF > 15 MHz)3,5 0.0 ns 7 1. 2. 3. 4. 5. 6. ∞ ∞ 1.8 ns 1.8 ns Instruction cycle time = ICYC = TC4 (see Figure 2-4) (46.7%–53.3% duty cycle) • With PLL disabled • With PLL enabled Notes: ∞ ICYC 13.33 ns 6.7 ns ∞ 8.53 µs Measured at 50 percent of the input transition. The maximum value for PLL enabled is given for minimum VCO frequency (see Table 2-4) and maximum MF. Periodically sampled and not 100 percent tested. The maximum value for PLL enabled is given for minimum VCO frequency and maximum DF. The skew is not guaranteed for any other MF value. The indicated duty cycle is for the specified maximum frequency for which a part is rated. The minimum clock high or low time required for correction operation, however, remains the same at lower operating frequencies; therefore, when a lower clock frequency is used, the signal symmetry may vary from the specified duty cycle as long as the minimum high time and low time requirements are met. 2.5.3 Phase Lock Loop (PLL) Characteristics Table 2-6. PLL Characteristics 150 MHz Characteristics Voltage Controlled Oscillator (VCO) frequency when PLL enabled (MF × Ef × 2/PDF) PLL external capacitor (PCAP pin to VCCP) (CPCAP1) • @ MF ≤ 4 • @ MF > 4 Note: 2-6 Unit Min Max 30 300 MHz (580 × MF) − 100 830 × MF (780 × MF) − 140 1470 × MF pF pF CPCAP is the value of the PLL capacitor (connected between the PCAP pin and VCCP) computed using the appropriate expression listed above. AC Electrical Characteristics 2.5.4 Reset, Stop, Mode Select, and Interrupt Timing Table 2-7. Reset, Stop, Mode Select, and Interrupt Timing6 150 MHz No. Characteristics 8 Delay from RESET assertion to all pins at reset value3 9 Required RESET duration4 • Power on, external clock generator, PLL disabled • Power on, external clock generator, PLL enabled • Power on, internal oscillator • During STOP, XTAL disabled (PCTL Bit 16 = 0) • During STOP, XTAL enabled (PCTL Bit 16 = 1) • During normal operation 10 Delay from asynchronous RESET deassertion to first external address output (internal reset deassertion)5 • Minimum • Maximum Expression Unit Min Max — — 26.0 ns Minimum: 50 × ETC 1000 × ETC 75000 × ETC 75000 × ETC 2.5 × TC 2.5 × TC 333.3 6.67 0.50 0.50 16.7 16.7 — — — — — — ns µs ms ms ns ns 3.25 × TC + 2.0 20.25 × TC + 10 23.7 — — 145.0 ns ns 13 Mode select set-up time 30.0 — ns 14 Mode select hold time 0.0 — ns 15 Minimum edge-triggered interrupt request assertion width 6.6 — ns 16 Minimum edge-triggered interrupt request deassertion width 6.6 — ns 17 Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to external memory access address out valid • Caused by first interrupt instruction fetch • Caused by first interrupt instruction execution Minimum: 4.25 × TC + 2.0 7.25 × TC + 2.0 30.4 51.0 — — ns ns Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to general-purpose transfer output valid caused by first interrupt instruction execution Minimum: 10 × TC + 5.0 72.0 — ns Delay from address output valid caused by first interrupt instruction execute to interrupt request deassertion for level sensitive fast interrupts1, Maximum: (WS + 3.75) × TC – 10.94 — Note 8 ns 18 19 7, 8 20 Delay from RD assertion to interrupt request deassertion for level sensitive fast interrupts1, 7, 8 Maximum: (WS + 3.25) × TC – 10.94 — Note 8 ns 21 Delay from WR assertion to interrupt request deassertion for level sensitive fast interrupts1, 7, 8 • DRAM for all WS • SRAM WS = 1 • SRAM WS = 2, 3 • SRAM WS ≥ 4 Maximum: (WS + 3.5) × TC – 10.94 (WS + 3.5) × TC – 10.94 (WS + 3) × TC – 10.94 (WS + 2.5) × TC – 10.94 — — — — Note 8 Note 8 Note 8 Note 8 ns ns ns ns 5.9 — ns PLC × ETC × PDF + (128 K − PLC/2) × TC 1.3 9.1 ms PLC × ETC × PDF + (23.75 ± 0.5) × TC (8.25 ± 0.5) × TC 232.5 ns 12.3 ms 51.7 58.3 24 Duration for IRQA assertion to recover from Stop state 25 Delay from IRQA assertion to fetch of first instruction (when exiting Stop)2, 3 • PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is enabled (Operating Mode Register Bit 6 = 0) • PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is not enabled (Operating Mode Register Bit 6 = 1) • PLL is active during Stop (PCTL Bit 17 = 1) (Implies No Stop Delay) ns 2-7 AC Electrical Characteristics Table 2-7. Reset, Stop, Mode Select, and Interrupt Timing6 (Continued) 150 MHz No. 26 27 28 29 Notes: Characteristics Duration of level sensitive IRQA assertion to ensure interrupt service (when exiting Stop)2, 3 • PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is enabled (Operating Mode Register Bit 6 = 0) • PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is not enabled (Operating Mode Register Bit 6 = 1) • PLL is active during Stop (PCTL Bit 17 = 1) (implies no Stop delay) Unit Min Max 13.6 — ms PLC × ETC × PDF + (20.5 ± 0.5) × TC 12.3 — ms Minimum: PLC × ETC × PDF + (128K − PLC/2) × TC 5.5 × TC 36.7 — ns Interrupt Requests Rate • HI08, ESSI, SCI, Timer • DMA • IRQ, NMI (edge trigger) • IRQ, NMI (level trigger) Maximum: 12 × TC 8 × TC 8 × TC 12 × TC — — — — 80.0 53.3 53.3 80.0 ns ns ns ns DMA Requests Rate • Data read from HI08, ESSI, SCI • Data write to HI08, ESSI, SCI • Timer • IRQ, NMI (edge trigger) Maximum: 6 × TC 7 × TC 2 × TC 3 × TC — — — — 40.0 46.7 13.3 20.0 ns ns ns ns Minimum: 4.25 × TC + 2.0 30.3 — ns Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to external memory (DMA source) access address out valid 1. 2. 3. 4. 5. 6. 7. 8. 2-8 Expression When fast interrupts are used and IRQA, IRQB, IRQC, and IRQD are defined as level-sensitive, timings 19 through 21 apply to prevent multiple interrupt service. To avoid these timing restrictions, the deasserted Edge-triggered mode is recommended when fast interrupts are used. Long interrupts are recommended for Level-sensitive mode. This timing depends on several settings: • For PLL disable, using internal oscillator (PLL Control Register (PCTL) Bit 16 = 0) and oscillator disabled during Stop (PCTL Bit 17 = 0), a stabilization delay is required to assure that the oscillator is stable before programs are executed. Resetting the Stop delay (Operating Mode Register Bit 6 = 0) provides the proper delay. While Operating Mode Register Bit 6 = 1 can be set, it is not recommended, and these specifications do not guarantee timings for that case. • For PLL disable, using internal oscillator (PCTL Bit 16 = 0) and oscillator enabled during Stop (PCTL Bit 17=1), no stabilization delay is required and recovery is minimal (Operating Mode Register Bit 6 setting is ignored). • For PLL disable, using external clock (PCTL Bit 16 = 1), no stabilization delay is required and recovery time is defined by the PCTL Bit 17 and Operating Mode Register Bit 6 settings. • For PLL enable, if PCTL Bit 17 is 0, the PLL is shutdown during Stop. Recovering from Stop requires the PLL to get locked. The PLL lock procedure duration, PLL Lock Cycles (PLC), may be in the range of 0 to 1000 cycles. This procedure occurs in parallel with the stop delay counter, and stop recovery ends when the last of these two events occurs. The stop delay counter completes count or PLL lock procedure completion. • PLC value for PLL disable is 0. • The maximum value for ETC is 4096 (maximum MF) divided by the desired internal frequency (that is, for 66 MHz it is 4096/66 MHz = 62 µs). During the stabilization period, TC, TH, and TL is not constant, and their width may vary, so timing may vary as well. Periodically sampled and not 100 percent tested. Value depends on clock source: • For an external clock generator, RESET duration is measured while RESET is asserted, VCC is valid, and the EXTAL input is active and valid. • For an internal oscillator, RESET duration is measured while RESET is asserted and VCC is valid. The specified timing reflects the crystal oscillator stabilization time after power-up. This number is affected both by the specifications of the crystal and other components connected to the oscillator and reflects worst case conditions. • When the VCC is valid, but the other “required RESET duration” conditions (as specified above) have not been yet met, the device circuitry is in an uninitialized state that can result in significant power consumption and heat-up. Designs should minimize this state to the shortest possible duration. If PLL does not lose lock. VCCQH = 3.3 V ± 0.3 V, VCC = 1.8 V ± 0.1 V; TJ = –40°C to +100°C, CL = 50 pF. WS = number of wait states (measured in clock cycles, number of TC). Use expression to compute maximum value. AC Electrical Characteristics VIH RESET 9 10 8 All Pins Reset Value A[0–17] First Fetch Figure 2-3. Reset Timing First Interrupt Instruction Execution/Fetch A[0–17] RD 20 WR 21 IRQA, IRQB, IRQC, IRQD, NMI 17 19 a) First Interrupt Instruction Execution General Purpose I/O 18 IRQA, IRQB, IRQC, IRQD, NMI b) General-Purpose I/O Figure 2-4. External Fast Interrupt Timing 2-9 AC Electrical Characteristics IRQA, IRQB, IRQC, IRQD, NMI 15 IRQA, IRQB, IRQC, IRQD, NMI 16 Figure 2-5. External Interrupt Timing (Negative Edge-Triggered) VIH RESET 13 14 VIH MODA, MODB, MODC, MODD, PINIT VIH IRQA, IRQB, IRQC, IRQD, NMI VIL VIL Figure 2-6. Operating Mode Select Timing 24 IRQA 25 First Instruction Fetch A[0–17] Figure 2-7. Recovery from Stop State Using IRQA 26 IRQA 25 A[0–17] First IRQA Interrupt Instruction Fetch Figure 2-8. Recovery from Stop State Using IRQA Interrupt Service 2-10 AC Electrical Characteristics DMA Source Address A[0–17] RD WR 29 IRQA, IRQB, IRQC, IRQD, NMI First Interrupt Instruction Execution Figure 2-9. External Memory Access (DMA Source) Timing 2.5.5 External Memory Expansion Port (Port A) 2.5.5.1 SRAM Timing Table 2-8. SRAM Timing No. Characteristics Symbol Expression1 150 MHz Unit Min 100 101 102 103 Address valid and AA assertion pulse width2 Address and AA valid to WR assertion WR assertion pulse width WR deassertion to address not valid tRC, tWC tAS tWP tWR Max (WS + 2) × TC − 4.0 [2 ≤ WS ≤ 7] (WS + 3) × TC − 4.0 [WS ≥ 8] 22.7 69.3 — ns 0.75 × TC – 3.0 [2 ≤ WS ≤ 3] 1.25 × TC – 3.0 [WS ≥ 4] 2.0 — ns 5.3 — ns WS × TC − 4.0 [2 ≤ WS ≤ 3] (WS − 0.5) × TC − 4.0 [WS ≥ 4] 9.3 — ns 19.3 — ns 4.3 — ns 11.0 — ns 1.25 × TC − 4.0 [2 ≤ WS ≤ 7] 2.25 × TC − 4.0 [WS ≥ 8] ns tAA, tAC (WS + 0.75) × TC − 6.5 [WS ≥ 2] — 11.8 ns RD assertion to input data valid tOE (WS + 0.25) × TC − 6.5 [WS ≥ 2] — 8.5 ns 106 RD deassertion to data not valid (data hold time) tOHZ 0.0 — ns 107 Address valid to WR deassertion2 tAW (WS + 0.75) × TC − 4.0 [WS ≥ 2] 14.3 — ns 108 Data valid to WR deassertion (data set-up time) tDS (tDW) (WS − 0.25) × TC − 5.4 [WS ≥ 2] 6.3 — ns 109 Data hold time from WR deassertion tDH 1.25 × TC − 4.0 [2 ≤ WS ≤ 7] 2.25 × TC − 4.0 [WS ≥ 8] 4.3 — ns 11.0 — ns 104 Address and AA valid to input data valid 105 2-11 AC Electrical Characteristics Table 2-8. SRAM Timing (Continued) No. 110 111 112 113 114 Characteristics WR assertion to data active WR deassertion to data high impedance Previous RD deassertion to data active (write) RD deassertion time WR deassertion time — — — — — Expression1 150 MHz Unit Min Max 0.25 × TC − 4.0 [2 ≤ WS ≤ 3] –0.25 × TC − 4.0 [WS ≥ 4] –2.4 — ns –5.7 — ns 1.25 × TC [2 ≤ WS ≤ 7] 2.25 × TC [WS ≥ 8] — 8.3 ns — 15.0 ns 2.25 × TC − 4.0 [2 ≤ WS ≤ 7] 3.25 × TC − 4.0 [WS ≥ 8] 11.0 — ns 17.7 — ns 1.75 × TC − 4.0 [2 ≤ WS ≤ 7] 2.75 × TC − 4.0 [WS ≥ 8] 7.6 — ns 14.3 — ns 9.3 — ns 16.0 — ns 2.0 × TC − 4.0 [2 ≤ WS ≤ 7] 3.0 × TC − 4.0 [WS ≥ 8] 115 Address valid to RD assertion — 0.5 × TC − 2.8 0.5 — ns 116 RD assertion pulse width — (WS + 0.25) × TC − 4.0 11.0 — ns 117 RD deassertion to address not valid — 1.25 × TC − 4.0 [2 ≤ WS ≤ 7] 2.25 × TC − 4.0 [WS ≥ 8] 4.3 — ns 11.0 — ns 3.2 — ns 0 — ns 118 TA set-up before RD or WR deassertion4 — 119 TA hold after RD or WR deassertion — Notes: 1. 2. 3. 4. 2-12 Symbol 0.25 × TC + 1.5 WS is the number of wait states specified in the BCR. The value is given for the minimum for a given category. (For example, for a category of [2 ≤ WS ≤ 7] timing is specified for 2 wait states.) Two wait states is the minimum otherwise. Timings 100 and107 are guaranteed by design, not tested. All timings for 150 MHz are measured from 0.5 × VCCQH to 0.5 × VCCQH. Timing 118 is relative to the deassertion edge of RD or WR even if TA remains asserted. AC Electrical Characteristics 100 A[0–17] AA[0–3] 113 117 116 RD 105 106 WR 104 118 119 TA Data In D[0–23] Note: Address lines A[0–17] hold their state after a read or write operation. AA[0–3] do not hold their state after a read or write operation. Figure 2-10. SRAM Read Access 100 A[0–17] AA[0–3] 107 101 102 103 WR 114 RD 119 118 TA 108 109 Data Out D[0–23] Note: Address lines A[0–17] hold their state after a read or write operation. AA[0–3] do not hold their state after a read or write operation. Figure 2-11. SRAM Write Access 2-13 AC Electrical Characteristics 2.5.5.2 DRAM Timing The selection guides in Figure 2-12 and Figure 2-15 are for primary selection only. Final selection should be based on the timing in the following tables. For example, the selection guide suggests that four wait states must be used for 100 MHz operation with Page Mode DRAM. However, consulting the appropriate table, a designer can evaluate whether fewer wait states might suffice by determining which timing prevents operation at 100 MHz, running the chip at a slightly lower frequency (for example, 95 MHz), using faster DRAM (if it becomes available), and manipulating control factors such as capacitive and resistive load to improve overall system performance. Note: DRAM type (tRAC ns) This figure should be used for primary selection. For exact and detailed timings, see the following tables. 100 80 70 60 Chip frequency 50 40 66 80 100 120 (MHz) 1 Wait states 3 Wait states 2 Wait states 4 Wait states Figure 2-12. DRAM Page Mode Wait State Selection Guide 2-14 AC Electrical Characteristics Table 2-9. DRAM Page Mode Timings, Three Wait States1,2,3 No. 131 Characteristics Symbol Page mode cycle time for two consecutive accesses of the same direction Expression4 100 MHz Unit Min Max 4 × TC 40.0 — ns Page mode cycle time for mixed (read and write) accesses tPC 3.5 × TC 35.0 — ns 132 CAS assertion to data valid (read) tCAC 2 × TC − 5.7 — 14.3 ns 133 Column address valid to data valid (read) tAA 3 × TC − 5.7 — 24.3 ns 134 CAS deassertion to data not valid (read hold time) tOFF 0.0 — ns 135 Last CAS assertion to RAS deassertion tRSH 2.5 × TC − 4.0 21.0 — ns 136 Previous CAS deassertion to RAS deassertion tRHCP 4.5 × TC − 4.0 41.0 — ns 137 CAS assertion pulse width tCAS 2 × TC − 4.0 16.0 — ns — 4.75 × TC − 6.0 6.75 × TC − 6.0 — 41.5 61.5 — — — — ns ns assertion5 Last CAS deassertion to RAS • BRW[1–0] = 00, 01—not applicable • BRW[1–0] = 10 • BRW[1–0] = 11 tCRP 139 CAS deassertion pulse width tCP 1.5 × TC − 4.0 11.0 — ns 140 Column address valid to CAS assertion tASC TC − 4.0 6.0 — ns 141 CAS assertion to column address not valid tCAH 2.5 × TC − 4.0 21.0 — ns 142 Last column address valid to RAS deassertion tRAL 4 × TC − 4.0 36.0 — ns 143 WR deassertion to CAS assertion tRCS 1.25 × TC − 4.0 8.5 — ns 144 CAS deassertion to WR assertion tRCH 0.75 × TC − 4.0 3.5 — ns 145 CAS assertion to WR deassertion tWCH 2.25 × TC − 4.2 18.3 — ns 146 WR assertion pulse width tWP 3.5 × TC − 4.5 30.5 — ns 147 Last WR assertion to RAS deassertion tRWL 3.75 × TC − 4.3 33.2 — ns 148 WR assertion to CAS deassertion tCWL 3.25 × TC − 4.3 28.2 — ns 149 Data valid to CAS assertion (write) tDS 0.5 × TC – 4.5 0.5 — ns 150 CAS assertion to data not valid (write) tDH 2.5 × TC − 4.0 21.0 — ns 151 WR assertion to CAS assertion tWCS 1.25 × TC − 4.3 8.2 — ns 152 Last RD assertion to RAS deassertion tROH 3.5 × TC − 4.0 31.0 — ns 153 RD assertion to data valid tGA 2.5 × TC − 5.7 — 19.3 ns 0.0 — ns 0.75 × TC – 1.5 6.0 — ns 0.25 × TC — 2.5 ns 138 6 154 RD deassertion to data not valid 155 WR assertion to data active 156 WR deassertion to data high impedance Notes: 1. 2. 3. 4. 5. 6. tGZ The number of wait states for Page mode access is specified in the DRAM Control Register. The refresh period is specified in the DRAM Control Register. The asynchronous delays specified in the expressions are valid for the DSP56311. All the timings are calculated for the worst case. Some of the timings are better for specific cases (for example, tPC equals 4 × TC for read-after-read or write-after-write sequences). An expression is used to compute the number listed as the minimum or maximum value listed, as appropriate. BRW[1–0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of page-access. RD deassertion always occurs after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ. 2-15 AC Electrical Characteristics Table 2-10. DRAM Page Mode Timings, Four Wait States1,2,3 No. 131 Characteristics Page mode cycle time for two consecutive accesses of the same direction Expression4 100 MHz Unit Min Max 5 × TC 50.0 — ns Page mode cycle time for mixed (read and write) accesses tPC 4.5 × TC 45.0 — ns 132 CAS assertion to data valid (read) tCAC 2.75 × TC − 5.7 — 21.8 ns 133 Column address valid to data valid (read) tAA 3.75 × TC − 5.7 — 31.8 ns 134 CAS deassertion to data not valid (read hold time) tOFF 0.0 — ns 135 Last CAS assertion to RAS deassertion tRSH 3.5 × TC − 4.0 31.0 — ns 136 Previous CAS deassertion to RAS deassertion tRHCP 6 × TC − 4.0 56.0 — ns 137 CAS assertion pulse width tCAS 2.5 × TC − 4.0 21.0 — ns — 5.25 × TC − 6.0 7.25 × TC − 6.0 — 46.5 66.5 — — — — ns ns assertion5 Last CAS deassertion to RAS • BRW[1–0] = 00, 01—Not applicable • BRW[1–0] = 10 • BRW[1–0] = 11 tCRP 139 CAS deassertion pulse width tCP 2 × TC − 4.0 16.0 — ns 140 Column address valid to CAS assertion tASC TC − 4.0 6.0 — ns 141 CAS assertion to column address not valid tCAH 3.5 × TC − 4.0 31.0 — ns 142 Last column address valid to RAS deassertion tRAL 5 × TC − 4.0 46.0 — ns 143 WR deassertion to CAS assertion tRCS 1.25 × TC − 4.0 8.5 — ns 144 CAS deassertion to WR assertion tRCH 1.25 × TC – 3.7 8.8 — ns 145 CAS assertion to WR deassertion tWCH 3.25 × TC − 4.2 28.3 — ns 146 WR assertion pulse width tWP 4.5 × TC − 4.5 40.5 — ns 147 Last WR assertion to RAS deassertion tRWL 4.75 × TC − 4.3 43.2 — ns 148 WR assertion to CAS deassertion tCWL 3.75 × TC − 4.3 33.2 — ns 149 Data valid to CAS assertion (write) tDS 0.5 × TC – 4.5 0.5 — ns 150 CAS assertion to data not valid (write) tDH 3.5 × TC − 4.0 31.0 — ns 151 WR assertion to CAS assertion tWCS 1.25 × TC − 4.3 8.2 — ns 152 Last RD assertion to RAS deassertion tROH 4.5 × TC − 4.0 41.0 — ns 153 RD assertion to data valid tGA 3.25 × TC − 5.7 — 26.8 ns 0.0 — ns 0.75 × TC – 1.5 6.0 — ns 0.25 × TC — 2.5 ns 138 6 154 RD deassertion to data not valid 155 WR assertion to data active 156 WR deassertion to data high impedance Notes: 1. 2. 3. 4. 5. 6. 2-16 Symbol tGZ The number of wait states for Page mode access is specified in the DRAM Control Register. The refresh period is specified in the DRAM Control Register. The asynchronous delays specified in the expressions are valid for the DSP56311. All the timings are calculated for the worst case. Some of the timings are better for specific cases (for example, tPC equals 3 × TC for read-after-read or write-after-write sequences). An expressions is used to calculate the maximum or minimum value listed, as appropriate. BRW[1–0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of-page access. RD deassertion always occurs after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ. AC Electrical Characteristics RAS 136 131 135 CAS 137 139 138 140 141 A[0–17] Row Add 142 Column Address Column Address 151 Last Column Address 144 145 147 WR 146 RD 148 155 156 150 149 D[0–23] Data Out Data Out Data Out Figure 2-13. DRAM Page Mode Write Accesses RAS 136 131 135 CAS 137 139 140 A[0–17] Row Add Column Address 138 141 142 Last Column Address Column Address 143 WR 132 133 152 153 RD 134 154 D[0–23] Data In Data In Data In Figure 2-14. DRAM Page Mode Read Accesses 2-17 AC Electrical Characteristics DRAM Type (tRAC ns) Note: This figure should be used for primary selection. For exact and detailed timings, see the following tables. 100 80 70 60 Chip Frequency 50 40 66 80 (MHz) 120 100 4 Wait States 11 Wait States 8 Wait States 15 Wait States Figure 2-15. DRAM Out-of-Page Wait State Selection Guide Table 2-11. DRAM Out-of-Page and Refresh Timings, Eleven Wait States1,2 No. 2-18 Characteristics Symbol Expression3 100 MHz Unit Min Max 157 Random read or write cycle time tRC 12 × TC 120.0 — ns 158 RAS assertion to data valid (read) tRAC 6.25 × TC − 7.0 — 55.5 ns 159 CAS assertion to data valid (read) tCAC 3.75 × TC − 7.0 — 30.5 ns 160 Column address valid to data valid (read) tAA 4.5 × TC − 7.0 — 38.0 ns 161 CAS deassertion to data not valid (read hold time) tOFF 0.0 — ns 162 RAS deassertion to RAS assertion tRP 4.25 × TC − 4.0 38.5 — ns 163 RAS assertion pulse width tRAS 7.75 × TC − 4.0 73.5 — ns 164 CAS assertion to RAS deassertion tRSH 5.25 × TC − 4.0 48.5 — ns 165 RAS assertion to CAS deassertion tCSH 6.25 × TC − 4.0 58.5 — ns 166 CAS assertion pulse width tCAS 3.75 × TC − 4.0 33.5 — ns 167 RAS assertion to CAS assertion tRCD 2.5 × TC ± 4.0 21.0 29.0 ns 168 RAS assertion to column address valid tRAD 1.75 × TC ± 4.0 13.5 21.5 ns 169 CAS deassertion to RAS assertion tCRP 5.75 × TC − 4.0 53.5 — ns 170 CAS deassertion pulse width tCP 4.25 × TC – 6.0 36.5 — ns AC Electrical Characteristics Table 2-11. DRAM Out-of-Page and Refresh Timings, Eleven Wait States1,2 (Continued) No. Characteristics Symbol Expression3 100 MHz Unit Min Max 171 Row address valid to RAS assertion tASR 4.25 × TC − 4.0 38.5 — ns 172 RAS assertion to row address not valid tRAH 1.75 × TC − 4.0 13.5 — ns 173 Column address valid to CAS assertion tASC 0.75 × TC − 4.0 3.5 — ns 174 CAS assertion to column address not valid tCAH 5.25 × TC − 4.0 48.5 — ns 175 RAS assertion to column address not valid tAR 7.75 × TC − 4.0 73.5 — ns 176 Column address valid to RAS deassertion tRAL 6 × TC − 4.0 56.0 — ns 177 WR deassertion to CAS assertion 178 tRCS 3.0 × TC − 4.0 26.0 — ns 4 tRCH 1.75 × TC – 3.7 13.8 — ns 4 CAS deassertion to WR assertion 179 RAS deassertion to WR assertion tRRH 0.25 × TC − 2.0 0.5 — ns 180 CAS assertion to WR deassertion tWCH 5 × TC − 4.2 45.8 — ns 181 RAS assertion to WR deassertion tWCR 7.5 × TC − 4.2 70.8 — ns 182 WR assertion pulse width tWP 11.5 × TC − 4.5 110.5 — ns 183 WR assertion to RAS deassertion tRWL 11.75 × TC − 4.3 113.2 — ns 184 WR assertion to CAS deassertion tCWL 10.25 × TC − 4.3 98.2 — ns 185 Data valid to CAS assertion (write) tDS 5.75 × TC − 4.0 53.5 — ns 186 CAS assertion to data not valid (write) tDH 5.25 × TC − 4.0 48.5 — ns 187 RAS assertion to data not valid (write) tDHR 7.75 × TC − 4.0 73.5 — ns 188 WR assertion to CAS assertion tWCS 6.5 × TC − 4.3 60.7 — ns 189 CAS assertion to RAS assertion (refresh) tCSR 1.5 × TC − 4.0 11.0 — ns 190 RAS deassertion to CAS assertion (refresh) tRPC 2.75 × TC − 4.0 23.5 — ns 191 RD assertion to RAS deassertion tROH 11.5 × TC − 4.0 111.0 — ns 192 RD assertion to data valid tGA 10 × TC − 7.0 — 93.0 ns 0.0 — ns 0.75 × TC – 1.5 6.0 — ns 0.25 × TC — 2.5 ns 5 193 RD deassertion to data not valid 194 WR assertion to data active 195 WR deassertion to data high impedance Notes: 1. 2. 3. 4. 5. tGZ The number of wait states for an out-of-page access is specified in the DRAM Control Register. The refresh period is specified in the DRAM Control Register. Use the expression to compute the maximum or minimum value listed (or both if the expression includes ±). Either tRCH or tRRH must be satisfied for read cycles. RD deassertion always occurs after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ. 2-19 AC Electrical Characteristics Table 2-12. DRAM Out-of-Page and Refresh Timings, Fifteen Wait States1,2 No. 2-20 Characteristics Symbol Expression3 100 MHz Unit Min Max 157 Random read or write cycle time tRC 16 × TC 160.0 — ns 158 RAS assertion to data valid (read) tRAC 8.25 × TC − 5.7 — 76.8 ns 159 CAS assertion to data valid (read) tCAC 4.75 × TC − 5.7 — 41.8 ns 160 Column address valid to data valid (read) tAA 5.5 × TC − 5.7 — 49.3 ns 161 CAS deassertion to data not valid (read hold time) tOFF 0.0 0.0 — ns 162 RAS deassertion to RAS assertion tRP 6.25 × TC − 4.0 58.5 — ns 163 RAS assertion pulse width tRAS 9.75 × TC − 4.0 93.5 — ns 164 CAS assertion to RAS deassertion tRSH 6.25 × TC − 4.0 58.5 — ns 165 RAS assertion to CAS deassertion tCSH 8.25 × TC − 4.0 78.5 — ns 166 CAS assertion pulse width tCAS 4.75 × TC − 4.0 43.5 — ns 167 RAS assertion to CAS assertion tRCD 3.5 × TC ± 2 33.0 37.0 ns 168 RAS assertion to column address valid tRAD 2.75 × TC ± 2 25.5 29.5 ns 169 CAS deassertion to RAS assertion tCRP 7.75 × TC − 4.0 73.5 — ns 170 CAS deassertion pulse width tCP 6.25 × TC – 6.0 56.5 — ns 171 Row address valid to RAS assertion tASR 6.25 × TC − 4.0 58.5 — ns 172 RAS assertion to row address not valid tRAH 2.75 × TC − 4.0 23.5 — ns 173 Column address valid to CAS assertion tASC 0.75 × TC − 4.0 3.5 — ns 174 CAS assertion to column address not valid tCAH 6.25 × TC − 4.0 58.5 — ns 175 RAS assertion to column address not valid tAR 9.75 × TC − 4.0 93.5 — ns 176 Column address valid to RAS deassertion tRAL 7 × TC − 4.0 66.0 — ns 177 WR deassertion to CAS assertion tRCS 5 × TC − 3.8 46.2 — ns 178 CAS deassertion to WR assertion tRCH 1.75 × TC – 3.7 13.8 — ns 179 RAS deassertion to WR4 assertion tRRH 0.25 × TC − 2.0 0.5 — ns 180 CAS assertion to WR deassertion tWCH 6 × TC − 4.2 55.8 — ns 181 RAS assertion to WR deassertion tWCR 9.5 × TC − 4.2 90.8 — ns 4 182 WR assertion pulse width tWP 15.5 × TC − 4.5 150.5 — ns 183 WR assertion to RAS deassertion tRWL 15.75 × TC − 4.3 153.2 — ns 184 WR assertion to CAS deassertion tCWL 14.25 × TC − 4.3 138.2 — ns 185 Data valid to CAS assertion (write) tDS 8.75 × TC − 4.0 83.5 — ns 186 CAS assertion to data not valid (write) tDH 6.25 × TC − 4.0 58.5 — ns 187 RAS assertion to data not valid (write) tDHR 9.75 × TC − 4.0 93.5 — ns 188 WR assertion to CAS assertion tWCS 9.5 × TC − 4.3 90.7 — ns 189 CAS assertion to RAS assertion (refresh) tCSR 1.5 × TC − 4.0 11.0 — ns 190 RAS deassertion to CAS assertion (refresh) tRPC 4.75 × TC − 4.0 43.5 — ns 191 RD assertion to RAS deassertion tROH 15.5 × TC − 4.0 151.0 — ns 192 RD assertion to data valid tGA 14 × TC − 5.7 — 134.3 ns 193 RD deassertion to data not valid5 tGZ 0.0 — ns 194 WR assertion to data active 195 WR deassertion to data high impedance 0.75 × TC – 1.5 6.0 — ns 0.25 × TC — 2.5 ns AC Electrical Characteristics Table 2-12. DRAM Out-of-Page and Refresh Timings, Fifteen Wait States1,2 (Continued) No. Characteristics Symbol Expression3 100 MHz Unit Min Notes: 1. 2. 3. 4. 5. Max The number of wait states for an out-of-page access is specified in the DRAM Control Register. The refresh period is specified in the DRAM Control Register. Use the expression to compute the maximum or minimum value listed (or both if the expression includes ±). Either tRCH or tRRH must be satisfied for read cycles. RD deassertion always occurs after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ. 157 163 162 162 165 RAS 167 164 169 168 170 166 CAS 171 173 174 175 A[0–17] Row Address Column Address 172 176 177 179 191 WR 178 160 159 RD 193 158 192 161 D[0–23] Data In Figure 2-16. DRAM Out-of-Page Read Access 2-21 AC Electrical Characteristics 157 162 163 162 165 RAS 167 169 164 168 166 170 CAS 173 171 174 172 176 Row Address A[0–17] Column Address 181 175 188 180 182 WR 184 183 RD 187 186 185 195 194 Data Out D[0–23] Figure 2-17. DRAM Out-of-Page Write Access 157 162 162 163 RAS 190 170 165 189 CAS 177 WR Figure 2-18. DRAM Refresh Access 2-22 AC Electrical Characteristics 2.5.5.3 Asynchronous Bus Arbitration Timings Table 2-13. Asynchronous Bus Timings 150 MHz No. Characteristics 250 BB assertion window from BG input deassertion. 251 Delay from BB assertion to BG assertion Notes: 1. 2. 3. Expression Unit Min Max 2.5 × Tc + 5 — 22 ns 2 × Tc + 5 18.3 — ns Bit 13 in the Operating Mode Register must be set to enable Asynchronous Arbitration mode. At 150 MHz, Asynchronous Arbitration mode is recommended. To guarantee timings 250 and 251, it is recommended that you assert non-overlapping BG inputs to different DSP56300 devices (on the same bus), as shown in Figure 2-19, where BG1 is the BG signal for one DSP56300 device while BG2 is the BG signal for a second DSP56300 device. BG1 BB 250 BG2 251 250+251 Figure 2-19. Asynchronous Bus Arbitration Timing The asynchronous bus arbitration is enabled by internal synchronization circuits on BG and BB inputs. These synchronization circuits add delay from the external signal until it is exposed to internal logic. As a result of this delay, a DSP56300 part may assume mastership and assert BB, for some time after BG is deasserted. This is the reason for timing 250. Once BB is asserted, there is a synchronization delay from BB assertion to the time this assertion is exposed to other DSP56300 components that are potential masters on the same bus. If BG input is asserted before that time, and BG is asserted and BB is deasserted, another DSP56300 component may assume mastership at the same time. Therefore, some non-overlap period between one BG input active to another BG input active is required. Timing 251 ensures that overlaps are avoided. 2-23 AC Electrical Characteristics 2.5.6 Host Interface Timing Table 2-14. Host Interface Timings1,2,12 Expression 317 Read data strobe assertion width5 HACK assertion width 318 Read data strobe deassertion width5 HACK deassertion width 319 Read data strobe deassertion width5 after “Last Data Register” reads8,11, or between two consecutive CVR, ICR, or ISR reads3 HACK deassertion width after “Last Data Register” reads8,11 320 Write data strobe assertion width6 321 322 323 324 TC + 6.5 2.5 × TC + 4.4 Unit Min Max 13.1 — ns 6.5 — ns 20.8 — ns 8.7 — ns 20.8 — ns 10.9 — ns 6.5 — ns 0.0 — ns 6.5 — ns width8 Write data strobe deassertion HACK write deassertion width • after ICR, CVR and “Last Data Register” writes • 2.5 × TC + 4.4 after IVR writes, or after TXH:TXM:TXL writes (with HLEND= 0), or after TXL:TXM:TXH writes (with HLEND = 1) HAS assertion width 4 HAS deassertion to data strobe assertion Host data input set-up time before write data strobe deassertion6 6 325 Host data input hold time after write data strobe deassertion 2.2 — ns 326 Read data strobe assertion to output data active from high impedance5 HACK assertion to output data active from high impedance 2.2 — ns 327 Read data strobe assertion to output data valid5 HACK assertion to output data valid — 16.5 ns 328 Read data strobe deassertion to output data high impedance5 HACK deassertion to output data high impedance — 6.5 ns 329 Output data hold time after read data strobe deassertion5 Output data hold time after HACK deassertion 2.2 — ns 330 HCS assertion to read data strobe deassertion5 13.1 — ns 331 HCS assertion to write data strobe deassertion6 6.5 — ns 332 HCS assertion to output data valid — 13.0 ns 333 HCS hold time after data strobe deassertion4 0.0 — ns 334 Address (HAD[0–7]) set-up time before HAS deassertion (HMUX=1) 3.0 — ns 335 Address (HAD[0–7]) hold time after HAS deassertion (HMUX=1) 2.2 — ns 336 HA[8–10] (HMUX=1), HA[0–2] (HMUX=0), HR/W set-up time before data strobe assertion4 • Read • Write 0 3.0 — — ns ns 2.2 — ns 337 2-24 150 MHz Characteristic10 No. HA[8–10] (HMUX=1), HA[0–2] (HMUX=0), HR/W hold time after data strobe deassertion4 TC + 6.5 AC Electrical Characteristics Table 2-14. Host Interface Timings1,2,12 (Continued) 150 MHz Characteristic10 No. Expression Unit Min Max 338 Delay from read data strobe deassertion to host request assertion for “Last Data Register” read5, 7, 8 TC + 3.5 10.1 — ns 339 Delay from write data strobe deassertion to host request assertion for “Last Data Register” write6, 7, 8 1.5 × TC + 3.5 13.4 — ns 340 Delay from data strobe assertion to host request deassertion for “Last Data Register” read or write (HROD=0)4, 7, 8 — 13.0 ns 341 Delay from data strobe assertion to host request deassertion for “Last Data Register” read or write (HROD=1, open drain host request)4, 7, 8, 9 — 300.0 ns Notes: See the Programmer’s Model section in the chapter on the HI08 in the DSP56311 User’s Manual. In the timing diagrams below, the controls pins are drawn as active low. The pin polarity is programmable. 3. This timing is applicable only if two consecutive reads from one of these registers are executed. 4. The data strobe is Host Read (HRD) or Host Write (HWR) in the Dual Data Strobe mode and Host Data Strobe (HDS) in the Single Data Strobe mode. 5. The read data strobe is HRD in the Dual Data Strobe mode and HDS in the Single Data Strobe mode. 6. The write data strobe is HWR in the Dual Data Strobe mode and HDS in the Single Data Strobe mode. 7. The host request is HREQ in the Single Host Request mode and HRRQ and HTRQ in the Double Host Request mode. 8. The “Last Data Register” is the register at address $7, which is the last location to be read or written in data transfers. This is RXL/TXL in the Big Endian mode (HLEND = 0; HLEND is the Interface Control Register bit 7—ICR[7]), or RXH/TXH in the Little Endian mode (HLEND = 1). 9. In this calculation, the host request signal is pulled up by a 4.7 kΩ resistor in the Open-drain mode. 10. VCCQH = 3.3 V ± 0.3 V, VCC = 1.8 V ± 0.1 V; TJ = –40°C to +100 °C, CL = 50 pF 11. This timing is applicable only if a read from the “Last Data Register” is followed by a read from the RXL, RXM, or RXH registers without first polling RXDF or HREQ bits, or waiting for the assertion of the HREQ signal. 12. After the external host writes a new value to the ICR, the HI08 is ready for operation after three DSP clock cycles (3 × Tc). 1. 2. 317 318 HACK 328 327 326 329 H[0–7] HREQ Figure 2-20. Host Interrupt Vector Register (IVR) Read Timing Diagram 2-25 AC Electrical Characteristics HA[2–0] 336 337 333 330 HCS 336 337 HRW 317 HDS 318 328 332 319 327 329 326 H[7–0] 338 340 341 HREQ (single host request) HRRQ (double host request) Figure 2-21. Read Timing Diagram, Non-Multiplexed Bus, Single Data Strobe HA[2–0] 336 337 333 330 HCS 317 HRD 318 328 332 319 327 329 326 H[7–0] 340 338 341 HREQ (single host request) HRRQ (double host request) Figure 2-22. Read Timing Diagram, Non-Multiplexed Bus, Double Data Strobe 2-26 AC Electrical Characteristics HA[2–0] 336 337 333 331 HCS 336 337 HRW 320 HDS 321 324 325 H[7–0] 339 340 341 HREQ (single host request) HTRQ (double host request) Figure 2-23. Write Timing Diagram, Non-Multiplexed Bus, Single Data Strobe HA[2–0] 336 337 333 331 HCS 320 HWR 321 324 325 H[7–0] 340 339 341 HREQ (single host request) HTRQ (double host request) Figure 2-24. Write Timing Diagram, Non-Multiplexed Bus, Double Data Strobe 2-27 AC Electrical Characteristics , HA[10–8] 336 322 HAS 337 323 336 337 HRW 317 HDS 334 318 335 319 327 328 329 HAD[7–0] Address Data 326 338 340 341 HREQ (single host request) HRRQ (double host request) Figure 2-25. Read Timing Diagram, Multiplexed Bus, Single Data Strobe HA[10–8] 336 322 HAS 337 323 317 HRD 334 318 335 319 327 328 329 HAD[7–0] Address Data 326 340 HREQ (single host request) HRRQ (double host request) 338 341 Figure 2-26. Read Timing Diagram, Multiplexed Bus, Double Data Strobe 2-28 AC Electrical Characteristics HA[10–8] 336 322 HAS 337 323 336 337 HRW 320 HDS 334 324 321 335 HAD[7–0] 325 Data Address 340 339 341 HREQ (single host request) HTRQ (double host request) Figure 2-27. Write Timing Diagram, Multiplexed Bus, Single Data Strobe , HA[10–8] 336 322 HAS 337 323 320 HWR 334 324 321 335 HAD[7–0] 325 Data Address 340 339 341 HREQ (single host request) HTRQ (double host request) Figure 2-28. Write Timing Diagram, Multiplexed Bus, Double Data Strobe 2-29 AC Electrical Characteristics 2.5.7 SCI Timing Table 2-15. SCI Timings Characteristics1 No. tSCC2 Expression Unit Min Max 8 × TC 53.3 — ns 400 Synchronous clock cycle 401 Clock low period tSCC/2 − 10.0 16.7 — ns 402 Clock high period tSCC/2 − 10.0 16.7 — ns 403 Output data set-up to clock falling edge (internal clock) tSCC/4 + 0.5 × TC −10.0 6.7 — ns 404 Output data hold after clock rising edge (internal clock) tSCC/4 − 0.5 × TC 10.0 — ns 405 Input data set-up time before clock rising edge (internal clock) tSCC/4 + 0.5 × TC + 25.0 41.7 — ns 406 Input data not valid before clock rising edge (internal clock) tSCC/4 + 0.5 × TC − 5.5 — 11.5 ns 407 Clock falling edge to output data valid (external clock) — 32.0 ns 408 Output data hold after clock rising edge (external clock) 14.7 — ns 409 Input data set-up time before clock rising edge (external clock) 0.0 — ns 410 Input data hold time after clock rising edge (external clock) 9.0 — ns 411 Asynchronous clock cycle 64 × TC 427.0 — ns 412 Clock low period tACC/2 − 10.0 203.5 — ns 413 Clock high period tACC/2 − 10.0 203.5 — ns 414 Output data set-up to clock rising edge (internal clock) tACC/2 − 30.0 183.5 — ns 415 Output data hold after clock rising edge (internal clock) tACC/2 − 30.0 183.5 — ns Notes: 1. 2. 3. 2-30 150 MHz Symbol TC + 8.0 tACC3 VCCQH = 3.3 V ± 0.3 V, VCC = 1.8 V ± 0.1 V; TJ = –40°C to +100 °C, CL = 50 pF tSCC = synchronous clock cycle time (for internal clock, tSCC is determined by the SCI clock control register and TC). tACC = asynchronous clock cycle time; value given for 1X Clock mode (for internal clock, tACC is determined by the SCI clock control register and TC). AC Electrical Characteristics SCLK (Output) TXD Data Valid RXD Data Valid a) Internal Clock SCLK (Input) TXD RXD Data Valid b) External Clock Figure 2-29. SCI Synchronous Mode Timing Figure 2-30. SCI Asynchronous Mode Timing 2-31 AC Electrical Characteristics 2.5.8 ESSI0/ESSI1 Timing Table 2-16. ESSI Timings Characteristics4, 6 No. 150 MHz Symbol Expression Min Max 430 431 432 6 × TC 8 × TC 40.0 53.4 — — Clock high period • For internal clock • For external clock 4 × TC − 10.0 3 × TC 16.7 20.0 — — ns ns Clock low period • For internal clock • For external clock 4 × TC − 10.0 3 × TC 16.7 20.0 — — ns ns Clock cycle1 tSSICC x ck i ck ns ns 433 RXC rising edge to FSR out (bit-length) high — — 37.0 22.0 x ck i ck a ns 434 RXC rising edge to FSR out (bit-length) low — — 37.0 22.0 x ck i ck a ns 435 RXC rising edge to FSR out (word-length-relative) high2 — — 39.0 x ck i ck a ns 37.0 RXC rising edge to FSR out (word-length-relative) low2 — — x ck i ck a ns 37.0 437 RXC rising edge to FSR out (word-length) high — — 36.0 21.0 x ck i ck a ns 438 RXC rising edge to FSR out (word-length) low — — 37.0 22.0 x ck i ck a ns 439 Data in set-up time before RXC (SCK in Synchronous mode) falling edge 10.0 — — x ck i ck ns 19.0 440 Data in hold time after RXC falling edge 5.0 3.0 — — x ck i ck ns 441 FSR input (bl, wr) high before RXC falling edge2 1.0 23.0 — — x ck i ck a ns 442 FSR input (wl) high before RXC falling edge 3.5 — — x ck i ck a ns 23.0 3.0 0.0 — — x ck i ck a ns 5.5 — — x ck i ck s ns 19.0 436 2-32 CondUnit ition5 443 FSR input hold time after RXC falling edge 444 Flags input set-up before RXC falling edge 39.0 445 Flags input hold time after RXC falling edge 6.0 0.0 — — x ck i ck s ns 446 TXC rising edge to FST out (bit-length) high — — 29.0 15.0 x ck i ck ns 447 TXC rising edge to FST out (bit-length) low — — 31.0 17.0 x ck i ck ns 448 TXC rising edge to FST out (word-length-relative) high2 — — 31.0 17.0 x ck i ck ns 449 TXC rising edge to FST out (word-length-relative) low2 — — 33.0 19.0 x ck i ck ns AC Electrical Characteristics Table 2-16. ESSI Timings (Continued) Characteristics4, 6 No. 150 MHz Symbol Expression Min Max CondUnit ition5 450 TXC rising edge to FST out (word-length) high — — 30.0 16.0 x ck i ck ns 451 TXC rising edge to FST out (word-length) low — — 31.0 17.0 x ck i ck ns 452 TXC rising edge to data out enable from high impedance — — 31.0 17.0 x ck i ck ns 453 TXC rising edge to Transmitter #0 drive enable assertion — — 34.0 20.0 x ck i ck ns 454 TXC rising edge to data out valid — — 38.4 21.0 x ck i ck ns 455 TXC rising edge to data out high impedance3 — — 31.0 16.0 x ck i ck ns 456 TXC rising edge to Transmitter #0 drive enable deassertion3 — — 34.0 20.0 x ck i ck ns 457 FST input (bl, wr) set-up time before TXC falling edge2 2.0 21.0 — — x ck i ck ns 458 FST input (wl) to data out enable from high impedance — 27.0 — ns 459 FST input (wl) to Transmitter #0 drive enable assertion — 31.0 — ns 460 FST input (wl) set-up time before TXC falling edge 2.5 — — x ck i ck ns 21.0 35 + 0.5 × TC 461 FST input hold time after TXC falling edge 4.0 0.0 — — x ck i ck ns 462 Flag output valid after TXC rising edge — — 32.0 18.0 x ck i ck ns Notes: 1. 2. 3. 4. 5. 6. For the internal clock, the external clock cycle is defined by the instruction cycle time (timing 7 in Table 2-5 on page 2-6) and the ESSI Control Register. The word-length-relative frame sync signal waveform operates the same way as the bit-length frame sync signal waveform, but spreads from one serial clock before the first bit clock (same as the Bit Length Frame Sync signal) until the one before last bit clock of the first word in the frame. Periodically sampled and not 100 percent tested VCCQH = 3.3 V ± 0.3 V, VCC = 1.8 V ± 0.1 V; TJ = –40°C to +100 °C, CL = 50 pF TXC (SCK Pin) = Transmit Clock RXC (SC0 or SCK Pin) = Receive Clock FST (SC2 Pin) = Transmit Frame Sync FSR (SC1 or SC2 Pin) Receive Frame Sync i ck = Internal Clock; x ck = External Clock i ck a = Internal Clock, Asynchronous Mode (asynchronous implies that TXC and RXC are two different clocks) i ck s = Internal Clock, Synchronous Mode (synchronous implies that TXC and RXC are the same clock) 2-33 AC Electrical Characteristics 430 431 432 TXC (Input/ Output) 446 447 FST (Bit) Out 450 451 FST (Word) Out 454 454 452 455 First Bit Data Out Last Bit 459 Transmitter #0 Drive Enable 457 453 456 461 FST (Bit) In 458 461 460 FST (Word) In 462 See Note Flags Out Note: In Network mode, output flag transitions can occur at the start of each time slot within the frame. In Normal mode, the output flag state is asserted for the entire frame period. Figure 2-31. ESSI Transmitter Timing 2-34 AC Electrical Characteristics 430 431 RXC 432 (Input/ Output) 433 434 FSR (Bit) Out 437 438 FSR (Word) 440 Out 439 First Bit Data In Last Bit 443 441 FSR (Bit) In 443 442 FSR (Word) In 444 445 Flags In Figure 2-32. ESSI Receiver Timing 2.5.9 Timer Timing Table 2-17. Timer Timing 150 MHz No. Characteristics Expression Unit Min Max 480 TIO Low 2 × TC + 2.0 15.4 — ns 481 TIO High 2 × TC + 2.0 15.4 — ns Note: VCCQH = 3.3 V ± 0.3 V, VCC = 1.8 V ± 0.1 V; TJ = –40°C to +100 °C, CL = 50 pF TIO 480 481 Figure 2-33. TIO Timer Event Input Restrictions 2-35 AC Electrical Characteristics 2.5.10 CONSIDERATIONS FOR GPIO USE 2.5.10.1 Operating Frequency of 100 MHz or Less Table 2-18. GPIO Timing 100 MHz No. Characteristics Expression Unit Min Max 490 CLKOUT edge to GPIO out valid (GPIO out delay time) — 8.5 ns 491 CLKOUT edge to GPIO out not valid (GPIO out hold time) 0.0 — ns 492 GPIO In valid to CLKOUT edge (GPIO in set-up time) 8.5 — ns 493 CLKOUT edge to GPIO in not valid (GPIO in hold time) 0.0 — ns 67.5 — ns Minimum: 6.75 × TC 494 Fetch to CLKOUT edge before GPIO change Note: VCC = 3.3 V ± 0.3 V; TJ = −40°C to +100 °C, CL = 50 pF CLKOUT (Output) 490 491 GPIO (Output) 492 GPIO (Input) 493 Valid A[0–17] 494 Fetch the instruction MOVE X0,X:(R0); X0 contains the new value of GPIO and R0 contains the address of the GPIO data register. Figure 2-34. GPIO Timing 2-36 AC Electrical Characteristics 2.5.10.2 With an Operating Frequency above 100 MHz The following considerations can be helpful when GPIO is used for output or input with an operating frequency above 100 MHz (that is, when CLKOUT is not available). • GPIO as Output: — The time from fetch of the instruction that changes the GPIO pin to the actual change is seven core clock cycles. This is true, assuming that the instruction is a one-cycle instruction and that there are no pipeline stalls or any other pipeline delays. — The maximum rise or fall time of a GPIO pin is 13 ns (TTL levels, assuming that the maximum of 50 pF load limit is met). • GPIO as Input—GPIO inputs are not synchronized with the core clock. When only one GPIO bit is polled, this lack of synchronization presents no problem, since the read value can be either the previous value or the new value of the corresponding GPIO pin. However, there is the risk of reading an intermediate state if: — Two or more GPIO bits are treated as a coupled group (for example, four possible status states encoded in two bits). — The read operation occurs during a simultaneous change of GPIO pins (for example, the change of 00 to 11 may happen through an intermediate state of 01 or 10). Therefore, when GPIO bits are read, the recommended practice is to poll continuously until two consecutive read operations have identical results. 2-37 AC Electrical Characteristics 2.5.11 JTAG Timing Table 2-19. JTAG Timing All frequencies No. Characteristics Unit Min Max 500 TCK frequency of operation 0.0 22.0 MHz 501 TCK cycle time in Crystal mode 45.0 — ns 502 TCK clock pulse width measured at 1.5 V 20.0 — ns 503 TCK rise and fall times 0.0 3.0 ns 504 Boundary scan input data set-up time 5.0 — ns 505 Boundary scan input data hold time 24.0 — ns 506 TCK low to output data valid 0.0 40.0 ns 507 TCK low to output high impedance 0.0 40.0 ns 508 TMS, TDI data set-up time 5.0 — ns 509 TMS, TDI data hold time 25.0 — ns 510 TCK low to TDO data valid 0.0 44.0 ns 511 TCK low to TDO high impedance 0.0 44.0 ns 512 TRST assert time 100.0 — ns 513 TRST set-up time to TCK low 40.0 — ns Notes: 1. 2. VCCQH = 3.3 V ± 0.3 V, VCC = 1.8 V ± 0.1 V; TJ = –40°C to +100 °C, CL = 50 pF All timings apply to OnCE module data transfers because it uses the JTAG port as an interface. 501 TCK (Input) VIH 503 502 502 VM VM VIL 503 Figure 2-35. Test Clock Input Timing Diagram 2-38 AC Electrical Characteristics TCK (Input) VIH VIL 504 Data Inputs 505 Input Data Valid 506 Data Outputs Output Data Valid 507 Data Outputs 506 Data Outputs Output Data Valid Figure 2-36. Boundary Scan (JTAG) Timing Diagram TCK (Input) VIH VIL 508 TDI TMS (Input) 509 Input Data Valid 510 TDO (Output) Output Data Valid 511 TDO (Output) 510 TDO (Output) Output Data Valid Figure 2-37. Test Access Port Timing Diagram TCK (Input) 513 TRST (Input) 512 Figure 2-38. TRST Timing Diagram 2-39 AC Electrical Characteristics 2.5.12 OnCE Module TimIng Table 2-20. OnCE Module Timing 150 MHz No. Characteristics Expression Unit Min Max 500 TCK frequency of operation Max 22.0 MHz 0.0 22.0 MHz 514 DE assertion time in order to enter Debug mode 1.5 × TC + 10.0 20.0 — ns 515 Response time when DSP56311 is executing NOP instructions from internal memory 5.5 × TC + 30.0 — 67.0 ns 516 Debug acknowledge assertion time 3 × TC + 5.0 25.0 — ns Note: VCCQH = 3.3 V ± 0.3 V, VCC = 1.8 V ± 0.1 V; TJ = –40°C to +100 °C, CL = 50 pF DE 514 515 Figure 2-39. OnCE—Debug Request 2-40 516 Chapter 3 Packaging 3.1 Pin-Out and Package This section provides diagrams of the package pin-outs and tables showing how the signals described in Chapter 1 are allocated for the package. The DSP56311 is available in a 196-pin Molded Array Process-Ball Grid Array (MAP-BGA) package. 3-1 MAP-BGA Package Description 3.2 MAP-BGA Package Description Top and bottom views of the MAP-BGA package are shown in Figure 3-1 and Figure 3-2 with their pin-outs. Top View 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A NC SC11 TMS TDO IRQB D23 VCCD D19 D16 D14 D11 D9 D7 NC B SRD1 SC12 TDI TRST IRQD D21 D20 D17 D15 D13 D10 D8 D5 NC C SC02 STD1 TCK IRQA IRQC D22 VCCQL D18 VCCD D12 VCCD D6 D3 D4 D PINIT SC01 DE GND GND GND GND GND GND GND GND D1 D2 VCCD E STD0 VCCS SRD0 GND GND GND GND GND GND GND GND A17 A16 D0 F RXD SC10 SC00 GND GND GND GND GND GND GND GND VCCQH A14 A15 G SCK1 SCLK TXD GND GND GND GND GND GND GND GND A13 VCCQL A12 H VCCQH VCCQL SCK0 GND GND GND GND GND GND GND GND VCCA A10 A11 J HACK HRW HDS GND GND GND GND GND GND GND GND A8 A7 A9 K VCCS HREQ TIO2 GND GND GND GND GND GND GND GND VCCA A5 A6 L HCS TIO1 TIO0 GND GND GND GND GND GND GND GND VCCA A3 A4 M HA1 HA2 HA0 VCCH H0 VCCP VCCQH EXTAL CLKOUT BCLK WR RD A1 A2 N H6 H7 H4 H2 RESET GNDP AA3 CAS VCCQL BCLK BR VCCC AA0 A0 P NC H5 H3 H1 PCAP AA2 XTAL VCCC TA BB AA1 BG NC GNDP1 Figure 3-1. DSP56311 MAP-BGA Package, Top View 3-2 MAP-BGA Package Description Bottom View 14 13 NC D7 NC 12 11 10 9 8 7 D9 D11 D14 D16 D19 VCCD D5 D8 D10 D13 D15 D17 D4 D3 D6 VCCD D12 VCCD VCCD D2 D1 GND GND D0 A16 A17 GND A15 A14 VCCQH A12 VCCQL A11 6 5 4 3 2 1 D23 IRQB TDO TMS SC11 NC A D20 D21 IRQD TRST TDI SC12 SRD1 B D18 VCCQL D22 IRQC IRQA TCK STD1 SC02 C GND GND GND GND GND GND DE SC01 PINIT D GND GND GND GND GND GND GND SRD0 VCCS STD0 E GND GND GND GND GND GND GND GND SC00 SC10 RXD F A13 GND GND GND GND GND GND GND GND TXD SCLK SCK1 G A10 VCCA GND GND GND GND GND GND GND GND SCK0 VCCQL VCCQH H A9 A7 A8 GND GND GND GND GND GND GND GND HDS HRW HACK J A6 A5 VCCA GND GND GND GND GND GND GND GND TIO2 HREQ VCCS K A4 A3 VCCA GND GND GND GND GND GND GND GND TIO0 TIO1 HCS L A2 A1 RD WR BCLK CLKOUT EXTAL VCCQH VCCP H0 VCCH HA0 HA2 HA1 M A0 AA0 VCCC BR BCLK VCCQL CAS AA3 GNDP RESET H2 H4 H7 H6 N NC BG AA1 BB TA VCCC XTAL AA2 GNDP1 PCAP H1 H3 H5 NC P Figure 3-2. DSP56311 MAP-BGA Package, Bottom View 3-3 MAP-BGA Package Description Table 3-1. Signal List by Ball Number Ball No. 3-4 Signal Name Ball No. Signal Name Ball No. Signal Name A1 Not Connected (NC), reserved B12 D8 D9 GND A2 SC11 or PD1 B13 D5 D10 GND A3 TMS B14 NC D11 GND A4 TDO C1 SC02 or PC2 D12 D1 A5 MODB/IRQB C2 STD1 or PD5 D13 D2 A6 D23 C3 TCK D14 VCCD A7 VCCD C4 MODA/IRQA E1 STD0 or PC5 A8 D19 C5 MODC/IRQC E2 VCCS A9 D16 C6 D22 E3 SRD0 or PC4 A10 D14 C7 VCCQL E4 GND A11 D11 C8 D18 E5 GND A12 D9 C9 VCCD E6 GND A13 D7 C10 D12 E7 GND A14 NC C11 VCCD E8 GND B1 SRD1 or PD4 C12 D6 E9 GND B2 SC12 or PD2 C13 D3 E10 GND B3 TDI C14 D4 E11 GND B4 TRST D1 PINIT/NMI E12 A17 B5 MODD/IRQD D2 SC01 or PC1 E13 A16 B6 D21 D3 DE E14 D0 B7 D20 D4 GND F1 RXD or PE0 B8 D17 D5 GND F2 SC10 or PD0 B9 D15 D6 GND F3 SC00 or PC0 B10 D13 D7 GND F4 GND B11 D10 D8 GND F5 GND MAP-BGA Package Description Table 3-1. Signal List by Ball Number (Continued) Ball No. Signal Name Ball No. Signal Name Ball No. Signal Name F6 GND H3 SCK0 or PC3 J14 A9 F7 GND H4 GND K1 VCCS F8 GND H5 GND K2 HREQ/HREQ, HTRQ/HTRQ, or PB14 F9 GND H6 GND K3 TIO2 F10 GND H7 GND K4 GND F11 GND H8 GND K5 GND F12 VCCQH H9 GND K6 GND F13 A14 H10 GND K7 GND F14 A15 H11 GND K8 GND G1 SCK1 or PD3 H12 VCCA K9 GND G2 SCLK or PE2 H13 A10 K10 GND G3 TXD or PE1 H14 A11 K11 GND G4 GND J1 HACK/HACK, HRRQ/HRRQ, or PB15 K12 VCCA G5 GND J2 HRW, HRD/HRD, or PB11 K13 A5 G6 GND J3 HDS/HDS, HWR/HWR, or PB12 K14 A6 G7 GND J4 GND L1 HCS/HCS, HA10, or PB13 G8 GND J5 GND L2 TIO1 G9 GND J6 GND L3 TIO0 G10 GND J7 GND L4 GND G11 GND J8 GND L5 GND G12 A13 J9 GND L6 GND G13 VCCQL J10 GND L7 GND G14 A12 J11 GND L8 GND H1 VCCQH J12 A8 L9 GND H2 VCCQL J13 A7 L10 GND 3-5 MAP-BGA Package Description Table 3-1. Signal List by Ball Number (Continued) Ball No. Signal Name Signal Name Ball No. Signal Name L11 GND M13 A1 P1 NC L12 VCCA M14 A2 P2 H5, HAD5, or PB5 L13 A3 N1 H6, HAD6, or PB6 P3 H3, HAD3, or PB3 L14 A4 N2 H7, HAD7, or PB7 P4 H1, HAD1, or PB1 M1 HA1, HA8, or PB9 N3 H4, HAD4, or PB4 P5 PCAP M2 HA2, HA9, or PB10 N4 H2, HAD2, or PB2 P6 GNDP1 M3 HA0, HAS/HAS, or PB8 N5 RESET P7 AA2/RAS2 M4 VCCH N6 GNDP P8 XTAL M5 H0, HAD0, or PB0 N7 AA3/RAS3 P9 VCCC M6 VCCP N8 CAS P10 TA M7 VCCQH N9 VCCQL P11 BB M8 EXTAL N10 BCLK2 P12 AA1/RAS1 M9 CLKOUT2 N11 BR P13 BG M10 BCLK2 N12 VCCC P14 NC M11 WR N13 AA0/RAS0 M12 RD N14 A0 Notes: 1. 2. 3-6 Ball No. Signal names are based on configured functionality. Most connections supply a single signal. Some connections provide a signal with dual functionality, such as the MODx/IRQx pins that select an operating mode after RESET is deasserted but act as interrupt lines during operation. Some signals have configurable polarity; these names are shown with and without overbars, such as HAS/HAS. Some connections have two or more configurable functions; names assigned to these connections indicate the function for a specific configuration. For example, connection N2 is data line H7 in non-multiplexed bus mode, data/address line HAD7 in multiplexed bus mode, or GPIO line PB7 when the GPIO function is enabled for this pin. Unlike in the TQFP package, most of the GND pins are connected internally in the center of the connection array and act as heat sink for the chip. Therefore, except for GNDP and GNDP1 that support the PLL, other GND signals do not support individual subsystems in the chip. CLKOUT, BCLK, and BCLK are available only if the operating frequency is ≤ 100 MHz. MAP-BGA Package Description Table 3-2. Signal List by Signal Name Signal Name Ball No. Signal Name Ball No. Signal Name Ball No. A0 N14 BR N11 D9 A12 A1 M13 CAS N8 DE D3 A10 H13 CLKOUT M9 EXTAL M8 A11 H14 D0 E14 GND D4 A12 G14 D1 D12 GND D5 A13 G12 D10 B11 GND D6 A14 F13 D11 A11 GND D7 A15 F14 D12 C10 GND D8 A16 E13 D13 B10 GND D9 A17 E12 D14 A10 GND D10 A2 M14 D15 B9 GND D11 A3 L13 D16 A9 GND E4 A4 L14 D17 B8 GND E5 A5 K13 D18 C8 GND E6 A6 K14 D19 A8 GND E7 A7 J13 D2 D13 GND E8 A8 J12 D20 B7 GND E9 A9 J14 D21 B6 GND E10 AA0 N13 D22 C6 GND E11 AA1 P12 D23 A6 GND F4 AA2 P7 D3 C13 GND F5 AA3 N7 D4 C14 GND F6 BB P11 D5 B13 GND F7 BCLK M10 D6 C12 GND F8 BCLK N10 D7 A13 GND F9 BG P13 D8 B12 GND F10 3-7 MAP-BGA Package Description Table 3-2. Signal List by Signal Name (Continued) 3-8 Signal Name Ball No. Signal Name Ball No. Signal Name Ball No. GND F11 GND K4 H7 N2 GND G4 GND K5 HA0 M3 GND G5 GND K6 HA1 M1 GND G6 GND K7 HA10 L1 GND G7 GND K8 HA2 M2 GND G8 GND K9 HA8 M1 GND G9 GND K10 HA9 M2 GND G10 GND K11 HACK/HACK J1 GND G11 GND L4 HAD0 M5 GND H4 GND L5 HAD1 P4 GND H5 GND L6 HAD2 N4 GND H6 GND L7 HAD3 P3 GND H7 GND L8 HAD4 N3 GND H8 GND L9 HAD5 P2 GND H9 GND L10 HAD6 N1 GND H10 GND L11 HAD7 N2 GND H11 GNDP N6 HAS/HAS M3 GND J4 GNDP1 P6 HCS/HCS L1 GND J5 H0 M5 HDS/HDS J3 GND J6 H1 P4 HRD/HRD J2 GND J7 H2 N4 HREQ/HREQ K2 GND J8 H3 P3 HRRQ/HRRQ J1 GND J9 H4 N3 HRW J2 GND J10 H5 P2 HTRQ/HTRQ K2 GND J11 H6 N2 HWR/HWR J3 MAP-BGA Package Description Table 3-2. Signal List by Signal Name (Continued) Signal Name Ball No. Signal Name Ball No. Signal Name Ball No. IRQA C4 PC3 H3 STD1 C2 IRQB A5 PC4 E3 TA P10 IRQC C5 PC5 E1 TCK C3 IRQD B5 PCAP P5 TDI B3 MODA C4 PD0 F2 TDO A4 MODB A5 PD1 A2 TIO0 L3 MODC C5 PD2 B2 TIO1 L2 MODD B5 PD3 G1 TIO2 K3 NC A1 PD4 B1 TMS A3 NC A14 PD5 C2 TRST B4 NC B14 PE0 F1 TXD G3 NC P1 PE1 G3 VCCA H12 NC P14 PE2 G2 VCCA K12 NMI D1 PINIT D1 VCCA L12 PB0 M5 RAS0 N13 VCCC N12 PB1 P4 RAS1 P12 VCCC P9 PB10 M2 RAS2 P7 VCCD A7 PB11 J2 RAS3 N7 VCCD C9 PB12 J3 RD M12 VCCD C11 PB13 L1 RESET N5 VCCD D14 PB14 K2 RXD F1 VCCH M4 PB15 J1 SC00 F3 VCCP M6 PB2 N4 SC01 D2 VCCQH F12 PB3 P3 SC02 C1 VCCQH H1 PB4 N3 SC10 F2 VCCQH M7 PB5 P2 SC11 A2 VCCQL C7 PB6 N1 SC12 B2 VCCQL G13 PB7 N2 SCK0 H3 VCCQL H2 PB8 M3 SCK1 G1 VCCQL N9 PB9 M1 SCLK G2 VCCS E2 PC0 F3 SRD0 E3 VCCS K1 PC1 D2 SRD1 B1 WR M11 PC2 C1 STD0 E1 XTAL P8 3-9 MAP-BGA Package Mechanical Drawing 3.3 MAP-BGA Package Mechanical Drawing Figure 3-3. DSP56311 Mechanical Information, 196-pin MAP-BGA Package 3-10 Chapter 4 Design Considerations 4.1 Thermal Design Considerations An estimate of the chip junction temperature, TJ, in °C can be obtained from this equation: Equation 1: TJ = T A + ( P D × R θJA ) Where: TA RθJA PD = = = ambient temperature °C package junction-to-ambient thermal resistance °C/W power dissipation in package Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance, as in this equation: Equation 2: R θJA = RθJC + R θCA Where: RθJA RθJC RθCA = = = package junction-to-ambient thermal resistance °C/W package junction-to-case thermal resistance °C/W package case-to-ambient thermal resistance °C/W RθJC is device-related and cannot be influenced by the user. The user controls the thermal environment to change the case-to-ambient thermal resistance, RθCA. For example, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on the printed circuit board (PCB) or otherwise change the thermal dissipation capability of the area surrounding the device on a PCB. This model is most useful for ceramic packages with heat sinks; some 90 percent of the heat flow is dissipated through the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where the heat flow is split between a path to the case and an alternate path through the PCB, analysis of the device thermal performance may need the additional modeling capability of a system-level thermal simulation tool. The thermal performance of plastic packages is more dependent on the temperature of the PCB to which the package is mounted. Again, if the estimates obtained from RθJA do not satisfactorily answer whether the thermal performance is adequate, a system-level model may be appropriate. 4-1 Electrical Design Considerations A complicating factor is the existence of three common ways to determine the junction-to-case thermal resistance in plastic packages. • To minimize temperature variation across the surface, the thermal resistance is measured from the junction to the outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink. • To define a value approximately equal to a junction-to-board thermal resistance, the thermal resistance is measured from the junction to the point at which the leads attach to the case. • If the temperature of the package case (TT) is determined by a thermocouple, thermal resistance is computed from the value obtained by the equation (T J – TT)/PD. As noted earlier, the junction-to-case thermal resistances quoted in this data sheet are determined using the first definition. From a practical standpoint, that value is also suitable to determine the junction temperature from a case thermocouple reading in forced convection environments. In natural convection, the use of the junction-to-case thermal resistance to estimate junction temperature from a thermocouple reading on the case of the package will yield an estimate of a junction temperature slightly higher than actual temperature. Hence, the new thermal metric, thermal characterization parameter or ΨJT, has been defined to be (TJ – TT)/PD. This value gives a better estimate of the junction temperature in natural convection when the surface temperature of the package is used. Remember that surface temperature readings of packages are subject to significant errors caused by inadequate attachment of the sensor to the surface and to errors caused by heat loss to the sensor. The recommended technique is to attach a 40-gauge thermocouple wire and bead to the top center of the package with thermally conductive epoxy. 4.2 Electrical Design Considerations CAUTION This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for example, either GND or VCC). 4-2 Electrical Design Considerations Use the following list of recommendations to ensure correct DSP operation. • Provide a low-impedance path from the board power supply to each VCC pin on the DSP and from the board ground to each GND pin. • Use at least six 0.01–0.1 µF bypass capacitors positioned as close as possible to the four sides of the package to connect the VCC power source to GND. • Ensure that capacitor leads and associated printed circuit traces that connect to the chip VCC and GND pins are less than 0.5 inch per capacitor lead. • Use at least a four-layer PCB with two inner layers for VCC and GND. • Because the DSP output signals have fast rise and fall times, PCB trace lengths should be minimal. This recommendation particularly applies to the address and data buses as well as the IRQA, IRQB, IRQC, IRQD, TA, and BG pins. Maximum PCB trace lengths on the order of 6 inches are recommended. • Consider all device loads as well as parasitic capacitance due to PCB traces when you calculate capacitance. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the VCC and GND circuits. • All inputs must be terminated (that is, not allowed to float) by CMOS levels except for the three pins with internal pull-up resistors (TRST, TMS, DE). • Take special care to minimize noise levels on the VCCP, GNDP, and GNDP1 pins. • The following pins must be asserted after power-up: RESET and TRST. • If multiple DSP devices are on the same board, check for cross-talk or excessive spikes on the supplies due to synchronous operation of the devices. • RESET must be asserted when the chip is powered up. A stable EXTAL signal should be supplied before deassertion of RESET. • The Port A data bus (D[0–23]), HI08, ESSI0, ESSI1, SCI, and timers all use internal keepers to maintain the last output value even when the internal signal is tri-stated. Typically, no pull-up or pull-down resistors should be used with these signal lines. However, if the DSP is connected to a device that requires pull-up resistors (such as an MPC8260), the recommended resistor value is 10 KΩ or less. If more than one DSP must be connected in parallel to the other device, the pull-up resistor value requirement changes as follows: — 2 DSPs = 7 KΩ or less — 3 DSPs = 4 KΩ or less — 4 DSPs = 3 KΩ or less — 5 DSPs = 2 KΩ or less — 6 DSPs = 1.5 KΩ or less 4-3 Power Consumption Considerations 4.3 Power Consumption Considerations Power dissipation is a key issue in portable DSP applications. Some of the factors affecting current consumption are described in this section. Most of the current consumed by CMOS devices is alternating current (ac), which is charging and discharging the capacitances of the pins and internal nodes. Current consumption is described by this formula: Equation 3: I = C × V × f Where: C V f = = = node/pin capacitance voltage swing frequency of node/pin toggle Example 4-1. Current Consumption For a Port A address pin loaded with 50 pF capacitance, operating at 3.3 V, with a 66 MHz clock, toggling at its maximum possible rate (33 MHz), the current consumption is expressed in Equation 4. I = 50 × 10 Equation 4: – 12 6 × 3.3 × 33 × 10 = 5.48 mA The maximum internal current (ICCImax) value reflects the typical possible switching of the internal buses on best-case operation conditions—not necessarily a real application case. The typical internal current (ICCItyp) value reflects the average switching of the internal buses on typical operating conditions. Perform the following steps for applications that require very low current consumption: 1. 2. 3. 4. 5. 6. 7. Set the EBD bit when you are not accessing external memory. Minimize external memory accesses, and use internal memory accesses. Minimize the number of pins that are switching. Minimize the capacitive load on the pins. Connect the unused inputs to pull-up or pull-down resistors. Disable unused peripherals. Disable unused pin activity (for example, CLKOUT, XTAL). One way to evaluate power consumption is to use a current-per-MIPS measurement methodology to minimize specific board effects (that is, to compensate for measured board current not caused by the DSP). A benchmark power consumption test algorithm is listed in Appendix A. Use the test algorithm, specific test current measurements, and the following equation to derive the current-per-MIPS value. Equation 5: I ⁄ MIPS = I ⁄ MHz = ( I typF2 – I typF1 ) ⁄ ( F2 – F1 ) Where: 4-4 ItypF2 ItypF1 F2 F1 = = = = current at F2 current at F1 high frequency (any specified operating frequency) low frequency (any specified operating frequency lower than F2) Note: F1 should be significantly less than F2. For example, F2 could be 66 MHz and F1 could be 33 MHz. The degree of difference between F1 and F2 determines the amount of precision with which the current rating can be determined for an application. PLL Performance Issues 4.4 PLL Performance Issues The following explanations should be considered as general observations on expected PLL behavior. There is no test that replicates these exact numbers. These observations were measured on a limited number of parts and were not verified over the entire temperature and voltage ranges. 4.4.1 Phase Skew Performance The phase skew of the PLL is defined as the time difference between the falling edges of EXTAL and CLKOUT for a given capacitive load on CLKOUT, over the entire process, temperature and voltage ranges. As defined in Figure 2-2, External Clock Timing, on page 2-5 for input frequencies greater than 15 MHz and the MF ≤ 4, this skew is greater than or equal to 0.0 ns and less than 1.8 ns; otherwise, this skew is not guaranteed. However, for MF < 10 and input frequencies greater than 10 MHz, this skew is between −1.4 ns and +3.2 ns. 4.4.2 Phase Jitter Performance The phase jitter of the PLL is defined as the variations in the skew between the falling edges of EXTAL and CLKOUT for a given device in specific temperature, voltage, input frequency, MF, and capacitive load on CLKOUT. These variations are a result of the PLL locking mechanism. For input frequencies greater than 15 MHz and MF ≤ 4, this jitter is less than ±0.6 ns; otherwise, this jitter is not guaranteed. However, for MF < 10 and input frequencies greater than 10 MHz, this jitter is less than ±2 ns. 4.4.3 Frequency Jitter Performance The frequency jitter of the PLL is defined as the variation of the frequency of CLKOUT. For small MF (MF < 10) this jitter is smaller than 0.5 percent. For mid-range MF (10 < MF < 500) this jitter is between 0.5 percent and approximately 2 percent. For large MF (MF > 500), the frequency jitter is 2–3 percent. 4.5 Input (EXTAL) Jitter Requirements The allowed jitter on the frequency of EXTAL is 0.5 percent. If the rate of change of the frequency of EXTAL is slow (that is, it does not jump between the minimum and maximum values in one cycle) or the frequency of the jitter is fast (that is, it does not stay at an extreme value for a long time), then the allowed jitter can be 2 percent. The phase and frequency jitter performance results are valid only if the input jitter is less than the prescribed values. 4-5 Input (EXTAL) Jitter Requirements 4-6 Appendix A Power Consumption Benchmark The following benchmark program evaluates DSP56311 power use in a test situation. It enables the PLL, disables the external clock, and uses repeated multiply-accumulate (MAC) instructions with a set of synthetic DSP application data to emulate intensive sustained DSP operation. ;************************************************************************** ;************************************************************************** ;* * ;* CHECKS Typical Power Consumption * ;* * ;************************************************************************** page 200,55,0,0,0 nolist I_VEC EQU START EQU INT_PROG INT_XDAT INT_YDAT $000000; Interrupt vectors for program debug only $8000; MAIN (external) program starting address EQU $100 ; INTERNAL program memory starting address EQU $0; INTERNAL X-data memory starting address EQU $0; INTERNAL Y-data memory starting address INCLUDE "ioequ.asm" INCLUDE "intequ.asm" list org P:START ; movep #$0243FF,x:M_BCR ;; BCR: Area 3 = 2 w.s (SRAM) ; Default: 2w.s (SRAM) ; movep #$0d0000,x:M_PCTL ; XTAL disable ; PLL enable ; CLKOUT disable ; ; Load the program ; move #INT_PROG,r0 move #PROG_START,r1 do #(PROG_END-PROG_START),PLOAD_LOOP move p:(r1)+,x0 move x0,p:(r0)+ nop PLOAD_LOOP ; ; Load the X-data ; move #INT_XDAT,r0 move #XDAT_START,r1 do #(XDAT_END-XDAT_START),XLOAD_LOOP move p:(r1)+,x0 move x0,x:(r0)+ XLOAD_LOOP ; ; Load the Y-data ; move #INT_YDAT,r0 move #YDAT_START,r1 do #(YDAT_END-YDAT_START),YLOAD_LOOP move p:(r1)+,x0 move x0,y:(r0)+ YLOAD_LOOP ; jmp PROG_START move move move move ; clr INT_PROG #$0,r0 #$0,r4 #$3f,m0 #$3f,m4 a A-1 Power Consumption Benchmark ; sbr clr move move move move bset b #$0,x0 #$0,x1 #$0,y0 #$0,y1 #4,omr dor mac mac add mac mac move #60,_end x0,y0,a x:(r0)+,x1 x1,y1,a x:(r0)+,x0 a,b x0,y0,a x:(r0)+,x1 x1,y1,a b1,x:$ff _end bra nop nop nop nop PROG_END nop nop XDAT_START ; org dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc A-2 sbr x:0 $262EB9 $86F2FE $E56A5F $616CAC $8FFD75 $9210A $A06D7B $CEA798 $8DFBF1 $A063D6 $6C6657 $C2A544 $A3662D $A4E762 $84F0F3 $E6F1B0 $B3829 $8BF7AE $63A94F $EF78DC $242DE5 $A3E0BA $EBAB6B $8726C8 $CA361 $2F6E86 $A57347 $4BE774 $8F349D $A1ED12 $4BFCE3 $EA26E0 $CD7D99 $4BA85E $27A43F $A8B10C $D3A55 $25EC6A $2A255B $A5F1F8 $2426D1 $AE6536 $CBBC37 $6235A4 $37F0D $63BEC2 $A5E4D3 $8CE810 $3FF09 $60E50E $CFFB2F $40753C $8262C5 $CA641A ; ebd y:(r4)+,y1 y:(r4)+,y0 y:(r4)+,y0 Power Consumption Benchmark dc dc dc dc dc dc dc dc dc dc XDAT_END YDAT_START ; org dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc YDAT_END $EB3B4B $2DA928 $AB6641 $28A7E6 $4E2127 $482FD4 $7257D $E53C72 $1A8C3 $E27540 y:0 $5B6DA $C3F70B $6A39E8 $81E801 $C666A6 $46F8E7 $AAEC94 $24233D $802732 $2E3C83 $A43E00 $C2B639 $85A47E $ABFDDF $F3A2C $2D7CF5 $E16A8A $ECB8FB $4BED18 $43F371 $83A556 $E1E9D7 $ACA2C4 $8135AD $2CE0E2 $8F2C73 $432730 $A87FA9 $4A292E $A63CCF $6BA65C $E06D65 $1AA3A $A1B6EB $48AC48 $EF7AE1 $6E3006 $62F6C7 $6064F4 $87E41D $CB2692 $2C3863 $C6BC60 $43A519 $6139DE $ADF7BF $4B3E8C $6079D5 $E0F5EA $8230DB $A3B778 $2BFE51 $E0A6B6 $68FFB7 $28F324 $8F2E8D $667842 $83E053 $A1FD90 $6B2689 $85B68E $622EAF $6162BC $E4A245 ;************************************************************************** A-3 Power Consumption Benchmark ; ; EQUATES for DSP56311 I/O registers and ports ; ; Last update: June 11 1995 ; ;************************************************************************** page opt ioequ ident 132,55,0,0,0 mex 1,0 ;-----------------------------------------------------------------------; ; EQUATES for I/O Port Programming ; ;-----------------------------------------------------------------------; Register Addresses M_HDR EQU $FFFFC9 M_HDDR EQU $FFFFC8 M_PCRC EQU $FFFFBF M_PRRC EQU $FFFFBE M_PDRC EQU $FFFFBD M_PCRD EQU $FFFFAF M_PRRD EQU $FFFFAE M_PDRD EQU $FFFFAD M_PCRE EQU $FFFF9F M_PRRE EQU $FFFF9E M_PDRE EQU $FFFF9D M_OGDB EQU $FFFFFC ; ; ; ; Host port GPIO data Register Host port GPIO direction Register Port C Control Register Port C Direction Register ; Port C GPIO Data Register ; Port D Control register ; Port D Direction Data Register ; Port D GPIO Data Register ; Port E Control register ; Port E Direction Register ; Port E Data Register ; OnCE GDB Register ;-----------------------------------------------------------------------; ; EQUATES for Host Interface ; ;-----------------------------------------------------------------------; Register Addresses M_HCR EQU $FFFFC2 M_HSR EQU $FFFFC3 M_HPCR EQU $FFFFC4 M_HBAR EQU $FFFFC5 M_HRX EQU $FFFFC6 M_HTX EQU $FFFFC7 ; ; ; ; Host Control Register Host Status Register Host Polarity Control Register Host Base Address Register ; Host Receive Register ; Host Transmit Register ; HCR bits definition M_HRIE EQU $0 ; Host Receive interrupts Enable M_HTIE EQU $1 ; Host Transmit Interrupt Enable M_HCIE EQU $2 ; Host Command Interrupt Enable M_HF2 EQU $3 ; Host Flag 2 M_HF3 EQU $4 ; Host Flag 3 ; HSR bits definition M_HRDF EQU $0 ; Host Receive Data Full M_HTDE EQU $1 ; Host Receive Data Empty M_HCP EQU $2 ; Host Command Pending M_HF0 EQU $3 ; Host Flag 0 M_HF1 EQU $4 ; Host Flag 1 ; HPCR bits definition M_HGEN EQU $0 ; Host Port GPIO Enable M_HA8EN EQU $1 ; Host Address 8 Enable M_HA9EN EQU $2 ; Host Address 9 Enable M_HCSEN EQU $3 ; Host Chip Select Enable M_HREN EQU $4 ; Host Request Enable M_HAEN EQU $5 ; Host Acknowledge Enable M_HEN EQU $6 ; Host Enable M_HOD EQU $8 ; Host Request Open Drain mode M_HDSP EQU $9 ; Host Data Strobe Polarity M_HASP EQU $A ; Host Address Strobe Polarity M_HMUX EQU $B ; Host Multiplexed bus select M_HD_HS EQU $C ; Host Double/Single Strobe select M_HCSP EQU $D ; Host Chip Select Polarity M_HRP EQU $E ; Host Request Polarity M_HAP EQU $F ; Host Acknowledge Polarity A-4 Power Consumption Benchmark ;-----------------------------------------------------------------------; ; EQUATES for Serial Communications Interface (SCI) ; ;-----------------------------------------------------------------------; Register Addresses M_STXH EQU $FFFF97 M_STXM EQU $FFFF96 M_STXL EQU $FFFF95 M_SRXH EQU $FFFF9A M_SRXM EQU $FFFF99 M_SRXL EQU $FFFF98 M_STXA EQU $FFFF94 M_SCR EQU $FFFF9C M_SSR EQU $FFFF93 M_SCCR EQU $FFFF9B ; ; Word Select Mask (WDS0-WDS3) ; Word Select 0 ; Word Select 1 ; Word Select 2 ; SCI Shift Direction ; Send Break ; Wakeup Mode Select ; Receiver Wakeup Enable ; Wired-OR Mode Select ; SCI Receiver Enable ; SCI Transmitter Enable ; Idle Line Interrupt Enable ; SCI Receive Interrupt Enable ; SCI Transmit Interrupt Enable ; Timer Interrupt Enable ; Timer Interrupt Rate ; SCI Clock Polarity ; SCI Error Interrupt Enable (REIE) SCI Status Register Bit Flags M_TRNE EQU M_TDRE EQU M_RDRF EQU M_IDLE EQU M_OR EQU 4 M_PE EQU 5 M_FE EQU 6 M_R8 EQU 7 ; SCI Transmit Data Register (high) SCI Transmit Data Register (middle) SCI Transmit Data Register (low) SCI Receive Data Register (high) SCI Receive Data Register (middle) SCI Receive Data Register (low) ; SCI Transmit Address Register ; SCI Control Register ; SCI Status Register ; SCI Clock Control Register SCI Control Register Bit Flags M_WDS EQU $7 M_WDS0 EQU 0 M_WDS1 EQU 1 M_WDS2 EQU 2 M_SSFTD EQU 3 M_SBK EQU 4 M_WAKE EQU 5 M_RWU EQU 6 M_WOMS EQU 7 M_SCRE EQU 8 M_SCTE EQU 9 M_ILIE EQU 10 M_SCRIE EQU 11 M_SCTIE EQU 12 M_TMIE EQU 13 M_TIR EQU 14 M_SCKP EQU 15 M_REIE EQU 16 ; ; ; ; ; ; ; 0 1 2 3 ; ; ; ; ; Transmitter Empty ; Transmit Data Register Empty ; Receive Data Register Full ; Idle Line Flag Overrun Error Flag Parity Error Framing Error Flag Received Bit 8 (R8) Address SCI Clock Control Register M_CD EQU $FFF M_COD EQU 12 M_SCP EQU 13 M_RCM EQU 14 M_TCM EQU 15 ; Clock Divider Mask (CD0-CD11) ; Clock Out Divider ; Clock Prescaler ; Receive Clock Mode Source Bit ; Transmit Clock Source Bit ;-----------------------------------------------------------------------; ; EQUATES for Synchronous Serial Interface (SSI) ; ;-----------------------------------------------------------------------; ; Register Addresses Of SSI0 M_TX00 EQU $FFFFBC ; SSI0 Transmit Data Register 0 M_TX01 EQU $FFFFBB ; SSIO Transmit Data Register 1 M_TX02 EQU $FFFFBA ; SSIO Transmit Data Register 2 M_TSR0 EQU $FFFFB9 ; SSI0 Time Slot Register M_RX0 EQU $FFFFB8 ; SSI0 Receive Data Register M_SSISR0 EQU $FFFFB7 ; SSI0 Status Register M_CRB0 EQU $FFFFB6 ; SSI0 Control Register B M_CRA0 EQU $FFFFB5 ; SSI0 Control Register A M_TSMA0 EQU $FFFFB4 ; SSI0 Transmit Slot Mask Register A M_TSMB0 EQU $FFFFB3 ; SSI0 Transmit Slot Mask Register B M_RSMA0 EQU $FFFFB2 ; SSI0 Receive Slot Mask Register A M_RSMB0 EQU $FFFFB1 ; SSI0 Receive Slot Mask Register B A-5 Power Consumption Benchmark ; Register Addresses Of SSI1 M_TX10 EQU $FFFFAC ; SSI1 Transmit Data Register 0 M_TX11 EQU $FFFFAB ; SSI1 Transmit Data Register 1 M_TX12 EQU $FFFFAA ; SSI1 Transmit Data Register 2 M_TSR1 EQU $FFFFA9 ; SSI1 Time Slot Register M_RX1 EQU $FFFFA8 ; SSI1 Receive Data Register M_SSISR1 EQU $FFFFA7 ; SSI1 Status Register M_CRB1 EQU $FFFFA6 ; SSI1 Control Register B M_CRA1 EQU $FFFFA5 ; SSI1 Control Register A M_TSMA1 EQU $FFFFA4 ; SSI1 Transmit Slot Mask Register A M_TSMB1 EQU $FFFFA3 ; SSI1 Transmit Slot Mask Register B M_RSMA1 EQU $FFFFA2 ; SSI1 Receive Slot Mask Register A M_RSMB1 EQU $FFFFA1 ; SSI1 Receive Slot Mask Register B ; SSI Control Register A Bit Flags M_PM EQU $FF M_PSR EQU 11 M_DC EQU $1F000 M_ALC EQU 18 M_WL EQU $380000 M_SSC1 EQU 22 ; SSI Control Register B Bit Flags M_OF EQU $3 M_OF0 EQU 0 M_OF1 EQU 1 M_SCD EQU $1C M_SCD0 EQU 2 M_SCD1 EQU 3 M_SCD2 EQU 4 M_SCKD EQU 5 M_SHFD EQU 6 M_FSL EQU $180 M_FSL0 EQU 7 M_FSL1 EQU 8 M_FSR EQU 9 M_FSP EQU 10 M_CKP EQU 11 M_SYN EQU 12 M_MOD EQU 13 M_SSTE EQU $1C000 M_SSTE2 EQU 14 M_SSTE1 EQU 15 M_SSTE0 EQU 16 M_SSRE EQU 17 M_SSTIE EQU 18 M_SSRIE EQU 19 M_STLIE EQU 20 M_SRLIE EQU 21 M_STEIE EQU 22 M_SREIE EQU 23 ; ; SSI Receive Slot Bits Mask A (RS0-RS15) SSI Receive Slot Mask Register B M_SSRSB EQU $FFFF A-6 ; SSI Transmit Slot Bits Mask B (TS16-TS31) SSI Receive Slot Mask Register A M_SSRSA EQU $FFFF ; ; SSI Transmit Slot Bits Mask A (TS0-TS15) SSI Transmit Slot Mask Register B M_SSTSB EQU $FFFF ; ; Serial Input Flag Mask ; Serial Input Flag 0 ; Serial Input Flag 1 ; Transmit Frame Sync Flag ; Receive Frame Sync Flag ; Transmitter Underrun Error FLag ; Receiver Overrun Error Flag ; Transmit Data Register Empty ; Receive Data Register Full SSI Transmit Slot Mask Register A M_SSTSA EQU $FFFF ; ; Serial Output Flag Mask ; Serial Output Flag 0 ; Serial Output Flag 1 ; Serial Control Direction Mask ; Serial Control 0 Direction ; Serial Control 1 Direction ; Serial Control 2 Direction ; Clock Source Direction ; Shift Direction ; Frame Sync Length Mask (FSL0-FSL1) ; Frame Sync Length 0 ; Frame Sync Length 1 ; Frame Sync Relative Timing ; Frame Sync Polarity ; Clock Polarity ; Sync/Async Control ; SSI Mode Select ; SSI Transmit enable Mask ; SSI Transmit #2 Enable ; SSI Transmit #1 Enable ; SSI Transmit #0 Enable ; SSI Receive Enable ; SSI Transmit Interrupt Enable ; SSI Receive Interrupt Enable ; SSI Transmit Last Slot Interrupt Enable ; SSI Receive Last Slot Interrupt Enable ; SSI Transmit Error Interrupt Enable ; SI Receive Error Interrupt Enable SSI Status Register Bit Flags M_IF EQU $3 M_IF0 EQU 0 M_IF1 EQU 1 M_TFS EQU 2 M_RFS EQU 3 M_TUE EQU 4 M_ROE EQU 5 M_TDE EQU 6 M_RDF EQU 7 ; ; Prescale Modulus Select Mask (PM0-PM7) ; Prescaler Range ; Frame Rate Divider Control Mask (DC0-DC7) ; Alignment Control (ALC) ; Word Length Control Mask (WL0-WL7) ; Select SC1 as TR #0 drive enable (SSC1) ; SSI Receive Slot Bits Mask B (RS16-RS31) Power Consumption Benchmark ;-----------------------------------------------------------------------; ; EQUATES for Exception Processing ; ;-----------------------------------------------------------------------; Register Addresses M_IPRC EQU $FFFFFF M_IPRP EQU $FFFFFE ; Interrupt Priority Register Core (IPRC) M_IAL EQU $7 M_IAL0 EQU 0 M_IAL1 EQU 1 M_IAL2 EQU 2 M_IBL EQU $38 M_IBL0 EQU 3 M_IBL1 EQU 4 M_IBL2 EQU 5 M_ICL EQU $1C0 M_ICL0 EQU 6 M_ICL1 EQU 7 M_ICL2 EQU 8 M_IDL EQU $E00 M_IDL0 EQU 9 M_IDL1 EQU 10 M_IDL2 EQU 11 M_D0L EQU $3000 M_D0L0 EQU 12 M_D0L1 EQU 13 M_D1L EQU $C000 M_D1L0 EQU 14 M_D1L1 EQU 15 M_D2L EQU $30000 M_D2L0 EQU 16 M_D2L1 EQU 17 M_D3L EQU $C0000 M_D3L0 EQU 18 M_D3L1 EQU 19 M_D4L EQU $300000 M_D4L0 EQU 20 M_D4L1 EQU 21 M_D5L EQU $C00000 M_D5L0 EQU 22 M_D5L1 EQU 23 ; ; Interrupt Priority Register Core ; Interrupt Priority Register Peripheral ; IRQA Mode Mask ; IRQA Mode Interrupt Priority Level (low) ; IRQA Mode Interrupt Priority Level (high) ; IRQA Mode Trigger Mode ; IRQB Mode Mask ; IRQB Mode Interrupt Priority Level (low) ; IRQB Mode Interrupt Priority Level (high) ; IRQB Mode Trigger Mode ; IRQC Mode Mask ; IRQC Mode Interrupt Priority Level (low) ; IRQC Mode Interrupt Priority Level (high) ; IRQC Mode Trigger Mode ; IRQD Mode Mask ; IRQD Mode Interrupt Priority Level (low) ; IRQD Mode Interrupt Priority Level (high) ; IRQD Mode Trigger Mode ; DMA0 Interrupt priority Level Mask ; DMA0 Interrupt Priority Level (low) ; DMA0 Interrupt Priority Level (high) ; DMA1 Interrupt Priority Level Mask ; DMA1 Interrupt Priority Level (low) ; DMA1 Interrupt Priority Level (high) ; DMA2 Interrupt priority Level Mask ; DMA2 Interrupt Priority Level (low) ; DMA2 Interrupt Priority Level (high) ; DMA3 Interrupt Priority Level Mask ; DMA3 Interrupt Priority Level (low) ; DMA3 Interrupt Priority Level (high) ; DMA4 Interrupt priority Level Mask ; DMA4 Interrupt Priority Level (low) ; DMA4 Interrupt Priority Level (high) ; DMA5 Interrupt priority Level Mask ; DMA5 Interrupt Priority Level (low) ; DMA5 Interrupt Priority Level (high) Interrupt Priority Register Peripheral (IPRP) M_HPL EQU $3 M_HPL0 EQU 0 M_HPL1 EQU 1 M_S0L EQU $C M_S0L0 EQU 2 M_S0L1 EQU 3 M_S1L EQU $30 M_S1L0 EQU 4 M_S1L1 EQU 5 M_SCL EQU $C0 M_SCL0 EQU 6 M_SCL1 EQU 7 M_T0L EQU $300 M_T0L0 EQU 8 M_T0L1 EQU 9 ; Host Interrupt Priority Level Mask ; Host Interrupt Priority Level (low) ; Host Interrupt Priority Level (high) ; SSI0 Interrupt Priority Level Mask ; SSI0 Interrupt Priority Level (low) ; SSI0 Interrupt Priority Level (high) ; SSI1 Interrupt Priority Level Mask ; SSI1 Interrupt Priority Level (low) ; SSI1 Interrupt Priority Level (high) ; SCI Interrupt Priority Level Mask ; SCI Interrupt Priority Level (low) ; SCI Interrupt Priority Level (high) ; TIMER Interrupt Priority Level Mask ; TIMER Interrupt Priority Level (low) ; TIMER Interrupt Priority Level (high) ;-----------------------------------------------------------------------; ; EQUATES for TIMER ; ;-----------------------------------------------------------------------; Register Addresses Of TIMER0 M_TCSR0 EQU $FFFF8F ; Timer 0 Control/Status Register A-7 Power Consumption Benchmark M_TLR0 EQU $FFFF8E M_TCPR0 EQU $FFFF8D M_TCR0 EQU $FFFF8C ; Register Addresses Of TIMER1 M_TCSR1 EQU M_TLR1 EQU M_TCPR1 EQU M_TCR1 EQU ; $FFFF8B $FFFF8A $FFFF89 $FFFF88 ; TIMER1 Control/Status Register ; TIMER1 Load Reg ; TIMER1 Compare Register ; TIMER1 Count Register Register Addresses Of TIMER2 M_TCSR2 EQU M_TLR2 EQU M_TCPR2 EQU M_TCR2 EQU M_TPLR EQU M_TPCR EQU ; ; TIMER0 Load Reg ; TIMER0 Compare Register ; TIMER0 Count Register $FFFF87 $FFFF86 $FFFF85 $FFFF84 $FFFF83 $FFFF82 ; ; ; ; ; Timer Control/Status Register Bit Flags M_TE EQU 0 M_TOIE EQU 1 M_TCIE EQU 2 M_TC EQU $F0 M_INV EQU 8 M_TRM EQU 9 M_DIR EQU 11 M_DI EQU 12 M_DO EQU 13 M_PCE EQU 15 M_TOF EQU 20 M_TCF EQU 21 ; ; ; ; ; ; ; ; ; ; ; ; ; Timer Enable Timer Overflow Interrupt Enable Timer Compare Interrupt Enable Timer Control Mask (TC0-TC3) Inverter Bit Timer Restart Mode Direction Bit Data Input Data Output Prescaled Clock Enable Timer Overflow Flag Timer Compare Flag Timer Prescaler Register Bit Flags M_PS EQU $600000 M_PS0 EQU 21 M_PS1 EQU 22 ; M_TC0 M_TC1 M_TC2 M_TC3 ; TIMER2 Control/Status Register TIMER2 Load Reg TIMER2 Compare Register TIMER2 Count Register TIMER Prescaler Load Register TIMER Prescalar Count Register ; Prescaler Source Mask Timer Control Bits EQU 4 ; Timer EQU 5 ; Timer EQU 6 ; Timer EQU 7 ; Timer Control Control Control Control 0 1 2 3 ;-----------------------------------------------------------------------; ; EQUATES for Direct Memory Access (DMA) ; ;-----------------------------------------------------------------------; M_DSTR M_DOR0 M_DOR1 M_DOR2 M_DOR3 ; M_DSR0 M_DDR0 M_DCO0 M_DCR0 ; M_DSR1 M_DDR1 M_DCO1 M_DCR1 ; Register Addresses Of DMA EQU FFFFF4 ; DMA Status Register EQU $FFFFF3 ; DMA Offset Register 0 EQU $FFFFF2 ; DMA Offset Register 1 EQU $FFFFF1 ; DMA Offset Register 2 EQU $FFFFF0 ; DMA Offset Register 3 Register Addresses Of DMA0 EQU EQU EQU EQU $FFFFEF $FFFFEE $FFFFED $FFFFEC ; ; ; ; DMA0 DMA0 DMA0 DMA0 Source Address Register Destination Address Register Counter Control Register Register Addresses Of DMA1 EQU EQU EQU EQU $FFFFEB $FFFFEA $FFFFE9 $FFFFE8 ; ; ; ; DMA1 DMA1 DMA1 DMA1 Source Address Register Destination Address Register Counter Control Register Register Addresses Of DMA2 M_DSR2 EQU $FFFFE7 ; DMA2 Source Address Register A-8 Power Consumption Benchmark M_DDR2 EQU $FFFFE6 ; DMA2 Destination Address Register M_DCO2 EQU $FFFFE5 ; DMA2 Counter M_DCR2 EQU $FFFFE4 ; DMA2 Control Register ; M_DSR3 M_DDR3 M_DCO3 M_DCR3 ; M_DSR4 M_DDR4 M_DCO4 M_DCR4 ; M_DSR5 M_DDR5 M_DCO5 M_DCR5 ; Register Addresses Of DMA4 EQU EQU EQU EQU $FFFFE3 $FFFFE2 $FFFFE1 $FFFFE0 ; ; ; ; DMA3 DMA3 DMA3 DMA3 Source Address Register Destination Address Register Counter Control Register Register Addresses Of DMA4 EQU EQU EQU EQU $FFFFDF $FFFFDE $FFFFDD $FFFFDC ; ; ; ; DMA4 DMA4 DMA4 DMA4 Source Address Register Destination Address Register Counter Control Register Register Addresses Of DMA5 EQU EQU EQU EQU $FFFFDB $FFFFDA $FFFFD9 $FFFFD8 ; ; ; ; DMA5 DMA5 DMA5 DMA5 Source Address Register Destination Address Register Counter Control Register DMA Control Register M_DSS EQU $3 ; DMA Source Space Mask (DSS0-Dss1) M_DSS0 EQU 0 ; DMA Source Memory space 0 M_DSS1 EQU 1 ; DMA Source Memory space 1 M_DDS EQU $C ; DMA Destination Space Mask (DDS-DDS1) M_DDS0 EQU 2 ; DMA Destination Memory Space 0 M_DDS1 EQU 3 ; DMA Destination Memory Space 1 M_DAM EQU $3f0 ; DMA Address Mode Mask (DAM5-DAM0) M_DAM0 EQU 4 ; DMA Address Mode 0 M_DAM1 EQU 5 ; DMA Address Mode 1 M_DAM2 EQU 6 ; DMA Address Mode 2 M_DAM3 EQU 7 ; DMA Address Mode 3 M_DAM4 EQU 8 ; DMA Address Mode 4 M_DAM5 EQU 9 ; DMA Address Mode 5 M_D3D EQU 10 ; DMA Three Dimensional Mode M_DRS EQU $F800; DMA Request Source Mask (DRS0-DRS4) M_DCON EQU 16 ; DMA Continuous Mode M_DPR EQU $60000; DMA Channel Priority M_DPR0 EQU 17 ; DMA Channel Priority Level (low) M_DPR1 EQU 18 ; DMA Channel Priority Level (high) M_DTM EQU $380000; DMA Transfer Mode Mask (DTM2-DTM0) M_DTM0 EQU 19 ; DMA Transfer Mode 0 M_DTM1 EQU 20 ; DMA Transfer Mode 1 M_DTM2 EQU 21 ; DMA Transfer Mode 2 M_DIE EQU 22 ; DMA Interrupt Enable bit M_DE EQU 23 ; DMA Channel Enable bit ; DMA Status Register M_DTD EQU $3F ; M_DTD0 EQU 0 ; M_DTD1 EQU 1 ; M_DTD2 EQU 2 ; M_DTD3 EQU 3 ; M_DTD4 EQU 4 ; M_DTD5 EQU 5 ; M_DACT EQU 8 ; M_DCH EQU $E00; M_DCH0 EQU 9 ; M_DCH1 EQU 10 ; M_DCH2 EQU 11 ; Channel Transfer Done Status MASK (DTD0-DTD5) DMA Channel Transfer Done Status 0 DMA Channel Transfer Done Status 1 DMA Channel Transfer Done Status 2 DMA Channel Transfer Done Status 3 DMA Channel Transfer Done Status 4 DMA Channel Transfer Done Status 5 DMA Active State DMA Active Channel Mask (DCH0-DCH2) DMA Active Channel 0 DMA Active Channel 1 DMA Active Channel 2 ;-----------------------------------------------------------------------; ; EQUATES for Enhanced Filter Co-Processor (EFCOP) ; ;-----------------------------------------------------------------------M_FDIR M_FDOR M_FKIR M_FCNT M_FCSR M_FACR EQU EQU EQU EQU EQU EQU $FFFFB0 $FFFFB1 $FFFFB2 $FFFFB3 $FFFFB4 $FFFFB5 ; ; ; ; ; ; EFCOP EFCOP EFCOP EFCOP EFCOP EFCOP Data Input Register Data Output Register K-Constant Register Filter Counter Control Status Register ALU Control Register A-9 Power Consumption Benchmark M_FDBA M_FCBA M_FDCH EQU EQU EQU $FFFFB6 $FFFFB7 $FFFFB8 ; EFCOP Data Base Address ; EFCOP Coefficient Base Address ; EFCOP Decimation/Channel Register ;-----------------------------------------------------------------------; ; EQUATES for Phase Locked Loop (PLL) ; ;-----------------------------------------------------------------------; Register Addresses Of PLL M_PCTL EQU $FFFFFD ; ; PLL Control Register PLL Control Register M_MF EQU $FFF : Multiplication Factor Bits Mask (MF0-MF11) M_DF EQU $7000 ; Division Factor Bits Mask (DF0-DF2) M_XTLR EQU 15 ; XTAL Range select bit M_XTLD EQU 16 ; XTAL Disable Bit M_PSTP EQU 17 ; STOP Processing State Bit M_PEN EQU 18 ; PLL Enable Bit M_PCOD EQU 19 ; PLL Clock Output Disable Bit M_PD EQU $F00000; PreDivider Factor Bits Mask (PD0-PD3) ;-----------------------------------------------------------------------; ; EQUATES for BIU ; ;-----------------------------------------------------------------------; Register Addresses Of BIU M_BCR EQU $FFFFFB; Bus Control Register M_DCR EQU $FFFFFA; DRAM Control Register M_AAR0 EQU $FFFFF9; Address Attribute Register M_AAR1 EQU $FFFFF8; Address Attribute Register M_AAR2 EQU $FFFFF7; Address Attribute Register M_AAR3 EQU $FFFFF6; Address Attribute Register M_IDR EQU $FFFFF5 ; ID Register ; 0 1 2 3 Bus Control Register M_BA0W EQU $1F ; Area 0 Wait Control Mask (BA0W0-BA0W4) M_BA1W EQU $3E0; Area 1 Wait Control Mask (BA1W0-BA14) M_BA2W EQU $1C00; Area 2 Wait Control Mask (BA2W0-BA2W2) M_BA3W EQU $E000; Area 3 Wait Control Mask (BA3W0-BA3W3) M_BDFW EQU $1F0000 ; Default Area Wait Control Mask (BDFW0-BDFW4) M_BBS EQU 21 ; Bus State M_BLH EQU 22 ; Bus Lock Hold M_BRH EQU 23 ; Bus Request Hold ; DRAM Control Register M_BCW EQU $3 ; In Page Wait States Bits Mask (BCW0-BCW1) M_BRW EQU $C ; Out Of Page Wait States Bits Mask (BRW0-BRW1) M_BPS EQU $300 ; DRAM Page Size Bits Mask (BPS0-BPS1) M_BPLE EQU 11 ; Page Logic Enable M_BME EQU 12 ; Mastership Enable M_BRE EQU 13 ; Refresh Enable M_BSTR EQU 14 ; Software Triggered Refresh M_BRF EQU $7F8000; Refresh Rate Bits Mask (BRF0-BRF7) M_BRP EQU 23 ; Refresh prescaler ; Address Attribute Registers M_BAT EQU $3 ; Ext. Access Type and Pin Def. Bits Mask (BAT0-BAT1) M_BAAP EQU 2 ; Address Attribute Pin Polarity M_BPEN EQU 3 ; Program Space Enable M_BXEN EQU 4 ; X Data Space Enable M_BYEN EQU 5 ; Y Data Space Enable M_BAM EQU 6 ; Address Muxing M_BPAC EQU 7 ; Packing Enable M_BNC EQU $F00 ; Number of Address Bits to Compare Mask (BNC0-BNC3) M_BAC EQU $FFF000; Address to Compare Bits Mask (BAC0-BAC11) A-10 Power Consumption Benchmark ; control and status bits in SR M_CP EQU $c00000; mask for CORE-DMA priority bits in SR M_CA EQU 0 ; Carry M_V EQU 1 ; Overflow M_Z EQU 2 ; Zero M_N EQU 3 ; Negative M_U EQU 4 ; Unnormalized M_E EQU 5 ; Extension M_L EQU 6 ; Limit M_S EQU 7 ; Scaling Bit M_I0 EQU 8 ; Interupt Mask Bit 0 M_I1 EQU 9 ; Interupt Mask Bit 1 M_S0 EQU 10 ; Scaling Mode Bit 0 M_S1 EQU 11 ; Scaling Mode Bit 1 M_SC EQU 13 ; Sixteen_Bit Compatibility M_DM EQU 14 ; Double Precision Multiply M_LF EQU 15 ; DO-Loop Flag M_FV EQU 16 ; DO-Forever Flag M_SA EQU 17 ; Sixteen-Bit Arithmetic M_CE EQU 19 ; Instruction Cache Enable M_SM EQU 20 ; Arithmetic Saturation M_RM EQU 21 ; Rounding Mode M_CP0 EQU 22 ; bit 0 of priority bits in SR M_CP1 EQU 23 ; bit 1 of priority bits in SR ; control and status bits in OMR M_CDP EQU $300 ; mask for CORE-DMA priority bits in OMR M_MA equ0 ; Operating Mode A M_MB equ1 ; Operating Mode B M_MC equ2 ; Operating Mode C M_MD equ3 ; Operating Mode D M_EBD EQU 4 ; External Bus Disable bit in OMR M_SD EQU 6 ; Stop Delay M_MS EQU 7 ; Memory Switch bit in OMR M_CDP0 EQU 8 ; bit 0 of priority bits in OMR M_CDP1 EQU 9 ; bit 1 of priority bits in OMR M_BEN EQU 10 ; Burst Enable M_TAS EQU 11 ; TA Synchronize Select M_BRT EQU 12 ; Bus Release Timing M_ATE EQU 15 ; Address Tracing Enable bit in OMR. M_XYS EQU 16 ; Stack Extension space select bit in OMR. M_EUN EQU 17 ; Extensed stack UNderflow flag in OMR. M_EOV EQU 18 ; Extended stack OVerflow flag in OMR. M_WRP EQU 19 ; Extended WRaP flag in OMR. M_SEN EQU 20 ; Stack Extension Enable bit in OMR. ;************************************************************************* ; ; EQUATES for DSP56311 interrupts ; ; Last update: June 11 1995 ; ;************************************************************************* page opt intequ ident 132,55,0,0,0 mex 1,0 if @DEF(I_VEC) ;leave user definition as is. else I_VEC EQU $0 endif ;-----------------------------------------------------------------------; Non-Maskable interrupts ;-----------------------------------------------------------------------I_RESET EQU I_VEC+$00 ; Hardware RESET I_STACK EQU I_VEC+$02 ; Stack Error I_ILL EQU I_VEC+$04 ; Illegal Instruction I_DBG EQU I_VEC+$06 ; Debug Request A-11 Power Consumption Benchmark I_TRAP EQU I_VEC+$08 I_NMI EQU I_VEC+$0A ; Trap ; Non Maskable Interrupt ;-----------------------------------------------------------------------; Interrupt Request Pins ;-----------------------------------------------------------------------I_IRQA EQU I_VEC+$10 ; IRQA I_IRQB EQU I_VEC+$12 ; IRQB I_IRQC EQU I_VEC+$14 ; IRQC I_IRQD EQU I_VEC+$16 ; IRQD ;-----------------------------------------------------------------------; DMA Interrupts ;-----------------------------------------------------------------------I_DMA0 EQU I_VEC+$18 ; DMA Channel 0 I_DMA1 EQU I_VEC+$1A ; DMA Channel 1 I_DMA2 EQU I_VEC+$1C ; DMA Channel 2 I_DMA3 EQU I_VEC+$1E ; DMA Channel 3 I_DMA4 EQU I_VEC+$20 ; DMA Channel 4 I_DMA5 EQU I_VEC+$22 ; DMA Channel 5 ;-----------------------------------------------------------------------; Timer Interrupts ;-----------------------------------------------------------------------I_TIM0C EQU I_VEC+$24 ; TIMER 0 compare I_TIM0OF EQU I_VEC+$26 ; TIMER 0 overflow I_TIM1C EQU I_VEC+$28 ; TIMER 1 compare I_TIM1OF EQU I_VEC+$2A ; TIMER 1 overflow I_TIM2C EQU I_VEC+$2C ; TIMER 2 compare I_TIM2OF EQU I_VEC+$2E ; TIMER 2 overflow ;-----------------------------------------------------------------------; ESSI Interrupts ;-----------------------------------------------------------------------I_SI0RD EQU I_VEC+$30 ; ESSI0 Receive Data I_SI0RDE EQU I_VEC+$32 ; ESSI0 Receive Data w/ exception Status I_SI0RLS EQU I_VEC+$34 ; ESSI0 Receive last slot I_SI0TD EQU I_VEC+$36 ; ESSI0 Transmit data I_SI0TDE EQU I_VEC+$38 ; ESSI0 Transmit Data w/ exception Status I_SI0TLS EQU I_VEC+$3A ; ESSI0 Transmit last slot I_SI1RD EQU I_VEC+$40 ; ESSI1 Receive Data I_SI1RDE EQU I_VEC+$42 ; ESSI1 Receive Data w/ exception Status I_SI1RLS EQU I_VEC+$44 ; ESSI1 Receive last slot I_SI1TD EQU I_VEC+$46 ; ESSI1 Transmit data I_SI1TDE EQU I_VEC+$48 ; ESSI1 Transmit Data w/ exception Status I_SI1TLS EQU I_VEC+$4A ; ESSI1 Transmit last slot ;-----------------------------------------------------------------------; SCI Interrupts ;-----------------------------------------------------------------------I_SCIRD EQU I_VEC+$50 ; SCI Receive Data I_SCIRDE EQU I_VEC+$52 ; SCI Receive Data With Exception Status I_SCITD EQU I_VEC+$54 ; SCI Transmit Data I_SCIIL EQU I_VEC+$56 ; SCI Idle Line I_SCITM EQU I_VEC+$58 ; SCI Timer ;-----------------------------------------------------------------------; HOST Interrupts ;-----------------------------------------------------------------------I_HRDF EQU I_VEC+$60 ; Host Receive Data Full I_HTDE EQU I_VEC+$62 ; Host Transmit Data Empty I_HC EQU I_VEC+$64 ; Default Host Command ;----------------------------------------------------------------------; EFCOP Filter Interrupts ;----------------------------------------------------------------------I_FDIIE I_FDOIE EQU EQU I_VEC+$68 ; EFilter input buffer empty I_VEC+$6A ; EFilter output buffer full ;-----------------------------------------------------------------------; INTERRUPT ENDING ADDRESS ;-----------------------------------------------------------------------I_INTEND EQU I_VEC+$FF ; last address of interrupt vector space A-12 Index A ac electrical characteristics 2-4 address bus 1-1 applications iv B benchmark test algorithm A-1 block diagram i bootstrap ROM iii Boundary Scan (JTAG Port) timing diagram 2-39 bus address 1-2 control 1-1 data 1-2 external address 1-5 external data 1-5 multiplexed 1-2 non-multiplexed 1-2 C clock 1-1, 1-4 external 2-4 clocks internal 2-4 crystal oscillator circuits 2-5 D data bus 1-1 data memory expansion iv Data Strobe (DS) 1-2 dc electrical characteristics 2-3 DE signal 1-18 Debug Event signal (DE signal) 1-18 Debug mode entering 1-18 external indication 1-18 Debug support iii design considerations electrical 4-2, 4-3 PLL 4-5 power consumption 4-4 thermal 4-1 documentation list v Double Data Strobe 1-2 DRAM controller iv out of page read access 2-21 wait states selection guide 2-18 write access 2-22 Page mode read accesses 2-17 wait states selection guide 2-14 write accesses 2-17 refresh access 2-22 DSP56300 Family Manual v DSP56311 block diagram i Technical Data v User’s Manual v E EFCOP interrupts A-12 electrical design considerations 4-2, 4-3 Enhanced Synchronous Serial Interface (ESSI) iii, 1-1, 1-2, 1-13, 1-14 receiver timing 2-35 transmitter timing 2-34 external address bus 1-5 external bus control 1-5, 1-6, 1-7 external clock operation 2-4 external data bus 1-5 external interrupt timing (negative edge-triggered) 2-10 external level-sensitive fast interrupt timing 2-9 external memory access (DMA Source) timing 2-11 External Memory Expansion Port 2-11 external memory expansion port 1-5 F functional groups 1-2 functional signal groups 1-1 G General-Purpose Input/Output (GPIO) iii, 1-2 ground 1-1, 1-3 PLL 1-3 H Host Interface (HI08) iii, 1-1, 1-2, 1-9, 1-10, 1-11, 1-12 Host Port Control Register (HPCR) 1-10, 1-12 host port configuration 1-9 usage considerations 1-9 Index-1 Index Host Port Control Register (HPCR) 1-10, 1-12 Host Request Double 1-2 Single 1-2 Host Request (HR) 1-2 I information sources v instruction cache iii internal clocks 2-4 interrupt and mode control 1-1, 1-8 interrupt control 1-8 interrupt timing 2-7 external level-sensitive fast 2-9 external negative edge-triggered 2-10 interrupts EFCOP A-12 J Joint Test Action Group (JTAG) interface 1-18 JTAG iii JTAG Port reset timing diagram 2-39 timing 2-39 JTAG/OnCE Interface signals Debug Event signal (DE signal) 1-18 JTAG/OnCE port 1-1, 1-2 K keeper circuit design considerations 4-3 M MAP-BGA ball grid drawing (bottom) 3-3 ball grid drawing (top) 3-2 mechanical drawing 3-10 maximum ratings 2-1, 2-2 memory expansion port iii mode control 1-8 Mode select timing 2-7 multiplexed bus 1-2 multiplexed bus timings read 2-28 write 2-29 N non-multiplexed bus 1-2 non-multiplexed bus timings Index-2 read 2-26 write 2-27 O off-chip memory iii OnCE module iii Debug request 2-40 on-chip DRAM controller iv On-Chip Emulation (OnCE) module interface 1-18 On-Chip Emulation module iii on-chip memory iii operating mode select timing 2-10 ordering information Back Cover P package MAP-BGA description 3-2, 3-3, 3-10 Phase-Lock Loop (PLL) 1-1, 2-6 design considerations 4-5 performance issues 4-5 PLL 1-4 Port A 1-1, 1-5, 2-11 Port B 1-1, 1-2, 1-11 Port C 1-1, 1-2, 1-13 Port D 1-1, 1-2, 1-14 Port E 1-1 power 1-1, 1-2, 1-3 power consumption design considerations 4-4 power consumption benchmark test A-1 power management iv program memory expansion iv program RAM iii R recovery from Stop state using IRQA 2-10 reset clock signals 1-4 interrupt signals 1-8 JTAG signals 1-18 mode control 1-8 OnCE signals 1-18 PLL signals 1-4 Reset timing 2-7, 2-9 ROM, bootstrap iii S Serial Communication Interface (SCI) iii, 1-1, 1-2, 1-16 Asynchronous mode timing 2-31 Index Synchronous mode timing 2-31 signal groupings 1-1 signals 1-1 functional grouping 1-2 Single Data Strobe 1-2 SRAM read access 2-13 support iv write access 2-13 Stop mode iv Stop state recovery from 2-10 Stop timing 2-7 supply voltage 2-2 Switch mode iii T target applications iv Test Access Port (TAP) iii timing diagram 2-39 Test Clock (TCLK) input timing diagram 2-38 thermal design considerations 4-1 Timer event input restrictions 2-35 Timers 1-1, 1-2, 1-17 W Wait mode iv World Wide Web v X X-data RAM iii Y Y-data RAM iii Index-3 Ordering Information Consult a Motorola Semiconductor sales office or authorized distributor to determine product availability and place an order. Supply Voltage Part DSP56311 1.8 V core 3.3 V I/O Package Type Molded Array Process-Ball Grid Array (MAP-BGA) Pin Count Core Frequency (MHz) Order Number 196 150 DSP56311VF150 HOW TO REACH US: Information in this document is provided solely to enable system and software implementers to use USA/EUROPE/LOCATIONS NOT LISTED: Motorola products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217 1-303-675-2140 or 1-800-441-2447 JAPAN: Motorola reserves the right to make changes without further notice to any products herein. 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