Revised September 2001 FIN1048 3.3V LVDS 4-Bit Flow-Through High Speed Differential Receiver General Description Features This quad receiver is designed for high speed interconnect utilizing Low Voltage Differential Signaling (LVDS) technology. The receiver translates LVDS levels, with a typical differential input threshold of 100mV, to LVTTL signal levels. LVDS provides low EMI at ultra low power dissipation even at high frequencies. This device is ideal for high speed transfer of clock and data. ■ Greater than 400Mbs data rate The FIN1048 can be paired with its companion driver, the FIN1047, or any other LVDS driver. ■ Power-Off protection ■ Flow-through pinout simplifies PCB layout ■ 3.3V power supply operation ■ 0.4ns maximum differential pulse skew ■ 2.5ns maximum propagation delay ■ Low power dissipation ■ Fail safe protection for open-circuit, shorted and terminated conditions ■ Meets or exceeds the TIA/EIA-644 LVDS standard ■ Pin compatible with equivalent RS-422 and LVPECL devices ■ 16-Lead SOIC and TSSOP packages save space Ordering Code: Order Number FIN1048M FIN1048MTC Package Number M16A MTC16 Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Name Description ROUT1, ROUT2, ROUT3, ROUT4 LVTTL Data Outputs RIN1+, RIN2+, RIN3+, RIN4+ Non-Inverting LVDS Inputs RIN1−, RIN2−, RIN3−, RIN4− Inverting LVDS Inputs EN Driver Enable Pin EN Inverting Driver Enable Pin VCC Power Supply GND Ground Function Table Inputs EN RIN+ ROUT− ROUT H L or Open H L H H L or Open L H H L or Open Fail Safe Condition DS500588 L H X H X X Z L or Open X X X Z H = HIGH Logic Level Z = High Impedance © 2001 Fairchild Semiconductor Corporation Outputs EN L = LOW Logic Level X = Don’t Care Fail Safe = Open, Shorted, Terminated www.fairchildsemi.com FIN1048 3.3V LVDS 4-Bit Flow-Through High Speed Differential Receiver September 2001 FIN1048 Absolute Maximum Ratings(Note 1) Supply Voltage (VCC) −0.5V to +4.6V Recommended Operating Conditions DC Input Voltage (VIN) −0.5V to +4.6V Supply Voltage (VCC) DC Input Voltage (VOUT) −0.5V to 6V DC Output Current (IO) Storage Temperature Range (TSTG) 16 mA (|VID|) −65°C to +150°C (Soldering, 10 seconds) 260°C ≥ 10,000V 0 to VCC −40°C to +85°C Operating Temperature (TA) Note 1: The “Absolute Maximum Ratings”: are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature and output/input loading variables. Fairchild does not recommend operation of circuits outside databook specification. ≥ 450V ESD (Machine Model) 0.05V to 2.35V Input Voltage (VIN) Lead Temperature (TL) ESD (Human Body Model) 100mV to VCC Common-Mode Input Voltage (VIC) 150°C Max Junction Temperature (TJ) 3.0V to 3.6V Magnitude of Differential Voltage DC Electrical Characteristics Over supply voltage and operating temperature ranges, unless otherwise specified Symbol Parameter Test Conditions Min Typ Max (Note 2) VTH Differential Input Threshold HIGH See Figure 1 and Table 1 VTL Differential Input Threshold LOW See Figure 1 and Table 1 IIN Input Current VIN = 0V or VCC ±20 µA II(OFF) Power-Off Input Current VCC = 0V, VIN = 0V or 3.6V ±20 µA VOH Output HIGH Voltage IOH = −100 µA Output LOW Voltage −100 V 2.4 IOH = 100 µA 0.2 IOL = 8 mA 0.5 IOZ Disabled Output Leakage Current EN = 0.8 and EN* = 2V, VOUT = 3.6V or 0V VIK Input Clamp Voltage IIK = −18 mA ICCZ Disabled Power Supply Current Receiver Disabled ICC Power Supply Current Receiver Enabled, (RIN+ = 1V and RIN− = 1.4V) CIN Input Capacitance COUT Output Capacitance µA 5 mA 15 mA V or (RIN+ = 1.4V and RIN− = 1V) www.fairchildsemi.com 2 V ±20 −1.5 Note 2: All typical values are at TA = 25°C and with VCC = 3.3V. mV mV VCC −0.2 IOH = −8 mA VOL 100 Units 3.5 pF 6 pF Over supply voltage and operating temperature ranges, unless otherwise specified Symbol Parameter Test Conditions Min Typ Max (Note 3) Units tPLH Propagation Delay LOW-to-HIGH 1.0 2.5 ns tPHL Propagation Delay HIGH-to-LOW 1.0 2.5 ns tTLH Output Rise Time (20% to 80%) |VID| = 400 mV, CL = 10 pF, 0.7 1.2 ns tTHL Output Fall Time (80% to 20%) RL = 1kΩ 0.7 1.2 ns tSK(P) Pulse Skew |tPLH - tPHL| See Figure 1 and Figure 2 0.4 ns tSK(LH) Channel-to-Channel Skew tSK(HL) (Note 4) 0.3 ns tSK(PP) Part-to-Part Skew (Note 5) 1.0 ns fMAX Maximum Operating Frequency RL = 1kΩ, CL = 10 pF, (Note 6) see Figure 1 and Figure 2 200 375 MHz tZH LVTTL Output Enable Time from Z to HIGH 6.0 ns tZL LVTTL Output Enable Time from Z to LOW RL = 1kΩ, CL = 10 pF, 6.0 ns tHZ LVTTL Output Disable Time from HIGH to Z See Figure 3 6.0 ns tLZ LVTTL Output Disable Time from LOW to Z 6.0 ns Note 3: All typical values are at TA = 25°C and with VCC = 3.3V. Note 4: tSK(LH), tSK(HL) is the skew between specified outputs of a single device when the outputs have identical loads and are switching in the same direction. Note 5: tSK(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices switching in the same direction (either LOW-to-HIGH or HIGH-to-LOW) when both devices operate with the same supply voltage, same temperature, and have identical test circuits. Note 6: fMAX Criteria: Input tR = tF < 1 ns, VID = 300 mV, (1.05V to 1.35V pp), 50% duty cycle; Output duty cycle 40% to 60%, VOL < 0.5V, VOH > 2.4V. All channels switching in phase. Note A: All differential input pulses have frequency = 10MHz, tR or tF = 1ns Note B: CL includes all probe and jig capacitances FIGURE 1. Differential Receiver Voltage Definitions and Propagation Delay and Transition Time Test Circuit TABLE 1. Receiver Minimum and Maximum Input Threshold Test Voltages Applied Voltages (V) Resulting Differential Input Resulting Common Mode Input Voltage (mA) Voltage (V) VIC VIA VIB VID 1.25 1.15 100 1.2 1.15 1.25 −100 1.2 2.4 2.3 100 2.35 2.3 2.4 −100 2.35 0.1 0 100 0.05 0 0.1 −100 0.05 1.2 1.5 0.9 600 0.9 1.5 −600 1.2 2.4 1.8 600 2.1 1.8 2.4 −600 2.1 0.6 0 600 0.3 0 0.6 −600 0.3 3 www.fairchildsemi.com FIN1048 AC Electrical Characteristics FIN1048 FIGURE 2. LVDS Input to LVTTL Output AC Waveforms Test Circuit for LVTTL Outputs Voltage Waveforms Enable and Disable Times FIGURE 3. LVTTL Outputs Test Circuit and AC Waveforms www.fairchildsemi.com 4 FIN1048 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A 5 www.fairchildsemi.com FIN1048 3.3V LVDS 4-Bit Flow-Through High Speed Differential Receiver Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 6