HD404328 Series Rev. 6.0 Sept. 1998 Description The HD404328 Series is an HMCS400-Series microcomputer designed to increase program productivity and also to incorporate large-capacity memory. Each microcomputer has an LCD controller/driver, A/D converter, and zero-crossing detection circuit. Each also has a 32.768-kHz oscillator and low-power dissipation modes. The HD404328 Series includes eight chips: the HD404324 and HD404324U with 4-kword ROM; the HD404326 and HD404326U with 6-kword ROM; the HD404328 and HD404328U with 8-kword ROM; the HD4074329 and HD4074329U with 16-kword PROM. The HD404324U, HD404326U, HD404328U and HD4074329U are designed to reduce current dissipation in subactive mode and watch mode. The HD4074329 and HD4074329U, which include PROM, are ZTAT microcomputers that can dramatically shorten system development periods and smooth the process from debugging to mass production. (The PROM program specifications are the same as for the 27256.) Features • 4,096-word × 10-bit ROM (HD404324, HD404324U) 6,144-word × 10-bit ROM (HD404326, HD404326U) • 8,192-word × 10-bit ROM (HD404328, HD404328U) 16,384-word × 10-bit PROM (HD4074329, HD4074329U) • 280-digit × 4-bit RAM (HD404324, HD404324U, HD404326, HD404326U, HD404328, HD404328U) 536-digit × 4-bit RAM (HD4074329, HD4074329U) • 35 I/O pins 2 input pins 33 input/output pins, including 8 high-current pins (15 mA, max.) and 16 pins multiplexed with LCD segment pins • Three timer/counters • 8-bit clock-synchronous serial interface • 8-bit × 4-channel A/D converter • 12-digit LCD controller/driver (24 S EG × 4 C OM) (HD404324U, HD404326U, HD404328U, HD4074329U: External LCD voltage division resistors are required) HD404328 Series • Zero-crossing detection circuit • Eight interrupt sources Two external sources, including one double-edge function Six internal sources • Subroutine stack Up to 16 levels, including interrupts • Four low-power dissipation modes Subactive mode Standby mode Watch mode Stop mode • Built-in oscillator Crystal or ceramic oscillator (external clock also enabled) 32.768 kHz crystal subclock • Instruction cycle time: 2 µs (fOSC = 4 MHz) • Two operating modes MCU mode PROM mode (HD4074329, HD4074329U) ZTAT is a trademark of Hitachi Ltd. 2 HD404328 Series Ordering Information Type Product Name Model Name ROM (Words) RAM (Digits) Package Mask ROM HD404324 4,096 280 HD404326 HD404328 HD404324U* HD404326U* HD404328U* ZTAT HD4074329 HD4074329U* Note: * HD404324S DP-64S HD404324FS FP-64B HD404324H FP-64A HD404326S 6,144 DP-64S HD404326FS FP-64B HD404326H FP-64A HD404328S 8,192 DP-64S HD404328FS FP-64B HD404328H FP-64A HD404324US 4,096 DP-64S HD404324UFS FP-64B HD404324UH FP-64A HD404326US 6,144 DP-64S HD404326UFS FP-64B HD404326UH FP-64A HD404328US 8,192 DP-64S HD404328UFS FP-64B HD404328UH FP-64A HD4074329S 16,384 536 DP-64S HD4074329FS FP-64B HD4074329US DP-64S HD4074329UFS FP-64B Type with external LCD voltage-dividing resistor. 3 HD404328 Series Pin Arrangement AVCC AN 0 AN 1 AN 2 AN 3 AVSS TEST OSC 1 OSC 2 DP–64S VCC COM4 COM3 COM2 COM1 64 63 62 61 60 59 58 57 56 55 54 53 52 1 51 SEG24 AN 2 AN 3 2 50 SEG23 AVSS SEG22 3 49 4 48 SEG21 TEST SEG20 OSC 1 5 47 OSC 2 6 46 SEG19 7 45 SEG18 RESET SEG17 8 44 X1 9 43 R5 3 /SEG16 X2 FP–64B R5 2 /SEG15 GND 10 42 D0 11 41 R5 1 /SEG14 D1 12 40 R5 0 /SEG13 D2 13 39 R4 3 /SEG12 D3 14 38 R4 2 /SEG11 D4 15 37 R4 1 /SEG10 D5 16 36 R4 0 /SEG9 D6 17 35 R3 3 /SEG8 D7 18 34 R3 2 /SEG7 19 33 R3 1 /SEG6 * 20 21 22 23 24 25 26 27 28 29 30 31 32 R3 0 /SEG5 R2 3 /SEG4 R2 2 /SEG3 R2 1 /SEG2 R2 0 /SEG1 R13 /BUZZ R12 /SO Note: * D8 /ZCD/EVENT R11 /SI AN 1 AN 0 AVCC V3 V2 V1 VCC COM4 COM3 COM2 COM1 SEG24 SEG23 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 AN 3 AN 2 AN 1 AN 0 AVCC V3 V2 V1 VCC COM4 COM3 COM2 COM1 SEG24 SEG23 SEG22 RESET X1 X2 GND D0 D1 D2 D3 D4 D5 D6 D7 * D9 /INT0 D10 /INT1 R00 R01 R02 R03 R10 /SCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 D9 /INT0 D 10 /INT1 R00 R01 R02 R03 R10 /SCK R11 /SI R12 /SO R13 /BUZZ R2 0 /SEG1 R2 1 /SEG2 R2 2 /SEG3 V1 V2 V3 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 FP–64A 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 * D9 /INT 0 D10 /INT 1 R0 0 R0 1 R0 2 R0 3 R10 /SCK R11 /SI R12 /SO /R13 /BUZZ R20 /SEG1 R21 /SEG2 R22 /SEG3 R23 /SEG4 R30 /SEG5 AV SS TEST OSC 1 OSC 2 RESET X1 X2 GND D0 D1 D2 D3 D4 D5 D6 D7 (top view) 4 SEG21 SEG20 SEG19 SEG18 SEG17 R53 /SEG16 R52 /SEG15 R51 /SEG14 R50 /SEG13 R43 /SEG12 R42 /SEG11 R41 /SEG10 R40 /SEG9 R33 /SEG8 R32 /SEG7 R31 /SEG6 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 R5 3 /SEG16 R5 2 /SEG15 R5 1 /SEG14 R5 0 /SEG13 R4 3 /SEG12 R4 2 /SEG11 R4 1 /SEG10 R4 0 /SEG9 R3 3 /SEG8 R3 2 /SEG7 R3 1 /SEG6 R3 0 /SEG5 R2 3 /SEG4 HD404328 Series Pin Description Pin Number Item Symbol DP-64S DC-64S FP-64B FP-64A Power supply VCC 64 58 56 Applies power voltage GND 16 10 8 Connected to ground Test TEST 10 4 2 I Used for factory testing only; connect this pin to VCC Reset RESET 13 7 5 I Resets the MCU Oscillator OSC 1 11 5 3 I Input/output pins for the internal oscillator circuit; connect them to a crystal, ceramic, or external oscillator circuit OSC 2 12 6 4 O X1 14 8 6 I X2 15 9 7 O D0–D 8 17–25 11–19 9–17 I/O Input/output ports addressed by individual bits; pins D0–D 7 are highcurrent pins that can each supply up to 15 mA D9, D10 26, 27 20, 21 18, 19 I Input ports addressable by individual bits R0 0–R5 3 28–51 22–45 20–43 I/O Input/output ports addressable in 4bit units Interrupt INT0, INT1 26, 27 20, 21 18, 19 I Input pins for external interrupts Serial interface SCK 32 26 24 I/O Serial interface clock input/output pin SI 33 27 25 I Serial interface receive data input pin SO 34 28 26 O Serial interface transmit data output pin Buzzer BUZZ 35 29 27 O Buzzer signal output pin LCD V1, V2, V3 1–3 59–61 57–59 COM1–COM4 60–63 54–57 52–55 O Common signal pins for LCD SEG1–SEG24 36–59 30–53 28–51 O Segment signal pins for LCD Port I/O Function Used for a 32.768-kHz crystal for clock purposes; if not used, fix X1 to VCC and leave X2 open Power pins for LCD driver; can be left open in operation because they are connected by internal voltage division resistors (except for HD404324U, HD404326U, HD404328U and HD4074329U) Voltage conditions are: VCC ≥ V 1 ≥ V 2 ≥ V 3 ≥ GND 5 HD404328 Series Pin Number Item Symbol DP-64S DC-64S FP-64B FP-64A A/D converter AVCC 4 62 60 Power pin for A/D converter; connect it to the same potential as VCC, as physically close as possible to the power source AVSS 9 3 1 Ground for AV CC; connect it to the same potential as GND, as physically close as possible to the power source AN 0–AN 3 5–8 63, 64, 1, 2 61–64 I Analog input pins for 4-channel A/D converter Zerocrossing detection ZCD 25 19 17 I Zero-crossing detection input pin Counter EVENT 25 19 17 I Event count input pin 6 I/O Function HD404328 Series GND VCC X2 X1 OSC2 OSC1 TEST RESET Block Diagram D0 INT1 D1 System control Interrupt control D2 D3 RAM (280 × 4 bits) (536 × 4 bits) D4 D port INT0 Timer A D5 D6 D7 W (2 bits) D8 D9 R0 port SPX (4 bits) BUZZ Buzzer ZCD Zerocrossing detection CPU ALU ST (1 bit) CA (1 bit) R3 port A/D converter SPY (4 bits) R4 port AVSS AN 0 AN 1 AN 2 AN 3 AVCC Internal data bus SCK Internal data bus Serial interface R2 port R1 port Y (4 bits) SI R5 port Timer C SO D10 Internal data bus EVENT X (4 bits) Timer B R00 R01 R02 R03 R10 R11 R12 R13 R20 R21 R22 R23 R30 R31 R32 R33 R40 R41 R42 R43 R50 R51 R52 R53 A (4 bits) Data bus B (4 bits) V1 V2 V3 COM1 COM2 COM3 COM4 SEG1 SEG2 SEG3 . . . . . SEG23 SEG24 SP (10 bits) LCD driver/ controller Instruction decoder Large-current pins PC (14 bits) Directional signal line ROM (4,096 × 10 bits) (6,144 × 10 bits) (8,192 × 10 bits) (16,384 × 10 bits) 7 HD404328 Series Memory Map ROM Memory Map The ROM memory map is shown in figure 1 and described below. 0 $0000 Vector address $000F $0010 15 16 4095 4096 Pattern (4,096 words) HD404324, HD404324U program (4,096 words) 2 4 $003F $0040 5 6 7 8 $0FFF $1000 9 10 11 HD404326, HD404326U program (6,144 words) 6143 6144 1 3 Zero-page subroutine (64 words) 63 64 0 12 13 $17FF $1800 JMPL instruction (jump to reset routine) $0000 JMPL instruction (jump to INT0 routine) $0002 JMPL instruction (jump to INT1 routine) $0004 JMPL instruction (jump to timer A routine) $0006 JMPL instruction (jump to timer B routine) $0008 JMPL instruction (jump to timer C routine) $000A JMPL instruction (jump to ZCD routine) $000C 14 JMPL instruction 15 (jump to A/D, serial routines) $0001 $0003 $0005 $0007 $0009 $000B $000D $000E $000F HD404328, HD404328U program (8,192 words) 8191 8192 $1FFF $2000 HD4074329, HD4074329U program (16,384 words) 16383 $3FFF Figure 1 ROM Memory Map Vector Address Area ($0000–$000F): Reserved for JMPL instructions that branch to the start addresses of the reset and interrupt routines. After MCU reset or an interrupt, program execution continues from the vector address. Zero-Page Subroutine Area ($0000–$003F): Reserved for subroutines. The program branches to a subroutine in this area in response to the CAL instruction. Pattern Area ($0000–$0FFF): Contains ROM data that can be referenced with the P instruction. Program Area (HD404324, HD404324U: $0000-$0FFF; HD404326, HD404326U: $0000-$17FF; HD404328, HD404328U: $0000–$1FFF; HD4074329, HD4074329U: $0000–$3FFF): Used for program coding. 8 HD404328 Series RAM Memory Map The MPU contains a 280-digit × 4-bit (HD404324, HD404324U, HD404326, HD404326U, HD404328, HD404328U) or 536-digit × 4-bit (HD4074329, HD4074329U) RAM area consisting of a data area and a stack area. In addition, interrupt control bits and special registers are mapped onto the same RAM memory space outside this area. The RAM memory map is shown in figure 2 and described below. 0 63 64 79 80 103 104 RAM-mapped registers (64 digits) Memory registers (MR) (16 digits) LCD display area (24 digits) $000 $03F $040 $04F $050 $067 $068 Not used 111 112 287 288 Data (176 digits) $06F $070 $11F $120 Data (256 digits) 543 544 $21F $220 Not used $3BF $3C0 959 960 Stack (64 digits) 1023 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Interrupt control bits area (PMRA) Port mode register A (SMR) Serial mode register Serial data register, lower (SRL) Serial data register, upper (SRU) (TMA) Timer mode register A (TMB) Timer mode register B (TCBL/TLRL) * Timer B (TCBU/TLRU) (MIS) Miscellaneous register (TMC) Timer mode register C (TCCL/TCRL) * Timer C (TCCU/TCRU) Interrupt mode register (IMR) Port mode register B (PMRB) Port mode register C (PMRC) LCD control register (LCR) LCD mode register (LMR) LCD output register (LOR) A/D mode register (AMR) A/D data register, lower (ADRL) A/D data register, upper (ADRU) Not used $3FF Shaded area can only be used by the HD4074329, and HD4074329U 32 35 $020 $023 Register flag area Not used 48 49 50 51 52 53 R: Read only W: Write only R/W: Read/write W W R/W R/W W W R/W R/W W W R/W R/W W W W W W W W R R $000 $001 $002 $003 $004 $005 $006 $007 $008 $009 $00A $00B $00C $00D $00E $00F $010 $011 $012 $013 $014 $015 $016 $017 $018 (DCR0) (DCR1) (DCR2) (DCR3) (DCR4) (DCR5) W W W W W W $030 $031 $032 $033 $034 $035 59 Port D0–D3 DCR (DCRB) 60 Port D4 –D7 DCR (DCRC) 61 Port D8 DCR (DCRD) 62 Not used 63 W W W $03B $03C $03D $03E $03F Port R0 DCR Port R1 DCR Port R2 DCR Port R3 DCR Port R4 DCR Port R5 DCR Not used Note: * Two registers mapped on the same area Timer/event counter B, lower (TCBL) Timer/event counter B, upper (TCBU) Timer counter C, lower (TCCL) Timer counter C, upper (TCCU) R R R R Timer load register B, lower (TLRL) Timer load register B, upper (TLRU) W $00A Timer load register C, lower (TCRL) Timer load register C, upper (TCRU) W $00E W $00B W $00F Figure 2 RAM Memory Map 9 HD404328 Series Interrupt Control Bits Area and Register Flag Area ($000–$003, $020–$023): Used for interrupt control bits and the bit register (figure 3). This area can be accessed only by RAM bit manipulation instructions. In addition, note that the interrupt request flag cannot be set by software, the RSP bit is used only to reset the stack ppointer, and the WDON flag can be set only by the SEM and SEMD instructions. Special Function Registers Area ($004–$01F, $024–$03F): Used as mode registers for external interrupts, serial interface, and timer/counters, and as data registers and as data control registers for I/O ports. As shown in figure 2, these registers can be classified into three types: write-only, read-only, and read/write. The SEM, SEMD, REM, and REMD instructions can be used for the LCD control register (LCR), but RAM bit manipulation instructions cannot be used for other registers. LCD Data Area ($050–$067): Used for storing LCD data which is automatically output to LCD segments as display data. Data 1 lights the corresponding LCD segment; data 0 extinguishes it. Data Area (HD404324, HD404324U, HD404326, HD404326U, HD404328, HD404328U: $040–$04F and $070–$11F, HD4074329, HD4074329U: $040–$04F and $070–$21F): The memory registers (MR), which consist of 16 digits ($040–$04F), can be accessed by the LAMR and XMRA instructions. Its structure is shown in figure 4. Stack Area ($3C0–$3FF): Used for saving the contents of the program counter (PC), status flag (ST), and carry flag (CA) at subroutine calls (CAL, CALL) and interrupts. This area can be used as a 16-level nesting subroutine stack in which one level requires four digits. The data to be saved and the save conditions are shown in figure 4. The program counter is restored by either the RTN or RTNI instruction, but the status and carry flags can only be restored by the RTNI instruction. Any unused space in this area is used for data storage. 10 HD404328 Series 0 1 2 3 Bit 3 IM0 (IM of INT0) IMTA (IM of timer A) IMTC (IM of timer C) IMAD (IM of A/D) DTON 32 (Direct transfer on flag) Bit 2 IF0 (IF of INT0) IFTA (IF of timer A) IFTC (IF of timer C) IFAD (IF of A/D) Bit 1 RSP (Reset SP bit) IM1 (IM of INT1) IMTB (IM of timer B) IMZC (IM of ZCD) Bit 0 IE (Interrupt enable flag) IF1 (IF of INT1) IFTB (IF of timer B) IFZC (IF of ZCD) ADSF (A/D start flag) WDON (Watchdog on flag) LSON (Low speed on flag) $000 $001 $002 $003 $020 $021 33 Not used 34 $022 IMS IFS 35 (IM of serial interface) (IF of serial interface) $023 IF: IM: IE: SP: Interrupt request flag Interrupt mask Interrupt enable flag Stack pointer Note: Bits in the interrupt control bits area and register flag area are set by the SEM or SEMD instruction, reset by the REM or REMD instruction, and tested by the TM or TMD instruction. Other instructions have no effect. However, note the following usage limitations of RAM bit manipulation instructions. SEM/SEMD REM/REMD TM/TMD IF Not executed Allowed Allowed RSP Not executed Allowed Inhibited WDON Allowed Not executed Inhibited DTON Not executed in active mode Allowed Allowed Used in subactive mode Note: WDON is reset by MCU reset. DTON is always reset in active mode. If the TM or TMD instruction is executed for the inhibited bits or non-existing bits, the value in ST becomes invalid. Figure 3 Configuration of Interrupt Control Bits and Register Flag Areas 11 HD404328 Series Memory registers 64 MR (0) $040 65 MR (1) $041 66 MR (2) $042 67 MR (3) $043 68 MR (4) $044 69 MR (5) $045 70 MR (6) $046 71 MR (7) $047 72 MR (8) $048 73 MR (9) $049 74 MR (10) $04A 75 MR (11) $04B 76 MR (12) $04C 77 MR (13) $04D 78 MR (14) $04E 79 MR (15) $04F Stack area 960 Level 16 $3C0 Level 15 Level 14 Level 13 Level 12 Level 11 Level 10 Level 9 Level 8 Level 7 Level 6 Level 5 Level 4 Level 3 Level 2 1023 Level 1 $3FF Bit 3 Bit 2 Bit 1 Bit 0 1020 ST PC 13 PC 12 PC 11 $3FC 1021 PC10 PC 9 PC 8 PC 7 $3FD 1022 CA PC 6 PC 5 PC 4 $3FE 1023 PC3 PC 2 PC 1 PC 0 $3FF PC13–PC 0 : Program counter ST: Status flag CA: Carry flag Figure 4 Configuration of Memory Registers and Stack Area, and Stack Position 12 HD404328 Series Functional Description Registers and Flags The MCU has nine registers and two flags for CPU operations. They are shown in figure 5 and described below. 3 Accumulator 0 (A) Initial value: Undefined, R/W 3 B register Initial value: Undefined, R/W 0 (B) 1 W register Initial value: Undefined, R/W 0 (W) 3 X register Initial value: Undefined, R/W 0 (X) 3 Y register Initial value: Undefined, R/W SPX register Initial value: Undefined, R/W 0 (Y) 3 0 (SPX) 3 SPY register Initial value: Undefined, R/W 0 (SPY) 0 Carry Initial value: Undefined, R/W Status Initial value: 1, no R/W (CA) 0 Program counter Initial value: 0, no R/W (ST) 13 0 (PC) 9 Stack pointer Initial value: $3FF, no R/W 1 5 1 1 1 0 (SP) Figure 5 Registers and Flags Accumulator (A), B Register (B): Four-bit registers used to hold results from the arithmetic logic unit (ALU) and transfer data between memory, I/O, and other registers. 13 HD404328 Series W Register (W), X Register (X), Y Register (Y): Two-bit (W) and four-bit (X and Y) registers used for indirect RAM addressing. The Y register is also used for D-port addressing. SPX Register (SPX), SPY Register (SPY): Four-bit registers used to supplement the X and Y registers. Carry Flag (CA): One-bit flag that stores any ALU overflow generated by an arithmetic operation. CA is affected by the SEC, REC, ROTL, and ROTR instructions. A carry is pushed onto the stack during an interrupt and popped from the stack by the RTNI instruction—but not by the RTN instruction. Status Flag (ST): One-bit flag that latches any overflow generated by an arithmetic or compare instruction, not-zero decision from the ALU, or result of a bit test. ST is used as a branch condition of the BR, BRL, CAL, and CALL instructions. The contents of ST remain unchanged until the next arithmetic, compare, or bit test instruction is executed, but become 1 after the BR, BRL, CAL, or CALL instruction is read, regardless of whether the instruction is executed or skipped. The contents of ST are pushed onto the stack during an interrupt and popped from the stack by the RTNI instruction—but not by the RTN instruction. Program Counter (PC): A 14-bit counter that points to the ROM address of the instruction being executed. Stack Pointer (SP): Ten-bit pointer that contains the address of the stack area to be used next. The SP is initialized to $3FF by MCU reset, is decremented by 4 when data is pushed onto the stack, and is incremented by 4 when data is popped from the stack. Since the top four bits of the SP are fixed at 1111, a stack of up to 16 levels can be used. The SP can be initialized to $3FF in another way: by resetting the RSP bit with the REM or REMD instruction. 14 HD404328 Series Reset The MCU is reset by inputting a high-level voltage to the RESET pin. At power-on or when stop mode is cancelled, RESET must be high for at least one tRC to enable the oscillator to stabilize. During operation, RESET must be high for at least two instruction cycles. Initial values after MCU reset are shown in table 1. Table 1 Initial Values After MCU Reset Item Abbr. Initial Value Contents Program counter (PC) $0000 Indicates program execution point from start address of ROM area Status flag (ST) 1 Enables conditional branching Stack pointer (SP) $3FF Stack level 0 (IE) 0 Inhibits all interrupts Interrupt request flag (IF) 0 Indicates there is no interrupt request Interrupt mask (IM) 1 Prevents (masks) interrupt requests Port data register (PDR) All bits 1 Enables output at level 1 Data control register (DCR) All bits 0 Turns output buffer off (to high impedance) Port mode register A (PMRA) 0000 Refer to description of port mode register A Port mode register B (PMRB) - - 00 Refer to description of port mode register B Port mode register C (PMRC) 0000 Refer to description of port mode register C Interrupt mode register (IMR) 0000 Refer to description of interrupt mode register Timer/ Timer mode counters, serial register A interface (TMA) 0000 Refer to description of timer mode register A Timer mode register B (TMB) 0000 Refer to description of timer mode register B Timer mode register C (TMC) 0000 Refer to description of timer mode register C Serial mode register (SMR) 0000 Refer to description of serial mode register Prescaler S $000 — Prescaler W $00 — Interrupt flags/mask I/O Interrupt enable flag Timer counter A (TCA) $00 — Timer counter B (TCB) $00 — 15 HD404328 Series Item Abbr. Initial Value Contents Timer counter C Timer/ counters, serial interface (TCC) $00 — Timer load register B (TLR) $00 — Timer load register C (TCR) $00 — Octal counter 000 — A/D A/D mode register (AMR) 00-0 Refer to description of A/D mode register LCD LCD control register (LCR) 000 Refer to description of LCD control register LCD mode register (LMR) 0000 Refer to description of LCD duty cycle/clock control register LCD output register (LOR) 0000 Refer to description of LCD output register Low speed on flag (LSON) 0 Refer to description of low-power dissipation modes Watchdog timer on flag (WDON) 0 Refer to description of timer C A/D start flag (ADSF) 0 Refer to description of A/D converter Direct transfer on flag (DTON) 0 Refer to description of low-power dissipation modes 0000 Refer to description of miscellaneous register Bit register Miscellaneous register (MIS) Note: The statuses of other registers and flags after MCU reset are as follows: Item Abbr. Carry flag (CA) Accumulator (A) B register (B) W register (W) X/SPX register (X/SPX) Y/SPY register (Y/SPY) Serial data register (SR) A/D data register (ADRL, ADRU) RAM 16 Status After Cancellation of Stop Mode by MCU Reset Status After Cancellation of all Other Types of Modes by MCU Reset Pre-MCU-reset values are not guaranteed: values must be initialized by program Pre-MCU-reset values are not guaranteed: values must be initialized by program Pre-MCU-reset (pre-STOPinstruction) values are retained HD404328 Series Interrupts The MCU has eight interrupt sources: two external signals (INT0 and INT1), three timer/counters (timer A, timer B, and timer C), serial interface, zero-crossing detection, and A/D converter. An interrupt request flag (IF), interrupt mask (IM), and vector address are provided for each interrupt source, and an interrupt enable flag (IE) controls the entire interrupt process. Vector addresses are shared by serial interface and A/D converter interrupt causes, so software must first check which type of request has occurred. Interrupt Control Bits and Interrupt Servicing: Locations $000–$003 and $020–$023 in RAM are reserved for the interrupt control bits which can be accessed by RAM bit manipulation instructions. The interrupt request flag (IF) cannot be set by software. MCU reset initializes the interrupt enable flag (IE) and the IF to 0 and the interrupt mask (IM) to 1. A block diagram of the interrupt control circuit is shown in figure 6, interrupt priorities and vector addresses are listed in table 2, and interrupt processing conditions for the eight interrupt sources are listed in table 3. An interrupt request occurs when the IF is set to 1 and the IM is set to 0. If the IE is 1 at that point, the interrupt is processed. Priority control logic generates the vector address assigned to that interrupt source. The interrupt processing sequence is shown in figure 7 and an interrupt processing flowchart is shown in figure 8. After an interrupt is acknowledged, the previous instruction is completed in the first cycle. The IE is reset in the second cycle, the carry flag, status flag, and program counter values are pushed onto the stack during the second and third cycles, and the program jumps to the vector address to execute the instruction in the third cycle. Program the JMPL instruction at each vector address, to branch the program to the start address of the interrupt program, and reset the IF by a software instruction within the interrupt program. 17 HD404328 Series $000, 0 IE INT0 interrupt Sequence control • Push PC/CA/ST • Reset IE • Jump to vector address $000, 2 IF0 $000, 3 IM0 Vector address Priority control logic $001, 0 INT1 interrupt IF1 $001, 1 IM1 $001, 2 Timer A interrupt IFTA $001, 3 IMTA $002, 0 Timer B interrupt IFTB $002, 1 IMTB $002, 2 Timer C interrupt IFTC $002, 3 IMTC $003, 0 ZCD interrupt IFZC $003, 1 IMZC Note: $m, n is RAM address $m, bit number n. $003, 2 A/D interrupt IFAD $003, 3 IMAD $023, 2 IFS Serial interrupt $023, 3 IMS Figure 6 Block Diagram of Interrupt Control Circuit 18 HD404328 Series Table 2 Vector Addresses and Interrupt Priorities Reset/Interrupt Priority Vector Address RESET — $0000 INT0 1 $0002 INT1 2 $0004 Timer A 3 $0006 Timer B 4 $0008 Timer C 5 $000A ZCD 6 $000C A/D, Serial 7 $000E Table 3 Interrupt Processing and Activation Conditions Interrupt Cause Interrupt Control Bit INT0 INT1 Timer A Timer B Timer C ZCD A/D, Serial IE 1 1 1 1 1 1 1 IF0 IM0 1 0 0 0 0 0 0 . . IF1 IM1 * 1 0 0 0 0 0 . IFTA IMTA * * 1 0 0 0 0 . IFTB IMTB * * * 1 0 0 0 . IFTC IMTC * * * * 1 0 0 . IFZC IMZC * * * * * 1 0 . * * * * * * 1 IFAD IMAD + IFS .IMS Note: Bits marked * can be either 0 or 1. Their values have no effect on operation. 19 HD404328 Series Instruction cycles 1 2 3 Stacking; IE reset Stacking; vector address generation 4 5 6 Instruction execution Interrupt acceptance Execution of JMPL instruction at vector address The stack is accessed and the IE reset after the instruction is executed, even if it is a two-cycle instruction. Figure 7 Interrupt Processing Sequence 20 Execution of instruction at start address of interrupt routine HD404328 Series Power on RESET=1? Yes No Interrupt request? No Yes No Reset MCU IE = 1? Yes Execute instruction Accept interrupt PC ← (PC) + 1 IE ← 0 Stack ← (PC) Stack ← (CA) Stack ← (ST) PC ← $0002 Yes INT0 interrupt? No PC ← $0004 Yes INT1 interrupt? No PC ← $0006 Yes Timer A interrupt? No PC ← $0008 Yes Timer B interrupt? No PC ← $000A Yes Timer C interrupt? No PC ← $000C Yes ZCD interrupt? No PC ← $000E (A/D, serial interrupt) Figure 8 Interrupt Processing Flowchart 21 HD404328 Series Interrupt Enable Flag (IE: $000, Bit 0): Controls the entire interrupt process. It is reset by the interrupt processing and set by the RTNI instruction, as shown in table 4. Table 4 Interrupt Enable Flag IE Interrupt Enabled/Disabled 0 Disabled 1 Enabled External Interrupts (INT0, INT1): Specified by port mode register A (PMRA: $004). External Interrupt Request Flags (IF0: $000, Bit 2; IF1: $001, Bit 0): Set at the rising or falling edges of the INT 0 and INT1 inputs, as shown in table 5. Table 5 External Interrupt Request Flags IF0, IF1 Interrupt Request 0 No 1 Yes IF0 is set at the falling edge of signals input to INT0, and IF1 is set at the rising and falling edges of signals input to INT1. The INT1 interrupt edge is selected by the interrupt mode register (IMR: $010), as shown in figure 9. Interrupt mode register (IMR): $010 3 2 1 0 Initial value: 0000, R/W: W INT1 detection edge selection ZCD detection edge selection IMR Bit 3 0 1 IMR Bit 2 ZCD Detection Edge 0 No detection 1 Falling-edge detection 0 Rising-edge detection 1 Double-edge detection Bit 1 0 1 Bit 0 0 No detection 1 Falling-edge detection 0 Rising-edge detection 1 Double-edge detection Figure 9 Interrupt Mode Register 22 INT1 Detection Edge HD404328 Series External Interrupt Masks (IM0: $000, Bit 3; IM1: $001, Bit 1): Prevent (mask) interrupt requests caused by the corresponding external interrupt request flags, as shown in table 6. Table 6 External Interrupt Masks IM0, IM1 Interrupt Request 0 Enabled 1 Disabled (Masked) Timer A Interrupt Request Flag (IFTA: $001, Bit 2): Set by overflow output from timer A, as shown in table 7. Table 7 Timer A Interrupt Request Flag IFTA Interrupt Request 0 No 1 Yes Timer A Interrupt Mask (IMTA: $001, Bit 3): Prevents (masks) an interrupt request caused by the timer A interrupt request flag, as shown in table 8. Table 8 Timer A Interrupt Mask IMTA Interrupt Request 0 Enabled 1 Disabled (Masked) Timer B Interrupt Request Flag (IFTB: $002, Bit 0): Set by overflow output from timer B, as shown in table 9. Table 9 Timer B Interrupt Request Flag IFTB Interrupt Request 0 No 1 Yes 23 HD404328 Series Timer B Interrupt Mask (IMTB: $002, Bit 1): Prevents (masks) an interrupt request caused by the timer B interrupt request flag, as shown in table 10. Table 10 Timer B Interrupt Mask IMTB Interrupt Request 0 Enabled 1 Disabled (Masked) Timer C Interrupt Request Flag (IFTC: $002, Bit 2): Set by overflow output from timer C, as shown in table 11. Table 11 Timer C Interrupt Request Flag IFTC Interrupt Request 0 No 1 Yes Timer C Interrupt Mask (IMTC: $002, Bit 3): Prevents (masks) an interrupt request caused by the timer C interrupt request flag, as shown in table 12. Table 12 Timer C Interrupt Mask IMTC Interrupt Request 0 Enabled 1 Disabled (Masked) Zero-Crossing Interrupt Request Flag (IFZC: $003, Bit 0): Set by a zero crossing of an AC input signal, as shown in table 13. The interrupt edge is selected by the interrupt mode register (IMR: $010), as shown in figure 9. Table 13 Zero-Crossing Interrupt Request Flag IFZC Interrupt Request 0 No 1 Yes Zero-Crossing Interrupt Mask (IMZC: $003, Bit 1): Prevents (masks) an interrupt request caused by the zero-crossing interrupt request flag, as shown in table 14. 24 HD404328 Series Table 14 Zero-Crossing Interrupt Mask IMZC Interrupt Request 0 Enabled 1 Disabled (Masked) A/D Interrupt Request Flag (IFAD: $003, Bit 2): Set at the completion of A/D conversion, as shown in table 15. Table 15 A/D Interrupt Request Flag IFAD Interrupt Request 0 No 1 Yes A/D Interrupt Mask (IMAD: $003, Bit 3): Prevents (masks) an interrupt request caused by the A/D interrupt request flag, as shown in table 16. Table 16 A/D Interrupt Mask IMAD Interrupt Request 0 Enabled 1 Disabled (Masked) Serial Interrupt Request Flag (IFS: $023, Bit 2): Set when the octal counter counts the eighth transmit clock signal or when data transfer is discontinued by resetting the octal counter (table 17). Table 17 Serial Interrupt Request Flag IFS Interrupt Request 0 No 1 Yes Serial Interrupt Mask (IMS: $023, Bit 3): Prevents (masks) an interrupt request caused by the serial interrupt request flag, as shown in table 18. Table 18 Serial Interrupt Mask IMS Interrupt Request 0 Enabled 1 Disabled (Masked) 25 HD404328 Series Operating Modes The MCU has five operating modes that are specified by how the clock is used. The functions available in each mode are listed in table 19, and operations are shown in table 20. Transitions between operating modes are shown in figure 10. Table 19 Functions Available in Each Operating Mode Mode Name Active Standby Stop Watch Subactive *4 Activation method RESET cancellation, interrupt request SBY instruction TMA3 = 0 STOP instruction TMA3 = 1 STOP instruction INT0 or timer A interrupt request from watch mode Status System oscillator OP OP Stopped Stopped Stopped Subsystem oscillator OP OP *1 OP OP OP Instruction execution (øCPU) OP Stopped Stopped Stopped OP Interrupt OP function interrupt (øPER) OP Stopped Stopped *5OP Clock function OP interrupt (øCLK) OP Stopped *2 OP *2OP RAM Retained Retained OP Retained OP 6 Retained Retained/ operating Retained OP Registers/flags OP Retained Reset* I/O Retained Reset*3 Cancellation method OP RESET input, RESET input RESET input STOP/SBY interrupt instruction request RESET input, RESET input, INT0 or timer STOP/SBY instruction A interrupt request Notes: OP: indicates in operation 1. To reduce current dissipation, stop all oscillation in external circuits. 2. Refer to the Interrupt Frame section for details. 3. Output pins are at high impedance. 4. Subactive mode is an optional function; specify it on the function option list. 5. The A/D converter does not operate. 6. Port mode register B retains the contents it had in active mode. 26 HD404328 Series System Clock (øCPU) Non-Time-Base Peripheral Function Clock (øPER) Operating Operating Stopped Active mode Standby mode Subactive mode Stopped — Watch mode (TMA3 = 1) Stop mode (TMA3 = 0) Table 20 Operations in Low-Power Dissipation Modes Function Stop Mode Watch Mode Standby Mode Subactive Mode*3 CPU Reset Retained Retained OP RAM Retained Retained Retained OP Timer A Reset OP OP OP Timer B Reset Stopped OP OP Timer C Reset Stopped OP OP Stopped* OP OP OP OP OP Retained Retained OP OP Stopped OP OP Serial interface Reset LCD Reset I/O Reset* A/D Reset Zero-crossing 3 1 Stopped 4 Stopped* 4 Stopped* detection Notes: OP: indicates in operation 1. Output pins are at high impedance. 2. Subactive mode is an optional function specified on the function option list. 3. Transmission/reception is activated if a clock is input in external clock mode. (However interrupts stop.) 4. The bias circuits still operate when the D 8/ZCD/EVENT pin is set to ZCD. 27 HD404328 Series Reset Standby mode Active mode Stop mode (TMA3 = 0) øOSC: fX: øCPU: øCLK: øPER: Operating Operating Stopped fcyc f cyc SBY (standby) Interrupt øOSC: fX: øCPU: øCLK: øPER: Operating Operating f cyc f cyc f cyc øOSC: fX: øCPU: øCLK: øPER: STOP (TMA3 = 0) Watch mode (TMA3 = 1, LSON = 0) (TMA3 = 1) øOSC: fX: øCPU: øCLK: øPER: Operating Operating Stopped fSUB f cyc SBY (standby) Interrupt øOSC: fX: øCPU: øCLK: øPER: Operating Operating f cyc fSUB f cyc STOP INT0, time-base*1 *2 øOSC: fX: øCPU: øCLK: øPER: øOSC: fX: øCPU: øCLK: øPER: Stopped Operating Stopped f SUB Stopped *3 Subactive mode øOSC: Main oscillation frequency fX: Suboscillation frequency, for time-base fcyc: fOSC/8 fSUB: fX/8 øCPU: System clock øCLK: Clock for time-base øPER: Clock for other peripheral functions LSON: Low speed on flag DTON: Direct transfer on flag Stopped Operating Stopped Stopped Stopped Stopped Operating fSUB fSUB fSUB STOP INT0, time-base *1 STOP/SBY (LSON = 1) *4 Notes: 1. 2. 3. 4. (TMA3 = 1, LSON = 1) øOSC: fX: øCPU: øCLK: øPER: Stopped Operating Stopped fSUB Stopped Interrupt source STOP/SBY (DTON = 1, LSON = 0) STOP/SBY (DTON = 0, LSON = 0) DTON can be 0 or 1. Figure 10 MCU Status Transitions Active Mode: The MCU operates according to the clock generated by the system oscillators OSC1 and OSC2. Standby Mode: The MCU enters standby mode when the SBY instruction is executed from active mode. In this mode, the oscillators, interrupts, timer/counters, and serial interface continue to operate, but all instruction execution-related clocks stop. The stopping of these clocks stops the CPU, retaining all RAM and register contents and maintaining the current I/O pin status. The standby mode is terminated by a RESET input or an interrupt request. If it is terminated by RESET input, the MCU is reset as well. After an interrupt request, the MCU enters active mode and resumes, executing the next instruction after the SBY instruction. If the interrupt enable flag is 1, that interrupt is then processed; if it is 0, the interrupt request is left pending and normal instruction execution continues. A flowchart of operation in standby mode is shown in figure 11. 28 HD404328 Series Standby Watch Oscillator: Stopped Sub-oscillator: Active Peripheral clocks: Stopped All other clocks: Stopped Oscillator: Active Peripheral clocks: Active All other clocks: Stopped RESET = 1? Yes No IF0 = 1? No Yes IM0 = 0? Yes IF1 = 1? No IFTA = 1? Yes No IM1 = 0? Yes No Yes IMTA = 0? No IFTB = 1? No Yes IFTC = 1? No Yes No Yes IMTB = 0? IFZC = 1? No Yes IMTC = 0? No Yes IFAD = 1? No Yes IMZC = 0? Yes No Yes IFS = 1? No IMAD = 0? Yes No Yes (SBY only) (SBY only) (SBY only) (SBY only) Execute next instruction Restart processor clocks No No (SBY only) IMS = 0? No (SBY Yes only) Restart processor clocks IF = 1, IM = 0, IE = 1? Yes Reset MCU Execute next instruction Accept interrupt Figure 11 MCU Operation Flowchart 29 HD404328 Series Stop Mode: The MCU enters stop mode if the STOP instruction is executed in active mode when TMA3 = 0. In this mode, the system oscillator stops, which stops all MCU functions as well. The stop mode is terminated by a RESET input as shown in figure 12. RESET must be high for at least one tRC to stabilize oscillation (refer to the AC Characteristics section). When the MCU restarts after stop mode is cancelled, all RAM contents are retained, but the accuracy of the contents of the accumulator, B register, W register, X/SPX register, Y/SPY register, carry flag, and serial data register cannot be guaranteed. Stop mode Oscillator Internal clock RESET t res STOP instruction execution t res ≥ t RC (stabilization time) Figure 12 Timing of Stop Mode Cancellation Watch Mode: The MCU enters watch mode if the STOP instruction is executed in active mode when TMA3 = 1, or if the STOP or SBY instruction is executed in subactive mode. The watch mode is terminated by a RESET input or a timer-A/INT0 interrupt request. For details of RESET input, refer to the Stop Mode section. When terminated by a timer-A/INT0 interrupt request, the MCU enters active mode if LSON is 0, or subactive mode if LSON is 1. After an interrupt request is generated, the time required to enter active mode is tRC for a timer A interrupt, and TX (where T + tRC < TX < 2T + t RC) for an INT 0 interrupt, as shown in figures 13 and 14. 30 HD404328 Series Oscillation stabilization period Active mode Watch mode Active mode Interrupt strobe INT0 Interrupt request generation T (During the transition from watch mode to active mode only) tRC T TX T: Interrupt frame length t RC : Oscillation stabilization period Figure 13 Interrupt Frame Miscellaneous register (MIS): $00C 3 2 1 0 MIS Initial value: 0000, R/W: W T *1 Bit 1 Bit 0 Setting for switching the system oscillator’s frequency 0.12207 ms 0 0 0.24414 ms 0 1 15.625 ms 7.8125 ms 1 0 125 ms 62.5 ms 1 1 tRC selection R12 /SO PMOS off t RC* 1 0.24414 * 2 ms Not used T: Interrupt frame length tRC: Oscillation stabilization period Notes: 1. The value of tRC applies only when using a 32.768-kHz crystal oscillator. 2. Only direct transfer. Figure 14 Miscellaneous Register 31 HD404328 Series Operation during mode transition is the same as that at standby mode cancellation (figure 11). Subactive Mode: The CPU operates with a clock generated by the X1 and X2 oscillation circuits. Functions that can operate in subactive mode are listed in table 20. When the STOP or SBY instruction is executed in subactive mode, the MCU enters either watch or active mode, depending on the statuses of LSON and DTON. The DTON flag can only be set in subactive mode; it is automatically reset after a transition to active mode. The subactive mode is an optional function that the user must specify on the function option list. Interrupt Frame: In watch and subactive modes, timer A and INT0 interrupts are generated in synchronism with the interrupt frame. Three interrupt frame lengths (T) can be selected by the settings of the miscellaneous register, as shown in figure 14. The time from an interrupt strobe to interrupt request generation is the oscillation stabilization period (tRC), as shown in figure 13. The interrupt request is generated synchronously with the interrupt strobe timing except during transition to active mode. The falling edge of the INT0 signal is input asynchronously with the interrupt frame timing, but it is regarded as input synchronously with the second interrupt strobe clock after the falling edge. An overflow and interrupt request in timer A is generated synchronously with the interrupt strobe timing. Operation during the transition from watch mode to active mode is the same as that at standby mode cancellation (figure 11). Direct Transfer: By controlling the DTON flag, the MCU will be placed directly from subactive to active mode. The detailed procedure is as follows: • Set the DTON flag in subactive mode while LSON = 0 and DTON = 1. • Execute the STOP or SBY instruction. • After the oscillation stabilization time (a fixed value), the MCU will move automatically from subactive to active mode (see figure 15). Note that DTON ($020, bit 3) is valid only in subactive mode. When the MCU is in active mode, this flag is always at reset. The transition time (tD) from subactive to active mode is tRC < tD < T + tRC. 32 HD404328 Series STOP/SBY execution Internal execution Subactive mode time Oscillation stabilization time Active mode (LSON = 0, DTON = 1) Interrupt strobe Direct transfer timing t RC T T: Interrupt frame length tRC: Oscillation stabilization period Figure 15 Direct Transfer Timing MCU Operation Sequence: The MCU operates in the sequence shown in figures 16 to 18. It is reset by an asynchronous RESET input, regardless of its state. The low-power mode operation sequence is shown in figure 18. With the IE flag cleared and an interrupt flag set together with its interrupt mask cleared, if a STOP/SBY instruction is executed, the instruction is cancelled (regarded as an NOP) and the following instruction is executed. Before executing a STOP/SBY instruction, make sure all interrupt flags are cleared or all interrupts are masked. Power on No RESET = 1? Yes MCU operation cycle Reset MCU Figure 16 MCU Operating Sequence (Power On) 33 HD404328 Series MCU operation cycle IF = 1? No Yes No IM = 0, IE = 1? Yes Instruction execution Yes SBY, STOP instruction? IE ← 0; stack ← (PC), (CA), (ST) No Low-power mode operation cycle IF: IM: IE: PC: CA: ST: PC ← next location PC ← vector address Interrupt request flag Interrupt mask Interrupt enable flag Program counter Carry flag Status flag Figure 17 MCU Operating Sequence (MCU Operation Cycle) 34 HD404328 Series Low-power mode operation cycle IF = 1, IM = 0? No Yes Standby/watch mode Stop mode For IF and IM operation, refer to figure 11. No IF = 1, IM = 0? Yes Hardware NOP execution Hardware NOP execution PC ← next location PC ← next location Instruction execution MCU operation cycle Figure 18 MCU Operating Sequence (Low-Power Mode Operation) Limitation on Use • In subactive mode, the timer A interrupt request or the external interrupt request (INT 0) occurs in synchronism with the interrupt strobe. If the STOP or SBY instruction is executed at the same time with the interrupt strobe, these interrupt requests will be cancelled and its corresponding interrupt request flags (IFTA, IF0) will be not set. In subactive mode, do not use the STOP or SBY instruction at the time of the interrupt strobe. 35 HD404328 Series • When the MCU is in watch mode or subactive mode, if the high level period before the falling edge of INT 0 is shorter than the interrupt frame, INT 0 is not detected. Also, if the low level period after the falling edge of INT 0 is shorter than the interrupt frame, INT 0 is not detected. Edge detection is shown in figure 19. The level of the INT 0 signal is sampled by a sampling clock. When this sampled value changes to low from high, a falling edge is detected. In figure 20, the level of the INT0 signal is sampled by an interrupt frame. In (a) the sampled value is low at point A, and also low at point B. Therefore, a falling edge is not detected. In (b), the sampled value is high at point A, and also high at point B. A falling edge is not detected in this case either. When the MCU is in watch mode or subactive mode, keep the high level and low level period of INT 0 longer than interrupt frame. INT0 Sampling High Low Low Figure 19 Edge Detection INT 0 INT 0 Interrupt frame Interrupt frame A: Low B: Low a. High level period Figure 20 Sampling Example 36 A: High B: High b. Low level period HD404328 Series Internal Oscillator Circuit A block diagram of the internal oscillator circuit is shown in figure 22. As shown in table 21, crystal and ceramic oscillators can be connected to OSC1 and OSC2, and a 32.768-kHz oscillator can be connected to X1 and X2. The system oscillator can also be operated by an external clock. Bit 3 of the miscellaneous register (MIS: $00C) must be set according to the frequency of the oscillator connected to OSC1 and OSC2. Note: If the MIS register setting does not match the oscillator frequency, subsystems using 32-kHz oscillation will malfunction. Set the system oscillator frequency to anything outside the range of 1.0 MHz to 1.6 MHz when using 32-kHz oscillation. Miscellaneous register (MIS): $00C 3 2 1 0 MIS Initial value: 0000, R/W: W tRC selection Bit 3 System Oscillator’s Frequency 0 1.6 MHz to 4.5 MHz 1 0.4 MHz to 1.0 MHz R12 /SO PMOS off Setting for switching the system oscillator’s frequency Figure 21 Miscellaneous Register OSC2 System oscillator Divide-by-8 circuit OSC1 X1 Sub-system oscillator X2 Divide-by-8 circuit Timing generator circuit Timing generator circuit Synch. (tcyc) Synch. (tsubcyc ) System clock (ø CPU) Mode control circuit System clock (ø PER) Time-base clock (ø CLK ) Figure 22 Internal Oscillator Circuit 37 HD404328 Series Table 21 Oscillator Circuit Examples Circuit Configuration External Clock Operation (OSC1, OSC2) Circuit Constants External oscillator OSC1 Open OSC2 C1 Ceramic Oscillator (OSC1, OSC2) Ceramic: CSA4.00MG (Murata) R f = 1 MΩ ±20% C 1 = C2 = 30 pF ±20% OSC1 Ceramic Rf OSC2 C2 GND Crystal Oscillator (OSC1, OSC2) R f: 1 MΩ ±20% C1 = C2 = 10 pF ±10% Crystal: Equivalent to circuit shown at bottom left C0 = 7 pF, max. RS = 100 Ω , max. f = 1.0 MHz to 4.5 MHz C1 OSC1 Crystal Rf OSC2 C2 GND AT-cut parallel resonance crystal L OSC1 CS RS OSC2 C0 Crystal Oscillator (X1, X2) C1 =C2 = 15 pF ±5% Crystal: 32.768 kHz, MX38T (Nippon Denpa) C0 = 1.5 pF, typ. RS = 14 kΩ , typ. C1 X1 Crystal X2 C2 GND X1 L CS RS X2 C0 Notes: 38 1. Circuit constants differ with different types of crystal and ceramic oscillators, and with the stray capacitance of the board, so consult the manufacturer of the oscillator to determine the circuit parameters. 2. The wiring between the OSC1 and OSC 2 pins (X1 and X2 pins) and the other elements should be as short as possible, and must not cross other wiring. Refer to figure 23. 3. If not using a 32.768-kHz crystal oscillator, fix the X1 pin to VCC and leave the X2 pin open. HD404328 Series D0 GND X2 X1 RESET OSC 2 OSC 1 TEST AV SS Figure 23 Typical Layout of Crystal and Ceramic Oscillators 39 HD404328 Series Input/Output The MCU has 2 input pins and 33 input/output pins, 8 of the input/output pins being large-current pins (15 mA, max.). A program-controlled pull-up MOS transistor is provided for each input/output pin. The output buffer is turned on and off by the data control register (DCR) during input through an input/output pin. I/O pin circuit types are shown in table 22. Table 22 Circuit Configurations of I/O Pins I/O Pin Type Common I/O Pin (with pull-up MOS transistor) Circuit Applicable Pins Pull-up control signal VCC VCC DCR Output data Input control PDR Input data Pull-up control signal VCC D 0–D 8 R 0 0–R 0 3 R 10–R 13 R 2 0–R 2 3 R 3 0–R 3 3 R 4 0–R 4 3 R 5 0–R 5 3 SCK VCC DCR Output data SCK (internal) SCK Output Pin (with pull-up MOS transistor) Pull-up control signal VCC VCC DCR Output data SO or BUZZ Input Pin INT0 INT1 Pull-up control signal PDR VCC Input data Input control AC input signal External capacitor Zero-crossing detection circuit Note: For details of the R12 /SO pin, refer to note 2 of table 23. 40 SO BUZZ SI EVENT D9 D 10 ZCD HD404328 Series D Port (D0–D10): Consist of 9 input/output pins and 2 input pins. Pins D0–D7 are high-current I/O pins, D8 is an ordinary input/output pin, and D 9 and D10 are input-only pins. These pins are set by the SED and SEDD instructions, reset by the RED and REDD instructions, and tested by the TD and TDD instructions. The operating modes of D8–D10 are set by bits 2 and 3 of port mode register A (PMRA) and bits 0 and 1 of port mode register B (PMRB), as shown in figure 24. The on/off status of the output buffer is controlled by D port data control registers (DCRB, DCRC, and DCRD) that are mapped to memory addresses. R Ports: Accessed in 4-bit units. Data is input to these ports by the LAR and LBR instructions and output from them by the LRA and LRB instructions. The on/off status of the output buffers of the R ports are controlled by R port data control registers (DCR0–DCR5) that are mapped to memory addresses. Pins R10–R13 are multiplexed with pins SCK, SI, SO, and BUZZ, respectively. The operating modes of these pins are controlled by bit 3 of the serial mode register (SMR), bits 1 and 0 of port mode register A (PMRA), and bit 2 of port mode register C (PMRC), as shown in figure 24. Ports R2–R5 are multiplexed with SEG1–SEG16. The functions of these pins must be specified by the LCD output register (LOR: $015). 41 HD404328 Series Serial mode register (SMR): $005 3 2 1 0 Initial value: 0000, R/W: W R10 /SCK pin mode selection SMR Bit 3 Port Selection 0 R10 1 SCK Port mode register A (PMRA): $004 3 2 1 0 Initial value: 0000, R/W: W R12 /SO pin mode selection R11 /SI pin mode selection D9 /INT0 pin mode selection D10/INT 1 pin mode selection PMRA PMRA Bit 3 Port Selection PMRA Bit 2 Port Selection 0 1 PMRA Bit 1 Port Selection Bit 0 Port Selection D10 0 D9 0 R11 0 INT1 1 R12 INT0 1 SI 1 SO Port mode register B (PMRB): $011 3 2 1 0 Initial value: 0000, R/W: W D8 /ZCD/EVENT pin mode selection Not used PMRB Bit 1 0 1 Port Selection Bit 0 0 ZCD (low sensitivity) 1 ZCD (high sensitivity) * 0 D8 1 EVENT Note: * Becomes low sensitivity in subactive mode. Figure 24 I/O Switching Mode Registers 42 HD404328 Series Port mode register C (PMRC): $012 3 2 1 0 Initial value: 0000, R/W: W BUZZ output frequency selection R13/BUZZ pin mode selection Pull-up MOS transistor on/off selection PMRC Bit 3 Pull-Up MOS On/Off Selection PMRC Bit 3 Port Selection 0 Off 0 R13 1 On 1 BUZZ LCD output register (LOR): $015 3 2 1 0 Initial value: 0000, R/W: W R2/SEG1–SEG4 pin mode selection R3/SEG5–SEG8 pin mode selection R4/SEG9–SEG12 pin mode selection R5/SEG13–SEG16 pin mode selection LOR LOR Bit 3 Port Selection LOR Bit 2 Port Selection 0 1 LOR Bit 1 Port Selection Bit 0 Port Selection R5 0 R4 0 R3 0 R2 SEG13–SEG16 1 SEG9–SEG12 1 SEG5–SEG8 1 SEG1–SEG4 Figure 24 I/O Switching Mode Registers (cont) Pull-Up MOS Transistor Control: A program-controlled pull-up MOS transistor is provided for each input/output pin. The on/off status of all these transistors is controlled by bit 3 of port mode register C (PMRC), and the on/off status of an individual transistor can also be controlled by the port data register of the corresponding pin—enabling on/off control of that pin alone. The on/off status of each transistor and the peripheral function mode of each pin can be set independently. The configuration of the I/O buffer is shown in figure 25, and the configurations of various programcontrolled I/O circuits are given in table 23. How to Deal with Unused I/O Pins: I/O pins that are not needed by the user system (floating) must be connected to V CC to prevent LSI malfunctions due to noise. These pins must either be pulled up to VCC by their pull-up MOS transistors or by resistors of about 100 kΩ. 43 HD404328 Series VCC PMRC3 VCC Pull-up MOS transistor PMOS (A) DCR NMOS (B) PDR Input data Input control Figure 25 I/O Buffer Configuration Table 23 Programmable I/O Circuits PMRC, Bit 3 0 DCR 0 PDR 0 1 0 1 0 1 0 1 PMOS (A) Off Off Off On Off Off Off On NMOS (B) Off Off On Off Off Off On Off Off Off Off Off Off On Off On CMOS Buffer Pull-Up MOS Transistor Notes: 1 1 1 1. Various I/O methods can be selected by different combinations of settings of the above mode registers (PMRC3, DCR, PDR). 2. The PMOS (A) transistor of the R12 /SO pin can be turned off by setting bit 2 of the miscellaneous register (MIS) to 1. MIS DCR Bit 3 Bit 2 Bit 1 Bit 0 Bit 2 R12 /SO Pin PMOS (A) DCR0 R0 3 R0 2 R0 1 R0 0 0 On DCR1 R1 3 R1 2 R1 1 R1 0 1 Off DCR2 R2 3 R2 2 R2 1 R2 0 DCR3 R3 3 R3 2 R3 1 R3 0 DCR4 R4 3 R4 2 R4 1 R4 0 DCR5 R5 3 R5 2 R5 1 R5 0 DCRB D3 D2 D1 D0 DCRC D7 D6 D5 D4 DCRD — — — D8 3. The relationships between DCRs and pins are as shown on the right. 44 0 HD404328 Series Timers The MCU has two prescalers (S and W) and three timer/counters (A, B, and C). Prescaler S: Eleven-bit counter that inputs a system clock signal. After being initialized to $000 by MCU reset, prescaler S divides the system clock. Prescaler S keeps counting, except in watch and stop modes, and at MCU reset. Of the prescaler S outputs, timer A input clock, timer B input clock, timer C input clock, and serial interface transmit clock are selected by timer mode register A (TMA), timer mode register B (TMB), timer mode register C (TMC), and the serial mode register (SMR). Prescaler W: Five-bit counter that inputs the X1 input clock signal divided by eight. Prescaler W output can be selected as a timer A input clock by timer mode register A (TMA). Timer A: Eight-bit timer that can be used as a clock time-base (figure 26). It is initialized to $00 and incremented at each input clock. If an input clock is applied to timer A after it has reached $FF, an overflow that sets the timer A interrupt request flag (IFTA: $001, bit 2) is generated, and timer A restarts from $00. Timer A is used to generate regular interrupts (every 256 clocks) for measuring times between events. It can also be used as a clock time-base when bit 3 of timer mode register A (TMA) is set to 1. The timer is driven by the 32-kHz oscillator clock frequency divided by prescaler W, and the clock input to timer A is controlled by TMA. In this case, prescaler W and timer A can be initialized to $00 by software. 1/4 fW 1/2 twcyc 2 fW Timer A interrupt request flag (IFTA) Prescaler W (PSW) ÷2 ÷8 ÷ 16 ÷ 32 32.768-kHz oscillator 1/2 twcyc Clock Timer counter A (TCA) Overflow System clock ø PER ÷2 ÷4 ÷8 ÷ 32 ÷ 128 ÷ 512 ÷ 1024 ÷ 2048 Selector Internal data bus Selector Selector Prescaler S (PSS) 3 Timer mode register A (TMA) Figure 26 Timer A Block Diagram 45 HD404328 Series Timer B (TCBL and TLRL: $00A, TCBU and TLRU: $00B): Eight-bit write-only timer load register (TLRL and TLRU) and read-only timer counter (TCBL and TCBU) located at the same addresses. The eight-bit configuration consists of lower and upper digits located at sequential addresses. A block diagram of timer B is shown in figure 27. Timer counter B is initialized by writing to timer load register B (TLR). In this case, the lower nibble must be written to first. The contents of TLR are loaded into the timer counter at the same time the upper nibble is written to, initializing the timer counter. TLR is initialized to $00 by MCU reset. The count of timer B is obtained by reading timer counter B. In this case, the upper digit must be read first; the count is latched when the upper nibble is read. An auto-reload function, input clock source, and prescaler division ratio of timer B depend on the state of timer mode register B (TMB). When an external event input is used as the input clock source of TMB, the D 8/ZCD/EVENT pin must be set to function as the ZCD or EVENT pin by setting port mode register B (PMRB: $011). Timer B is initialized to the value set in TMB by software, and is then incremented by one by each clock input. If an input is applied to timer B after it has reached $FF, an overflow is generated. In this case, if the auto-reload function is enabled, timer B is initialized to its initial value; if auto-reload is disabled, the timer is initialized to $00. The overflow sets the timer B interrupt request flag (IFTB: $002, bit 0). Interrupt request flag of timer B (IFTB) Clock Free-running/ reload timer control signal ÷2 ÷4 ÷8 ÷ 32 ÷ 128 ÷ 512 ÷ 2048 ø PER Prescaler S (PSS) Overflow Timer load register B upper (TLRU) Timer load register B lower (TLRL) Selector EVENT System clock Timer/counter B (TCB) 3 Timer mode register B (TMB) Figure 27 Timer B Free-Running and Reload Operation Block Diagram 46 Internal data bus Timer latch register B (TLB) HD404328 Series Timer C (TCCL and TCRL: $00A, TCCU and TCRU: $00B): Eight-bit write-only timer load register (TCRL and TCRU) and read-only timer counter (TCCL and TCCU) located at the same addresses. The eight-bit configuration consists of lower and upper digits located at sequential addresses. The operation of timer C is basically the same as that of timer B. A block diagram of timer C is shown in figure 28. The auto-reload function and prescaler division ratio of timer C depend on the state of timer mode register C (TMC). Timer C is initialized to the value set in TMC by software, then is incremented by one at each clock input. If an input is applied to timer C after it has reached $FF, an overflow is generated. In this case, if the auto-reload function is enabled, timer C is initialized to its initial value; if auto-reload is disabled, the timer is initialized to $00. The overflow sets the timer C interrupt request flag (IFTC: $002, bit 2). Timer C also functions as a watchdog timer. If a program routine runs out of control and an overflow is generated while the watchdog on (WDON) flag is set, the MCU is reset. This error can be detected by having the program control timer C reset before timer C reaches $FF. The WDON can only have 1 written to it; it is cleared to 0 only by MCU reset. System reset signal Watchdog on flag (WDON) Interrupt request flag of timer C (IFTC) Watchdog timer controller Clock Timer/counter C (TCC) Overflow Timer load register C upper (TCRU) ÷2 ÷4 ÷8 ÷ 32 ÷ 128 ÷ 512 ÷ 1024 ÷ 2048 Selector System clock ø PER Free-running/ reload timer control signal Internal data bus Timer latch register C (TLC) Timer load register C lower (TCRL) 3 Prescaler S (PSS) Timer mode register C (TMC) Figure 28 Timer C Block Diagram 47 HD404328 Series Timer Mode Register A (TMA: $008): Four-bit write-only register that controls timer A as shown in table 24. Table 24 Timer Mode Register A TMA Bit 3 Bit 2 Bit 1 Bit 0 Source Prescaler, Input Clock Period, Operating Mode 0 0 0 1 1 0 1 1 0 0 1 1 0 1 0 PSS, 2048 tcyc 1 PSS, 1024 tcyc 0 PSS, 512 tcyc 1 PSS, 128 tcyc 0 PSS, 32 tcyc 1 PSS, 8 tcyc 0 PSS, 4 tcyc 1 PSS, 2 tcyc 0 PSW, 32 t subcyc 1 PSW, 16 t subcyc 0 PSW, 8 t subcyc 1 PSW, 2 t subcyc 0 PSW, 1/2 tsubcyc 1 Do not use 0 PSW, TCA reset Timer A mode Time-base mode 1 t subcyc = 244.14 µs (when 32.768-kHz crystal oscillator is used) t cyc = 1.9074 µs (when 4.1943-MHz crystal oscillator is used) Timer counter overflow output period (seconds) = input clock period (seconds) × 256. If PSW or TCA reset is selected while the LCD is operating, LCD operation halts (power switch goes off and all SEG and COM pins are grounded). When an LCD is connected for display, the PSW and TCA reset periods must be set in the program to the minimum. 5. The division ratio must not be modified during time-base mode operation, otherwise an overflow cycle error will occur. Notes: 1. 2. 3. 4. Timer Mode Register B (TMB: $009): Four-bit write-only register that selects the auto-reload function, input clock source, and the prescaler division ratio as shown in table 25. It is initialized to $0 by MCU reset. Writing to this register is valid from the second instruction execution cycle. Timer B initialization set by writing to TMB must be done after a mode change becomes valid. 48 HD404328 Series Table 25 Timer Mode Register B TMB Bit 3 Auto Reload Function 0 Disabled 1 Enabled TMB Bit 2 Bit 1 Bit 0 Input Clock Period/ Input Clock Source 0 0 0 2048 tcyc 1 512 tcyc 0 128 tcyc 1 32 tcyc 0 8 tcyc 1 4 tcyc 0 2 tcyc 1 ZCD/EVENT (external event input) 1 1 0 1 Timer Mode Register C (TMC: $00D): Four-bit write-only register that selects the auto-reload function and prescaler division ratio as shown in table 26. It is initialized to $0 by MCU reset. Writing to this register is valid from the second instruction execution cycle. Timer C initialization set by writing to TMC must be done after a mode change becomes valid. Table 26 Timer Mode Register C TMC Bit 3 Auto Reload Function 0 Disabled 1 Enabled 49 HD404328 Series TMC Bit 2 Bit 1 Bit 0 Input Clock Period 0 0 0 2048 tcyc 1 1024 tcyc 0 512 tcyc 1 128 tcyc 0 32 tcyc 1 8 tcyc 0 4 tcyc 1 2 tcyc 1 1 0 1 Pulse Output The MCU has a built-in pulse output function called BUZZ. The pulse frequency can be selected from the prescaler S’ s outputs, and the output frequency depends on the state of port mode register C (PMRC: $012), as shown in table 27. The duty cycle of the pulse output is fixed at 50%. When the pulse output function is used, the R13/BUZZ pin must be specified as BUZZ by PMRC. Table 27 Port Mode Register C PMRC Bit 1 Bit 0 Prescaler Division Ratio 0 0 ÷ 1024 1 ÷ 512 0 ÷ 256 1 ÷ 128 1 50 HD404328 Series Serial Interface The MCU has a clock-synchronous serial interface which transmits and receives 8-bit data. The serial interface consists of a serial data register (SR), serial mode register (SMR), port mode register A (PMRA), octal counter, and selector, as shown in figure 29. The R10/SCK pin and the transmit clock are controlled by writing data to the SMR. The transmit clock shifts the contents of the SR, which can be read and written to by software, before transmission starts between two MCUs. The serial interface is activated by the STS instruction. The octal counter is reset to 000 by this instruction, it starts counting at the falling edge of the transmit clock (SCK), and it increments at the rising edge of the clock. A serial interrupt request flag is set when the eighth transmit clock signal is input (the serial interface is reset) or when serial transmission is discontinued (the octal counter is reset). Serial interrupt request flag (IFS) Octal counter (OC) SO SCK I/O controller SI Selector Clock 1/2 Transfer control signal Internal data bus Serial data register (SR) Selector ÷2 ÷8 ÷ 32 ÷ 128 ÷ 512 ÷ 2048 3 System clock øPER Serial mode register (SMR) Prescaler S (PSS) Figure 29 Serial Interface Block Diagram Serial Mode Register (SMR: $005): Four-bit write-only register that controls the R10/SCK pin, transmit clock, and prescaler division ratio as shown in figure 30. Writing to this register initializes the serial interface. A write signal input to the serial mode register discontinues the input of the transmit clock to the serial data register and octal counter. Therefore, if a write is performed during data transmission, the octal counter is reset to 000 to stop transmission, and, at the same time, the serial interrupt request flag is set. 51 HD404328 Series Write operations are valid from the second instruction execution cycle, so the STS instruction must be executed after at least two cycles have been executed. The serial mode register is initialized to $0 by MCU reset. Serial mode register (SMR): $005 3 2 1 0 Initial value: 0000, R/W: W SMR R10 /SCK Pin Bit 3 Transmit clock selection R10 /SCK pin mode selection SMR Transmit Clock Period 0 SCK output Prescaler ÷ 2048 4096 tcyc 1 SCK output Prescaler ÷ 512 1024 t cyc 0 SCK output Prescaler ÷ 128 256 t cyc 1 SCK output Prescaler ÷ 32 64 tcyc 0 SCK output Prescaler ÷8 16 tcyc 1 SCK output Prescaler ÷2 4 t cyc 0 SCK output System clock — 1 tcyc 1 SCK input External clock — — 0 0 1 SCK input or output pin Prescaler Division Ratio Bit 0 0 1 Clock Source Bit 1 1 R10 port input or output pin R1 0 /SCK Pin Bit 2 1 0 Note: t cyc = 1.9074 µs (with 4.1943-MHz crystal oscillator used at 1/8 division ratio) Figure 30 Serial Mode Register Serial Data Register (SRL: $006, SRU: $007): Eight-bit read/write register separated into upper and lower digits located at sequential addresses. Data in this register is output from the SO pin, LSB first, in synchronism with the falling edge of the transmit clock; and data is input, LSB first, through the SI pin at the rising edge of the transmit clock. Input/output timing is shown in figure 31. Data cannot be read or written during serial data transmission. If a read/write occurs during transmission, the accuracy of the resultant data cannot be guaranteed. 52 HD404328 Series Transmit clock 1 Serial output data 2 3 4 5 6 7 8 MSB LSB Serial input data latch timing Figure 31 Timing of Serial Interface Output Selecting and Changing Operating Mode: Table 28 lists the serial interface’s operating modes. To select an operating mode, use one of these combinations of PMR and SMR settings; to change the operating mode, always initialize the serial interface internally by writing data to the SMR. Table 28 Serial Interface Operating Modes SMR PMRA Bit 3 Bit 1 Bit 0 Operating Mode 1 0 0 Continuous clock output mode 1 Transmit mode 0 Receive mode 1 Transmit/receive mode 1 Serial Interface Operation: Three operating modes are provided for the serial interface; transitions between them are shown in figure 32. In STS wait state, the serial interface is initialized and the transmit clock is ignored. If the STS instruction is then executed, the serial interface enters transmit clock wait state. In transmit clock wait state, input of the transmit clock increments the octal clock, shifts the serial clock register, and activates serial transmission. However, note that if clock output mode is selected, the transmit clock is continuously output but data is not transmitted. During transfer state, the input of eight clocks or the execution of the STS instruction sets the octal counter to 000, and the serial interface enters transmit clock wait state. If the state changes from transmit to another state, the serial interrupt request flag is set by the octal counter reaching 000. In this state, if the internal clock has been selected, the transmit clock is output in answer to the execution of the STS instruction, but serial transmission is inhibited after the eighth clock is output. 53 HD404328 Series If port mode register A (PMRA) is written to in transmit clock wait state or transfer state, the serial mode register (SMR) must be written to, to initialize the serial interface. The serial interface then enters STS wait state. If the serial interface shifts from transfer state to another state, the octal counter returns to 000, setting the serial interrupt request flag. STS instruction wait state (octal counter = 000, transmit clock disabled) SMR write STS instruction 8 transmit clocks (internal clock) (IFS ← 1) SMR write (IFS ← 1) Transmit clock Transmit clock wait state (octal counter = 000) 8 transmit clocks (external clock) STS instruction (IFS ← 1) Transfer state (octal counter ≠ 000) Figure 32 Serial Interface Mode Transitions Transmit Clock Error Detection: The serial interface will malfunction if a spurious pulse caused by external noise conflicts with a normal transmit clock during transmission. A transmit clock error of this type can be detected as shown in figure 33. If more than eight transmit clocks are input in transmit clock wait state, the serial interface’s state changes to transfer, transmit clock wait, then back to transfer. If the serial interface is set to STS wait state by writing data to the SMR after the serial interrupt request flag has been reset, the flag is reset again. 54 HD404328 Series Transmission completion (IFS ← 1) Interrupts inhibited IFS ← 0 SMR write IFS = 1? Yes Transmit clock error processing No Normal termination Figure 33 Transmit Clock Error Detection Note on Use: The serial interrupt request flag might not be set if the status is changed from transfer by the execution of an SMR write or STS instruction during the first period that the transmit clock is low. To prevent this, program a check that the SCK pin is at 1 (by executing an input instruction for the R1 port) before the execution of an SMR write or STS instruction, to ensure that the serial interrupt request flag is set. 55 HD404328 Series A/D Converter The MCU has a built-in A/D converter that uses a sequential comparison method with a resistor ladder. It can measure four analog inputs with an eight-bit resolution. As shown in the block diagram of figure 34, the A/D converter has a four-bit A/D mode register, a one-bit A/D start flag, and a four-bit plus four-bit A/D data register. Internal bus line (S2) 4 1 A/D mode register (AMR: $016) 2 Internal bus line (S1) 1 A/D start flag (ADSF: $020) 4 A/D data register (ADRL: $017, ADRU: $018) 1 AN 2 AN 3 Selector AN 0 AN 1 4 IFAD Comparator + Control logic AVCC Counter – AVSS Operation mode signal (Stop mode, Watch mode, Subactive mode: Value is 0) Figure 34 A/D Converter Block Diagram A/D Mode Register (AMR: $016): Four-bit write-only register which selects the A/D conversion period and indicates analog input pin information. Bit 0 of the AMR selects the A/D conversion period, and bits 2 and 3 select a channel, as shown in figure 35. A/D Start Flag (ADSF: $020, Bit 2): One-bit flag that initiates A/D conversion when 1 is written to it. At the completion of A/D conversion, the converted data is stored in the A/D data register and the ADSF is cleared. Refer to figure 35. Note: Use the SEM and SEMD instructions to write data to the ADSF, but make sure that the ADSF is not written to during A/D conversion. 56 HD404328 Series A/D mode register (AMR): $016 3 2 1 0 Initial value: 0000, R/W: W Switching time Not used Analog input selection AMR Switching Time Bit 0 0 34 tcyc 1 67 tcyc AMR Analog Input Selection Bit 3 Bit 2 0 0 AN 0 1 AN 1 0 AN 2 1 AN 3 1 Special flag bits: $020 3 2 1 0 LSON (refer to description of low-power dissipation modes) WDON (refer to description of timers) A/D start flag (ADSF) DTON (refer to description of low-power dissipation modes) Bit 2 A/D Start Flag (ADSF) 1 A/D conversion started 0 A/D conversion completed Figure 35 A/D Registers A/D Data Register (ADRL: $017, ADRU: $018): Eight-bit read-only register that is not cleared by a reset. Note that data read from this register during A/D conversion cannot be guaranteed. After the completion of A/D conversion, the resultant eight-bit data is held in this register, as shown in figure 36, until the start of the next conversion. 57 HD404328 Series ADRL: $017 ADRU: $018 3 2 1 0 3 2 1 0 MSB LSB Bit 7 Bit 0 Result Figure 36 A/D Data Registers Note on Use: The contents of the A/D data register are not guaranteed during A/D conversion. To ensure that the A/D converter operates stably, do not execute port output instructions during A/D conversion. 58 HD404328 Series LCD Controller/Driver The MCU has an LCD controller and driver which drive four common signal pins and 24 segment pins. The controller consists of a RAM area in which display data is stored, a display control register (LCR), and a duty cycle/clock control register (LMR), as shown in figures 37 and 38. Four duty cycles and the LCD clock are program-controllable, and a built-in dual-port RAM ensures that display data can be automatically transmitted to the segment signal pins without program intervention. If a 32-kHz oscillation clock is selected as the LCD clock source, the LCD can be used even in watch mode, in which the system clock stops. VCC Power switch V1 LCD power control circuit V2 * V3 COM1 COM2 COM3 COM4 LCD common driver * LCD clock * GND LCD output register (LOR: $015) Display on/off 4 1 2 Display control register (LCR: $013) R2 0 /SEG1 R2 1 /SEG2 $050 Display area (dual-port RAM) LCD segment driver Segment/ R2–R5 port multiplexer R5 3 /SEG16 SEG17 $067 LCD duty cycle/ clock control register (LMR: $014) 2 2 SEG24 RAM area Duty cycle selection LCD clock 3 Divided system clock output 1 Divided 32-kHz clock output Clock selection Note: * HD404324U, HD404326U, HD404328U and HD4074329U require external LCD voltage division resistors. LCD: Liquid crystal display Figure 37 Block Diagram of LCD Controller/Driver 59 HD404328 Series LCD control register (LCR): $013 2 1 0 Initial value: 000, R/W: W Blank/display Power switch on/off Display on/off in watch mode or subactive mode (not used) LCD mode register (LMR): $014 3 2 1 0 Initial value: 0000, R/W: W Duty cycle selection Input clock selection LCD output register (LOR): $015 3 2 1 0 Initial value: 0000, R/W: W R2/SEG1–SEG4 pin mode selection R3/SEG5–SEG8 pin mode selection R4/SEG9–SEG12 pin mode selection R5/SEG13–SEG16 pin mode selection Figure 38 LCD Registers LCD Data Area and Segment Data ($050–$067): As shown in figure 39, each bit of the storage area corresponds to one of four duty cycles. If data is written to an area corresponding to a certain duty cycle, it is automatically output to the corresponding segments as display data. 60 HD404328 Series Bit 3 Bit 2 Bit 1 Bit 0 80 SEG1 SEG1 SEG1 SEG1 $050 92 SEG13 SEG13 SEG13 SEG13 $05C 81 SEG2 SEG2 SEG2 SEG2 $051 93 SEG14 SEG14 SEG14 SEG14 $05D 82 SEG3 SEG3 SEG3 SEG3 $052 94 SEG15 SEG15 SEG15 SEG15 $05E 83 SEG4 SEG4 SEG4 SEG4 $053 95 SEG16 SEG16 SEG16 SEG16 $05F 84 SEG5 SEG5 SEG5 SEG5 $054 96 SEG17 SEG17 SEG17 SEG17 $060 85 SEG6 SEG6 SEG6 SEG6 $055 97 SEG18 SEG18 SEG18 SEG18 $061 86 SEG7 SEG7 SEG7 SEG7 $056 98 SEG19 SEG19 SEG19 SEG19 $062 87 SEG8 SEG8 SEG8 SEG8 $057 99 SEG20 SEG20 SEG20 SEG20 $063 88 SEG9 SEG9 SEG9 SEG9 $058 100 SEG21 SEG21 SEG21 SEG21 $064 89 SEG10 SEG10 SEG10 SEG10 $059 101 SEG22 SEG22 SEG22 SEG22 $065 90 SEG11 SEG11 SEG11 SEG11 $05A 102 SEG23 SEG23 SEG23 SEG23 $066 91 SEG12 SEG12 SEG12 SEG12 $05B 103 SEG24 SEG24 SEG24 SEG24 $067 COM4 COM3 COM2 Bit 3 COM1 COM4 Bit 2 COM3 Bit 1 COM2 Bit 0 COM1 Figure 39 Configuration of LCD RAM Area (for Dual-Port RAM) LCD Control Register (LCR: $013): Three-bit write-only register which controls LCD blanking, the turning on and off of the liquid-crystal display’s power supply division resistor, and display in watch and subactive modes, as shown in table 29. • Blank/display Blank: Segment signals are turned off, regardless of LCD RAM data setting. Display: LCD RAM data is output as segment signals. • Power switch on/off Off: The power switch is off. On: The power switch is on and V1 is VCC. • Watch/subactive mode display Off: In watch and subactive modes, all common and segment pins are grounded and the liquid-crystal power switch is turned off. On: In watch and subactive modes, LCD RAM data is output as segment signals. 61 HD404328 Series Table 29 LCD Control Register LCR LCR LCR Bit 2 Display in Watch Mode or Subactive Mode Bit 1 Power Switch On/Off Bit 0 Blank/Display 0 Off 0 Off 0 Blank 1 On 1 On 1 Display Note: When using an LCD in watch mode or subactive mode, use the divided output of a 32-kHz oscillator as the LCD clock and set bit 2 of the LCR to 1. If using the divided output of the system clock as the LCD clock, always set bit 2 of the LCR to 0. LCD Duty Cycle/Clock Control Register (LMR: $014): Four-bit write-only register which selects the display duty cycle and LCD clock source, as shown in table 30. The dependence of frame frequency on duty cycle is shown in table 31. Table 30 LCD Duty Cycle/Clock Control Register LMR Bit 3 Bit 2 Bit 1 Bit 0 Duty Selection/Input Clock Selection — — 0 0 1/4 duty cycle 1 1/3 duty cycle 0 1/2 duty cycle 1 Static — CL0 (32.768/64 kHz when using a 32.768-kHz oscillator) 1 0 1 0 — 1 CL1 (fcyc/256) 0 CL2 (fcyc/2048) 1 CL3 (refer to table 31) Note: f cyc is the divided system clock output. 62 HD404328 Series Table 31 LCD Frame Periods for Different Duty Cycles Static Duty Cycle LMR Bit 3 Bit 2 Bit 3 Bit 2 Bit 3 Bit 2 Bit 3 Bit 2 0 0 0 1 1 0 1 1 Instruction Cycle Time CL0 CL1 CL2 CL3* 2 µs 512 Hz 1953 Hz 244 Hz 122 Hz/64 Hz 1/2 Duty Cycle LMR Bit 3 Bit 2 Bit 3 Bit 2 Bit 3 Bit 2 Bit 3 Bit 2 0 0 0 1 1 0 1 1 Instruction Cycle Time CL0 CL1 CL2 CL3* 2 µs 256 Hz 976.5 Hz 122 Hz 61 Hz/32 Hz 1/3 Duty Cycle LMR Bit 3 Bit 2 Bit 3 Bit 2 Bit 3 Bit 2 Bit 3 Bit 2 0 0 0 1 1 0 1 1 Instruction Cycle Time CL0 CL1 CL2 CL3* 2 µs 170.6 Hz 651 Hz 81.3 Hz 40.6 Hz/21.3 Hz 1/4 Duty Cycle LMR Bit 3 Bit 2 Bit 3 Bit 2 Bit 3 Bit 2 Bit 3 Bit 2 0 0 0 1 1 0 1 1 Instruction Cycle Time CL0 CL1 CL2 CL3* 2 µs 128 Hz 488.2 Hz 61 Hz 30.5 Hz/16 Hz Note: * The division ratio depends on the value of bit 3 of timer mode register A (TMA); the first value is for TMA3 = 0 and the second is for TMA3 = 1. When TMA3 = 0, CL3 = f cyc /4096 When TMA3 = 1, CL3 = 32.768 kHz/512. 63 HD404328 Series LCD Output Register (LOR: $015): Write-only register used to specify that ports R2–R5 act as pins SEG1–SEG16, as shown in table 32. Table 32 LCD Output Register LOR LOR LOR LOR Bit 3 Port Selection Bit2 Port Selection Bit 1 Port Selection Bit 0 Port Selection 0 R5 0 R4 0 R3 0 R2 1 SEG16–SEG13 1 SEG12–SEG9 1 SEG8–SEG5 1 SEG4–SEG1 Large Liquid-Crystal Panel Drive and VLCD : To drive a large-capacity LCD, decrease the resistance of the built-in division resistors by attaching external resistors in parallel, as shown in figure 40. Since HD404328U and HD4074329U do not have built-in division resistors, they require external LCD voltage division resistors for voltage adjustment. The size of these resistors cannot be simply calculated from the LCD load capacitance because the matrix configuration of the LCD complicates the paths of charge/discharge currents flowing through the capacitors—and the resistance will also vary with lighting conditions. This size must be determined by trial-and-error, taking into account the power dissipation of the device using the LCD, but a resistance of 1 kΩ to 10 kΩ would usually be suitable. (Another effective method is to attach capacitors of 0.1 µF to 0.3 µF.) Always turn off the power switch (set bit 1 of the LCR to 0) before changing the liquid-crystal drive voltage (VLCD). 64 HD404328 Series R VCC (V1) R V2 V2 C R VCC (V1) R C V3 V3 R R C GND GND C = 0.1 µF to 0.3 µF 1 V CC COM1 3-digit LCD V1 VCC VLCD V2 V3 GND 24 SEG1– SEG24 Static drive V CC V1 VCC VLCD COM1 COM2 2 6-digit LCD V2 V3 GND 24 SEG1– SEG24 1/2 duty cycle, 1/2 bias drive V CC V1 VCC VLCD COM1– COM3 3 8-digit LCD V2 V3 GND 24 SEG1– SEG24 1/3 duty cycle, 1/3 bias drive V CC V1 VCC VLCD COM1– COM4 4 12-digit LCD V2 V3 SEG1– SEG24 1/4 duty cycle, 1/3 bias drive 24 GND VCC ≥ VLCD ≥ GND Figure 40 LCD Connection Examples 65 HD404328 Series Zero-Crossing Detection Circuit The MCU has a zero-crossing detection circuit that generates a digital signal in synchronism with an AC signal input to the ZCD pin through an external capacitor. A block diagram of the zero-crossing detection circuit is shown in figure 41. The zero-crossing detection circuit has two modes (low sensitivity mode and high sensitivity mode) which are set by port mode register B (PMRB: $011) as shown in table 33. A digital signal generated by the zero-crossing detection circuit sets the zero-crossing interrupt request flag (IFZC). The interrupt edge is selected by the interrupt mode register (IMR: $010). This signal can be made as the input clock of timer B by setting the input clock source of timer mode register B (TMB: $009) for external event input. Note: After MCU reset, the D8/ZCD/EVENT pin is set to ZCD. With this setting, a supply current (bias current) always flows because a bias circuit within the zero-crossing circuit is still operating. This current flows in all MCU operation modes, but it is particularly critical in stop mode because the MCU is more affected by bias current since the other circuits of the LSI are not dissipating much current. If the zero-crossing detection function is not being used, use port mode register B to set this pin to D8 or EVENT. This prevents the bias current from flowing. D8 port input AC input signal EVENT (Refer to figure 27.) MPX D 8/ZCD/ EVENT pin MPX Zero-crossing detection circuit MPX MPX 2 2 IFZC External capacitor Port mode register B Interrupt mode register Figure 41 Block Diagram of Zero-Crossing Detection Circuit Table 33 Port Mode Register B PMRB 1 0 Port Selection 0 0 ZCD (low sensitivity mode) 1 ZCD (high sensitivity mode)* 0 D8 1 EVENT 1 Note: * Becomes low sensitivity in subactive mode. 66 HD404328 Series Table 34 Registers in Special Register Area Name Address R/W Bit Description PMRA $004 0 R1 2/S0 pin mode selection 1 R1 1/SI pin mode selection 2 D9/INT0 pin mode selection 3 D10/INT1 pin mode selection 2–0 Serial transmit clock speed selection 3 R1 0/SCK pin mode selection SMR $005 W W SRL $006 R/W 3–0 Serial interface data register, lower 4 bits SRU $007 R/W 3–0 Serial interface data register, upper 4 bits TMA $008 W 2–0 Input clock selection (timer A) 3 Timer-A/time-base mode selection 2–0 Input clock selection (timer B) 3 Auto-reload function selection TMB $009 W TCBL/TLRL $00A R/W 3–0 Timer counter/timer load register (timer B), lower 4 bits TCBU/TLRU $00B R/W 3–0 Timer counter/timer load register (timer B), upper 4 bits MIS $00C W 1, 0 Interrupt frame period selection 2 R1 2/SO PMOS off 3 Changeover to setting by system oscillator frequency 2–0 Input clock selection (timer C) 3 Auto-reload function selection TMC $00D W TCCL/TCRL $00E R/W 3–0 Timer counter/timer load register (timer C), lower 4 bits TCCU/TCRU $00F R/W 3–0 Timer counter/timer load register (timer C), upper 4 bits IMR $010 W 1, 0 INT1 detection edge selection 3, 2 Zero-crossing detection edge selection 1, 0 D8/ZCD/EVENT pin mode selection 3, 2 Do not use 1, 0 Buzzer frequency selection 2 R1 3/ BUZZ pin mode selection 3 Pull-up MOS transistor on/off selection 0 LCD display selection 1 LCD power switch on/off selection 2 LCD display selection during watch mode 3 Do not use 1, 0 LCD duty cycle selection 3, 2 LCD input clock selection PMRB PMRC LCR LMR $011 $012 $013 $014 W W W W 67 HD404328 Series Name Address R/W Bit Description LOR $015 0 R2/SEG1–SEG4 pin mode selection 1 R3/SEG5–SEG8 pin mode selection 2 R4/SEG9–SEG12 pin mode selection 3 R5/SEG13–SEG16 pin mode selection 0 Conversion timing selection (A/D) 1 Do not use 3, 2 Analog input selection (A/D) AMR $016 W W ADRL $017 R 3–0 A/D data register, lower 4 bits ADRU $018 R 3–0 A/D data register, upper 4 bits DCR0 $030 W 3–0 Data control register for port R0 DCR1 $031 W 3–0 Data control register for port R1 DCR2 $032 W 3–0 Data control register for port R2 DCR3 $033 W 3–0 Data control register for port R3 DCR4 $034 W 3–0 Data control register for port R4 DCR5 $035 W 3–0 Data control register for port R5 DCRB $03B W 3–0 Data control register for port D0–D 3 DCRC $03C W 3–0 Data control register for port D4–D 7 DCRD $03D W 0 Data control register for port D8 3–1 Do not use 68 HD404328 Series PROM Mode Description Programming the Built-In ROM The MCU’s built-in ROM is programmed in PROM mode in which the pins are arranged as shown in figure 42. PROM mode is set by pulling TEST, M0, and M1 low, and RESET high as shown in figure 43. In PROM mode, the MCU does not operate, but it can be programmed in the same way as any other commercial 27256-type EPROM using a standard PROM programmer and a 64-to-28–pin socket adapter. Recommended PROM programmers and socket adapters are listed in table 35. Since an HMCS400-series instruction is ten bits long, the HMCS400-series MCU has a built-in conversion circuit to enable use of a general-purpose PROM programmer. This circuit splits each instruction into a lower five bits and an upper five bits that are read from or written to consecutive addresses. This means that if, for example, 16 kwords of built-in PROM are to be programmed by a general-purpose PROM programmer, a 32-kbyte address space ($0000–$7FFF) must be specified. VCC M0 M1 VCC VCC GND TEST VCC RESET GND GND A7 A8 A0 A 10 A 11 A 12 A 13 A 14 A9 VPP A5 A6 O4 O3 O2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 HD4074329S HD4074329US HD4074329C 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VCC M 0 M 1VCC VCC VCC GND TEST VCC RESET GND OE CE A4 A3 A2 A1 O7 O6 O5 O4 O3 O2 O1 O0 VCC O0 O1 GND A7 A8 A0 A 10 A 11 A 12 A 13 A 14 VCC 64 63 62 61 60 59 58 57 56 55 54 53 52 1 51 2 50 3 49 4 48 5 47 6 46 7 45 8 44 9 43 HD4074329FS 10 42 HD4074329UFS 11 41 12 40 13 39 14 38 15 37 16 36 17 35 18 34 19 33 20 21 22 23 24 25 26 27 28 29 30 31 32 OE CE A4 A3 A2 A1 O7 O6 O5 O4 O3 A 9VPP A 5 A 6 O 4 O 3 O 2 O 1 O 0VCCO 0 O 1 O 2 Note: Externally connect pins of the same name. This is not necessary if one of the sockets listed in table 35 is used. Figure 42 Pin Arrangement in PROM Mode 69 HD404328 Series VCC VCC VCC RESET TEST M0 M1 O0 –O7 Data O0 –O7 A 0–A14 Address A 0–A14 VPP VPP OE OE CE CE GND Figure 43 PROM Mode Connections Table 35 Recommended PROM Programmers and Socket Adapters PROM Programmer Socket Adapter Manufacturer Model Name Package Model Name Manufacturer DATA I/O Corp. 29B DP-64S DC-64S HS432ESS01H Hitachi FP-64B HS432ESF01H Hitachi DP-64S DC-64S HS432ESS01H Hitachi FP-64B HS432ESF01H Hitachi AVAL Data Corp. 70 PKW-1000 HD404328 Series Warnings 1. Always specify addresses $0000 to $7FFF when programming with a PROM programmer. If address $8000 or higher is accessed, the PROM may not be programmed or verified correctly. Set all data in unused addresses to $FF. Note that the plastic-package version cannot be erased and reprogrammed, but the ceramic windowpackage version can be reprogrammed after being exposed to ultraviolet light. 2. Make sure that the PROM programmer, socket adapter, and LSI are aligned correctly (their pin 1 positions match), otherwise overcurrents may damage the LSI. Before starting programming, make sure that the LSI is firmly fixed in the socket adapter and the socket adapter is firmly fixed in the programmer. 3. PROM programmers have two voltages (VPP ): 12.5 V and 21 V. Remember that ZTAT devices require a VPP of 12.5 V—the 21-V setting will damage them. 12.5 V is the Intel 27256 setting. Programming and Verification: The built-in PROM of the MCU can be programmed at high speed without risk of voltage stress or damage to data reliability. Programming and verification modes are selected as shown in table 36. For details of PROM programming, refer to the Notes on PROM Programming section. Table 36 PROM Mode Selection Pin Mode CE OE VPP O0–O7 Programming Low High VPP Data input Verification High Low VPP Data output Programming inhibited High High VPP High impedence Erasure (Window Package) Data in the PROM is erased by exposing the LSI to ultraviolet light of a wavelength of 2537 Å for an integrated dose of at least 15 W.s/cm2. These conditions can be satisfied by placing the LSI about 2 cm to 3 cm away from an ultraviolet lamp with a rating of 12,000 µW/cm2 for about 20 minutes. After erasure, all PROM bits are set to 1. For details of packages with windows, refer to the Notes on Window Packages section. 71 HD404328 Series Addressing Modes RAM Addressing Modes The MCU has three RAM addressing modes, as shown in figure 44 and described below. Register Indirect Addressing Mode: The contents of the W, X, and Y registers (10 bits in total) are used as a RAM address. Direct Addressing Mode: A direct addressing instruction consists of two words. The first word contains the opcode, and the contents of the second word (10 bits) are used as a RAM address. Memory Register Addressing Mode: The memory registers (MR), which consist of 16 digits from $040– $04F, are accessed with the LAMR and XMRA instructions. W register W1 RAM address X register W0 X 3 X2 X1 Y register X0 Y3 Y2 Y1 Y0 AP 9 AP 8 AP 7 AP 6 AP 5 AP 4 AP 3 AP 2 AP 1 AP 0 Register Indirect Addressing 1st word of instruction 2nd word of instruction Opcode d9 RAM address d8 d7 d6 d5 d4 d3 d2 d1 d0 AP9 AP8 AP7 AP 6 AP 5 AP 4 AP 3 AP 2 AP 1 AP 0 Direct Addressing Instruction Opcode 0 RAM address 0 0 1 0 m2 m1 m0 0 AP 9 AP 8 AP 7 AP 6 AP 5 AP 4 AP 3 AP 2 AP 1 AP 0 Memory Register Addressing Figure 44 RAM Addressing Modes 72 m3 HD404328 Series ROM Addressing Modes and the P Instruction The MCU has four ROM addressing modes, as shown in figure 45 and described below. Direct Addressing Mode: A program can branch to any address in the ROM memory space by executing the JMPL, BRL, or CALL instruction. Each of these instructions replaces the 14 program counter bits (PC 13–PC0) with 14-bit immediate data. Current Page Addressing Mode: The MCU has 64 pages of ROM with 256 words per page. A program can branch to any address in the current page by executing the BR instruction. This instruction replaces the eight low-order bits of the program counter (PC7–PC0) with eight-bit immediate data. If the BR instruction is on a page boundary (address 256n + 255), executing that instruction transfers the PC contents to the next physical page, as shown in figure 47. This means that the execution of the BR instruction on a page boundary will make the program branch to the next page. Note that the HMCS400-Series cross macroassembler has an automatic paging feature for ROM pages. Zero-Page Addressing Mode: A program can branch to the zero-page subroutine area located at $000– $003F by executing the CAL instruction. When the CAL instruction is executed, 6 bits of immediate data are placed in the six low-order bits of the program counter (PC5–PC0), and 0s are placed in the eight highorder bits (PC13–PC6). Table Data Addressing Mode: A program can branch to an address determined by the contents of fourbit immediate data, the accumulator, and the B register by executing the TBR instruction. P Instruction: ROM data addressed in table data addressing mode can be referenced with the P instruction as shown in figure 46. If bit 8 of the ROM data is 1, eight bits of ROM data are written to the accumulator and the B register. If bit 9 is 1, eight bits of ROM data are written to the R0 and R1 port output registers. If both bits 8 and 9 are 1, ROM data is written to the accumulator and the B register, and also to the R0 and R1 port output registers at the same time. The P instruction has no effect on the program counter. 73 HD404328 Series 1st word of instruction [JMPL] [BRL] [CALL] p3 Opcode 2nd word of instruction p2 p1 p0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 Program counter PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Direct Addressing Instruction [BR] Opcode b 7 b6 b5 b4 b3 b2 b1 b0 Program counter PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Current Page Addressing Instruction [CAL] 0 0 0 0 Opcode 0 0 a5 0 a4 a3 a2 a1 a0 0 Program counter PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Zero Page Addressing Instruction [TBR] p3 Opcode p2 p1 p0 B register B3 0 B2 B1 Accumulator B0 A3 A2 A1 A0 0 Program counter PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Table Data Addressing Figure 45 ROM Addressing Modes 74 HD404328 Series Instruction [P] p3 Opcode p2 p1 p0 B register B3 0 B2 B1 Accumulator B0 A3 A2 A1 A0 0 Referenced ROM address RA13 RA12 RA11 RA10 RA 9 RA 8 RA 7 RA 6 RA 5 RA 4 RA 3 RA 2 RA 1 RA 0 Address Specification ROM data RO9 RO8 RO7 RO6 RO5 RO4 RO3 RO2 RO1 RO0 Accumulator, B register B3 B2 B1 B0 A3 A2 A1 A0 If RO8 = 1 ROM data RO9 RO8 RO7 RO6 RO5 RO4 RO3 RO2 RO1 RO0 Output registers R0, R1 R13 R12 R11 R1 0 R0 3 R0 2 R0 1 R0 0 If RO9 = 1 Pattern Output Figure 46 P Instruction BR AAA NOP BR BR BBB 256(n – 1) + 255 AAA 256n AAA 256n + 254 BBB 256n + 255 256(n + 1) NOP Figure 47 Branching when Branch Destination is on a Page Boundary 75 HD404328 Series Absolute Maximum Ratings Item Symbol Value Unit Notes Power voltage VCC –0.3 to +7.0 V Programming voltage VPP –0.3 to +14.0 V Pin voltage VT –0.3 to VCC + 0.3 V Total permissible input current ∑Io 100 mA 2 Total permissible output current –∑Io 50 mA 3 Maximum input current Io 4 mA 4, 5 30 mA 4, 6 7, 8 Maximum output current –I o 4 mA Operating temperature Topr –20 to +75 °C Storage temperature Tstg –55 to +125 °C 1 Notes: Permanent damage may occur if these absolute maximum ratings are exceeded. Normal operation must be under the conditions stated in the Electrical Characteristics table. If these conditions are exceeded, the LSI may malfunction or its reliability may be affected. 1. D10 (VPP) of the HD4074329 and HD4074329U. 2. The total permissible input current is the total of input currents simultaneously flowing in from all the I/O pins to ground. 3. The total permissible output current is the total of output currents simultaneously flowing out from VCC to all I/O pins. 4. The maximum input current is the maximum current flowing from any I/O pin to ground. 5. Applies to D 8, R0–R5. 6. Applies to D 0–D 7. 7. The maximum output current is the maximum current flowing from V CC to any I/O pin. 8. Applies to D 0–D 8, R0–R5. 76 HD404328 Series Electrical Characteristics DC Characteristics (HD404324, HD404326, HD404328: V CC = 2.7 V to 6.0 V, GND = 0.0 V, Ta = –20°C to +75°C; HD404324U, HD404326U, HD404328U: VCC = 2.7 V to 6.0 V, GND = 0.0 V, Ta = –40°C to +85°C; HD4074329, HD4074329U: VC C = 2.9 V to 5.5 V, GND = 0.0 V, Ta = –20°Cto+75°C; unless otherwise specified) Item Symbol Pin(s) Min Typ Max Unit Test Conditions Input high voltage VIH RESET, SCK, INT0, INT1, SI,EVENT 0.8VCC — V VCC + 0.3 Notes HD404324, HD404324U: HD404326, HD404326U: HD404328, HD404328U: VCC = 3.5 V to 6.0 V HD4074329, HD4074329U: VCC = 3.5 V to 5.5 V OSC1 0.9VCC — VCC + 0.3 V VCC – 0.5 — VCC + 0.3 V HD404324, HD404324U: HD404326, HD404326U: HD404328, HD404328U: VCC = 3.5 V to 6.0 V HD4074329, HD4074329U: VCC = 3.5 V to 5.5 V Input low voltage VIL RESET, SCK, INT0, INT1,EVENT, SI VCC – 0.3 — VCC + 0.3 V –0.3 — 0.2VCC V HD404324, HD404324U: HD404326, HD404326U: HD404328, HD404328U: VCC = 3.5 V to 6.0 V HD4074329, HD4074329U: VCC = 3.5 V to 5.5 V –0.3 — 0.1VCC V 77 HD404328 Series DC Characteristics (HD404324, HD404326, HD404328: V CC = 2.7 V to 6.0 V, GND = 0.0 V, Ta = –20°C to +75°C; HD404324U, HD404326U, HD404328U: VCC = 2.7 V to 6.0 V, GND = 0.0 V, Ta = –40°C to +85°C; HD4074329, HD4074329U: VC C = 2.9 V to 5.5 V, GND = 0.0 V, Ta = –20°Cto+75°C; unless otherwise specified) (cont) Item Symbol Pin(s) Min Typ Max Unit Test Conditions Input low voltage VIL OSC1 –0.3 — V 0.5 Notes HD404324, HD404324U: HD404326, HD404326U: HD404328, HD404328U: VCC = 3.5 V to 6.0 V HD4074329, HD4074329U: VCC = 3.5 V to 5.5 V –0.3 — 0.3 V VOH SCK, SO, BUZZ VCC – 1.0 — — V –I OH = 0.5 mA Output low voltage VOL SCK, SO, BUZZ — — 0.4 V IOL = 0.4 mA I/O leakage current |IIL| RESET, SCK, INT0, INT1, SI, SO, OSC1, — — 1.0 µA Vin = 0 to VCC 1 — 3 6 mA VCC = 5.0 V, 2 Output high voltage BUZZ Current dissipation ICC in active mode VCC Current dissipation ISBY in standby mode VCC Current dissipation ISUB in subactive mode VCC fOSC = 4 MHz — 0.6 1.5 mA VCC = 3.0 V, 3 LCD on — 50 70 µA HD404324, HD404326, HD404328: VCC = 3.0 V, LCD on — 40 60 µA HD404324U, HD404326U, HD404328U: VCC = 3.0 V, LCD on — 70 150 µA HD4074329: VCC = 3.0 V, LCD on — 60 140 µA HD4074329U: VCC = 3.0 V, LCD on Current dissipation IWTC1 in watch mode(1) 78 VCC — 4 15 µA VCC = 3.0 V, LCD off 4 HD404328 Series DC Characteristics (HD404324, HD404326, HD404328: VCC = 2.7 V to 6.0 V, GND = 0.0 V, Ta = –20°C to +75°C; HD404324U, HD404326U, HD404328U: VCC = 2.7 V to 6.0 V, GND = 0.0 V, Ta = –40°C to +85°C; HD4074329, HD4074329U: VCC = 2.9 V to 5.5 V, GND = 0.0 V, Ta = –20°C to +75°C; unless otherwise specified) (cont) Item Symbol Current dissipation IWTC2 in watch mode(2) Pin(s) Min Typ Max Unit Test Conditions Notes VCC — 15 µA 4 35 HD404324, HD404326, HD404328, HD4074329: VCC = 3.0 V, LCD on — 5 25 µA HD404324U, HD404326U, HD404328U, HD4074329U: 4 VCC = 3.0 V, LCD on Current dissipation ISTOP in stop mode VCC Stop mode retain voltage VCC VSTOP — 1 10 µA VCC = 3.0 V, 4 X1 = VCC 2 — — V No 32-kHz oscillator 5 Notes: 1. Output buffer current is excluded. 2. I CC1 is the source current when no I/O current is flowing while the MCU is in reset state. Test conditions: MCU: Reset Pins: RESET, TEST, D0–D 7, D9, D10, R0–R5 at V CC D8 open 3. I SBY is the source current when no I/O current is flowing while the MCU timer is in operation. Test conditions: MCU: I/O reset Serial interface stopped Standby mode Pins: RESET at GND TEST, D0–D 7, D9, D10, R0–R5 at V CC D8 open 4. D10 is connected to V CC in the HD4074329 and HD4074329U. 5. RAM data retention. 79 HD404328 Series I/O Characteristics for Standard Pins (HD404324, HD404326, HD404328: VCC = 2.7 V to 6.0 V, GND = 0.0 V, Ta = –20°C to +75°C; HD404324U, HD404326U, HD404328U: VCC = 2.7 V to 6.0 V, GND = 0.0 V, T a = –40°C to +85°C; HD4074329, HD4074329U: VCC = 2.9 V to 5.5 V, GND = 0.0 V, Ta = –20°C to +75°C; unless otherwise specified) Item Symbol Pin(s) Min Typ Max Unit Test Conditions Input high voltage VIH 0.7VCC — VCC + 0.3 V –0.3 — 0.3VCC V D8–D10 , Note R0–R5 Input low voltage VIL D8–D10 , Output high voltage VOH D8, R0–R5 VCC – 1.0 — — V –I OH = 0.5 mA Output low voltage VOL D8, R0–R5 — — 0.4 V IOL = 0.4 mA I/O leakage current |IIL| D8, D9, — — 1.0 µA Vin = 0 to VCC * — — 1.0 µA HD404324, HD404324U, HD404326, HD404326U, HD404328, HD404328U: * — — 20.0 µA R0–R5 R0–R5 D10 Vin = 0 to VCC HD4074329, HD4074329U Vin = 0 to VCC Pull-up MOS current –I pu D8, R0–R5 Note: * Output buffer current is excluded. 80 5 25 90 µA VCC = 3.0 V, Vin = 0.0 V HD404328 Series I/O Characteristics for High-Current Pins (HD404324, HD404326, HD404328: VCC = 2.7 V to 6.0 V, GND = 0.0 V, Ta = –20°C to +75°C; HD404324U, HD404326U, HD404328U: VCC = 2.7 V to 6.0 V, GND = 0.0 V, Ta = –40°C to +85°C; HD4074329, HD4074329U: VCC = 2.9 V to 5.5 V, GND = 0.0 V, Ta = –20°C to +75°C; unless otherwise specified) Item Symbol Pin(s) Min Typ Max Unit Test Conditions Input high voltage VIH D0–D7 0.7VCC — V Input low voltage VIL D0–D7 –0.3 — 0.3VCC V Output high voltage VOH D0–D7 VCC – 1.0 — — V –I OH = 0.5 mA Output low voltage VOL D0–D7 — — 0.4 V IOL = 0.4 mA — — 2.0 V HD404324, HD404324U, HD404326, HD404326U, HD404328, HD404328U: VCC + 0.3 Note IOL = 15 mA, VCC = 4.5 V to 6.0 V HD4074329, HD4074329U: IOL = 15 mA, VCC = 4.5 V to 5.5 V I/O leakage current |IIL| D0–D7 — — 1.0 µA Vin = 0 to VCC Pull-up MOS current D0–D7 5 25 90 µA VCC = 3.0, Vin = 0 –I pu * Note: * Output buffer current is excluded. 81 HD404328 Series LCD Circuit Characteristics (HD404324, HD404326, HD404328: VCC = 2.7 V to 6.0 V, GND = 0.0 V, T a = –20°C to +75°C; HD404324U, HD404326U, HD404328U: V CC = 2.7 V to 6.0 V, GND = 0.0 V, Ta = –40°C to +85°C; HD4074329, HD4074329U: VCC = 2.9 V to 5.5 V, GND = 0.0 V, Ta = –20°C to +75°C; unless otherwise specified) Item Symbol Pin(s) Min Typ Max Unit Test Conditions Segment driver voltage drop VDS SEG1–SEG24 — — 0.6 V Id = 3.0 µA 1 Common driver voltage drop VDC COM1–COM4 — — 0.3 V Id = 3.0 µA 1 100 300 900 kΩ HD404324, HD404326, HD404328, HD4074329: LCD power supply RW division resistor Note Between V 1 and GND, V1 = VCC LCD voltage VLCD V1 2.7 — VCC V HD404324, HD404324U, HD404326, HD404326U, HD404328, HD404328U 2 2.9 — VCC V HD4074329, HD4074329U 2 Notes: 1. VDS and VDC are the voltage drops from power supply pins V1, V2, and V 3, and GND to each segment pin and each common pin. 2. When VLCD is supplied from an external source, the following relations must be retained: VCC ≥ V 1 ≥ V 2 ≥ V 3 ≥ GND 82 HD404328 Series A/D Converter Characteristics (HD404324, HD404326, HD404328: V CC = 2.7 V to 6.0 V, AV SS = 0.0 V, Ta = –20°C to +75°C; HD404324U, HD404326U, HD404328U: VCC = 2.7 V to 6.0 V, AVSS = 0.0 V, T a = –40°C to +85°C; HD4074329, HD4074329U: VCC = 2.9 V to 5.5 V, AVSS = 0.0 V, T a = –20°C to +75°C; unless otherwise specified) Item Symbol Pin(s) Min Typ Max Unit Test Conditions Analog power voltage AV CC AV CC VCC – 0.3 VCC VCC + 0.3 V Analog input voltage AV in AN0–AN 3 AV SS — AV CC V Current between AV CC and AVSS IAD — — 50 — µA Analog input capacitance CAin AN0–AN 3 — 30 — pF Resolution 8 8 8 Bit Number of inputs 0 — 4 Cha nnel Absolute accuracy — — ±2.0 LSB Conversion period 34 — 67 tcyc 1 — — MΩ f = 1 MHz, Analog input impedance AN0–AN 3 Note VCC = AVCC = 5.0 V * Vin = 0.0 V Note: * Operating frequency of A/D conversion fOSC is from 1 (MHz) to 4.5 (MHz). Zero-Crossing Detection Circuit Characteristics Low Sensitivity Mode (HD404324, HD404324U, HD404326, HD404326U, HD404328, HD404328U: VCC = 2.7 V to 6.0 V, GND = 0.0 V, Ta = 0°C to +70°C; HD4074329, HD4074329U: VCC = 3.0 V to 5.5 V, GND = 0.0 V, Ta = 0°C to +70°C; unless otherwise specified) Item Symbol Pin Min Typ Max Unit Test Conditions Note Zero-crossing detection input voltage VZC ZCD 2.0 — VP-P AC connection, Zero-crossing detection accuracy VAZC Zero-crossing detection input frequency f ZC 3.0 C = 0.1 µF — — ±750 mV f ZC = 50/60 Hz (sine wave), f OSC = 4 MHz 45 — 250 Refer to figure 48 Hz 83 HD404328 Series High Sensitivity Mode (VCC = 5.0 V, GND = 0.0 V, Ta = 0°C to 70°C, unless otherwise specified) Item Symbol Pin Min Typ Max Unit Test Conditions Zero-crossing detection input voltage VZC ZCD 2.0 — VP-P AC connection, 3.0 Note C = 0.1 µF Zero-crossing VAZC detection accuracy — — ±100 mV f ZC = 50/60 Hz (sine wave), f OSC = 4 MHz, Refer to figure 48 VCC = 5.0 V Zero-crossing detection input frequency f ZC 45 — 1000 Hz 1/f ZC VAZC AC input VAZC VZC(P-P) Internal CPU signal Note: The internal CPU signal is shown lagging behind the original waveform in the figure, but this is not fixed—it could actually lead. Figure 48 Zero-Crossing Detection 84 HD404328 Series AC Characteristics (HD404324, HD404326, HD404328: V CC = 2.7 V to 6.0 V, GND = 0.0 V, Ta = –20°C to +75°C; HD404324U, HD404326U, HD404328U: VCC = 2.7 V to 6.0 V, GND = 0.0 V, Ta = –40°C to +85°C; HD4074329, HD4074329U: VCC = 2.9 V to 5.5 V, GND = 0.0 V, Ta = –20°C to +75°C; unless otherwise specified) Item Symbol Clock oscillation frequency fOSC Pin(s) Min Typ Max Unit Test Conditions Note OSC1, OSC2 0.4 4.0 4.5 MHz 1/8 division, 1 32 kHz used 0.4 4.0 4.5 MHz 1/8 division used, — 32.768 — kHz — 2 — µs fOSC = 4 MHz — — 40 ms HD404324, HD404324U, HD404326, HD404326U, HD404328, HD404328U: 32 kHz not used X1, X2 Instruction cycle time tcyc Oscillation stabilization time(crystal) tRC OSC1, OSC2 2 VCC = 3.5 V to 6.0 V HD4074329, HD4074329U: VCC = 3.5 V to 5.5 V Oscillation stabilization time(ceramic) tRC OSC1, OSC2 — — 60 ms — — 20 ms 2 HD404324, HD404324U, HD404326, HD404326U, HD404328, HD404328U: 2 VCC = 3.5 V to 6.0 V HD4074329, HD4074329U: VCC = 3.5 V to 5.5 V — — 60 ms 2 Oscillation stabilization time tRC X1, X2 — — 3 s 3 External clock high width tCPH OSC1 90 — — ns 4 External clock low width tCPL OSC1 90 — — ns 4 External clock rise time tCPr OSC1 — — 20 ns 4 External clock fall time tCPf OSC1 — — 20 ns 4 INT0, INT1, EVENT high width tIH INT0, INT1, 2 — — tcyc / tsubcyc 5 INT0, INT1, EVENT width tIL 2 — — tcyc / tsubcyc 5 EVENT INT0, INT1, EVENT 85 HD404328 Series Item Symbol Pin(s) Min Typ Max Unit Test Conditions Note RESET high width tRSTH RESET 2 — — fcyc 6 RESET fall time tRSTf RESET — — 20 ms 6 Input capacitance Cin All pins except D10 , AN 0–AN 3 — — 30 pF f = 1 MHz, Vin = 0.0 V D10 — — 30 pF HD404324, HD404324U, HD404326, HD404326U, HD404328, HD404328U: f = 1 MHz, Vin = 0.0 V — — 180 pF HD4074329, HD4074329U: f = 1 MHz, Vin = 0.0 V Notes: 1. If fOSC = 0.4 MHz to 1.0 MHz, bit 3 of the miscellaneous register (MIS: $00C) must be set to 1; if f OSC = 1.6 MHz to 4.5 MHz, bit 3 must be set to 0. Do not use fOSC = 1.0 MHz to1.6 MHz with 32kHz oscillation. 2. The oscillation stabilization time is the time required for the oscillator to stabilize after V CC reaches 2.7 V (2.9 V for the HD4074329 and HD4074329U, or 3.5 V if VCC = 3.5 V to 5.5 V) at power-on or after RESET input goes high after stop mode is canceled. At power-on and when stop mode is cancelled, RESET must be input for at least t RC to ensure the oscillation stabilization time. If using a crystal oscillator or a ceramic oscillator, contact its manufacturer to determine what stabilization time is required, since it will depend on the circuit constants and stray capacitances. 3. The oscillation stabilization time is the time required for the oscillator to stabilize after V CC reaches 2.7 V (2.9 V for the HD4074329 and HD4074329U) at power-on—at least tRC must be ensured. If using a 32.768-kHz crystal oscillator, contact its manufacturer to determine what stabilization time is required, since it will depend on the circuit constants and stray capacitances. 4. Refer to figure 49. 5. Refer to figure 50. The t cyc unit applies when the MCU is in standby or active mode. The t subcyc unit applies when the MCU is in watch or subactive mode. tsubcyc = 244.14 µs (32.768kHz crystal) 6. Refer to figure 51. 86 HD404328 Series Serial Interface Timing Characteristics (HD404324, HD404326, HD404328: VCC = 2.7 V to 6.0 V, GND = 0.0 V, Ta = –20°C to +75°C; HD404324U, HD404326U, HD404328U: VCC = 2.7 V to 6.0 V, GND = 0.0 V, Ta = –40°C to +85°C; HD4074329, HD4074329U: VCC = 2.9 V to 5.5 V, GND = 0.0 V, Ta = –20°C to +75°C; unless otherwise specified) During Transmit Clock Output Item Symbol Pin Min Typ Max Unit Test Conditions Notes Transmit clock cycle time tScyc SCK 1.0 — — tcyc , tsubcyc Load shown in figure 53 1, 2 Transmit clock high width tSCKH SCK 0.3 — — tScyc Load shown in figure 53 1 Transmit clock low width tSCKL SCK 0.3 — — tScyc Load shown in figure 53 1 Transmit clock rise time tSCKr SCK — — 100 ns HD404324, HD404324U, 1 HD404326, HD404326U, HD404328, HD404328U: VCC = 3.5 V to 6.0 V, load shown in figure 53 HD4074329, HD4074329U: 1 VCC = 3.5 V to 5.5 V, load shown in figure 53 Transmit clock fall time tSCKf SCK — — 200 ns Load shown in figure 53 1 — — 100 ns HD404324, HD404324U, 1 HD404326, HD404326U, HD404328, HD404328U: VCC = 3.5 V to 6.0 V, load shown in figure 53 HD4074329, HD4074329U: 1 VCC = 3.5 V to 5.5 V, load shown in figure 53 Serial output data delay time tDSO SO — — 200 ns Load shown in figure 53 1 — — 300 ns HD404324, HD404324U, 1 HD404326, HD404326U, HD404328, HD404328U: VCC = 3.5 V to 6.0 V, load shown in figure 53 HD4074329, HD4074329U: 1 VCC = 3.5 V to 5.5 V, load shown in figure 53 — — 500 ns Load shown in figure 53 1 Notes: 1. Refer to figure 52. 2. The t subcyc unit applies when subactive mode is operating. 87 HD404328 Series Item Symbol Pin Min Typ Max Unit Test Conditions Serial input data setup time tSSI SI 200 — — ns HD404324, HD404324U, * HD404326, HD404326U, HD404328, HD404328U: Note VCC = 3.5 V to 6.0 V HD4074329, HD4074329U: * VCC = 3.5 V to 5.5 V Serial input data hold time tHSI SI 300 — — ns * 150 — — ns HD404324, HD404324U, * HD404326, HD404326U, HD404328, HD404328U VCC = 3.5 V to 6.0 V HD4074329, HD4074329U * VCC = 3.5 V to 5.5 V 300 Note: * Refer to figure 52. 88 — — ns * HD404328 Series During Transmit Clock Input Item Symbol Pin Min Typ Max Unit Transmit clock cycle time tScyc Transmit clock high width Test Conditions Notes SCK 1.0 — — tcyc , t subcyc 1, 2 tSCKH SCK 0.3 — — tScyc 1 Transmit clock low width tSCKL SCK 0.3 — — tScyc Transmit clock rise time tSCKr SCK — — 100 ns 1 HD404324, HD404324U, HD404326, HD404326U, HD404328, HD404328U: 1 VCC = 3.5 V to 6.0 V HD4074329, HD4074329U: 1 VCC = 3.5 V to 5.5 V Transmit clock fall time tSCKf SCK — — 200 ns — — 100 ns 1 HD404324, HD404324U, HD404326, HD404326U, HD404328, HD404328U: 1 VCC = 3.5 V to 6.0 V HD4074329, HD4074329U: 1 VCC = 3.5 V to 5.5 V Serial output data delay time tDSO SO — — 200 ns — — 300 ns 1 HD404324, HD404324U, HD404326, HD404326U, HD404328, HD404328U: 1 VCC = 3.5 V to 6.0 V, load shown in figure 53 HD4074329, HD4074329U: 1 VCC = 3.5 V to 5.5 V, load shown in figure 53 Serial input data setup time tSSI SI — — 500 ns Load shown in figure 53 1 200 — — ns HD404324, HD404324U, HD404326, HD404326U, HD404328, HD404328U: 1 VCC = 3.5 V to 6.0 V HD4074329, HD4074329U: 1 VCC = 3.5 V to 5.5 V Serial input data hold time tHSI SI 300 — — ns 150 — — ns 1 HD404324, HD404324U, HD404326, HD404326U, HD404328, HD404328U: 1 VCC = 3.5 V to 6.0 V HD4074329, HD4074329U: 1 VCC = 3.5 V to 5.5 V 300 — — ns 1 Notes: 1. Refer to figure 52. 2. The t subcyc unit applies when subactive mode is operating. 89 HD404328 Series V CC = 3.5 V to 6.0 V (HD404324, HD404324U, HD404326, HD404326U, HD404328, HD404328U) V CC = 3.5 V to 5.5 V (HD4074329, HD4074329U) 1/fcp VCC – 0.5 V OSC 1 0.5 V t CPH t CPr t CPL t CPf VCC = 2.7 V to 3.5 V (HD404324, HD404324U, HD404326, HD404326U, HD404328, HD404328U) VCC = 2.9 V to 3.5 V (HD4074329, HD4074329U) 1/fcp VCC – 0.3 V OSC 1 0.3 V t CPH t CPr t CPL t CPf Figure 49 Oscillator Timing VCC = 3.5 V to 6.0 V (HD404324, HD404324U, HD404326, HD404326U, HD404328, HD404328U) VCC = 3.5 V to 5.5 V (HD4074329, HD4074329U) INT0 , INT1 , EVENT 0.8VCC 0.2VCC t IH t IL VCC = 2.7 V to 3.5 V (HD404324, HD404324U, HD404326, HD404326U, HD404328, HD404328U) VCC = 2.9 V to 3.5 V (HD4074329, HD4074329U) INT0 , INT1 , EVENT 0.9VCC 0.1VCC t IH t IL Figure 50 Interrupt Timing 90 HD404328 Series VCC = 3.5 V to 6.0 V (HD404324, HD404324U, HD404326, HD404326U, HD404328, HD404328U) VCC = 3.5 V to 5.5 V (HD4074329, HD4074329U) RESET 0.8VCC 0.2VCC t RSTH t RSTf VCC = 2.7 V to 3.5 V (HD404324, HD404324U, HD404326, HD404326U, HD404328, HD404328U) VCC = 2.9 V to 3.5 V (HD4074329, HD4074329U) RESET 0.9VCC 0.1VCC t RSTH t RSTf Figure 51 Reset Timing 91 HD404328 Series VCC = 3.5 V to 6.0 V (HD404324, HD404324U, HD404326, HD404326U, HD404328, HD404328U) VCC = 3.5 V to 5.5 V (HD4074329, HD4074329U) t Scyc t SCKf t SCKr t SCKHD t SCKL V – 2.0 V (0.8VCC ) * SCK CC t SCKH 0.8 V (0.2VCC ) * t DSO SO VCC – 2.0 V 0.8 V t SSI t HSI 0.8VCC 0.2VCC SI Note: * VCC – 2.0 V and 0.8 V are the threshold voltages for transmit clock output, 0.8VCC and 0.2VCC are the threshold voltages for transmit clock input, and t DSO , tSSI , and t HSI are the timings used with transmit clock input voltages. VCC = 2.7 V to 3.5 V (HD404324, HD404324U, HD404326, HD404326U, HD404328, HD404328U) VCC = 2.9 V to 3.5 V (HD4074329, HD4074329U) t Scyc t SCKf t SCKr t SCKHD t SCKL V – 0.5 V (0.9VCC ) * SCK CC t SCKH 0.4 V (0.1VCC ) * t DSO SO VCC – 0.5 V 0.4 V t SSI t HSI 0.9VCC 0.1VCC SI Note: * VCC – 0.5 V and 0.4 V are the threshold voltages for transmit clock output, 0.9VCC and 0.1VCC are the threshold voltages for transmit clock input, and t DSO , tSSI , and t HSI are the timings used with transmit clock input voltages. Figure 52 Serial Interface Timing VCC Test point C 30 pF RL = 2.6 kΩ R 12 kΩ Ω 1S2074 H or equivalent Figure 53 Timing Load Circuit 92 HD404328 Series Option List HD404324, HD404324Li, HD404326, HD404326U, HD404328, HD404328U Please check off the appropriate applications and enter the necessary information. Date of order / / Customer 1. ROM size Department HD404324 4-kword With internal ROM code name HD404326 6-kword LCD voltage HD404328 8-kword division registers LSI number (to be filled in by Hitachi) HD404324U 4-kword Without internal HD404326U 6-kword LCD voltage HD404328U 8-kword division registers 2. Optional Function (1) * With 32-kHz CPU operation * Without 32-kHz CPU operation, with time-base for clock Without 32-kHz CPU operation, without time-base Note: * Options marked with an asterisk require a subsystem crystal oscillator (X1, X2). 3. Optional Function (2) With zero-crossing detection function Without zero-crossing detection function 4. ROM Code Media Please specify the first type below (the upper bits and lower bits are mixed together), when using the EPROM on-package microcomputer type (including ZTAT™ version). EPROM: The upper bits and lower bits are mixed together. The upper five bits and lower five bits are programmed to the same EPROM in alternating order (i.e., LULULU...). EPROM: The upper bits and lower bits are separated. The upper five bits and lower five bits are programmed to different EPROMS. 5. System Oscillator for OSC1 and OSC2 Ceramic oscillator f= MHz Crystal oscillator f= MHz External clock f= MHz 6. Stop Mode 7. Packages Used DP-64S Not used FP-64A FP-64B 93 HD404328 Series Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi’s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products. Hitachi, Ltd. Semiconductor & Integrated Circuits. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 URL NorthAmerica : http:semiconductor.hitachi.com/ Europe : http://www.hitachi-eu.com/hel/ecg Asia (Singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm Asia (Taiwan) : http://www.hitachi.com.tw/E/Product/SICD_Frame.htm Asia (HongKong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm Japan : http://www.hitachi.co.jp/Sicd/indx.htm For further information write to: Hitachi Semiconductor (America) Inc. 179 East Tasman Drive, San Jose,CA 95134 Tel: <1> (408) 433-1990 Fax: <1>(408) 433-0223 Hitachi Europe GmbH Electronic components Group Dornacher Straße 3 D-85622 Feldkirchen, Munich Germany Tel: <49> (89) 9 9180-0 Fax: <49> (89) 9 29 30 00 Hitachi Europe Ltd. Electronic Components Group. Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA, United Kingdom Tel: <44> (1628) 585000 Fax: <44> (1628) 778322 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia Ltd. Taipei Branch Office 3F, Hung Kuo Building. No.167, Tun-Hwa North Road, Taipei (105) Tel: <886> (2) 2718-3666 Fax: <886> (2) 2718-8180 Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Tsim Sha Tsui, Kowloon, Hong Kong Tel: <852> (2) 735 9218 Fax: <852> (2) 730 0281 Telex: 40815 HITEC HX Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan. 94