54FCT574 Octal D-Type Flip-Flop with TRI-STATE ® Outputs General Description Features The ’FCT574 is an octal flip-flop with a buffered common Clock (CP) and a buffered common Output Enable (OE). The information presented to the D inputs is stored in the flip-flops on the LOW-to-HIGH Clock (CP) transition. n Inputs and outputs on opposite sides of package allowing easy interface with microprocessors n Useful as input or output port for microprocessors n Functionally identical to ’FCT374 n TRI-STATE outputs for bus-oriented applications n Output sink capability of 32 mA, source capability of 12 mA n TTL input and output level compatible n CMOS power consumption n Standard Microcircuit Drawing (SMD) 5962-8951301 The device is functionally identical to the ’FCT374 except for the pinouts. Ordering Code Military Package Number Package Description 54FCT574DMQB J20A 20-Lead Ceramic Dual-In-Line 54FCT574FMQB W20A 20-Lead Cerpack 54FCT574LMQB E20A 20-Lead Ceramic Leadless Chip Carrier, Type C Connection Diagrams Pin Assignment for DIP and Flatpak Pin Descriptions Pin Description Names D0–D7 Data Inputs CP Clock Pulse Input OE TRI-STATE Output Enable O0–O7 TRI-STATE Outputs (Active Rising Edge) Input (Active LOW) DS100966-1 Pin Assignment for LCC DS100966-2 TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 1999 National Semiconductor Corporation DS100966 www.national.com 54FCT574 Octal D-Type Flip-Flop with TRI-STATE Outputs October 1999 54FCT574 Functional Description Inputs The ’FCT574 consists of eight edge-triggered flip-flops with individual D-type inputs and TRI-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold times requirements on the LOW-to-HIGH Clock (CP) transition. With the Output Enable (OE) LOW, the contents of the eight flip-flops are available at the outputs. When OE is HIGH, the outputs are in a high impedance state. Operation of the OE input does not affect the state of the flip-flops. Inputs Internal Outputs CP D Q O H H or L L NC Z Function CP D Q O H H or L H NC Z H N L L Z Load H N H H Z Load L N L L L Data Available L N H H H Data Available L H or L L NC NC No Change in Data L H or L H NC NC No Change in Data Hold H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance N = LOW-to-HIGH Transition NC = No Change Function Table OE Internal Outputs OE Function Hold Logic Diagram DS100966-3 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.national.com 2 Current Applied to Output in LOW State (Max) DC Latchup Source Current Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias Ceramic VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Any Output in the Disabled or Power-Off State in the HIGH State twice the rated IOL (mA) −500 mA Recommended Operating Conditions −65˚C to +150˚C −55˚C to +125˚C Free Air Ambient Temperature Military Supply Voltage Military −55˚C to +175˚C −0.5V to +7.0V −0.5V to +7.0V −30 mA to +5.0 mA −55˚C to +125˚C +4.5V to +5.5V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. −0.5V to 5.5V −0.5V to VCC Note 2: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol Parameter FCT574 Min Units VIH Input HIGH Voltage VIL Input LOW Voltage 0.8 V VCD Input Clamp Diode Voltage −1.2 V VOH Output HIGH Voltage VOL 2.0 Output LOW Voltage VCC Conditions Max V Recognized HIGH Signal Min 54FCT 4.3 V Min 54FCT 2.4 V Min 54FCT 0.2 V Min 54FCT 0.5 V Min µA Max µA Max IIH Input HIGH Current 5 IIL Input LOW Current −5 5 −5 Recognized LOW Signal IIN = −18 mA IOH = −300 µA IOH = −12 mA IOL = 300 µA IOL = 32mA VIN = 2.7V (Note 3) VIN = VCC VIN = 0.5V (Note 3) VIN = 0.0V VOUT = 2.7V; OE = 2.0V IOZH Output Leakage Current 10 µA 0 − 5.5V IOZL Output Leakage Current −10 µA 0 − 5.5V IOS Output Short-Circuit Current mA Max ICCQ Power Supply Current 1.5 mA Max VIN = 0.2V or VIN = 5.3V, fI = 0MHz ∆ICC Power Supply Current 2.0 mA Max ICCT Additional ICC/Input 6.0 mA Max 5.5 mA Max VIN = 3.4V VI = VCC − 2.1V or VIN = GND, fCP = 10MHz, Outputs open, OE = GND, one bit toggling at fI = 5MHz, 50% duty cycle VI = 5.3V or VCC = 0.2V, fCP = 10MHz, Outputs open, OE = GND, one bit toggling at fI = 5MHz, 50% duty cycle 0.40 mA/ MHz Max ICCD Dynamic ICC No Load −60 VOUT = 0.5V; OE = 2.0V VOUT = 0.0V Outputs Open, OE = GND, One bit toggling, 50% duty cycle, VIN = 5.3V or VIN = 0.2V Note 3: Guaranteed, but not tested. 3 www.national.com 54FCT574 Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. 54FCT574 AC Electrical Characteristics Symbol 54FCT TA = −55˚C to +125˚C VCC = 4.5V to 5.5V Parameter Fig. No. Units CL = 50 pF Min Max tPLH Propagation Delay 2.0 11.0 tPHL CP to On 2.0 11.0 tPZH Output Enable Time tPZL tPHZ Output Disable Time tPLZ 1.5 14.0 1.5 14.0 1.5 8.0 1.5 8.0 ns Figure 4 ns Figure 6 ns Figure 6 AC Operating Requirements Symbol 54FCT TA = −55˚C to +125˚C VCC = 4.5V to 5.5V Parameter Fig. Units No. ns Figure 7 ns Figure 7 ns Figure 5 CL = 50 pF Min ts(H) Setup Time, HIGH 3.5 ts(L) or LOW Dn to CP 3.5 th(H) Hold Time, HIGH 2.0 th(L) or LOW Dn to CP 2.0 tw(H) Pulse Width, CP, 7.0 tw(L) HIGH or LOW 7.0 Max Capacitance Symbol Parameter Typ CIN Input Capacitance 5.0 pF COUT (Note 4) Output Capacitance 9.0 pF Note 4: COUT is measured at frequency f = 1 MHz, per MIL-STD-883B, Method 3012. www.national.com Units 4 Conditions TA = 25˚C VCC = 0V VCC = 5.0V 54FCT574 AC Loading DS100966-4 DS100966-6 *Includes jig and probe capacitance FIGURE 2. VM = 1.5V FIGURE 1. Standard AC Test Load Input Pulse Requirements Amplitude Rep. Rate tw tr tf 3.0V 1 MHz 500 ns 2.5 ns 2.5 ns FIGURE 3. Test Input Signal Requirements DS100966-8 FIGURE 4. Propagation Delay Waveforms for Inverting and Non-Inverting Functions DS100966-5 FIGURE 5. Propagation Delay, Pulse Width Waveforms DS100966-7 FIGURE 6. TRI-STATE Output HIGH and LOW Enable and Disable Times DS100966-9 FIGURE 7. Setup Time, Hold Time and Recovery Time Waveforms 5 www.national.com 54FCT574 Physical Dimensions inches (millimeters) unless otherwise noted 20-Terminal Ceramic Chip Carrier (L) NS Package Number E20A 20-Lead Ceramic Dual-In-Line Package (D) NS Package Number J20A www.national.com 6 54FCT574 Octal D-Type Flip-Flop with TRI-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Ceramic Flatpak (F) NS Package Number W20A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: [email protected] www.national.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: [email protected] Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Français Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 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