Agilent HPFC-5000 Tachyon Fibre Channel Interface Controller Product Brief Description Tachyon is a fundamental building block compatible with Agilent Technologies’ Fibre Channel solution which includes interface controllers, physical link modules, adapters, switches and disk drives. Internal Block Diagram The Internal Block Diagram in Figure 1 below shows the high-level chip architecture for Tachyon. Inbound Message Queue MFS SFS Buffer Buffer Queue Queue Inbound Data Outbound Host-Based Data Structures Command Queue SCSI Exchange State Table High-Priority Command Queue Outbound Data Backplane Interface Inbound Block Mover Inbound Message Channel Inbound SFS and MFS Buffer Channels SCSI Read/Write Channel Outbound Message Channel High Priority Message Channel Outbound Block Mover Inbound Sequence Manager Inbound Data FIFO Receive ACKs 20B/16B Decoder • Standards: Intended to be compliant with ANSI standards and FCSI/FCA profile definitions Outbound Sequence Manager Outbound Frame FIFO ACK FIFO OS Processor CRC Checker Transmit Elastic Store/ Smoothing Buffer OS/CRC Generator Loop/N_Port State Machine 10B/20B De-MUX 16B/20B Encoder 20B/10B MUX Link Figure 1. • Packaging: 208-pin metal quad flat pack Sequence Management ACKs Specifications • System clock frequency: 20 – 40 MHz backplane operation • Testability: Full internal scan path IEEE Standard 1149.1 boundary scan FCP Assists SCSI SCSI Buffer Exchange Manager Manager Inbound Data Manager The Tachyon architecture supports both networking and mass storage connections to provide a low cost, high performance solution with low host overhead. Features • Single chip Fibre Channel interface (no I/O processor required) Pin-out Block Diagram Figure 2 below shows the pin-out block diagram for Tachyon. • Supports 1062, 531 and 266 Mbaud links TACHYON Backplane Interface • Supports 3 topologies – direct connect, fabric and Fibre Channel Arbitrated Loop (FC-AL) TAD [31..0] Gigabit Link Module Interface PAR_ID [1..0] PARITY • Supports Fibre Channel Class 1, 2 and 3 services RX [19..0] AVCS_L RBC TYPE [2..0] READY_L COM_DET PREFETCH_L L_UNUSE • Sequence segmentation/reassembly in hardware RETRY_L LCKREF_L • Automatic ACK frame generation and processing INT_L • Supports up to 2 Kbyte frame payload for all classes of service Gigabit Link Module Backplane Receive ERROR_L EWRAP RESET_L Transmit FAULT TBR_L [1..0] • On-chip support of FCP for SCSI initiators and targets TX [19..0] TBG_L SCLK • Supports up to 16384 concurrent SCSI I/O transactions Scan Test Interface • Compliant with Internet MIB-II network management TDI TDO • Direct interface to industry standard 10 and 20-bit Gigabit Link Module (GLM) TCK TRST TBC Clock Generator TXCLK_SEL TMS • Hardware assists for TCP/UDP/IP networking • Parity protection on internal data path Figure 2. • Eight internal DMA channels • Full duplex internal architecture that allows Tachyon to process inbound and outbound data simultaneously System Adapter Card Block Diagram Figure 3 below shows an example of a Tachyon on a generic host bus adapter. Backplane Interface Gigabit Link Module TACHYON CLK Figure 3. www.semiconductor.agilent.com Data subject to change. Copyright © 2001 Agilent Technologies, Inc. Obsoletes 5965-1215 April 25, 2001 5988-2605EN