HY51V(S)16163HG/HGL 1M x 16Bit EDO DRAM PRELIMINARY DESCRIPTION The HY51V(S)16163HG/HGL is the new generation dynamic RAM organized 1,048,576 words x 16bit. HY51V(S)16163HG/HGL has realized higher density, higher performance and various functions by utilizing advanced CMOS process technology. The HY51V(S)16163HG/HGL offers Extended Data Out PageMode as a high speed access mode. Multiplexed address inputs permit the HY51V(S)16163HG/HGL to be packaged in standard 400mil 42pin SOJ and 44(50) pin TSOP-II. The package size provides high system bit densities and is compatible with widely available automated testing and insertion equipment. FEATURES • • • • • • • Extended Data Out Mode capability Read-modify-write capability Multi-bit parallel test capability TTL(3.3V) compatible inputs and outputs /RAS only, CAS-before-/RAS, Hidden and self refresh(L-version) capability Fast access time and cycle time • • • • • JEDEC standard pinout 42pin plastic SOJ / 44(50)pin TSOP-II (400mil) Single power supply of 3.3V +/- 0.3V Battery back up operation(L-version) 2CAS byte control Part No tRAC tCAC tRC tHPC HY51V(S)16163HG/HGL-5 50ns 13ns 84ns 20ns HY51V(S)16163HG/HGL-6 60ns 15ns 104ns 25ns HY51V(S)16163HG/HGL-7 70ns 18ns 124ns 30ns Power dissipation Active Standby • 50ns 60ns 70ns 396mW 360mW 324mW 7.2mW(CMOS level Max) 0.83mW (L-version : Max) Refresh cycle Part No Ref Normal HY51V16163HG 4K 64ms HY51V16163HGL 4K L-part 128ms ORDERING INFORMATION Part Number Access Time Package HY51V(S)16163HGJ/HG(L)J-5 HY51V(S)16163HGJ/HG(L)J-6 HY51V(S)16163HGJ/HG(L)J-7 50ns 60ns 70ns 400mil 42pin SOJ HY51V(S)16163HGT/HG(L)T-5 HY51V(S)16163HGT/HG(L)T-6 HY51V(S)16163HGT/HG(L)T-7 50ns 60ns 70ns 400mil 44(50)pin TSOP-II (S) : Self refresh, (L) : Low power This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev.0.1/Apr.01 HY51V(S)16163HG/HGL PIN CONFIGURATION VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC VCC 1 42 VSS I/O0 I/O1 2 41 3 40 I/O15 I/O14 I/O2 I/O3 4 39 5 38 I/O13 I/O12 VCC 6 37 VSS I/O4 I/O5 7 36 8 35 I/O11 I/O10 I/O6 I/O7 9 34 10 33 NC 11 32 NC WE 12 31 13 30 LCAS UCAS RAS 14 29 OE A11 A10 A0 15 28 16 27 17 26 A9 A8 A7 18 25 19 24 20 23 21 22 A1 A2 A3 VCC I/O9 I/O8 NC A6 A5 A4 VSS 42 Pin Plastic SOJ 1 50 2 49 3 48 4 47 5 46 6 45 7 44 8 43 9 42 10 41 11 40 VSS I/O15 I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8 NC NC NC 15 36 NC 16 35 WE RAS A11 A10 A0 A1 A2 A3 VCC 17 34 LCAS UCAS OE A9 A8 A7 A6 A5 A4 VSS 18 33 19 32 20 31 21 30 22 29 23 28 24 27 25 26 44(50) Pin Plastic TSOP-II PIN DESCRIPTION Pin Function /RAS Row Address Strobe /CAS Column Address Strobe /WE Write Enable /OE Output Enable A0-A11 Address Inputs A0-A11 Refresh Address Inputs I/O 0- I/O 15 Data Input / Output Vcc Power (3.3V) Vss Ground NC No connection Rev.0.1/Apr.01 2 HY51V(S)16163HG/HGL ABSOLUTE MAXIMUM RATINGS Parameter Symbol Rating Unit Ambient Temperature TA 0 ~ 70 o C Storage Temperature TSTG -55 ~ 125 o C Voltage on Any Pin relative to Vss VT -0.5 ~ Vcc + 0.5 (Max 4.6V) V Voltage on Vcc relative to Vss Vcc -0.5 ~ 4.6 V Short Circuit Output Current IOUT 50 mA Power Dissipation PT 1 W Recommended DC OPERATING CONDITIONS (TA=0 to 70 oC) Parameter Symbol Min Typ. Max Unit Power Supply Voltage Vcc 3.0 3.3 3.6 V Input High Voltage VIH 2.0 - Vcc + 0.3 V Input Low Voltage VIL -0.3 - 0.8 V Note Note : All voltages are referenced to Vss Rev.0.1/Apr.01 3 HY51V(S)16163HG/HGL Truth Table /RAS /LCAS /UCAS /WE /OE Output Operation Notes H D D D D Open Standby 1 ,3 L L H H L Valid Lower byte L H L H L Valid Upper byte L L L H L Valid Word L L H L D Open Lower byte L H L L D Open Upper byte L L L L D Open Word L L H L H Undefined Lower byte L H L L H Undefined Upper byte L L L L H Undefined Word L L H H to L L to H Valid Lower byte L H L H to L L to H Valid Upper byte L L L H to L L to H Valid Word H to L H L D D Open Word H to L L H D D Open Word H to L L L D D Open Word L H H D D Open Word L L L H H Open Read cycle 1, 3 Early write cycle 1, 2, 3 Delayed write cycle 1, 2, 3 Read-modify-write Cycle 1, 3 CBR refresh or Self refresh (L-series) /RAS only refresh cycle Read cycle (Output disabled) 1, 3 1, 3 1, 3 Notes : 1. H : High ( inactive) L : Low ( active) D : H or L 2. t WCS >= 0ns Early write cycle twcs < 0ns Delayed write cycle 3. Mode is determined by the OR function of the /UCAS and /LCAS (mode is set by earliest of /UCAS and /LCAS active edge and reset by the latest of /UCAS and /LCAS inactive edge), However write operation and output High-Z control are done independently by each /UCAS, /LCAS ex) if /RAS = H to L, /UCAS = H, /LCAS = L, then /CAS-before-/RAS refresh cycle is selected Rev.0.1/Apr.01 4 HY51V(S)16163HG/HGL DC CHARACTERISTICS (Vcc = 3.3V +/- 10%, TA=0 to 70°C) Symbol Parameter Min Max Unit 2.4 Vcc V 0 0.4 V 50ns - 110 60ns - 100 70ns - 90 - 2 50ns - 110 60ns - 100 70ns - 90 50ns - 105 60ns - 95 70ns - 85 CMOS interface ( /RAS, /CAS >= Vcc-0.2V, Dout = High-Z) - 1 mA Standby current ( L-version) - 150 uA 50ns - 110 60ns - 100 70ns - 90 VOH Output Level Output Level voltage(Iout= -2mA) VOL Output Level Output Level voltage(Iout=2mA) ICC1 Operating current Average power supply operating current ( /RAS, /CAS Cycling : tRC = tRC min) ICC2 Standby current (TTL interface) Power supply standby current (/RAS, /CAS=VIH, Dout = High-Z) ICC3 /RAS only refresh current Average power supply current /RAS only refresh mode (tRC= tRC min) ICC4 EDO page mode current Average power supply current EDO page mode (tPC=tPC min) mA Note 1, 2 mA mA 2 mA 1, 3 ICC5 ICC6 /CAS-before-/RAS refresh current (tRC=tRC min) 5 mA ICC7 Standby current (RAS=VIH, /CAS=VIL, Dout=Enable) - 5 mA 1 ICC8 Battery back up operating current ( standby with CBR ref.) (CBR refresh, tRC=31.3us, tRAS <= 0.3us, Dout = High-Z, CMOS interface) - 400 uA 4, 5 ICC9 Self refresh current (/RAS, /CAS <=0.2V, Dout=High-Z, CMOS interface) - 250 uA 5 II(L) Input leakage current, Any input (0V<= Vin<=4.6V) -10 10 uA IO(L) Output leakage current, (Dout is disabled, 0V<= Vout<=4.6V) -10 10 uA Note : 1. Icc depends on output load condition when the device is selected, Icc(max) is specified at the output open condition 2. Address can be changed once or less while /RAS=VIL 3. Address can be changed once or less while /CAS=VIH 4. /CAS = L (<=0.2) while /RAS=L (<=0.2) 5. L-Version Rev.0.1/Apr.01 5 HY51V(S)16163HG/HGL CAPACITANCE (Vcc=3.3V +/-10%, TA=25°C) Parameter Symbol Min. Max Unit Note Input capacitance (Address) CI1 - 5 pF 1 Input capacitance (Clocks) CI2 - 7 pF 1 Output capacitance (Data-in, Data-out) CI/O - 7 pF 1, 2 Note : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. /CAS = VIH to disable Dout AC CHARACTERISTICS (Vcc=3.3V +/-10%, TA=0~70C, Note 1, 2, 18,19,20) Test Condition • • • Input rise and fall times = 2ns Input timing refrence levels : VIL=0.8V, VIH=2.0V Input timing reference level : VIL/VIH = 0.8/2.0V • Output timing reference level : VOL/VOH=0.8/0.2V Output load : 1 TTL gate + CL (100pF) ( including scope and jig ) • Read, Write, Read-modify-Write and Refresh Cycle -50 Parameter -60 -70 Symbol Unit Min Max Min Max Min Max Note Random read or write cycle time tRC 84 - 104 - 124 - ns /RAS precharge time tRP 30 - 40 - 50 - ns /CAS precharge time tCP 8 - 10 - 13 - ns /RAS pulse width tRAS 50 10,000 60 10,000 70 10,000 ns /CAS pulse width tCAS 8 10,000 10 10,000 13 10,000 ns Row address set-up time tASR 0 - 0 - 0 - ns Row address hold time tRAH 8 - 10 - 10 - ns Column address set-up time tASC 0 - 0 - 0 - ns 21 Column address hold time tCAH 8 - 10 - 13 - ns 21 /RAS to /CAS delay time tRCD 12 37 14 45 14 52 ns 3 /RAS to Column address delay time tRAD 10 25 12 30 12 35 ns 4 /RAS hold time tRSH 10 - 13 - 13 - ns /CAS hold time tCSH 35 - 40 - 45 - ns 23 /CAS to /RAS precharge time tCRP 5 - 5 - 5 - ns 22 Rev.0.1/Apr.01 6 HY51V(S)16163HG/HGL - continued -50 Parameter -60 -70 Symbol Min Max Min Max Min Max Unit Note /OE to Din delay time tOED 13 - 15 - 18 - ns 5 /OE delay time from Din tDZO 0 - 0 - 0 - ns 6 /CAS delay time from Din tDZC 0 - 0 - 0 - ns 6 Transition time ( Rise and Fall) tT 2 50 2 50 2 50 ns 7 - 64 - 64 - 64 ms 4K Ref. - 128 - 128 - 128 ms 4K Ref. Unit Note Refresh period tREF Refresh period (L-version) Read Cycle -50 Parameter -60 -70 Symbol Min Max Min Max Min Max Access time from /RAS tRAC - 50 - 60 - 70 ns 8,9 Access time from /CAS tCAC - 13 - 15 - 18 ns 9,10, 17 Access time from column address tAA - 25 - 30 - 35 ns 9,11, 17 Access time from /OE tOEA - 13 - 15 - 18 ns 9 Read command set-up time tRCS 0 - 0 - 0 - ns 21 Read command hold time to /CAS tRCH 0 - 0 - 0 - ns 12,22 Read command hold time to /RAS tRRH 5 - 5 - 5 - ns 12 Column address to /RAS lead time tRAL 25 - 30 - 35 - ns Column address to /CAS lead time tCAL 15 - 18 - 23 - ns /CAS to output in low-Z tCLZ 0 - 0 - 0 - ns Output data hold time tOH 3 - 3 - 3 - ns Output data hold time from /OE tOHO 3 - 3 - 3 - ns Output buffer turn off time tOFF - 13 - 15 - 15 ns 13,27 Output buffer turn off time to /OE tOEZ - 13 - 15 - 15 ns 13 /CAS to Din delay time tCDD 13 - 15 - 18 - ns 5 Read command hold time from /RAS tRCHR 50 - 60 - 70 - ns Output data hold time from /RAS tOHR 3 - 3 - 3 - ns 27 Output buffer turn-off time to /RAS tOFR - 13 - 15 - 15 ns 27 Output buffer turn off time to /WE tWEZ - 13 - 15 - 15 ns /WE to DIN delay time tWDD 13 - 15 - 18 - ns /RAS to DIN delay time tRDD 13 - 15 - 18 - ns Rev.0.1/Apr.01 27 7 HY51V(S)16163HG/HGL Write Cycle -50 Parameter -60 -70 Symbol Min Max Min Max Min Max Unit Note Write command set-up time tWCS 0 - 0 - 0 - ns 14,21 Write command hold time tWCH 8 - 10 - 13 - ns 21 Write command pulse width tWP 8 - 10 - 10 - ns Write command to /RAS lead time tRWL 8 - 10 - 13 - ns Write command to /CAS lead time tCWL 8 - 10 - 13 - ns Data-in set-up time tDS 0 - 0 - 0 - ns 15,23 Data-in hold time tDH 8 - 10 - 13 - ns 15,23 Unit Note Read-Modify-Write Cycle -50 Parameter -60 -70 Symbol Min Max Min Max Min Max Read-modify-write cycle time tRWC 111 - 136 - 161 - ns /RAS to /WE delay time tRWD 67 - 79 - 92 - ns 14 /CAS to /WE delay time tCWD 30 - 34 - 40 - ns 14 Column address to /WE delay time tAWD 42 - 49 - 57 - ns 14 /OE hold time from /WE tOEH 13 - 15 - 18 - ns Refresh cycle -50 Parameter -60 -70 Symbol Min Max Min Max Min Max Unit Note /CAS set-up time ( /CAS-before-/RAS Refresh Cycle) tCSR 5 - 5 - 5 - ns 21 /CAS hold time ( /CAS-before-/RAS Refresh Cycle) tCHR 8 - 10 - 10 - ns 22 /WE setup time ( /CAS-before-/RAS Refresh Cycle) tWRP 0 - 0 - 0 - ns /WE hold time ( /CAS-before-/RAS Refresh Cycle) tWRH 10 - 10 - 10 - ns /RAS precharge to /CAS hold time ( /CAS-before-/RAS Refresh Cycle) tRPC 5 - 5 - 5 - ns Rev.0.1/Apr.01 21 8 HY51V(S)16163HG/HGL EDO Page Mode Cycle -50 Parameter -60 -70 Symbol Min Max Min Max Min Max Unit Note EDO mode cyle time tHPC 20 - 25 - 30 - ns 25 EDO mode /RAS pulse width tRASP - 100K - 100K - 100K ns 16 Access time from /CAS precharge tACP - 30 - 35 - 40 ns 9,17,22 /RAS hold time from /CAS precharge tRHCP 30 - 35 - 40 - ns Output data hold time from /CAS low tDOH 3 - 3 - 3 - ns /CAS hold time referred /OE tCOL 8 - 10 - 13 - ns /CAS to /OE setup time tCOP 5 - 5 - 5 - ns Read command hold time from /CAS precharge tRHCP 30 - 35 - 40 - ns 9 EDO Page Mode Read-Modify-Write Cycle -50 Parameter -60 -70 Symbol Unit Min Max Min Max Min Max Note EDO Page read-modify-write cycle time tHPRWC 57 - 68 - 79 - ns EDO Page mode read-modify-write cycle /CAS precharge to /WE delay time tCPW 45 - 54 - 62 - ns 14,22 Unit Note 29 Self Refresh Mode(L-version) -50 Parameter -60 -70 Symbol Min Max Min Max Min Max /RAS pulse width (self refresh) tRASS 100 - 100 - 100 - us /RAS precharge time(self refresh) tRPS 90 - 110 - 130 - ns /CAS hold time(self refresh) tCHS -50 - -50 - -50 - ns Rev.0.1/Apr.01 9 HY51V(S)16163HG/HGL Notes : 1. AC measurements assume t T = 2ns 2. AC initial pause of 200us is required after power up followed by a minimum of eight initialization cycles ( any combination of cycles containing /RAS-only refresh or /CAS-before-/RAS refresh) If the internal refresh counter is used, a minimum of eight /CAS-before-/RAS refresh cycle are required. 3. Operation with the tRCD(max) limit insures that tRAC(max) can be met, t RCD(max) is specified as a reference point only : if tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC. 4. Operation with the tRAD(max) limit insures that tRAC(max) can be met, tRAD(max) is specified as a reference point only : if tRAD is greater than the specified tRAD(max) limit, then access time is controlled exclusively by tAA. 5. Either tODD or tCDD must be satisfied. 6. Either tDZO or tDZC must be satisfied. 7. VIH(min) and VIL(max) are reference levels for measuring timing of input signals, also transition times are measured between V IH(min) and VIL(max) 8. Assumes that tRCD<=tRCD(max) and tRAD<=tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown 9. Measured with a load circuit equivalent to 1 TTL loads and 100pF.( VOH=2.0V, VOL=0.8V) 10. Assumes that tRCD>=tRCD(max) and tRCD + tCAC(max) >= tRAD + tAA(max) 11. Assumes that tRAD>=tRAD(max) and tRCD + tCAC(max) <= tRAD + tAA(max) 12. Either tRCH of tRRH must be satified for a read cycles 13. tOFF(max), tOEZ(max), tOFR(max) and tWEZ(max) define the time at which the outputs achieve the open circuit condition and is not referenced to output voltage levels 14. tWCS, tRWD, tCWD, tAWD and tCPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only : If tWCS >=tWCS(min), the cycle is an early write cycle and the data out pin will remain open circuit(high impedance) throughout the entire cycle : If tRWD>=tRWD(min), tCWD>=tCWD(min), tAWD>=tAWD(min), the cycle is a read-modify-write and the data output will contain data read from the selected cell : if neither of the above sets of conditions is satified, the condition of the data out (at access time) is indeterminate. 15. These parameters are referenced to /CAS leading edge in early write cycles and to /WE leading edge in delayed write or read-modify-write cycles 16. tRASP defines /RAS pulse width in EDO page mode cycles Rev.0.1/Apr.01 10 HY51V(S)16163HG/HGL 17. Access time is determined by the longest among tAA or tCAC or tACP 18. In delayed write or read-modify-write cycels, OE must disable output buffer prior to applying data to the device, After /RAS is reset, if tOEH>=tCWL, the I/O pin will remain open circuit (high impedance) If tOEH < tCWL, invalid data will be out at each I/O 19. When both /UCAS and /LCAS go low at the same time, all 16 bit data are written into the device /UCAS and /LCAS cannot be staggered within the same write / read cycles. 20. All the Vcc and Vss pins shall be supplied with the same voltages 21. tASC, tCAH, tRCS, tWCS, tWCH, tCSR and tRPC are determined by the earlier falling edge of /UCAS or /LCAS. 22. tCRP, tCHR, tRCH, tACP and tCPW are determined by the later rising edge of /UCAS or /LCAS. 23. tCWL, tDH, tDS and tCSH should be satisfied by both /UCAS and /LCAS 24. tCP is determined by that time the both /UCAS and /LCAS are high. 25. When output buffers are enabled once, sustain the low impedance state until valid data is obtained When output buffer is turned on and off within a very short time, generally it causes large Vcc/Vss line noise, which causes to degrade V IH min / VIL max level 26. Please do not use tRASS timing, 10us <= tRASS <= 100us. During this period, the device is in transition state from normal operation mode to self refresh mode. If tRASS >= 100us, then /RAS precharge time should use tRPS instead of tRP 27.If you use distributed CBR refresh within 15.6us interval in normal read/write cycle, CBR refresh should be executed within 15.6us immediately after exiting from and before entering into self refresh mode 28. If you use /RAS only refresh or CBR burst refresh mode in normal read/write cycle, 4096 or 1024cycles of distributed CBR refresh with 15.6us interval should be executed within 64 or 16ms immediately after exiting from and before entering into the self refresh mode 29. Repetitive self refresh mode without refreshing all memory is not allowed, Once you exit from self refresh mode, all memory cells need to be refreshed before re-entering the self refresh mode again. 30. H or L ( H : VIH(min) <=VIN <= VIH(max), L : VIL(min) <= VIN <= VIL(max)) Rev.0.1/Apr.01 11 HY51V(S)16163HG/HGL PACKAGE INFORMATION 42pin SOJ Unit: Inches (mm) 0.025(0.64) 0.360(9.15) MIN 0.380(9.65) MAX 0.435(11.06) MIN 0.445(11.30) MAX 0.395(10.03) MIN 0.405(10.29) MAX MIN 0.093(2.38) 1.058(26.89) MAX MIN 1.072(27.23) MAX 0.128(3.25) MIN 0.148(3.75) MAX 0.050(1.27) 0.026(0.66) MIN 0.032(0.81) MAX TYP 0.015(0.38) MIN 0.020(0.50) MAX 44(50)pin TSOP II 0.016(0.40) MIN 0.024(0.60) MAX 0.471(11.96) MAX 0.455(11.56) MIN 0.394(10.03) MIN 0.405(10.29) MAX 0 ~ 5 Deg 0.004(0.12) MIN 0.008(0.21) MAX 0.820(20.82) MIN 0.830(21.08) MAX 0.037(0.95) MIN 0.041(1.05) MAX 0.047(1.20) MAX 0.012(0.30) MIN 0.017(0.45) MAX Rev.0.1/Apr.01 0.031(0.80) TYP 0.002(0.05) MIN 0.006(0.15) MAX 12