HY51V(S)17400HG/HGL 4M x 4Bit Fast Page DRAM PRELIMINARY DESCRIPTION The HY51V(S)17400HG/HGL is the new generation dynamic RAM organized 4,194,304 words x 4bit. HY51V(S)17400HG/HGL has realized higher density, higher performance and various functions by utilizing advanced CMOS process technology. The HY51V(S)17400HG/HGL offers Fast Page Mode as a high speed access mode. Multiplexed address inputs permit the HY51V(S)17400HG/HGL to be packaged in standard 300mil 24(26)pin SOJ and 24(26) pin TSOP-II. The package size provides high system bit densities and is compatible with widely available automated testing and insertion equipment. System oriented features include single power supply 3.3V +/- 0.3V tolerance, direct interfacing capability with high performance logic families such as Schottky TTL. FEATURES • • • • • • • Fast Page Mode capability Read-modify-write capability Multi-bit parallel test capability TTL(3.3V) compatible inputs and outputs /RAS only, CAS-before-/RAS, Hidden and self refresh(L-version) capability Fast access time and cycle time • • • • JEDEC standard pinout 24(26)pin plastic SOJ/TSOP-II(300mil) Single power supply of 3.3V +/- 0.3V Battery back up operation(L-version) Part No tRAC tCAC tRC tPC HY51V(S)17400HG/HGL-5 50ns 13ns 90ns 35ns HY51V(S)17400HG/HGL-6 60ns 15ns 110ns 40ns HY51V(S)17400HG/HGL-7 70ns 18ns 130ns 45ns Power dissipation Active Standby • 50ns 60ns 70ns 432mW 396mW 360mW 7.2mW(CMOS level Max) 0.36mW (L-version : Max) Refresh cycle Part No Ref Normal HY51V17400HG 2K 32ms HY51V17400HGL 2K L-part 128ms ORDERING INFORMATION Part Number Access Time Package HY51V(S)17400HGJ/HG(L)J-5 HY51V(S)17400HGJ/HG(L)J-6 HY51V(S)17400HGJ/HG(L)J-7 50ns 60ns 70ns 300mil 24(26)pin SOJ HY51V(S)17400HGT/HG(L)T-5 HY51V(S)17400HGT/HG(L)T-6 HY51V(S)17400HGT/HG(L)T-7 50ns 60ns 70ns 300mil 24(26)pin TSOP-II (S) : Self refresh, (L) : Low power This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev.0.1/Apr.01 HY51V(S)17400HG/HGL PIN CONFIGURATION VCC 1 26 VSS VCC 1 26 VSS I/O1 2 25 I/O4 I/O1 2 25 I/O4 I/O2 3 24 I/O3 I/O2 3 24 I/O3 WE 4 23 CAS WE 4 23 CAS RAS 5 22 OE RAS 5 22 OE A11 6 21 A9 A11 6 21 A9 A10 8 19 A8 A10 8 19 A8 A0 9 18 A7 A0 9 18 A7 A1 10 17 A6 A1 10 17 A6 A2 11 16 A5 A2 11 16 A5 A3 12 15 A4 A3 12 15 A4 VCC 13 14 VSS VCC 13 14 VSS 24(26) Pin Plastic SOJ 24(26) Pin Plastic TSOP-II PIN DESCRIPTION Pin Function /RAS Row Address Strobe /CAS Column Address Strobe /WE Write Enable /OE Output Enable A0-A10 Address Inputs A0-A10 Refresh Address Inputs I/O 1- I/O 4 Data Input / Output Vcc Power (3.3V) Vss Ground NC No connection Rev.0.1/Apr.01 2 HY51V(S)17400HG/HGL ABSOLUTE MAXIMUM RATINGS Parameter Symbol Rating Unit Ambient Temperature TA 0 ~ 70 o C Storage Temperature TSTG -55 ~ 125 o C Voltage on Any Pin relative to Vss VT -0.5 ~ Vcc + 0.5 (Max 4.6V) V Voltage on Vcc relative to Vss Vcc -0.5 ~ 4.6 V Short Circuit Output Current IOUT 50 mA Power Dissipation PT 1 W Recommended DC OPERATING CONDITIONS (TA=0 to 70 oC) Parameter Symbol Min Typ. Max Unit Power Supply Voltage Vcc 3.0 3.3 3.6 V Input High Voltage VIH 2.0 - Vcc + 0.3 V Input Low Voltage VIL -0.3 - 0.8 V Note Note : All voltages are referenced to Vss Rev.0.1/Apr.01 3 HY51V(S)17400HG/HGL DC CHARACTERISTICS (Vcc = 3.3V +/- 10%, TA=0 to 70°C) Symbol Parameter Min Max Unit 2.4 Vcc V 0 0.4 V 50ns - 100 60ns - 90 70ns - 80 - 2 50ns - 100 60ns - 90 70ns - 80 50ns - 90 60ns - 80 70ns - 70 CMOS interface ( /RAS, /CAS >= Vcc-0.2V, Dout = High-Z) - 1 mA Standby current ( L-version) - 100 uA 50ns - 100 60ns - 90 70ns - 80 VOH Output Level Output Level voltage(Iout= -2mA) VOL Output Level Output Level voltage(Iout=2mA) ICC1 Operating current Average power supply operating current ( /RAS, /CAS Cycling : tRC = tRC min) ICC2 Standby current (TTL interface) Power supply standby current (/RAS, /CAS=VIH, Dout = High-Z) ICC3 /RAS only refresh current Average power supply current /RAS only refresh mode (tRC= tRC min) ICC4 Fast page mode current Average power supply current Fast page mode (tPC=tPC min) mA Note 1, 2 mA mA 2 mA 1, 3 ICC5 ICC6 /CAS-before-/RAS refresh current (tRC=tRC min) 4 mA ICC7 Battery back up operating current (standby with CBR refresh) (CBR refresh, tRC=31.3us, tRAS<=0.3us, Dout=High-Z, CMOS interface) - 300 uA 4 ICC8 Standby current ( /RAS = VIH, /CAS = VIL, Dout=Enable) - 5 uA 1 ICC9 Self refresh current (/RAS, /CAS <=0.2V, Dout=High-Z, CMOS interface) - 200 uA 4 II(L) Input leakage current, Any input (0V<= Vin<=4.6) -10 10 uA IO(L) Output leakage current, (Dout is disabled, 0V<= Vout<=4.6) -10 10 uA Note : 1. Icc depends on output load condition when the device is selected, Icc(max) is specified at the output open condition 2. Address can be changed once or less while /RAS=VIL 3. Address can be changed once or less while /CAS=VIH 4. L-Version Rev.0.1/Apr.01 4 HY51V(S)17400HG/HGL CAPACITANCE (Vcc=3.3V +/-10%, TA=25°C) Parameter Symbol Min. Max Unit Note Input capacitance (Address) CI1 - 5 pF 1 Input capacitance (Clocks) CI2 - 5 pF 1 Output capacitance (Data-in, Data-out) CI/O - 7 pF 1, 2 Note : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. /RAS, /UCAS and /LCAS = VIH to disable Dout AC CHARACTERISTICS (Vcc=3.3V +/-10%, TA=0~70C, Note 1, 2, 18, 19) Test Condition • • • Input rise and fall times = 5ns Input timing reference level : VIL/VIH = 0.8/2.0V Output timing reference level : VOL/VOH=0.8/0.2V Output load : 1 TTL gate + CL (100pF) ( including scope and jig ) • Read, Write, Read-modify-Write and Refresh Cycle -50 Parameter -60 -70 Symbol Unit Min Max Min Max Min Max Note Random read or write cycle time tRC 90 - 110 - 130 - ns /RAS precharge time tRP 30 - 40 - 50 - ns /CAS precharge time tCP 8 - 10 - 10 - ns /RAS pulse width tRAS 50 10,000 60 10,000 70 10,000 ns /CAS pulse width tCAS 13 10,000 15 10,000 18 10,000 ns Row address set-up time tASR 0 - 0 - 0 - ns Row address hold time tRAH 8 - 10 - 10 - ns Column address set-up time tASC 0 - 0 - 0 - ns Column address hold time tCAH 8 - 10 - 15 - ns /RAS to /CAS delay time tRCD 18 45 20 45 20 52 ns 3 /RAS to Column address delay time tRAD 13 30 15 30 15 35 ns 4 /RAS hold time tRSH 13 - 15 - 18 - ns /CAS hold time tCSH 50 - 60 - 70 - ns /CAS to /RAS precharge time tCRP 5 - 5 - 5 - ns Rev.0.1/Apr.01 5 HY51V(S)17400HG/HGL - continued -50 Parameter -60 -70 Symbol Min Max Min Max Min Max Unit Note /OE to Din delay time tODD 13 - 15 - 18 - ns 5 /OE delay time from Din tDZO 0 - 0 - 0 - ns 6 /CAS delay time from Din tDZC 0 - 0 - 0 - ns 6 Transition time ( Rise and Fall) tT 3 50 3 50 3 50 ns 7 - 32 - 32 - 32 ms 2K Ref. - 128 - 128 - 128 ms 2K Ref. Unit Note Refresh period tREF Refresh period (L-version) Read Cycle -50 Parameter -60 -70 Symbol Min Max Min Max Min Max Access time from /RAS tRAC - 50 - 60 - 70 ns 8,9,19 Access time from /CAS tCAC - 13 - 15 - 18 ns 9,10, 17,19 Access time from column address tAA - 25 - 30 - 35 ns 9,11, 17,19 Access time from /OE tOAC - 13 - 15 - 18 ns 9 Read command set-up time tRCS 0 - 0 - 0 - ns Read command hold time to /CAS tRCH 0 - 0 - 0 - ns 12 Read command hold time to /RAS tRRH 5 - 5 - 5 - ns 12 Column address to /RAS lead time tRAL 25 - 30 - 35 - ns Column address to /CAS lead time tCAL 25 - 30 - 35 - ns /CAS to output in low-Z tCLZ 0 - 0 - 0 - ns Output data hold time tOH 3 - 3 - 3 - ns Output data hold time from /OE tOHO 3 - 3 - 3 - ns Output buffer turn off time to /OE tOEZ - 13 - 15 - 15 ns 13 Output buffer turn off time tOFF - 13 - 15 - 15 ns 13 /CAS to Din delay time tCDD 13 - 15 - 18 - ns 5 Rev.0.1/Apr.01 6 HY51V(S)17400HG/HGL Write Cycle -50 Parameter -60 -70 Symbol Min Max Min Max Min Max Unit Note 14 Write command set-up time tWCS 0 - 0 - 0 - ns Write command hold time tWCH 8 - 10 - 15 - ns Write command pulse width tWP 8 - 10 - 15 - ns Write command to /RAS lead time tRWL 13 - 15 - 18 - ns Write command to /CAS lead time tCWL 13 - 15 - 18 - ns Data-in set-up time tDS 0 - 0 - 0 - ns 15 Data-in hold time tDH 8 - 10 - 15 - ns 15 Unit Note Read-Modify-Write Cycle -50 Parameter -60 -70 Symbol Min Max Min Max Min Max Read-modify-write cycle time tRWC 131 - 155 - 181 - ns /RAS to /WE delay time tRWD 73 - 85 - 98 - ns 14 /CAS to /WE delay time tCWD 36 - 40 - 46 - ns 14 Column address to /WE delay time tAWD 48 - 55 - 63 - ns 14 /OE hold time from /WE tOEH 13 - 15 - 18 - ns Refresh cycle -50 Parameter -60 -70 Symbol Unit Min Max Min Max Min Max /CAS set-up time ( /CAS-before-/RAS Refresh Cycle) tCSR 5 - 5 - 5 - ns /CAS hold time ( /CAS-before-/RAS Refresh Cycle) tCHR 8 - 10 - 10 - ns /WE set-up time ( /CAS-before-/RAS Refresh Cycle) tWRP 0 - 0 - 0 - ns /WE hold time ( /CAS-before-/RAS Refresh Cycle) tWRH 8 - 10 - 10 - ns /RAS precharge to /CAS hold time ( /CAS-before-/RAS Refresh Cycle) tRPC 5 - 5 - 5 - ns Rev.0.1/Apr.01 Note 7 HY51V(S)17400HG/HGL Fast Page Mode Cycle -50 Parameter -60 -70 Symbol Unit Min Max Min Max Min Max Note Fast page mode cyle time tPC 35 - 40 - 45 - ns Fast page mode /RAS pulse width tRASP - 100K - 100K - 100K ns 17 Access time from /CAS precharge tACP - 30 - 35 - 40 ns 10,18, ,19 /RAS hold time from /CAS precharge tRHCP 30 - 35 - 40 - ns Fast Page Mode Read-Modify-Write Cycle -50 Parameter -60 -70 Symbol Unit Min Max Min Max Min Max Note Fast Page read-modify-write cycle time tPRWC 76 - 85 - 96 - ns Fast page mode read-modify-write cycle /CAS precharge to /WE delay time tCPW 53 - 60 - 68 - ns 15 Unit Note Test Mode Cycle -50 Parameter -60 -70 Symbol Min Max Min Max Min Max Test mode /WE setup time tWTS 0 - 0 - 0 - ns Test mode /WE hold time tWTH 10 - 10 - 10 - ns Self Refresh Cycle (L-Version) -50 Parameter -60 -70 Symbol Unit Min Max Min Max Min Max /RAS pulse width ( self refresh) tRASS 100 - 100 - 100 - us /RAS precharge time ( self refresh) tRPS 90 - 110 - 130 - ns /CAS hold time ( self refresh) tCHS -50 - -50 - -50 - ns Rev.0.1/Apr.01 Note 8 HY51V(S)17400HG/HGL Notes : 1. AC measurements assume t T = 5ns 2. AC initial pause of 200us is required after power up followed by a minimum of eight initialization cycles ( any combination of cycles containing /RAS-only refresh or /CAS-before-/RAS refresh) 3. Operation with the tRCD(max) limit insures that tRAC(max) can be met, t RCD(max) is specified as a reference point only : if tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC. 4. Operation with the tRAD(max) limit insures that tRAC(max) can be met, tRAD(max) is specified as a reference point only : if tRAD is greater than the specified tRAD(max) limit, then access time is controlled exclusively by tAA. 5. Either tODD or tCDD must be satisfied. 6. Either tDZO or tDZC must be satisfied. 7. VIH(min) and VIL(max) are reference levels for measuring timing of input signals, also transition times are measured between V IH(min) and VIL(max) 8. Assumes that tRCD<=tRCD(max) and tRAD<=tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown 9. Measured with a load circuit equivalent to 1 TTL loads and 100pF.( VOH=2.0V, VOL=0.8V) 10. Assumes that tRCD>=tRCD(max) and tRCD + tCAC(max) >= tRAD + tAA(max) 11. Assumes that tRAD>=tRAD(max) and tRCD + tCAC(max) <= tRAD + tAA(max) 12. Either tRCH of tRRH must be satified for a read cycles 13. tOFF(max), tOEZ(max), tOFR(max) and tWEZ(max) define the time at which the outputs achieve the open circuit condition and is not referenced to output voltage levels 14. tWCS, tRWD, tCWD, tAWD and tCPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only : If tWCS >=tWCS(min), the cycle is an early write cycle and the data out pin will remain open circuit(high impedance) throughout the entire cycle : If tRWD>=tRWD(min), tCWD>=tCWD(min), tAWD>=tAWD(min), the cycle is a read-modify-write and the data output will contain data read from the selected cell : if neither of the above sets of conditions is satified, the condition of the data out (at access time) is indeterminate. 15. These parameters are referenced to /CAS leading edge in early write cycles and to /WE leading edge in delayed write or read-modify-write cycles 16. tRASP defines /RAS pulse width in Fast page mode cycles Rev.0.1/Apr.01 9 HY51V(S)17400HG/HGL 17. Access time is determined by the longest among tAA or tCAC or tACP 18. In delayed write or read-modify-write cycels, OE must disable output buffer prior to applying data to the device, After /RAS is reset, if tOEH>=tCWL, the I/O pin will remain open circuit (high impedance) If tOEH < tCWL, invalid data will be out at each I/O 19. In a test mode read cycle, the value of tRAC, tAA, tCAC is delayed by 2ns to 5ns for the specified value. These parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet Rev.0.1/Apr.01 10 HY51V(S)17400HG/HGL PACKAGE INFORMATION 24(26)pin SOJ Unit: Inches (mm) 0.025(0.64) 0.275(6.99) MAX 0.260(6.60) MIN 0.329(8.38) MIN 0.340(8.64) MAX 0.305(7.75) MAX 0.295(7.49) MIN MIN 0.085(2.16) 0.661(16.80) MIN 0.669(17.00) MAX MIN 0.128(3.25) MIN 0.147(3.75) MAX 0.026(0.66) MIN 0.032(0.81) MAX 0.050(1.27) TYP 0.015(0.38) MIN 0.020(0.50) MAX 24(26)pin TSOP-II 0.016(0.40) MIN 0.024(0.60) MAX 0.371(9.42) MAX 0.355(9.02) MIN 0.303(7.72) MAX 0.296(7.52) MIN 0 ~ 5 Deg 0.670(17.04) MIN 0.678(17.24) MAX 0.004(0.12) MIN 0.008(0.21) MAX 0.037(0.95) MIN 0.041(1.05) MAX 0.047(1.20) MAX 0.012(0.30) MIN 0.020(0.50) MAX Rev.0.1/Apr.01 0.050(1.27) TYP 0.003(0.08) MIN 0.007(0.18) MAX 11