HYS 64Vx20(2)0GCDL 144-pin SO-DIMM SDRAM Modules 3.3 V SDRAM Modules 144-pin SO-DIMM SDRAM Modules PC100/PC133 32 MB, 64 MB & 128 MB Density in COB Technique • 144-pin Eight Byte Small Outline Dual-In-Line Synchronous DRAM Modules for notebook applications • Auto Refresh (CBR) and Self Refresh • One bank 4M × 64 non-parity organization • All inputs and outputs are LVTTL compatible • Decoupling capacitors mounted on substrate • Serial Presence Detect with E2PROM • Two bank 8M × 64 and 16M × 64 non-parity module organization • Uses COB (“Chip-on-Board”) technique • 4096 refresh cycles every 64 ms • suitable for use in PC100 and PC133 applications • Gold contact pad • Auto ReSingle + 3.3 V (± 0.3 V) power supply • This module family is fully pin and functional compatible with the latest INTEL SO-DIMM specification • Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave) • Performance: -7.5 -8 PC133 3-3-3 PC100 2-2-2 Unit fCK Clock Frequency (max.) 133 100 MHz tAC Clock Access Time CAS Latency = 2 & 3 5.4 6 ns This Infineon module family are industry standard 144-pin 8-byte Synchronous DRAM (SDRAM) Small Outline Dual In-line Memory Modules (SO-DIMM) which are organized as x64 high speed memory arrays designed for use in non-parity applications. These SO-DIMMs use COB (“Chip-onBoard”) technology. Decoupling capacitors are mounted on the board. The DIMMs use optional serial presence detects implemented via a serial E 2PROM using the 2-pin I2C protocol. The first 128 bytes are utilized by the DIMM manufacturer and the second 128 bytes are available to the end user. All Infineon 144-pin SO-DIMMs provide a high performance, flexible 8-byte interface in a 67.5 mm long footprint. Data Book 1 Powered by ICminer.com Electronic-Library Service CopyRight 2003 12.99 HYS 64Vx20(2)0GCDL 144-pin SO-DIMM SDRAM Modules Product Sprectrum Organization Partnumber SDRAMs Row Bank Used Addr. Select 4M × 64 HYS64V4220GCDL-7.5 4 4M × 16 12 BA0, BA1 8 4k 64 ms 8M × 64 HYS64V8220GCDL-7.5 8 4M × 16 12 BA0, BA1 8 4k 64 ms 16M × 64 HYS64V16220GCDL-7.5 16 8M × 8 12 BA0, BA1 9 4k 64 ms 4M × 64 HYS64V4220GCDL-8 4 4M × 16 12 BA0, BA1 8 4k 64 ms 8M × 64 HYS64V8220GCDL-8 8 4M × 16 12 BA0, BA1 8 4k 64 ms 16 8M × 8 12 BA0, BA1 9 4k 64 ms 16M × 64 HYS64V16220GCDL-8 Column Refresh Period Addr. Note: All partnumbers end with a place code (not shown), designating the die revision. Consult factory for current revision. Example: HYS 64V16220GCDL-8-B, indicating Rev.B dies are used for SDRAM components. Card Dimensions Organization PCB-Board L × H × T [mm] 4M × 64 L-DIM-144-C8 67.60 × 25.40 × 3.80 8M × 64 L-DIM-144-C8 67.60 × 25.40 × 3.80 16M × 64 L-DIM-144-C9 67.60 × 25.40 × 3.80 Pin Definitions and Functions A0 - A11 Address Inputs DQMB0 DQMB7 Data Mask BA0, BA1 Bank Selects CS0 - CS3 Chip Select DQ0 - DQ63 Data Input/Output VDD Power (+ 3.3 V) RAS Row Address Strobe VSS Ground CAS Column Address Strobe SCL Clock for Presence Detect WE Read/Write Input SDA Serial Data Out for Presence Detect CKE0 Clock Enable N.C. No Connection CLK0 Clock Input – – Data Book 2 Powered by ICminer.com Electronic-Library Service CopyRight 2003 12.99 HYS 64Vx20(2)0GCDL 144-pin SO-DIMM SDRAM Modules Pin Configuration PIN# Front Side PIN# Back Side PIN# Front Side PIN# Back Side 1 VSS 2 VSS 73 N.C. 74 CLK1 3 DQ0 4 DQ32 75 VSS 76 VSS 5 DQ1 6 DQ33 77 N.C. 78 N.C. 7 DQ2 8 DQ34 79 N.C. 80 N.C. 9 DQ3 10 DQ35 81 VDD 82 VDD 11 VDD 12 VDD 83 DQ16 84 DQ48 13 DQ4 14 DQ36 85 DQ17 86 DQ49 15 DQ5 16 DQ37 87 DQ18 88 DQ50 17 DQ6 18 DQ38 89 DQ19 90 DQ51 19 DQ7 20 DQ39 91 VSS 92 VSS 21 VSS 22 VSS 93 DQ20 94 DQ52 23 DQMB0 24 DQMB4 95 DQ21 96 DQ53 25 DQMB1 26 DQMB5 97 DQ22 98 DQ54 27 VDD 28 VDD 99 DQ23 100 DQ55 29 A0 30 A3 101 VDD 102 VDD 31 A1 32 A4 103 A6 104 A7 33 A2 34 A5 105 A8 106 BA0 35 VSS 36 VSS 107 VSS 108 VSS 37 DQ8 38 DQ40 109 A9 110 BA1 39 DQ9 40 DQ41 111 A10 112 A11 41 DQ10 42 DQ42 113 VDD 114 VDD 43 DQ11 44 DQ43 115 DQMB2 116 DQMB6 45 VDD 46 VDD 117 DQMB3 118 DQMB7 47 DQ12 48 DQ44 119 VSS 120 VSS 49 DQ13 50 DQ45 121 DQ24 122 DQ56 51 DQ14 52 DQ46 123 DQ25 124 DQ57 53 DQ15 54 DQ47 125 DQ26 126 DQ58 55 VSS 56 VSS 127 DQ27 128 DQ59 57 N.C. 58 N.C. 129 VDD 130 VDD 59 N.C. 60 N.C. 131 DQ28 132 DQ60 61 CLK0 62 CKE0 133 DQ29 134 DQ61 63 VDD 64 VDD 135 DQ30 136 DQ62 65 RAS 66 CAS 137 DQ31 138 DQ63 Data Book 3 Powered by ICminer.com Electronic-Library Service CopyRight 2003 12.99 HYS 64Vx20(2)0GCDL 144-pin SO-DIMM SDRAM Modules Pin Configuration (cont’d) PIN# Front Side PIN# Back Side PIN# Front Side PIN# Back Side 67 WE 68 CKE1 139 VSS 140 VSS 69 CS0 70 (A12) 141 SDA 142 SCL 71 CS1 72 (A13) 143 VDD 144 VDD WE CS0 CS WE LDQM DQ0-DQ7 DQMB0 DQ0-DQ7 DQMB1 DQ8-DQ15 DQMB4 DQ32-DQ39 DQMB5 DQ40-DQ47 UDQM DQ8-DQ15 D0 CS WE LDQM DQ0-DQ7 DQMB2 DQ16-DQ23 DQMB3 DQ24-DQ31 DQMB6 DQ48-DQ55 DQMB7 DQ56-DQ63 UDQM DQ8-DQ15 D1 A0-A11, BA0, BA1 VCC CS WE LDQM DQ0-DQ7 UDQM DQ8-DQ15 D2 CS WE LDQM DQ0-DQ7 UDQM DQ8-DQ15 D3 D0-D3 E2PROM (256 word x 8 Bit) D0-D3 C 1-C 4 VSS D0-D3 RAS D0-D3 CAS D0-D3 CKE0 D0-D3 CLK0 4 SDRAM SA0 SA1 SA2 SCL SDA Note: All resistors are 10 Ω CLK1 10 pF SPB04133 Block Diagram: One Bank 4M × 64 SDRAM DIMM Module Data Book 4 Powered by ICminer.com Electronic-Library Service CopyRight 2003 12.99 HYS 64Vx20(2)0GCDL 144-pin SO-DIMM SDRAM Modules WE CS0 CS1 CS WE LDQM DQ0-DQ7 DQMB0 DQ0-DQ7 DQMB1 DQ8-DQ15 CS WE LDQM DQ0-DQ7 DQMB4 DQ32-DQ39 DQMB5 DQ40-DQ47 UDQM UDQM DQ8-DQ15 DQ8-DQ15 D0 D4 CS WE LDQM DQ0-DQ7 DQMB2 DQ16-DQ23 DQMB3 DQ24-DQ31 CS WE LDQM DQ0-DQ7 DQMB6 DQ48-DQ55 DQMB7 DQ56-DQ63 UDQM UDQM DQ8-DQ15 DQ8-DQ15 D1 D5 A0-A11, BA0, BA1 VCC CS WE LDQM DQ0-DQ7 CS WE LDQM DQ0-DQ7 UDQM UDQM DQ8-DQ15 DQ8-DQ15 D2 D6 CS WE LDQM DQ0-DQ7 CS WE LDQM DQ0-DQ7 UDQM UDQM DQ8-DQ15 DQ8-DQ15 D3 D7 D0-D7 E2PROM (256 word x 8 Bit) D0-D7 C 1-C 4 VSS D0-D7 RAS D0-D7 CAS D0-D7 CKE0 D0-D7 CLK0 4 SDRAM CLK1 4 SDRAM SA0 SA1 SA2 SCL SDA Note: All resistors are 10 Ω SPB04134 Block Diagram: Two Bank 8M × 64 SDRAM DIMM Module Data Book 5 Powered by ICminer.com Electronic-Library Service CopyRight 2003 12.99 HYS 64Vx20(2)0GCDL 144-pin SO-DIMM SDRAM Modules CS1 CS0 DQMB0 DQ0-DQ7 CS DQM DQ0-DQ7 CS DQM DQ0-DQ7 DQMB4 DQ32-DQ39 CS DQM DQ0-DQ7 CS DQM DQ0-DQ7 DQMB1 DQ8-DQ15 DQM DQ0-DQ7 DQM DQ0-DQ7 DQMB5 DQ40-DQ47 DQM DQ0-DQ7 DQM DQ0-DQ7 D4 D0 D6 D2 DQMB2 DQ16-DQ23 CS DQM DQ0-DQ7 CS DQM DQ0-DQ7 DQMB6 DQ48-DQ55 CS DQM DQ0-DQ7 CS DQM DQ0-DQ7 DQMB3 DQ24-DQ31 DQM DQ0-DQ7 DQM DQ0-DQ7 DQMB7 DQ56-DQ63 DQM DQ0-DQ7 DQM DQ0-DQ7 D1 A0-A11, BA0, BA1 D5 D3 D0-D7 VDD E 2 PROM (256 word x 8 Bit) D0-D7 SA0 SA1 SA2 C VSS D0-D7 RAS, CAS, WE D0-D15 CKE0 D0-D3 CKE1 D4-D7 CLK0 CLK1 4 SDRAM 4 SDRAM D7 SCL SDA Note: 1. DQ wiring may differ than describes in this drawing, however DQ/DQMB/CKE/CS relationship must be maintained as shown. 2. In this design each of the D0-D7 components are represented by two 8 M x 8 chips. These two chips effectively work as a single 8 M x 16 device. SPB04202 Block Diagram: Two Bank 16M × 64 SDRAM DIMM Module Data Book 6 Powered by ICminer.com Electronic-Library Service CopyRight 2003 12.99 HYS 64Vx20(2)0GCDL 144-pin SO-DIMM SDRAM Modules DC Characteristics TA = 0 to 70 °C; VSS = 0 V; VDD,VDDQ = 3.3 V ± 0.3 V Parameter Symbol Limit Values min. max. Unit Input High Voltage VIH 2.0 VDD + 0.3 V Input Low Voltage VIL – 0.5 0.8 V Output High Voltage (IOUT = – 4.0 mA) VOH 2.4 – V Output Low Voltage (IOUT = 4.0 mA) VOL – 0.4 V Input Leakage Current, any input (0 V < VIN < 3.6 V, all other inputs = 0 V) II(L) – 20 20 µA Output Leakage Current (DQ is disabled, 0 V < VOUT < VDD) IO(L) – 20 20 µA Capacitance TA = 0 to 70 °C; VDD = 3.3 V ± 0.3 V, f = 1 MHz Parameter Symbol Limit Values Unit 4M × 64 max. 8M × 64 max. 16M × 64 max. Input Capacitance (A0 to A11, BA0, BA1) CI1 25 50 65 pF Input Capacitance (RAS, CAS, WE) CI2 35 50 75 pF Input Capacitance (CLK0, CLK1) CI3 35 35 58 pF Input Capacitance (CS0, CS1) CI4 25 30 40 pF Input Capacitance (DQMB0 - DQMB7) CI5 10 15 15 pF Input/Output Capacitance (DQ0 - DQ63) CIO 25 25 50 pF Input Capacitance (SCL, SA0 - 2) CSC 10 15 18 pF Input/Output Capacitance CSD 8 8 8 pF Data Book 7 Powered by ICminer.com Electronic-Library Service CopyRight 2003 12.99 HYS 64Vx20(2)0GCDL 144-pin SO-DIMM SDRAM Modules Operating Currents per Memory Bank TA = 0 to 70 °C, VDD = 3.3 V ± 0.3 V 16M × 64 (Recommended Operating Conditions unless otherwise noted) Unit Note Operating current – ICC1 260 520 1024 mA 1) tCK = min. ICC2P 4 8 16 mA 1) tCK = infinity ICC2PS 2 4 8 mA 1) tCK = min. ICC2N 70 140 280 mA 1) tCK = infinity ICC2NS 10 20 mA 1) CKE ≥ VIH(MIN.) ICC3N 90 180 360 mA 1) CKE ≤ VIL(MAX.) ICC3P 16 32 mA 1) Burst operating current tCK = min., Read command cycling – ICC4 200 400 800 mA 1), 2) Auto refresh current tCK = min., Auto Refresh command cycling – ICC5 260 520 1040 mA 1) Self refresh current Self Refresh Mode, CKE = 0.2 V – ICC6 1.6 1) 8M × 64 Test Condition Symbol 4M × 64 Parameter tRC = tRC(MIN.), tCK = tCK(MIN.) Outputs open, Burst Length = 4, CL = 3 All banks operated in random access, all banks operated in ping-pong manner to maximize gapless data access Precharge stand-by current in Power Down Mode CS = VIH(MIN.), CKE ≤ VIL(MAX.) Precharge Stand-by Current in Non-Power Down Mode 40 CS = VIH (MIN.), CKE ≥ VIH(MIN.) No operating current tCK = min., CS = VIH(MIN.), 64 active state (max. 4 banks) 3.2 6.4 mA Notes 1. These parameters depend on the cycle rate. These values are measured at 100 MHz operation frequency. Input signals are changed once during tCK, excepts for ICC6 and for stand-by currents when tCK = infinity. 2. These parameters are measured with continuous data stream during read access and all DQ toggling. CL = 3 and BL = 4 are assumed and the VDDQ current is excluded. Data Book 8 Powered by ICminer.com Electronic-Library Service CopyRight 2003 12.99 HYS 64Vx20(2)0GCDL 144-pin SO-DIMM SDRAM Modules AC Characteristics 1), 2) TA = 0 to 70 °C; VSS = 0 V; VDD = 3.3 V ± 0.3 V, tT = 1 ns Parameter Symbol Limit Values -7.5 PC133-333 Unit Note -8 PC100-222 min. max. min. max. 7.5 10 – – 10 10 – – Clock and Access Time Clock Cycle Time CAS Latency = 3 CAS Latency = 2 tCK Clock Frequency CAS Latency = 3 CAS Latency = 2 fCK Access Time from Clock CAS Latency = 3 CAS Latency = 2 tAC Clock High Pulse Width – ns ns – – – 133 100 – – 100 100 MHz MHz 2), 3) – – 5.4 6 – – 6 6 ns ns tCH 2.5 – 3 – ns – Clock Low Pulse Width tCL 2.5 – 3 – ns – Transition Time tT 0.3 1.2 0.5 10 ns – Input Setup Time tIS 1.5 – 2 – ns 4) Input Hold Time tIH 0.8 – 1 – ns 4) Power Down Mode Entry Time tSB – 1 – 1 CLK 4) Power Down Mode Exit Setup Time tPDE 0.8 – 1 – CLK 4) Mode Register Set-up Time tRSC 2 – 2 – CLK – Row to Column Delay Time tRCD 20 – 20 – ns 5) Row Precharge Time tRP 20 – 20 – ns 5) Row Active Time tRAS 45 100k 50 100k ns 5) Row Cycle Time tRC 67 – 70 – ns 5) Activate (a) to Activate (b) Command Period tRRD 14 – 16 – ns 5) CAS(a) to CAS(b) Command Period tCCD 1 – 1 – CLK – Setup and Hold Parameters Common Parameters Data Book 9 Powered by ICminer.com Electronic-Library Service CopyRight 2003 12.99 HYS 64Vx20(2)0GCDL 144-pin SO-DIMM SDRAM Modules AC Characteristics (cont’d) 1), 2) TA = 0 to 70 °C; VSS = 0 V; VDD = 3.3 V ± 0.3 V, tT = 1 ns Parameter Symbol Limit Values -7.5 PC133-333 Unit Note -8 PC100-222 min. max. min. max. Refresh Cycle Refresh Period (4096 cycles) tREF – 64 – 64 ms – Self Refresh Exit Time tSREX 1 – 1 – CLK 6) Data Out Hold Time tOH 3 – 3 – ns – Data Out to Low Impedance Time tLZ 1 – 0 – ns – Data Out to High Impedance Time tHZ 3 7 3 8 ns 7) DQM Data Out Disable Latency tDQZ – 2 – 2 CLK – Data Input to Precharge (write recovery) tWR 2 – 2 – CLK – DQM Write Mask Latency tDQW 0 – 0 – CLK – Read Cycle Write Cycle Data Book 10 Powered by ICminer.com Electronic-Library Service CopyRight 2003 12.99 HYS 64Vx20(2)0GCDL 144-pin SO-DIMM SDRAM Modules Notes 1. An initial pause of 100 µs is required after power-up. Then a Precharge All Banks command must be given followed by eight Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin. 2. AC timing tests have VIL = 0.4 V and VIH = 2.4 V with the timing referenced to the 1.4 V crossover point. The transition time is measured between VIH and VIL. All AC measurements assume tT = 1 ns with the AC output load circuit shown. Specified tAC and tOH parameters are measured with a 50 pF only, without any resistive termination and with a input signal of 1 V/ns edge rate between 0.8 V and 2.0 V. 3. If clock rising time is longer than 1 ns, a time (tT – 0.5) ns must be added to this parameter. 4. If tT is longer than 1 ns, a time (tT – 1) ns must be added to this parameter. 5. Whenever the refresh Period has been exceeded, a minimum of two Auto (CRB) Refresh commands must be given to “wake-up” the device. 6. Self Refresh Exit is a synchronous operation and begins on the second positive clock edge after CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied after the Self Refresh Exit command is registered. 7. Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels. t CH 2.4 V 0.4 V CLOCK t CL t SETUP tT t HOLD INPUT 1.4 V t AC t LZ t AC I/O t OH 50 pF OUTPUT 1.4 V Measurement conditions for tAC and tOH t HZ SPT03404 A serial presence detect storage device - E2PROM - is assembled onto the module. Information about the module configuration, speed, etc. is written into the E 2PROM device during module production using a serial presence detect protocol (I2C synchronous 2-wire bus). Data Book 11 Powered by ICminer.com Electronic-Library Service CopyRight 2003 12.99 HYS 64Vx20(2)0GCDL 144-pin SO-DIMM SDRAM Modules SPD-Table for PC100 2-2-2 SO-DIMM Modules Description SPD Entry Value 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Number of SPD Bytes Total Bytes in Serial PD Memory Type Number of Row Addresses (without BS) Number of Column Addresses Number of DIMM Banks Module Data Width Module Data Width (cont’d) Module Interface Levels SDRAM Cycle Time at CL = 3 SDRAM Access Time from Clock at CL = 3 DIMM Config (Error Det/Corr.) Refresh Rate/Type SDRAM Width, Primary Error Checking SDRAM Data Width Minimum Clock Delay for Back-to-Back Random Column Address Burst Length Supported Number of SDRAM Banks Supported CAS Latencies CS Latencies WE Latencies SDRAM DIMM Module Attributes SDRAM Device Attributes: General SDRAM Cycle Time at CL = 2 SDRAM Access Time from Clock at CL = 2 SDRAM Cycle Time at CL = 1 SDRAM Access Time from Clock at CL = 1 Minimum Row Precharge Time Minimum Row Active to Row Active Delay Minimum RAS to CAS Delay Minimum RAS Pulse Width Module Bank Density (per bank) SDRAM Input Setup Time SDRAM Input Hold Time SDRAM Data Input Setup Time SDRAM Data Input Hold Time 128 256 SDRAM – – 1/2 64 0 LVTTL 10.0 ns 6.0 ns none Self-Refresh, 15.6 µs x16 n/a/x8 tCCD = 1 CLK Hex 4M × 64 -8 8M × 64 -8 16M × 64 -8 Byte# 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Data Book 12 Powered by ICminer.com Electronic-Library Service CopyRight 2003 08 01 1, 2, 4, 8 & full page 2 2, & 3 CS latency = 0 Write latency = 0 non buffered/non reg. VDD tol +/– 10% 10.0 ns 6.0 ns not supported not supported 20 ns 16 ns 20 ns 45 ns 32 MB/64 MB 08 2 ns 1 ns 2 ns 1 ns 80 08 04 0C 08 09 02 02 40 00 01 A0 60 00 80 10 00 01 8F 04 06 01 01 00 0E A0 60 FF FF 14 10 14 2D 08 20 10 20 10 10 12.99 HYS 64Vx20(2)0GCDL 144-pin SO-DIMM SDRAM Modules SPD-Table for PC100 2-2-2 SO-DIMM Modules (cont’d) Description SPD Entry Value 36-61 62 63 64-125 126 127 128+ Superset Information SPD Revision Checksum for Bytes 0 - 62 Manufactures’s Information (optional) Frequency Specification Details Unused Storage Locations – Revision 1.2 – – PC100 – – Hex 4M × 64 -8 8M × 64 -8 16M × 64 -8 Byte# Data Book 13 Powered by ICminer.com Electronic-Library Service CopyRight 2003 DF 64 87 FF 12 E0 FF 64 C7 FF E9 64 C7 12.99 HYS 64Vx20(2)0GCDL 144-pin SO-DIMM SDRAM Modules SPD-Table for PC133 3-3-3 SO-DIMM Modules Description SPD Entry Value 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Number of SPD Bytes Total Bytes in Serial PD Memory Type Number of Row Addresses (without BS) Number of Column Addresses Number of DIMM Banks Module Data Width Module Data Width (cont’d) Module Interface Levels SDRAM Cycle Time at CL = 3 SDRAM Access Time from Clock at CL = 3 DIMM Config (Error Det/Corr.) Refresh Rate/Type SDRAM Width, Primary Error Checking SDRAM Data Width Minimum Clock Delay for Back-to-Back Random Column Address Burst Length Supported Number of SDRAM Banks Supported CAS Latencies CS Latencies WE Latencies SDRAM DIMM Module Attributes SDRAM Device Attributes: General SDRAM Cycle Time at CL = 2 SDRAM Access Time from Clock at CL = 2 SDRAM Cycle Time at CL = 1 SDRAM Access Time from Clock at CL = 1 Minimum Row Precharge Time Minimum Row Active to Row Active Delay Minimum RAS to CAS Delay Minimum RAS Pulse Width Module Bank Density (per bank) SDRAM Input Setup Time SDRAM Input Hold Time SDRAM Data Input Setup Time SDRAM Data Input Hold Time 128 256 SDRAM – – 1/2 64 0 LVTTL 7.5 ns 5.4 ns none Self-Refresh, 15.6µs x16 n/a/x8 tCCD = 1 CLK Hex 4M × 64 -7.5 8M × 64 -7.5 16M × 64 -7.5 Byte# 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Data Book 14 Powered by ICminer.com Electronic-Library Service CopyRight 2003 08 01 1, 2, 4, 8 & full page 2 2, & 3 CS latency = 0 Write latency = 0 non buffered/non reg. VDD tol +/– 10% 10.0 ns 6.0 ns not supported not supported 20 ns 14 ns 20 ns 45 ns 32 MB/64 MB 08 1.5 ns 0.8 ns 1.5 ns 0.8 ns 80 08 04 0C 08 09 02 02 40 00 01 75 54 00 80 10 00 01 8F 04 06 01 01 00 0E A0 60 FF FF 14 0F 14 2D 08 15 08 15 08 10 12.99 HYS 64Vx20(2)0GCDL 144-pin SO-DIMM SDRAM Modules SPD-Table for PC133 3-3-3 SO-DIMM Modules (cont’d) Description SPD Entry Value 36-61 62 63 64-125 126 127 128+ Superset Information SPD Revision Checksum for Bytes 0 - 62 Manufactures’s Information (optional) Frequency Specification Details Unused Storage Locations – Revision 1.2 – – PC133 – – Hex 4M × 64 -7.5 8M × 64 -7.5 16M × 64 -7.5 Byte# Data Book 15 Powered by ICminer.com Electronic-Library Service CopyRight 2003 81 64 87 FF 12 82 FF 64 C7 FF 03 64 C7 12.99 HYS 64Vx20(2)0GCDL 144-pin SO-DIMM SDRAM Modules Package Outlines 32 & 64 MByte SO-DIMM Module Package (144-pin, Dual Read-out, Single In-line Memory Module) 67,6 63,6 6,0 1 59 3,3 25,40 20,0 4,0 3,8 143 61 1.0 +0.1 - 32.8 23.2 24.5 4,6 2,5 3,7 O 1,8 60 2 62 144 2.54 min 0.25 max Detail of Contacts: 0,8 Data Book 0,6+/- 0.05 4Mx64/8Mx64 COB-SDRAM SODIMM DM144-C8.WMF 16 Powered by ICminer.com Electronic-Library Service CopyRight 2003 12.99 HYS 64Vx20(2)0GCDL 144-pin SO-DIMM SDRAM Modules 128 MByte SO-DIMM Module Package (144-pin, Dual Read-out, Single In-line Memory Module) 67.6 63.6 25.4 3.8 1 3.3 23.2 59 61 32.8 143 1 ± 0.1 2.5 24.5 1.5 ±0.1 3.7 2 60 1.8 62 144 4 20 6 4 ±0.1 4.6 2.54 min. 0.25 max. Detail of Contacts 0.6 ±0.05 0.8 Data Book GLD09192 17 Powered by ICminer.com Electronic-Library Service CopyRight 2003 12.99 HYS 64Vx20(2)0GCDL 144-pin SO-DIMM SDRAM Modules Rev Changes: 12.98 12.1.99 19.3.99 20.4.99 5.5.99 21.7.99 29.7.99 23.8.99 27.8.99 6.9.99 3.12.99 Data Book 4M x 64 version added, 128 MByte version SPD byte changed from 08h to 10h (x16 device), check sum adjusted. Capacitance values according to measurments on samples adjusted Preliminary changed to final Input Capacitances adjusted 128 MB block diagram clarified ICC6 low-power versions reduced to 400 µA * components Infineon logo added Serial resistors for clock inputs and dummy loading corrected Some capacitance values changes due to new measured data PC133 versions added Editorial changes made according to Mr. Lewbel findings PC133 Byte 126 changed to 64h Drawing for C8 optimised, old drawing may be missleading Template from R&L PC133 timing parameters changed according to INTEL PC133 specification 18 Powered by ICminer.com Electronic-Library Service CopyRight 2003 12.99