CD4046BM/CD4046BC Micropower Phase-Locked Loop General Description The CD4046B micropower phase-locked loop (PLL) consists of a low power, linear, voltage-controlled oscillator (VCO), a source follower, a zener diode, and two phase comparators. The two phase comparators have a common signal input and a common comparator input. The signal input can be directly coupled for a large voltage signal, or capacitively coupled to the self-biasing amplifier at the signal input for a small voltage signal. Phase comparator I, an exclusive OR gate, provides a digital error signal (phase comp. I Out) and maintains 90§ phase shifts at the VCO center frequency. Between signal input and comparator input (both at 50% duty cycle), it may lock onto the signal input frequencies that are close to harmonics of the VCO center frequency. Phase comparator II is an edge-controlled digital memory network. It provides a digital error signal (phase comp. II Out) and lock-in signal (phase pulses) to indicate a locked condition and maintains a 0§ phase shift between signal input and comparator input. The linear voltage-controlled oscillator (VCO) produces an output signal (VCO Out) whose frequency is determined by the voltage at the VCOIN input, and the capacitor and resistors connected to pin C1A, C1B, R1 and R2. The source follower output of the VCOIN (demodulator Out) is used with an external resistor of 10 kX or more. The INHIBIT input, when high, disables the VCO and source follower to minimize standby power consumption. The zener diode is provided for power supply regulation, if necessary. Features Y Y Y Y Y Wide supply voltage range 3.0V to 18V Low dynamic 70 mW (typ.) at power consumption fo e 10 kHz, VDD e 5V VCO frequency 1.3 MHz (typ.) at VDD e 10V Low frequency drift 0.06%/§ C at VDD e 10V with temperature High VCO linearity 1% (typ.) Applications Y Y Y Y Y Y Y Y FM demodulator and modulator Frequency synthesis and multiplication Frequency discrimination Data synchronization and conditioning Voltage-to-frequency conversion Tone decoding FSK modulation Motor speed control Block & Connection Diagrams Dual-In-Line Package TL/F/5968 – 2 Top View Order Number CD4046B TL/F/5968 – 1 FIGURE 1 C1995 National Semiconductor Corporation TL/F/5968 RRD-B30M115/Printed in U. S. A. CD4046BM/CD4046BC Micropower Phase-Locked Loop November 1995 Absolute Maximum Ratings (Notes 1 & 2) Recommended Operating Conditions (Note 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. DC Supply Voltage (VDD) Input Voltage (VIN) Storage Temperature Range (TS) Power Dissipation (PD) Dual-In-Line Small Outline Lead Temperature (TL) (Soldering, 10 seconds) DC Supply Voltage (VDD) Input Voltage (VIN) Operating Temperature Range (TA) CD4046BM CD4046BC b 0.5 to a 18 VDC b 0.5 to VDD a 0.5 VDC b 65§ C to a 150§ C 3 to 15 VDC 0 to VDD VDC b 55§ C to a 125§ C b 40§ C to a 85§ C 700 mW 500 mW 260§ C DC Electrical Characteristics CD4046BM (Note 2) Symbol Parameter b 55§ C Conditions Min IDD Quiescent Device Current Pin 5 e VDD, Pin 14 e VDD, Pin 3, 9 e VSS VDD e 5V VDD e 10V VDD e 15V Pin 5 e VDD, Pin 14 e Open, Pin 3, 2 e VSS VDD e 5V VDD e 10V VDD e 15V VOL Low Level Output Voltage VDD e 5V VDD e 10V VDD e 15V VOH High Level Output Voltage VDD e 5V VDD e 10V VDD e 15V VIL Low Level Input Voltage Comparator and Signal In VDD e 5V, VO e 0.5V or 4.5V VDD e 10V, VO e 1V or 9V VDD e 15V, VO e 1.5V or 13.5V VIH High Level Input Voltage Comparator and Signal In VDD e 5V, VO e 0.5V or 4.5V VDD e 10V, VO e 1V or 9V VDD e 15V, VO e 1.5V or 13.5V IOL Low Level Output Current VDD e 5V, VO e 0.4V (Note 4) VDD e 10V, VO e 0.5V VDD e 15V, VO e 1.5V IOH High Level Output Current VDD e 5V, VO e 4.6V (Note 4) VDD e 10V, VO e 9.5V VDD e 15V, VO e 13.5V IIN Input Current Input Capacitance Any Input (Note 3) PT Total Power Dissipation fo e 10 kHz, R1 e 1 MX R2 e % , VCOIN e VDD/2 VDD e 5V VDD e 10V VDD e 15V a 25§ C Min 5 10 20 0.005 0.01 0.015 5 10 20 150 300 600 mA mA mA 45 450 1200 5 20 50 35 350 900 185 650 1500 mA mA mA 0.05 0.05 0.05 0 0 0 0.05 0.05 0.05 0.05 0.05 0.05 V V V 4.95 9.95 14.95 1.5 3.0 4.0 5 10 15 2.25 4.5 6.25 Min Units Max Max 4.95 9.95 14.95 1.5 3.0 4.0 V V V 1.5 3.0 4.0 V V V 3.5 7.0 11.0 3.5 7.0 11.0 2.75 5.5 8.25 3.5 7.0 11.0 V V V 0.64 1.6 4.2 0.51 1.3 3.4 0.88 2.25 8.8 0.36 0.9 2.4 mA mA mA b 0.64 b 1.6 b 4.2 b 0.51 b 1.3 b 3.4 b 0.88 b 2.25 b 8.8 b 0.36 b 0.9 b 2.4 mA mA mA b 0.1 0.1 b 10 b 5 b 0.1 10b5 0.07 0.6 2.4 2 a 125§ C Typ 4.95 9.95 14.95 All Inputs Except Signal Input VDD e 14V, VIN e 0V VDD e 15V, VIN e 15V CIN Max 0.1 b 1.0 1.0 mA mA 7.5 pF mW mW mW DC Electrical Characteristics CD4046BC (Note 2) Symbol Parameter b 40§ C Conditions Min IDD Quiescent Device Current Pin 5 e VDD, Pin 14 e VDD, Pin 3, 9 e VSS VDD e 5V VDD e 10V VDD e 15V Pin 5 e VDD, Pin 14 e Open, Pin 3, 9 e VSS VDD e 5V VDD e 10V VDD e 15V VOL Low Level Output Voltage VDD e 5V VDD e 10V VDD e 15V VOH High Level Output Voltage VDD e 5V VDD e 10V VDD e 15V VIL Low Level Input Voltage Comparator and Signal In VDD e 5V, VO e 0.5V or 4.5V VDD e 10V, VO e 1V or 9V VDD e 15V, VO e 1.5V or 13.5V VIH High Level Input Voltage Comparator and Signal In VDD e 5V, VO e 0.5V or 4.5V VDD e 10V, VO e 1V or 9V VDD e 15V, VO e 1.5V or 13.5V IOL Low Level Output Current VDD e 5V, VO e 0.4V (Note 4) VDD e 10V, VO e 0.5V VDD e 15V, VO e 1.5V IOH High Level Output Current VDD e 5V, VO e 4.6V (Note 4) VDD e 10V, VO e 9.5V VDD e 15V, VO e 13.5V IIN Input Current Input Capacitance Any Input (Note 3) PT Total Power Dissipation fo e 10 kHz, R1 e 1 MX, R2 e % , VCOIN e VDD/2 VDD e 5V VDD e 10V VDD e 15V Min a 85§ C Max 20 40 80 0.005 0.01 0.015 20 40 80 150 300 600 mA mA mA 70 530 1500 5 20 50 55 410 1200 205 710 1800 mA mA mA 0.05 0.05 0.05 0 0 0 0.05 0.05 0.05 0.05 0.05 0.05 V V V 4.95 9.95 14.95 1.5 3.0 4.0 5 10 15 2.25 4.5 6.25 Min Units Typ 4.95 9.95 14.95 All Inputs Except Signal Input VDD e 15V, VIN e 0V VDD e 15V, VIN e 15V CIN Max a 25§ C Max 4.95 9.95 14.95 1.5 3.0 4.0 V V V 1.5 3.0 4.0 V V V 3.5 7.0 11.0 3.5 7.0 11.0 2.75 5.5 8.25 3.5 7.0 11.0 V V V 0.52 1.3 3.6 0.44 1.1 3.0 0.88 2.25 8.8 0.36 0.9 2.4 mA mA mA b 0.52 b 1.3 b 3.6 b 0.44 b 1.1 b 3.0 b 0.88 b 2.25 b 8.8 b 0.36 b 0.9 b 2.4 mA mA mA b 0.3 0.3 b 10 b 5 b 0.3 10b5 0.3 7.5 0.07 0.6 2.4 b 1.0 1.0 mA mA pF mW mW mW Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical Characteristics’’ provides conditions for actual device operation. Note 2: VSS e 0V unless otherwise specified. Note 3: Capacitance is guaranteed by periodic testing. Note 4: IOH and IOL are tested one output at a time. 3 AC Electrical Characteristics* CD4046BM/CD4046BC TA e 25§ C, CL e 50 pF Symbol Parameter Conditions Min Typ Max Units VCO SECTION IDD fMAX Operating Current fo e 10 kHz, R1 e 1 MX, R2 e % , VCOIN e VDD/2 VDD e 5V VDD e 10V VDD e 15V Maximum Operating Frequency Linearity VCOIN e 2.5V g 0.3V, R1 t 10 kX, VDD e 5V VCOIN e 5V g 2.5V, R1 t 400 kX, VDD e 10V VCOIN e 7.5V g 5V, R1 t 1 MX, VDD e 15V Temperature-Frequency Stability No Frequency Offset, fMIN e 0 Frequency Offset, fMIN C1 e 50 pF, R1 e 10 kX, R2 e % , VCOIN e VDD VDD e 5V VDD e 10V VDD e 15V i 0 0.4 0.6 1.0 20 90 200 mA mA mA 0.8 1.2 1.6 MHz MHz MHz 1 % 1 % 1 % %/§ C*1/f. VDD R2 e % VDD e 5V VDD e 10V VDD e 15V 0.12 – 0.24 0.04 – 0.08 0.015 – 0.03 %/§ C %/§ C %/§ C VDD e 5V VDD e 10V VDD e 15V 0.06 – 0.12 0.05 – 0.1 0.03 – 0.06 %/§ C %/§ C %/§ C VCOIN Input Resistance VDD e 5V VDD e 10V VDD e 15V 106 106 106 MX MX MX VCO Output Duty Cycle VDD e 5V VDD e 10V VDD e 15V 50 50 50 % % % tTHL VCO Output Transition Time VDD e 5V 90 200 ns VDD e 10V VDD e 15V 50 45 100 80 ns ns tTHL *AC Parameters are guaranteed by DC correlated testing. 4 AC Electrical Characteristics* CD4046BM/CD4046BC TA e 25§ C, CL e 50 pF (Continued) Symbol Parameter Conditions Min Typ 1 0.2 0.1 3 0.7 0.3 106 106 106 Max Units PHASE COMPARATORS SECTION RIN Input Resistance Signal Input Comparator Input AC-Coupled Signal Input Voltage Sensitivity VDD VDD VDD VDD VDD VDD e e e e e e 5V 10V 15V 5V 10V 15V MX MX MX MX MX MX CSERIES e 1000 pF f e 50 kHz VDD e 5V VDD e 10V VDD e 15V 200 400 700 400 800 1400 mV mV mV Offset Voltage RS t 10 kX, VDD e 5V RS t 10 kX, VDD e 10V RS t 50 kX, VDD e 15V 1.50 1.50 1.50 2.2 2.2 2.2 V V V Linearity RS t 50 kX VCOIN e 2.5V g 0.3V, VDD e 5V VCOIN e 5V g 2.5V, VDD e 10V VCOIN e 7.5V g 5V, VDD e 15V 0.1 0.6 0.8 DEMODULATOR OUTPUT VCOINb VDEM % % % ZENER DIODE VZ RZ Zener Diode Voltage IZ e 50 mA Zener Dynamic Resistance IZ e 1 mA *AC Parameters are guaranteed by DC correlated testing. 5 6.3 7.0 100 7.7 V X Phase Comparator State Diagrams TL/F/5968 – 3 FIGURE 2 Typical Waveforms TL/F/5968–4 FIGURE 3. Typical Waveform Employing Phase Comparator I in Locked Condition TL/F/5968 – 5 FIGURE 4. Typical Waveform Employing Phase Comparator II in Locked Condition 6 Typical Performance Characteristics Typical Center Frequency vs C1 for R1 e 10 kX, 100 kX and 1 MX TL/F/5968 – 6 FIGURE 5a Typical Frequency vs C1 for R2 e 10 kX, 100 kX and 1 MX TL/F/5968 – 13 FIGURE 5b Note: To obtain approximate total power dissipation of PLL system for no-signal input: Phase Comparator I, PD (Total) e PD (fo) a PD (fMIN) a PD (RS); Phase Comparator II, PD (Total) e PD (fMIN). 7 Typical Performance Characteristics (Continued) Typical fMAX/fMIN vs R2/R1 TL/F/5968 – 14 FIGURE 5C Typical VCO Power Dissipation at Center Frequency vs R1 TL/F/5968 – 15 FIGURE 6a Note: To obtain approximate total power dissipation of PLL system for no-signal input: Phase Comparator I, PD (Total) e PD (fo) a PD (fMIN) a PD (RS); Phase Comparator II, PD (Total) e PD (fMIN). 8 Typical Performance Characteristics (Continued) Typical VCO Power Dissipation at fMIN vs R2 TL/F/5968 – 16 FIGURE 6b Typical Source Follower Power Dissipation vs RS TL/F/5968 – 17 FIGURE 6c Note: To obtain approximate total power dissipation of PLL system for no-signal input: Phase Comparator I, PD (Total) e PD (fo) a PD (fMIN) a PD (RS); Phase Comparator II, PD (Total) e PD (fMIN). 9 Typical Performance Characteristics (Continued) TL/F/5968 – 18 TL/F/5968 – 19 FIGURE 7. Typical VCO Linearity vs R1 and C1 Note: To obtain approximate total power dissipation of PLL system for no-signal input: Phase Comparator I, PD (Total) e PD (fo) a PD (fMIN) a PD (RS); Phase Comparator II, PD (Total) e PD (fMIN). 10 Design Information In addition to the given design information, refer to Figure 5 for R1, R2 and C1 component selections. This information is a guide for approximating the value of external components for the CD4046B in a phase-lockedloop system. The selected external components must be within the following ranges: R1, R2 t 10 kX, RS t 10 kX, C1 t 50 pF. Using Phase Comparator I Characteristics VCO Without Offset R2 e % Using Phase Comparator II VCO With Offset VCO Without Offset R2 e % VCO With Offset VCO Frequency TL/F/5968–7 For No Signal Input TL/F/5968 – 9 TL/F/5968 – 8 VCO in PLL system will adjust to center frequency, fo Frequency Lock Range, 2 fL TL/F/5968 – 10 VCO in PLL system will adjust to lowest operating frequency, fmin 2 fL e full VCO frequency range 2 fL e fmax b fmin Frequency Capture Range, 2 fC 2 fC & TL/F/5968–11 1 q 0 2 q fL u1 fC e fL Loop Filter Component Selection For 2 fC, see Ref. TL/F/5968–12 Phase Angle Between Single and Comparator 90§ at center frequency (fo), approximating 0§ and 180§ at ends of lock range (2 fL) Always 0§ in lock Locks on Harmonics of Center Frequency Yes No Signal Input Noise Rejection High Low VCO Component Selection Given: fo. Given: fo and fL. Given: fmax. Given: fmin and fmax. Use fo with Figure 5a to determine R1 and C1. Calculate fmin from the equation Calculate fo from the equation fmin e fo b fL. fmax . fo e 2 Use fmin with Figure 5b to determine R2 and C1. fmax Calculate . fmin fmax Use with Figure 5c fmin to determine ratio R2/R1 to obtain R1. Use fmin with Figure 5b to determine R2 and C1. fmax Calculate fmin Use fo with Figure 5a to determine R1 and C1. from the equation fmax f a fL e o . fmin fo b fL fmax Use with Figure 5c fmin to determine ratio R2/ R1 to obtain R1. References G.S. Moschytz, ‘‘Miniaturized RC Filters Using Phase-Locked Loop’’, BSTJ, May, 1965. Floyd Gardner, ‘‘Phaselock Techniques’’, John Wiley & Sons, 1966. 11 12 Physical Dimensions inches (millimeters) Order Number CD4046BMJ or CD4046BCJ NS Package Number J16A 13 CD4046BM/CD4046BC Micropower Phase-Locked Loop Physical Dimensions inches (millimeters) (Continued) Order Number CD4046BMN or CD4046BCN NS Package Number N16E LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 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