www.fairchildsemi.com ILC7082 150mA SOT-23 Ultra Low Noise CMOS RF-LDO™ Regulator Features Description • • • • The ILC7082 is a 150mA low dropout (LDO) voltage regulator designed to provide a high performance solution to low power systems. The device offers a typical combination of low dropout and low quiescent current expected of CMOS parts, while uniquely providing the low noise and high ripple rejection characteristics usually only associated with bipolar LDO regulators. • • • • • • • • Ultra low 1mV dropout per 1mA load 1% output voltage accuracy Only 30mVRMS noise Uses low ESR ceramic output capacitor to minimize noise and output ripple Only 100mA ground current at 100mA load Ripple rejection up to 85dB at 1kHz, 60dB at 1MHz Excellent line and load transient response Over current / over temperature protection Guaranteed to 150mA output current Industry standard five lead SOT-23 package Fixed 2.8V, 3.0V, 3.3V,3.6V, 4.7V, 5.0V and adjustable output voltage options Metal mask option available for custom voltages between 2.5V and 10V The device has been optimized to meet the needs of modern wireless communications design; Low noise, low dropout, small size, high peak current, high noise immunity. The ILC7082 is designed to make use of low cost ceramic capacitors while outperforming other devices that require tantalum capacitors. Applications • • • • Cellular phones Wireless communicators PDAs / palmtops / organizers Battery powered portable electronics Typical Applications VOUT 5 C OUT VIN SOT-23-5 4 C NOISE ILC7082 1 2 3 ON C IN OFF Rev. 1.4 ©2001 Fairchild Semiconductor Corporation ILC7082 Pin Assignments VOUT CNOISE VOUT 4 5 SOT-23-5 5 ILC7082-xx 1 GND 3 1 PIN DESCRIPTION ILC7082-xx Pin Name 1 VIN 2 GND 3 ON/OFF 4 CNOISE 2 VIN ON/OFF Fixed Voltage option Pin Number SOT-23-5 4 ILC7082-xx 2 VIN VADJ GND 3 ON/OFF Adjustable Voltage option (fixed voltage version) Pin Description Connect directly to supply Ground pin. Local ground for CNOISE and COUT. By applying less than 0.4V to this pin the device will be turned off. Optional noise bypass capacitor may be connected between this pin and GND (pin 2). Do not connect CNOISE directly to the main power ground plane. 5 VOUT Output Voltage. Connect COUT between this pin and GND (pin 2). PIN DESCRIPTION ILC7082-AIK-XX (SOIC fixed voltage version) Pin Number Pin Name Pin Description 1 GND 2 ON/OFF 3 VIN Connect directly to supply 4 N/C No Connection 5 N/C No Connection 6 VOUT Output Voltage. Connect COUT between this pin and GND (pin 2). 7 N/C No Connection 8 N/C No Connection Connect directly to supply Ground pin. Local ground for CNOISE and COUT. ©2001 Fairchild Semiconductor Corporation 2 ILC7082 PIN DESCRIPTION ILC7082-ADJ (adjustable voltage version) Pin Number Pin Name Pin Description 1 VIN 2 GND 3 ON/OFF 4 VADJ Voltage feedback pin to set the adjustable output voltage. Do not connect a capacitor to this pin. 5 VOUT Output Voltage. Connect COUT between this pin and GND (pin 2). Connect directly to supply Ground pin. Local ground for CNOISE and COUT. By applying less than 0.4V to this pin the device will be turned off. Internal Block Diagram V IN INTERNAL V DD CNOISE BANDGAP REFERENCE V REFD TRANSCONDUCTANCE AMPLIFIER ERROR AMPLIFIER V OUT FEEDBACK GND ON/OFF Absolute Maximum Ratings Parameter Symbol Ratings Units VIN VON/OFF -0.3 to +13.5 V Output Current IOUT Short circuit protected mA Output Voltage VOUT -0.3 to VIN+0.3 V PD 250 (Internally Limited) mW TJ(max) -40~+150 °C TSTG -40~+125 °C Operating Ambient Temperature TA -40 to +85 °C Package Thermal Resistance θJA 333 °C/W Input Voltage On/Off Input Voltage Package Power Dissipation (SOT-23-5) Maximum Junction Temp Range Storage Temperature -0.3 to VIN ©2001 Fairchild Semiconductor Corporation 3 ILC7082 ELECTRICAL CHARACTERISTICS ILC7082AIM5 Unless otherwise specified, all limits are at TA=25°C; VIN = VOUT(NOM) +1V, IOUT = 1mA, COUT = 1µF, VON/OFF = 2V.. The • denotes specifications which apply over the specified operating temperature range. Parameter Input Voltage Range Symbol Conditions VIN Min 1mA < IOUT < 100mA Feedback Voltage (ADJ version) Line Regulation VOUT(NOM) +1 VOUT(NOM) • +1.5 +2.5 VOUT(NOM) • -2.5 -3.5 +2.5 +3.5 1.215 1.202 1.240 • 1.265 1.278 0.014 0.032 VADJ ∆VOUT/ (VOUT*∆VIN) VOUT(NOM) +1V < VIN < 12V IOUT= 0mA (Note 4) IOUT = 10mA Dropout Voltage (Note 3) VIN - VOUT IOUT = 0mA IOUT = 10mA IGND IOUT = 50mA IOUT = 100mA IOUT = 150mA Shutdown (OFF) Current ION/OFF VON/OFF = 0V ON/OFF Input Voltage VON/OFF High = Regulator On Low = Regulator Off VON/OFF = 0.6V, regulator OFF ON/OFF Pin Input Current (Note 5) IIN( ON/OFF) Peak Output Current (Note 4) IOUT(peak) Output Noise Voltage (RMS) eN Ripple Rejection 10 • 50 100 • 150 • 95 • 100 • 100 • 100 • 115 • • • • 0.1 1.5 VON/OFF = 2V, regulator ON VOUT > 0.95VOUT(NOM), tpw = 2ms BW = 300Hz to 50kHz, CIN = 1µF 400 1 2 25 35 75 100 150 200 225 300 200 220 220 240 220 240 240 260 260 280 2 %VOUT (NOTM) V %/V mV µA µA 13 0.6 0.3 1 µA 500 mA 30 µVRMS CNOISE = 0.01µF, C OUT = 2.2µF, IOUT = 10mA ∆VOUT/∆VIN COUT = 4.7µF, Freq. = 1kHz Freq. = 10kHz Freq. = 1MHz VIN: VOUT(NOM) + 1V to 85 70 60 14 mV IOUT: 1mA to 150mA; tr < 5µS 40 mV VOUT = 0V 600 mA IOUT = 100mA Dynamic Line Regulation 0.1 • • IOUT = 150mA Ground Pin Current 0.007 • IOUT = 50mA IOUT = 100mA V -1 1mA < IOUT < 150mA 1mA < IOUT < 150mA Units 13 -1.5 -2.5 1mA < IOUT < 100mA VOUT Max 2 Iout = 1mA Output Voltage Typ • ∆VOUT(line) dB VOUT(NOM) + 2V, tr/tf = 2ms; IOUT = 150mA Dynamic Load Regulation Short Circuit Current ∆VOUT(load) ISC ©2001 Fairchild Semiconductor Corporation 4 ILC7082 Notes: 1: Absolute maximum ratings indicate limits which when exceeded may result in damage to the component. Electrical specifications do not apply when operating the device outside of its rated operating conditions. 2: Specified Min/Max limits are production tested or guaranteed through correlation based on statistical control methods. Measurements are taken at constant junction temperature as close to ambient as possible using low duty pulse testing. 3: Dropout voltage is defined as the input to output differential voltage at which the output voltage drops 2% below the nominal value measured with an IV differential. 4: Guaranteed by design 5: The device’s shutdown pin includes a 2MΩ internal pulldown resistor connected to ground. OPERATION A block diagram of the regulator circuit used in the ILC7082 is shown in figure 2, which shows the input-to-output isolation and the cascaded sequence of amplifiers that implement the pole-zero scheme outlined above. DOMINANT POLE 85 dB OUTPUT POLE GAIN The ILC7082 LDO design is based on an advanced circuit configuration for which patent protection has been applied. Typically it is very difficult to drive a capacitive output with an amplifier. The output capacitance produces a pole in the feedback path, which upsets the carefully tailored dominant pole of the internal amplifier. Traditionally the pole of the output capacitor has been “eliminated” by reducing the output impedance of the regulator such that the pole of the output capacitor is moved well beyond the gain bandwidth product of the regulator. In practice, this is difficult to do and still maintain high frequency operation. Typically the output impedance of the regulator is not simply resistive, such that the reactive output impedance interacts with the reactive impedance of the load resistance and capacitance. In addition, it is necessary to place the dominant pole of the circuit at a sufficiently low frequency such that the gain of the regulator has fallen below unity before any of the complex interactions between the output and the load occur. The ILC7082 does not try to eliminate the output pole, but incorporates it into the stability scheme. The load and output capacitor forms a pole, which rolls off the gain of the regulator below unity. In order to do this the output impedance of the regulator must be high, looking like a current source. The output stage of the regulator becomes a transconductance amplifier, which converts a voltage to a current with a substantial output impedance. The circuit which drives the transconductance amplifier is the error amplifier, which compares the regulator output to the band gap reference and produces an error voltage as the input to the transconductance amplifier. The error amplifier has a dominant pole at low frequency and a “zero” which cancels out the effects of the pole. The zero allows the regulator to have gain out to the frequency where the output pole continues to reduce the gain to unity. The configuration of the poles and zero are shown in figure 1. Instead of powering the critical circuits from the unregulated input voltage, the CMOS RF LDO powers the internal circuits such as the bandgap, the error amplifier and most of the transconductance amplifier from the boot strapped regulated output voltage of the regulator. This technique offers extremely high ripple rejection and excellent line transient response. COMPENSATING ZERO UNITY GAIN FREQUENCY Figure 1: ILC7082 RF LDO frequency response V IN INTERNAL V DD CNOISE BANDGAP REFERENCE V REFD TRANSCONDUCTANCE AMPLIFIER ERROR AMPLIFIER V OUT FEEDBACK GND ON/OFF Figure 2: ILC7082 RF LDO regulator block diagram The ILC7082 is designed in a CMOS process with some minor additions, which allow the circuit to be used at input voltages up to 13V. The resulting circuit exceeds the frequency response of traditional bipolar circuits. The ILC7082 is very tolerant of output load conditions with the inclusion of both short circuit and thermal overload protection. The device has a very low dropout voltage, typically a linear response of 1mV per milliamp of load current, and none of the quasi-saturation characteristics of a bipolar output devices. All the good features of the frequency response and regulation are valid right to the point where the regulator goes out of regulation in a 4 millivolt transition region. Because there is no base drive, the regulator is capable of providing high current surges while remaining in regulation. This is shown in the high peak current of 500mA which allows for the ILC7082 to be used in systems that require short burst mode operation. ©2001 Fairchild Semiconductor Corporation 5 ILC7082 Shutdown (ON/OFF) Operation The ILC7082 output can be turned off by applying 0.4V or less to the device’s ON/OFF pin (pin 3). In shutdown mode, the ILC7082 draws less than 1mA quiescent current. The output of the ILC7081 is enabled by applying 1.5V to 13V at the ON/OFF pin. In applications were the ILC7082 output will always remain enabled, the ON/OFF pin may be connected to V IN (pin 1). The ILC7082’s shutdown circuitry includes hysteresis, as such the device will operate properly even if a slow moving signal is applied to the ON/OFF pin. The device’s shutdown pin includes a 2m Ω internal pull down resistor connected to ground. Short Circuit Protection The ILC7082 output can withstand momentary short circuit to ground. Moreover, the regulator can deliver very high output peak current due to its 1A instantaneous short circuit current capability. Thermal Protection The ILC7082 also includes a thermal protection circuit which shuts down the regulator when die temperature exceeds 170°C due to overheating. In thermal shutdown, once the die temperature cools to below 160°C, the regulator is enabled. If the die temperature is excessive due to high package power dissipation, the regulator’s thermal circuit will continue to pulse the regulator on and off. This is called thermal cycling. Excessively high die temperature may occur due to high differential voltage across the regulator or high load current or high ambient temperature or a combination of all three. Thermal protection protects the regulator from such fault conditions and is a necessary requirement in today’s designs. In normal operation, the die temperature should be limited to under 150°C. Adjustable Output Voltage Figure 5 shows how an adjustable output voltage can be easily achieved using ILC7082-ADJ. The output voltage, VOUT is given by the following equation: For best results, a resistor value of 470kΩ or less may be used for R2. The output voltage can be programmed from 2.5V to 12V Note that an external capacitor should not be connected to the adjustable feedback pin (pin 4). Connecting an external capacitor to pin 4 may cause regulator instability and lead to oscillations. Maximum Output Current The maximum output current available from the ILC7082 is limited by the maximum package power dissipation as well as the device’s internal current limit. For a given ambient temperature, TA, the maximum package power dissipation is given by: PD(MAX) = (TJ(MAX) - TA) / θJA where TJ(MAX) = 150°C is the maximum junction temperature and qJA = 333°C/W is the package thermal resistance. For example at A = 85°C ambient temperature, the maximum package power dissipation is; PD(MAX) = 195mΩ. The maximum output current can be calculated from the following equation: IOUT(MAX) < PD(MAX) / (VIN - VOUT) For example at VIN = 6V, VOUT = 5V and TA = 85°C, the maximum output current is IOUT(MAX) < 195mA. At higher output current, the die temperature will rise and cause the thermal protection circuit to be enabled. APPLICATION HINTS Figure 4 shows the typical application circuit for the ILC7082. VOUT 5 SOT23-5 4 VIN R1 VOUT VIN R2 CIN CIN 2 2 3 ON Figure 4: Basic application circuit for fixed output voltage versions ILC7082-ADJ 1 1 OFF 5 SOT23-5 4 VADJ COUT ILC7082 COUT VOUT = 1.24V x (R1/R2 + 1) CNOISE 3 ON OFF Fig. 3: Application circuit for adjustable output voltage ©2001 Fairchild Semiconductor Corporation 6 ILC7082 Input Capacitor An input capacitor CIN of value 1mF or larger should be connected from V IN to the main ground plane. This will help to filter supply noise from entering the LDO. The input capacitor should be connected as close to the LDO regulator input pin as is practical. Using a high-value input capacitor will offer superior line transient response as well as better power supply ripple rejection. A ceramic or tantalum capacitor may be used at the input of the LDO regulator. Note that there is a parasitic diode from the LDO regulator output to the input. If the input voltage swings below the regulator’s output voltage by a couple of hundred milivolts then the regulator may be damaged. This condition must be avoided. In many applications a large value input capacitor, CIN, will hold VIN higher than VOUT and decay slower than VOUT when the LDO is powered off. Output Capacitor Selection Fairchild strongly recommends the use of low ESR (equivalent series resistance) ceramic capacitors for C OUT and CNOISE The ILC7082 is stable with low ESR capacitor (as low as zero Ω). The value of the output capacitor should be 1mF or higher. Either ceramic chip or a tantalum capacitor may be used at the output. Use of ceramic chip capacitors offer significant advantages over tantalum capacitors. A ceramic capacitor is typically cheaper than a tantalum capacitor, it usually has a smaller footprint, lower height, and lighter weight than a tantalum capacitor. Furthermore, unlike tantalum capacitors which are polarized and can be damaged if connected incorrectly, ceramic capacitors are non-polarized. Low value ceramic chip capacitors with X5R or X7R dielectric are available in the 100pF to 4.7mF range. Beware of using ceramic capacitors with Y5V dielectric since their ESR increases significantly at cold temperatures. Figure 12 shows a list of recommended ceramic capacitors for use at the output of ILC7082. Note: If a tantalum output capacitor is used then for stable operation Impala recommends a low ESR tantalum capacitor with maximum rated ESR at or below 0.4W. Low ESR tantalum capacitors, such as the TPS series from AVX Corporation (www.avxcorp.com) or the T495 series from Kemet (www.kemet.com) may be used. In applications where a high output surge current can be expected, use a high value but low ESR output capacitor for superior load transient response. The ILC7082 is stable with no load. Noise bypass capacitors with a value as low as 470pF may be used. However, for optimum performance, use a 0.01mF or larger, ceramic chip capacitor. Note that the turn on and turn off response of the ILC7082 is inversely proportional to the value of the noise bypass capacitor. For fast turn on and turn off, use a small value noise bypass capacitor. In applications were exceptionally low output noise is not required, consider omitting the noise bypass capacitor altogether. The Effects of ESR (Equivalent Series Resistance) The ESR of a capacitor is a measure of the resistance due to the leads and the internal connections of the component. Typically measured in m Ω (milli-ohms) it can increase to ohms in some cases. Wherever there is a combination of resistance and current, voltages will be present. The control functions of LDOs use two voltages in order to maintain the output precisely; VOUT and VREF. With reference to the block diagram in figure 4, V OUT is fed back to the error amplifier and is used as the supply voltage for the internal components of the ILC7082. So any change in VOUT will cause the error amplifier to try to compensate to maintain VOUT at the set level and noise on V OUT will be reflected into the supply of each internal components of the ILC7082. So any change in VOUT will cause the error amplifier to try to compensate to maintain VOUT at the set level and noise on VOUT will be reflected into the supply of each internal circuit. The reference voltage, VREF, is influenced by the CNOISE pin. Noise into this pin will add to the reference voltage and be fed through the circuit. These factors will not cause a problem if some simple steps are taken. Figure 5 shows where these added ESR resistances are present in the typical LDO circuit. V OUT IOUT R* IC RC COUT 5 SOT-23-5 4 CNOISE ILC7082 VIN 1 R* CIN 2 RF LDO TM Regulator 3 ON OFF Figure 5: ESR present in COUT and CNOISE Noise Bypass Capacitor In low noise applications, the self noise of the ILC7082 can be decreased further by connecting a capacitor from the noise bypass pin (pin 4) to ground (pin 2). The noise bypass pin is a high impedance node as such care should be taken in printed circuit board layout to avoid noise pick-up from external sources. Moreover, the noise bypass capacitor should have low leakage. With this in mind low ESR components will offer better performance where the LDO may be subjected to large load transients current. ESR is less of a problem with CIN as the voltage fluctuations at the input will be filtered by the LDO. ©2001 Fairchild Semiconductor Corporation 7 ILC7082 V OUT 4 CNOISE ILC7082 SOT-23-5 C IN 1 GND2 2 3 C OUT CNOISE V IN LOAD 5 GND However, being aware of these current flows, there is also another potential source of induced voltage noise from the resistance inherent in the PCB trace. Figure 6 shows where the additive resistance of the PCB can manifest itself. Again these resistances may be very small, but a summation of several currents can develop detectable voltage ripple and will be amplified by the LDO. Particularly the accumulation of current flows in the ground plane can develop significant voltages unless care is taken. With a degree of care, the ILC7082 will yield outstanding performance. ON/OFF IC OUT Printed Circuit Board Layout Guidelines As was mentioned in the previous section, to take full advantage of any high performance LDO regulator requires paying careful attention to grounding and printed circuit board (PCB) layout. True GND (0V) GND1 I LOAD I LOAD +IC OUT +IC OUT +IC NOISE +IC GND3 GND4 GND5 I LOAD I LOAD +IC OUT NOISE +IGND Figure 7: Effects of poor circuit layout R PCB I1 COUT ESR VOUT IOUT ESR R PCB 5 SOT-23-5 4 CNOISE ILC7082 VIN CIN 1 RPCB 2 3 R PCB ON OFF Figure 8 shows an optimum schematic. In this schematic, high output surge current has little effect on the ground current and noise bypass current return of the LDO regulator Note that the key difference here is that COUT and CNOISE are directly connected to the LDO regulator’s ground pin. The LDO is then separately connected to the main ground plane and returned to a single point system ground. The layout of the LDO and its external components are also based on some simple rules to minimize EMI and output voltage ripple. Figure 6: Inherent PCB resistance Figure 7 shows the effects of poor grounding and PCB layout magnified by the ESR and PCB resistances and the accumulation of current flows. Note thatparticularly during high output load current, the LDO regulator’s ground pin and the ground return for C OUT and C NOISE are not at the same potential as the system ground. This is due to high frequency impedance caused by PCB’s trace inductance and DC resistance. The current loop between COUT, C NOISE and the LDO regulator’s ground pin will degrade performance of the LDO. ©2001 Fairchild Semiconductor Corporation 8 ILC7082 V OUT 5 4 COUT ILC7082 SOT-23-5 1 2 ON/OFF Local CIN + GND Ground Plane Ground Plane ESR<0.5Ω 3 Ground V IN DC/DC Converter V BATT LOAD CNOISE Ground Plane Ground Plane Figure 8: Recommended application circuit schematic. Fairchild Semiconductor - Eval. Board Figure 9: Recommended application circuit layout ( not drawn to scale) Note, ground plane is bottom layer of PCB and connects to top layer ground connections through vias. Evaluation Board Parts List For Printed Circuit Board Shown Above Label Part Number Manufacturer Description U1 ILC7082AIM5-30 Fairchild Semiconductor 150mA RF LDOTM regulator J1 69190-405 Berg Connector, four position header Cin GRM40 Y5V 105Z16 muRata Ceramic capacitor, 1µF,16V, SMT ( size 0805 ) Cnoise ECU-V1H103KBV Panasonic Ceramic capacitor, 0.01µF,16V, SMT ( size 0603 ) Cout GRM42-6X5R475K10 muRata Ceramic capacitor, 4.7µF,16V, SMT ( size 1206) GROUNDING RECOMMENDATIONS 1. Connect CIN between VIN of the ILC7082 and the “GROUND PLANE”. 2. Keep the ground side of COUT and CNOISE connected to the “LOCAL GROUND” and not directly to the “GROUND PLANE”. 3. On multilayer boards use component side copper for grounding around the ILC7082 and connect back to a “GROUND PLANE” using vias. 4. If using a DC-DC converter in your design, use a star grounding system with separate traces for the power ground and the control signals. The star should radiate from where the power supply enters the PCB. LAYOUT CONSIDERATIONS 1. Place all RF LDO related components; ILC7082, input capacitor CIN, noise bypass capacitor CNOISE and output capacitor COUT as close together as possible. 2. Keep the output capacitor COUT as close to the ILC7082 as possible with very short traces to the VOUT and GND pins. 3. The traces for the related components; ILC7082, input capacitor CIN, noise bypass capacitor CNOISE and output capacitor COUT can be run with minimum trace widths close to the LDO. 4. Maintain a separate “LOCAL GROUND” remote from the “GROUND PLANE” to ensure a quiet ground near the LDO. Figure 9 shows how this circuit can be translated into a PCB layout. ©2001 Fairchild Semiconductor Corporation 9 ILC7082 Recommended Ceramic Output Capacitors COUT Capacitor Size IOUT Dielectric Part Number Capacitor Vendor 1µF 0805 0 to 150mA X5R C2012X5R1A105KT TDK “ 0805 “ X7R GRM40X7R105K010 muRata “ 0805 “ X7R LMK212BJ105KG Taiyo-Yuden “ 1206 “ X7R GRM42-6X7R105K016 muRata “ 1206 “ X7R EMK316BJ105KL Taiyo-Yuden “ 1206 “ X5R TMK316BJ105KL Taiyo-Yuden 2.2µF 0805 0 to 150mA X5R GRM40X5R225K 6.3 muRata “ 0805 “ X5R C2012X5R0J225KT TDK “ 1206 “ X5R EMK316BJ225ML Taiyo-Yuden 4.7µF 1206 0 to 150mA X5R GRM42-6X5R475K010 muRata “ 1206 “ X7R LMK316BJ475ML Taiyo-Yuden ©2001 Fairchild Semiconductor Corporation 10 ILC7082 TYPICAL PERFORMANCE CHARACTERISTICS ILC7082 Unless otherwise specified: TA = 25°C, VIN = VOUT(NOM) + 1V, ON/OFF pin tied to VIN Dropout Characteristics Output Voltage vs Temperature 3.4 3.015 3.01 IOUT = 0mA IOUT = 10mA IOUT = 50mA 3.3 3.005 VOUT (V) Output voltage (V) VOUT = 3.3V COUT = 1µF (Ceramic) VOUT = 3.0V COUT = 1µF (Ceramic) 3 2.995 3.2 IOUT = 100mA IOUT = 150mA 3.1 2.99 3 2.985 -50 0 50 100 3 150 3.2 3.6 VIN (V) Temperature (°C) Dropout Voltage vs Temperature Dropout Voltage vs IOUT 250 250 IOUT = 150mA VOUT = 3.0V VOUT = 3.0V 200 Dropout voltage (mV) Dropout voltage (mV) 3.4 IOUT = 100mA 150 100 IOUT = 50mA 50 TA = 85°C 200 TA = 25°C 150 100 TA = –40°C 50 IOUT = 0mA 0 0 –40 25 85 0 Temperature (°C) 100 150 Line Transient Response Ground Current vs Input Voltage 6 150 VIN (V) VOUT = 3.0 V IOUT = 10mA COUT = 1µF (Ceramic) IOUT = 50mA 125 IOUT = 150mA 5 VIN: tr/tf < 1 µs VOUT = 3.0V COUT = 2.2 µF (Ceramic IOUT = 100 mA IOUT = 0mA 4 100 VOUT (V) IGND (µA) 50 Output Current (mA) IOUT = 100mA 75 3.01 3.00 2.99 2.98 50 2 4 6 8 10 12 14 5µs/div VIN (V) ©2001 Fairchild Semiconductor Corporation 11 ILC7082 TYPICAL PERFORMANCE CHARACTERISTICS ILC7082 Unless otherwise specified: TA = 25°C, VIN = VOUT(NOM) + 1V, ON/OFF pin tied to VIN Load Transient Response VOUT (V) 3.15 3.10 Short Circuit Current VOUT = 3.0V COUT = 1 µF || 0.47 µF (Ceramic) 1.5 3.05 ISC (A) 3.00 IOUT (mA) 2.95 1.0 0.5 0 1 10 5 VOUT = 2.8V IOUT = 10mA COUT = 1µF Without CNOISE Capacitor On/Off Transient Response VON/OFF (V) 15 15 10 5 0 3 3 2 2 VOUT (V) 0 1 0 VOUT = 2.8V IOUT = 150mA Without CNOISE Capacitor COUT = 1µF 1 0 100µS/div 100µS/div 5 VOUT = 2.8V IOUT = 10mA CNOISE = 0.01µF, C OUT = 1µF VON/OFF (V) 10 On/Off Transient Response 15 10 5 0 0 3 3 2 2 VOUT (V) VOUT (V) VON/OFF (V) On/Off Transient Response 15 1 0 5mS/div 5ms/div t=0 On/Off Transient Response VON/OFF (V) Output Shorted to Gnd at time, t = 0 100 100µs/div VOUT (V) Thermal Cycling VIN = 4V VOUT = 2.8V IOUT = 150mA CNOISE = 0.01µF, C OUT = 1µF 1 0 5mS/div ©2001 Fairchild Semiconductor Corporation 12 ILC7082 TYPICAL PERFORMANCE CHARACTERISTICS ILC7082 Unless otherwise specified: TA = 25°C, VIN = VOUT(NOM) + 1V, ON/OFF pin tied to VIN Spectral Noise Density Spectral Noise Density 10 Noise (µV/Rt Hz) VOUT = 2.8V IOUT = 50mA CNOISE = 0.01µF 1 Noise (µV/Rt Hz) 10 COUT = 1µF (Ceramic 0.1 VOUT = 2.8V COUT = 2.2µF CNOISE = 0.01µ 1 IOUT = 50mA, 100mA or 150 mA 0.1 COUT = 2.2µF or 4.7µF (Ceramic) 0.01 0.01 IOUT = 1 mA COUT = 10µF (Ceramic) 0.001 0.001 10 100 1K 10K 1M 100K 10M 10 100 1K Frequency (Hz) Output Noise Voltage vs. CNOISE Output Noise Voltage vs. CNOISE 90 VOUT = 3V IOU = 10mA COUT = 2.2µF (Ceramic) CNOISE = 1.2nF 50 40 30 80 VOUT = 3V IOUT = 10mA COUT = 4.7µF(Ceramic) CNOISE = 1.2nF 70 5.6nF Noise (µVrms) Noise (µVrms) 70 60 8.2nF 0.039µF 0.047µF 20 0.022µF 60 50 40 5.6nF 8.2nF 0.039µF 30 20 0.01µF 10 0.047µF 100 Hz– 50 KHz 100 Hz– 100 KHz 300 Hz– 50 KHz 0.022µF 0.016µ 10 0 0 300 Hz– 100 KHz 100 Hz– 50 KHz 100 Hz– 100 KHz Freq Band 300 Hz– 50 KHz 300 Hz– 100 KHz Freq Band Ripple Rejection vs. Frequency Ripple Rejection vs. Frequency 80 120 Ripple Rejection (dB) VOUT = 3V IOUT = 10mA 100 Ripple Rejection (dB) 1M 100K Frequency (Hz) 90 80 10K COUT = 4.7µF 80 COUT = 10µF 60 COUT = 1µF 40 COUT = 2.2µF COUT = 4.7µF 60 50 40 30 COUT = 1µF COUT = 10µF 20 COUT = 2.2µF 20 VOUT = 2.8V IOUT = 150mA 70 10 0 0 10 100 1K 10K 100K Frequency (Hz) 1M 10M 10 100 1K 10K 100K 1M 10M Frequency (Hz) ©2001 Fairchild Semiconductor Corporation 13 ILC7082 Package Outline Dimensions Dimensions shown in mm and (inches). 8-Lead plastic surface mount (SOIC) 5.0 (.196) 4.8 (.189) 6.2 (.2440) 5.8 (.2284) 4.0 (.157) 3.8 (.150) PIN 1 0.127 bsc (.050 bsc) 0.25 (.0098) 0.19 (.0075) 0° - (8°) 1.27 (.050) 0.40 (0.16) 1.75 (.0688) 1.35 (.0532) Seating Plane 3.8 (.150) 4.0 (.157) 0.51 (.020) 0.33 (0.13) Package Outline Dimensions Dimensions shown in inches and (mm). 5-Lead plastic surface mount (SOT-23-5) 0.122 (3.10) 0.106 (2.70) 0.071 (1.80) 0.055 (1.40) 0.118 (3.00) 0.102 (2.60) PIN 1 0.037 (0.95) BSC 0.055 (1.40) 0.0393 (1.0) 0.0059 (0.15) 0.0019 (0.05) 0.057 (1.45) 0.035 (0.90) 0.019 (0.50) 0.0138 (0.35) SEATING PLANE 0.0078 (0.2) 0.0031 (0.08) 10° 0° 0.0217 (0.55) 0.0138 (0.35) ©2001 Fairchild Semiconductor Corporation 14 ILC7082 SOT-23 PACKAGE MARKINGS - ILC7082AIM5-XX Output Voltage (V) Grade *Package Order Information Marking Supplied as: 2.8 A ILC7082AIM5-28 EAXX 3k Units on Tape and Reel 2.85 A ILC7082AIM5-285 EJXX 3k Units on Tape and Reel 3.0 A ILC7082AIM5-30 EBXX 3k Units on Tape and Reel 3.1 A ILC7082AIM5-31 EHXX 3k Units on Tape and Reel 3.3 A ILC7082AIM5-33 ECXX 3k Units on Tape and Reel 3.6 A ILC7082AIM5-36 EDXX 3k Units on Tape and Reel 4.7 A ILC7082AIM5-47 EGXX 3k Units on Tape and Reel 5.0 A ILC7082AIM5-50 EEXX 3k Units on Tape and Reel ADJ A ILC7082AIM5-ADJ EFXX 3k Units on Tape and Reel * Note: First two characters identify the product and the last two characters identify the date code SOIC PACKAGE MARKINGS - ILC7082AIK-xx Output Voltage (V) Grade Order Information Package Marking Supplied as: 2.85 A ILC7082AIK-285 7082AIK285-XX 2,500 Units on Tape and Reel 3.3 A ILC7082AIK-33 7082AIK33-XX 2,500 Units on Tape and Reel Ordering Information Ordering Information (TA = -40°C to +85°C) ILC7082AIM5-xx 150mA, fixed voltage ILC7082AIM5-ADJ 150mA, adjustable voltage ILC7082AIK-xx 150mA, fixed voltage (soic-8) DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 10/15/01 0.0m 001 Stock#DSxxxxxxxx 2001 Fairchild Semiconductor Corporation