ISSI ® IS62LV12816LL 128K x 16 CMOS STATIC RAM NOVEMBER 2000 FEATURES DESCRIPTION • High-speed access time: 55, 70, 100 ns • CMOS low power operation – 120 mW (typical) operating – 6 µW (typical) CMOS standby • TTL compatible interface levels • Single 2.5V-3.45V VCC power supply • Fully static operation: no clock or refresh required • Three state outputs • Data control for upper and lower bytes • Industrial temperature available • Available in the 44-pin TSOP (Type II) and 48-pin mini BGA (6mm x 8mm) The ISSI IS62LV12816LL is a high-speed, 2,097,152-bit static RAM organized as 131,072 words by 16 bits. It is fabricated using ISSI 's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IS62LV12816LL is packaged in the JEDEC standard 44-pin TSOP (Type II) and 48-pin mini BGA. (6mm x 8mm) FUNCTIONAL BLOCK DIAGRAM A0-A16 DECODER 128K x 16 MEMORY ARRAY I/O DATA CIRCUIT COLUMN I/O VCC GND I/O0-I/O7 Lower Byte I/O8-I/O15 Upper Byte CE OE WE CONTROL CIRCUIT UB LB ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. D 12/15/00 1 ISSI IS62LV12816LL ® PIN CONFIGURATIONS 48-Pin mini BGA 44-Pin TSOP (Type II) A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 Vcc GND I/O4 I/O5 I/O6 I/O7 WE A16 A15 A14 A13 A12 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 A5 A6 A7 OE UB LB I/O15 I/O14 I/O13 I/O12 GND Vcc I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 NC A 1 2 3 4 5 6 LB OE A0 A1 A2 N/C CE I/O0 B I/O8 UB A3 A4 C I/O9 I/O10 A5 A6 I/O1 I/O2 D GND I/O11 NC A7 I/O3 Vcc E Vcc I/O12 NC A16 I/O4 GND F I/O14 I/O13 A14 A15 I/O5 I/O6 G I/O15 NC A12 A13 WE I/O7 H NC A8 A9 A10 A11 NC PIN DESCRIPTIONS A0-A16 Address Inputs LB Lower-byte Control (I/O0-I/O7) I/O0-I/O15 Data Inputs/Outputs UB Upper-byte Control (I/O8-I/O15) CE Chip Enable Input NC No Connection OE Output Enable Input Vcc Power WE Write Enable Input GND Ground TRUTH TABLE Mode Not Selected Output Disabled Read Write 2 WE CE OE LB UB X H X H H H L L L H L L L L L L L L X H X L L L X X X X X H L H L L H L X X H H L L H L L I/O PIN I/O0-I/O7 I/O8-I/O15 High-Z High-Z High-Z DOUT High-Z DOUT DIN High-Z DIN High-Z High-Z High-Z High-Z DOUT DOUT High-Z DIN DIN Vcc Current ISB1, ISB2 I CC ICC ICC Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. D 12/15/00 ISSI IS62LV12816LL ® OPERATING RANGE Range Commercial Industrial Ambient Temperature 0°C to +70°C –40°C to +85°C VCC 2.5V - 3.45V 2.5V - 3.45V 1 2 ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM TBIAS VCC TSTG PT Parameter Terminal Voltage with Respect to GND Temperature Under Bias Vcc Related to GND Storage Temperature Power Dissipation Value –0.5 to Vcc+0.5 –40 to +85 –0.3 to +4.0 –65 to +150 1.0 Unit V °C V °C W 3 4 Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 5 6 DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol Parameter Test Conditions Min. Max. Unit VOH Output HIGH Voltage VCC = Min., IOH = –1 mA 2.0 — V VOL Output LOW Voltage VCC = Min., IOL = 2.1 mA — 0.4 V VIH VIL(1) Input HIGH Voltage 2.2 VCC + 0.2 V Input LOW Voltage –0.2 0.4 V ILI Input Leakage GND ≤ VIN ≤ VCC –1 1 µA ILO Output Leakage GND ≤ VOUT ≤ VCC, Outputs Disabled –1 1 µA 7 8 9 Notes: 1. VIL (min.) = –2.0V for pulse width less than 10 ns. 10 CAPACITANCE(1) Symbol Parameter CIN Input Capacitance COUT Input/Output Capacitance 11 Conditions Max. Unit VIN = 0V 6 pF VOUT = 0V 8 pF 12 Note: 1. Tested initially and after any design or process changes that may affect these parameters. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. D 12/15/00 3 ISSI IS62LV12816LL ® AC TEST CONDITIONS Parameter Unit Input Pulse Level 0.4V to 2.2V Input Rise and Fall Times 5 ns Input and Output Timing and Reference Level 1.3V Output Load See Figures 1 and 2 AC TEST LOADS 3070 Ω 3070 Ω 3.0V 3.0V OUTPUT OUTPUT 100 pF Including jig and scope 3150 Ω 3150 Ω 5 pF Including jig and scope Figure 1 Figure 2 POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) -55 Min. Max. -70 Min. Max. -100 Min. Max. Symbol Parameter Test Conditions Unit ICC Vcc Dynamic Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX Com. Ind. — — 40 60 — — 30 50 — — 20 40 mA ISB1 TTL Standby Current (TTL Inputs) VCC = Max., VIN = VIH or VIL CE ≥ VIH , f = 0 Com. Ind. — — 0.4 1.0 — — 0.4 1.0 — — 0.4 1.0 mA ISB2 CMOS Standby Current (CMOS Inputs) VCC = Max., CE ≥ VCC – 0.2V, VIN ≥ VCC – 0.2V, or VIN ≤ 0.2V, f = 0 Com. Ind. — — 5 5 — — 5 5 — — 5 5 µA Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 4 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. D 12/15/00 ISSI IS62LV12816LL ® READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter Min. -55 Max. Min. -70 Max. -100 Min. Max. tRC Read Cycle Time 55 — 70 — 100 — ns tAA Address Access Time — 55 — 70 — 100 ns tOHA Output Hold Time 10 — 10 — 15 — ns tACE CE Access Time — 55 — 70 — 100 ns OE Access Time — 30 — 35 — 50 ns OE to High-Z Output — 20 — 25 — 30 ns tLZOE(2) OE to Low-Z Output 5 — 5 — 5 — ns tHZCE(2) CE to High-Z Output 0 20 0 25 0 30 ns tLZCE CE to Low-Z Output 10 — 10 — 10 — ns tBA LB, UB Access Time — 20 — 35 — 50 ns tHZB LB, UB to High-Z Output 0 25 0 25 0 35 ns tLZB LB, UB to Low-Z Output 0 — 0 — 0 — ns tDOE tHZOE (2) (2) 1 Unit 2 3 4 5 Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0.4 to 2.2V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 6 7 AC WAVEFORMS 8 READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIL, UB or LB = VIL) 9 tRC ADDRESS tAA tOHA DOUT PREVIOUS DATA VALID 10 tOHA DATA VALID 11 12 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. D 12/15/00 5 ISSI IS62LV12816LL ® AC WAVEFORMS READ CYCLE NO. 2(1,3) (CS, OE, AND UB/LB Controlled) tRC ADDRESS tAA tOHA OE tHZOE tDOE tLZOE CE tACE tHZCE tLZCE LB, UB tBA DOUT HIGH-Z tHZB tLZB DATA VALID Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE, UB, or LB = VIL. 3. Address is valid prior to or coincident with CE LOW transition. WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range) Symbol Parameter Min. -55 Max. Min. -70 Max. -100 Min. Max. Unit tWC Write Cycle Time 55 — 70 — 100 — ns tSCE CE to Write End 50 — 65 — 80 — ns tAW Address Setup Time to Write End 50 — 65 — 80 — ns tHA Address Hold from Write End 0 — 0 — 0 — ns tSA Address Setup Time 0 — 0 — 0 — ns tPWB LB, UB Valid to End of Write 45 — 60 — 80 — ns tPWE WE Pulse Width 45 — 60 — 80 — ns tSD Data Setup to Write End 25 — 30 — 40 — ns tHD Data Hold from Write End 0 — 0 — 0 — ns tHZWE(3) WE LOW to High-Z Output — 30 — 30 — 40 ns tLZWE WE HIGH to Low-Z Output 5 — 5 — 5 — ns (3) Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0.4V to 2.2V and output loading specified in Figure 1. 2. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 6 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. D 12/15/00 ISSI IS62LV12816LL ® AC WAVEFORMS WRITE CYCLE NO. 1(1,2) (CS Controlled, OE = HIGH or LOW) 1 t WC 2 VALID ADDRESS ADDRESS t SA t SCS t HA CS 3 t AW t PWE1 t PWE2 WE 4 t PBW UB, LB t HZWE DOUT DATA UNDEFINED HIGH-Z t SD DIN 5 t LZWE t HD 6 DATAIN VALID UB_CSWR1.eps Notes: 1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CS and WE inputs and at least one of the LB and UB inputs being in the LOW state. 2. WRITE = (CS) [ (LB) = (UB) ] (WE). 7 8 9 10 11 12 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. D 12/15/00 7 ISSI IS62LV12816LL ® WRITE CYCLE NO. 2 (WE Controlled: OE is HIGH During Write Cycle) t WC ADDRESS VALID ADDRESS t HA OE CS LOW t AW t PWE1 WE t SA t PBW UB, LB t HZWE DOUT t LZWE HIGH-Z DATA UNDEFINED t SD t HD DATAIN VALID DIN UB_CSWR2.eps WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle) t WC ADDRESS VALID ADDRESS OE LOW CS LOW t HA t AW t PWE2 WE t SA t PBW UB, LB t HZWE DOUT DATA UNDEFINED t LZWE HIGH-Z t SD DIN t HD DATAIN VALID UB_CSWR3.eps 8 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. D 12/15/00 ISSI IS62LV12816LL ® DATA RETENTION SWITCHING CHARACTERISTICS Symbol Parameter Test Condition Min. Max. Unit VDR Vcc for Data Retention See Data Retention Waveform 1.5 3.45 V IDR Data Retention Current Vcc = 2.0V, CE ≥ Vcc – 0.2V — 5 µA tSDR tRDR Data Retention Setup Time See Data Retention Waveform 0 — ns Recovery Time See Data Retention Waveform tRC — ns 1 2 3 DATA RETENTION WAVEFORM (CE Controlled) tSDR Data Retention Mode 4 tRDR VCC 2.3V 2.0V 5 VDR CE GND CE ≥ VCC — 0.2V 6 7 8 9 10 11 12 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. D 12/15/00 9 ISSI IS62LV12816LL ® ORDERING INFORMATION Commercial Range: 0°C to +70°C Speed (ns) Industrial Range: –40°C to +85°C Speed (ns) Order Part No. Package Order Part No. Package 55 IS62LV12816LL-55T IS62LV12816LL-55B TSOP (Type II) Mini BGA (6mm x 8mm) 55 IS62LV12816LL-55TI TSOP (Type II) IS62LV12816LL-55BI Mini BGA 70 IS62LV12816LL-70T IS62LV12816LL-70B TSOP (Type II) Mini BGA (6mm x 8mm) 70 IS62LV12816LL-70TI TSOP (Type II) IS62LV12816LL-70BI Mini BGA 100 IS62LV12816LL-10T IS62LV12816LL-10B TSOP (Type II) Mini BGA (6mm x 8mm) 100 IS62LV12816LL-10TI TSOP (Type II) IS62LV12816LL-10BI Mini BGA (6mm x 8mm) ISSI ® Integrated Silicon Solution, Inc. 2231 Lawson Lane Santa Clara, CA 95054 Tel: 1-800-379-4774 Fax: (408) 588-0806 E-mail: [email protected] www.issi.com 10 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. D 12/15/00