® ispLSI 2128/A In-System Programmable High Density PLD Features Functional Block Diagram • ENHANCEMENTS fmax = 100 MHz Maximum Operating Frequency tpd = 10 ns Propagation Delay • IN-SYSTEM PROGRAMMABLE D0 C7 A1 C6 A2 A3 Logic Array A4 A5 D Q D Q D Q D Q C5 C4 GLB C3 C2 A6 C1 Global Routing Pool (GRP) A7 B0 B1 B2 B3 N Output Routing Pool (ORP) B4 B5 C0 B6 B7 Output Routing Pool (ORP) A0 S Output Routing Pool (ORP) D1 Output Routing Pool (ORP) 0139(9A)/2128 Description R TTL Compatible Inputs and Outputs Electrically Erasable and Reprogrammable Non-Volatile 100% Tested at Time of Manufacture Unused Product Term Shutdown Saves Power D2 The ispLSI 2128 and 2128A are High Density Programmable Logic Devices. The devices contains128 Registers, 128 Universal I/O pins, eight Dedicated Input pins, three Dedicated Clock Input pins, two dedicated Global OE input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 2128 and 2128A feature 5V insystem programmability and in-system diagnostic capabilities. The ispLSI 2128 and 2128A offer nonvolatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. FO — — — — — — — D4 CLK 0 CLK 1 CLK 2 • HIGH PERFORMANCE E2CMOS® TECHNOLOGY D3 D5 ES IG N 6000 PLD Gates 128 I/O Pins, Eight Dedicated Inputs 128 Registers High Speed Global Interconnect Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Random Logic Output Routing Pool (ORP) — — — — — Output Routing Pool (ORP) D6 D • HIGH DENSITY PROGRAMMABLE LOGIC Output Routing Pool (ORP) D7 EW Output Routing Pool (ORP) — ispLSI 2128A is Fully Form and Function Compatible to the ispLSI 2128, with Identical Timing Specifcations and Packaging — ispLSI 2128A is Built on an Advanced 0.35 Micron E2CMOS® Technology 8E — In-System Programmable (ISP™) 5V Only — Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality — Reprogram Soldered Devices for Faster Prototyping I2 12 • OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS LS — Complete Programmable Device Can Combine Glue Logic and Structured Designs — Enhanced Pin Locking Capability — Three Dedicated Clock Input Pins — Synchronous and Asynchronous Clocks — Programmable Output Slew Rate Control to Minimize Switching Noise — Flexible Pin Placement — Optimized Global Routing Pool Provides Global Interconnectivity U SE is p The basic unit of logic on these devices is the Generic Logic Block (GLB). The GLBs are labeled A0, A1 .. D7 (Figure 1). There are a total of 32 GLBs in the ispLSI 2128 and 2128A devices. Each GLB is made up of four macrocells. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any GLB on the device. Copyright © 2002 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com 2128_09 1 January 2002 Specifications ispLSI 2128/A Functional Block Diagram SDI/IN 7 SDO/IN 6 I/O 99 I/O 98 I/O 97 I/O 96 I/O 103 I/O 102 I/O 101 I/O 100 I/O 107 I/O 106 I/O 105 I/O 104 I/O 111 I/O 110 I/O 109 I/O 108 I/O 115 I/O 114 I/O 113 I/O 112 I/O 119 I/O 118 I/O 117 I/O 116 I/O 123 I/O 122 I/O 121 I/O 120 I/O 127 I/O 126 I/O 125 I/O 124 Figure 1. ispLSI 2128/A Functional Block Diagram RESET Input Bus GOE 0 GOE 1 Output Routing Pool (ORP) S Output Routing Pool (ORP) Megablock D7 D6 D5 D4 D2 D3 D1 IN 5 IN 4 D0 D ES IG N Generic Logic Blocks (GLBs) I/O 95 I/O 94 I/O 93 I/O 92 A0 FO R C2 C1 C0 E A7 SCLK/IN 0 MODE/IN 1 B0 B1 B2 B3 B5 B4 Output Routing Pool (ORP) I/O 83 I/O 82 I/O 81 I/O 80 I/O 79 I/O 78 I/O 77 I/O 76 I/O 75 I/O 74 I/O 73 I/O 72 I/O 71 I/O 70 I/O 69 I/O 68 I/O 67 I/O 66 I/O 65 I/O 64 B7 B6 Output Routing Pool (ORP) CLK 0 CLK 1 CLK 2 I/O 28 I/O 29 I/O 30 I/O 31 C3 A6 28 I/O 24 I/O 25 I/O 26 I/O 27 A5 I/O 87 I/O 86 I/O 85 I/O 84 C4 A4 21 I/O 20 I/O 21 I/O 22 I/O 23 Global Routing Pool (GRP) A3 Output Routing Pool (ORP) I/O 16 I/O 17 I/O 18 I/O 19 A2 Input Bus I/O 12 I/O 13 I/O 14 I/O 15 C5 I/O 91 I/O 90 I/O 89 I/O 88 Input Bus I/O 8 I/O 9 I/O 10 I/O 11 A1 EW I/O 4 I/O 5 I/O 6 I/O 7 N Output Routing Pool (ORP) C6 Output Routing Pool (ORP) I/O 0 I/O 1 I/O 2 I/O 3 Output Routing Pool (ORP) C7 Y0 Y1 Y2 I/O 60 I/O 61 I/O 62 I/O 63 I/O 56 I/O 57 I/O 58 I/O 59 I/O 52 I/O 53 I/O 54 I/O 55 I/O 48 I/O 49 I/O 50 I/O 51 I/O 44 I/O 45 I/O 46 I/O 47 I/O 40 I/O 41 I/O 42 I/O 43 I/O 36 I/O 37 I/O 38 I/O 39 pL IN 2 IN 3 ispEN I/O 32 I/O 33 I/O 34 I/O 35 SI Input Bus 0139(10A)/2128 The GRP has as its inputs, the outputs from all of the GLBs and all of the inputs from the bi-directional I/O cells. All of these signals are made available to the inputs of the GLBs. Delays through the GRP have been equalized to minimize timing skew. SE is The device also has 128 I/O cells, each of which is directly connected to an I/O pin. Each I/O cell can be individually programmed to be a combinatorial input, output or bi-directional I/O pin with 3-state control. The signal levels are TTL compatible voltages and the output drivers can source 4 mA or sink 8 mA. Each output can be programmed independently for fast or slow output slew rate to minimize overall output switching noise. U Clocks in the ispLSI 2128 and 2128A devices are selected using the dedicated clock pins. Three dedicated clock pins (Y0, Y1, Y2) or an asynchronous clock can be selected on a GLB basis. The asynchronous or Product Term clock can be generated in any GLB for its own clock. Eight GLBs, 32 I/O cells, two dedicated inputs and two ORPs are connected together to make a Megablock (Figure 1). The outputs of the eight GLBs are connected to a set of 32 universal I/O cells by the two ORPs. Each ispLSI 2128 and 2128A device contains four Megablocks. 2 Specifications ispLSI 2128/A Absolute Maximum Ratings 1 Supply Voltage Vcc .................................. -0.5 to +7.0V Input Voltage Applied ........................ -2.5 to VCC +1.0V Off-State Output Voltage Applied ..... -2.5 to VCC +1.0V S Storage Temperature ................................ -65 to 150°C D ES IG N Case Temp. with Power Applied .............. -55 to 125°C Max. Junction Temp. (TJ) with Power Applied ... 150°C 1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). SYMBOL EW DC Recommended Operating Condition PARAMETER VIL VIH Input Low Voltage 4.75 5.25 V Industrial TA = -40°C to + 85°C 4.5 5.5 V 0 0.8 V 2.0 Vcc+1 TYPICAL UNITS I/O and Dedicated Input Capacitance 8 pf VCC = 5.0V, VI/O, IN = 2.0V Clock Capacitance 15 pf VCC = 5.0V, VY = 2.0V 21 28 PARAMETER V Table 2 - 0005/2128 FO E Capacitance (TA=25°C, f=1.0 MHz) C1 C2 UNITS TA = 0°C to + 70°C Input High Voltage SYMBOL MAX. Commercial N Supply Voltage R VCC MIN. TEST CONDITIONS Table 2-0006/2128 SI Data Retention Specifications pL PARAMETER Data Retention MINIMUM MAXIMUM UNITS 20 – Years 10,000 – Cycles is Erase/Reprogram Cycles U SE Table 2-0008/2128 3 Specifications ispLSI 2128/A Switching Test Conditions Input Pulse Levels Figure 2. Test Load GND to 3.0V Input Rise and Fall Time ≤ 3ns 10% to 90% Input Timing Reference Levels 1.5V Output Timing Reference Levels 1.5V R1 3-state levels are measured 0.5V from steady-state Table 2 - 0003/2000 active level. S See Figure 2 Device Output D ES IG N Output Load + 5V B C R2 CL 470Ω 390Ω 35pF Active High ∞ 390Ω 35pF Active Low 470Ω 390Ω 35pF Active High to Z at VOH -0.5V ∞ 390Ω 5pF Active Low to Z at VOL +0.5V 470Ω 390Ω 5pF *CL includes Test Fixture and Probe Capacitance. 0213A EW A R1 N TEST CONDITION C L* R2 Output Load Conditions (see Figure 2) Test Point R Table 2 - 0004A/2000 FO DC Electrical Characteristics Over Recommended Operating Conditions SYMBOL – – 0.4 V IOH = -4 mA 2.4 – – V 0V ≤ VIN ≤ VIL (Max.) – – -10 µA Input or I/O High Leakage Current 3.5V ≤ VIN ≤ VCC – – 10 µA ispEN Input Low Leakage Current 0V ≤ VIN ≤ VIL – – -150 µA I/O Active Pull-Up Current 0V ≤ VIN ≤ VIL – – -150 µA Output Short Circuit Current VCC = 5V, VOUT = 0.5V Operating Power Supply Current VIL = 0.0V, VIH = 3.0V fCLOCK = 1 MHz – – – – 165 165 -200 325 – mA mA mA E 28 Output High Voltage SI 21 Input or I/O Low Leakage Current Commercial Industrial MAX. UNITS Table 2-0007/2128 is ICC2, 4 IOL= 8 mA pL VOL VOH IIL IIH IIL-isp IIL-PU IOS1 TYP. Output Low Voltage CONDITION 3 MIN. PARAMETER U SE 1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test problems by tester ground degradation. Characterized but not 100% tested. 2. Measured using eight 16-bit counters. 3. Typical values are at VCC = 5V and TA = 25°C. 4. Maximum I CC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption section of this data sheet and the Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum I CC . 4 Specifications ispLSI 2128/A External Timing Parameters Over Recommended Operating Conditions 4 -100 1 -80 MIN. MAX. MIN. MAX. UNITS 1 Data Propagation Delay, 4PT Bypass, ORP Bypass – 10.0 – 15.0 ns 2 Data Propagation Delay – 13.0 – 18.5 ns 100 – 81.0 – MHz 77.0 – 57.0 – MHz 100 – 83.0 – MHz 6.5 – 9.0 – ns – 5.0 – 6.5 ns 0.0 – 0.0 – ns 8.0 – 11.0 – ns – 6.0 – 8.0 ns 0.0 – 0.0 – ns – 13.5 – 17.0 ns 6.5 – 10.0 – ns – 15.0 – 18.0 ns – 15.0 – 18.0 ns 3 Clock Frequency with Internal Feedback – 4 Clock Frequency with External Feedback ( – 5 Clock Frequency, Max. Toggle 1 tsu2 + tco1 ) 6 GLB Reg. Setup Time before Clock, 4 PT Bypass 7 GLB Reg. Clock to Output Delay, ORP Bypass – 8 GLB Reg. Hold Time after Clock, 4 PT Bypass – 9 GLB Reg. Setup Time before Clock – 10 GLB Reg. Clock to Output Delay 11 GLB Reg. Hold Time after Clock 12 Ext. Reset Pin to Output Delay – 13 Ext. Reset Pulse Duration B 14 Product Term OE, Enable C 15 Product Term OE, Disable N – A EW – A D ES IG N A 3 S A A – 9.0 – 12.0 ns – 9.0 – 12.0 ns 18 External Synchronous Clock Pulse Duration, High 5.0 – 6.0 – ns 19 External Synchronous Clock Pulse Duration, Low 5.0 – 6.0 – ns B 16 Global OE, Enable C 17 Global OE, Disable – – 28 E Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock. Refer to Timing Model in this data sheet for further details. Standard 16-bit counter using GRP feedback. Reference Switching Test Conditions section. U SE is pL SI 21 1. 2. 3. 4. DESCRIPTION R tpd1 tpd2 fmax fmax (Ext.) fmax (Tog.) tsu1 tco1 th1 tsu2 tco2 th2 tr1 trw1 tptoeen tptoedis tgoeen tgoedis twh twl TEST 2 # COND. FO PARAMETER 5 Table 2-0030B/2128-100 Specifications ispLSI 2128/A Internal Timing Parameters1 Over Recommended Operating Conditions PARAMETER #2 -80 -100 DESCRIPTION MIN. MAX. MIN. MAX. UNITS Inputs 20 Input Buffer Delay – 0.5 – 1.8 ns 21 Dedicated Input Delay – 2.2 – 4.4 ns tgrp D ES IG N GRP 22 GRP Delay GLB t4ptbpc t4ptbpr t1ptxor t20ptxor txoradj tgbp tgsu tgh tgco tgro tptre tptoe tptck 23 4 Product Term Bypass Path Delay 24 4 Product Term Bypass Path Delay 25 1 Product Term/XOR Path Delay 26 20 Product Term/XOR Path Delay 28 GLB Register Bypass Delay 30 GLB Register Hold Time after Clock R 31 GLB Register Clock to Output Delay – 1.7 – 2.6 ns – 5.8 – 8.1 ns – 5.8 – 6.8 ns – 6.8 – 8.0 ns – 7.3 – 8.8 ns – 8.0 – 9.8 ns – 0.5 – 1.3 ns 1.2 – 1.4 – ns 4.0 – 6.0 – ns – 0.3 – 0.4 ns – 1.3 – 1.6 ns 33 GLB Product Term Reset to Register Delay – 6.1 – 8.6 ns 34 GLB Product Term Output Enable to I/O Cell Delay – 8.6 – 9.0 ns 4.1 7.1 5.6 10.2 ns – 1.4 – 2.0 ns – 0.4 – 0.5 ns 38 Output Buffer Delay – 1.6 – 2.0 ns 39 Output Slew Limited Delay Adder – 10.0 – 10.0 ns 40 I/O Cell OE to Output Enabled – 4.2 – 4.6 ns 41 I/O Cell OE to Output Disabled – 4.2 – 4.6 ns 42 Global Output Enable – 4.8 – 7.4 ns 43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) 2.7 2.7 3.6 3.6 ns 44 Clock Delay, Y1 or Y2 to Global GLB Clock Line 2.7 2.7 3.6 3.6 ns – 9.2 – 11.4 ns E 35 GLB Product Term Clock Delay FO 32 GLB Register Reset to Output Delay 36 ORP Delay 21 37 ORP Bypass Delay 28 torp torpbp Outputs SE is pL SI tob tsl toen todis tgoe tgy0 tgy1/2 N 29 GLB Register Setup Time befor Clock ORP Clocks 3 EW 27 XOR Adjacent Path Delay S tio tdin Global Reset U tgr 45 Global Reset to GLB 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros. 6 Table 2- 0036C/2128-100 Specifications ispLSI 2128/A ispLSI 2128/A Timing Model I/O Cell GRP GLB ORP I/O Cell Feedback I/O Delay GRP Reg 4 PT Bypass GLB Reg Bypass ORP Bypass #20 #22 #24 #28 #37 20 PT XOR Delays GLB Reg Delay ORP Delay D #25 - 27 Q RST #45 Reset #29 - 32 Control RE PTs OE #33 - 35 CK EW #42 N GOE0, 1 R Derivations of tsu, th and tco from the Product Term Clock Logic + Reg su - Clock (min) (tio + tgrp + t20ptxor) + (tgsu) - (tio + tgrp + tptck(min)) (#20+ #22+ #26) + (#29) - (#20+ #22+ #35) (0.5 + 1.7 + 7.3) + (1.2) + (0.5 + 1.7 + 4.1) th Clock (max) + Reg h - Logic (tio + tgrp + tptck(max)) + (tgh) - (tio + tgrp + t20ptxor) (#20+ #22+ #35) + (#30) - (#20+ #22+ #26) (0.5 + 1.7 + 7.1) + ( 4.0) + (0.5 + 1.7 + 7.3) tco Clock (max) + Reg co + Output (tio + tgrp + tptck(max)) + (tgco) + (torp + tob) (#20+ #22+ #35) + (#31) + (#36 + #38) (0.5 + 1.7 + 7.1) + (0.3) + (1.4 + 1.6) E 28 pL = = = 12.6 ns = 21 = = = 3.8 ns = SI = = = 4.4 ns = FO tsu Table 2-0042/2128 U SE is Note: Calculations are based upon timing specifications for the ispLSI 2128/A-100L. 7 #36 #40, 41 #43, 44 Y0,1,2 #38, 39 0491 I/O Pin (Output) S I/O Pin (Input) Comb 4 PT Bypass #23 #21 D ES IG N Ded. In Specifications ispLSI 2128/A Power Consumption used. Figure 4 shows the relationship between power and operating speed. Power consumption in the ispLSI 2128 and 2128A devices depends on two primary factors: the speed at which the device is operating and the number of Product Terms ICC (mA) 300 ispLSI 2128/A 250 200 150 0 20 EW 100 D ES IG N S Figure 4. Typical Device Power Consumption vs fmax 40 60 80 fmax (MHz) 100 N Notes: Configuration of eight 16-bit counters Typical current at 5V, 25° C R ICC can be estimated for the ispLSI 2128/A using the following equation: FO ICC (mA) = 20 + (# of PTs * 0.48) + (# of nets * Max freq * 0.009) 28 E Where: # of PTs = Number of Product Terms used in design # of nets = Number of Signals used in device Max freq = Highest Clock Frequency to the device (in MHz) 21 The ICC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of two GLB loads on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions and the program in the device, the actual ICC should be verified. U SE is pL SI 0127B/2128 8 Specifications ispLSI 2128/A Pin Description PQFP/MQFP PIN NUMBERS 100, 99, 110, 109, RESET 20 22 Y0, Y1, Y2 18, 19, 101 19, 21, 111 ispEN 21 23 SDI/IN 72 22 SCLK/IN 02 23 MODE/IN 12 24 VCC NC1 pL SI 21 U GND 114 1, 81, 12, 111, 10, 107, 31, 131, 27, 45, 63, 125, 143 51, 71, 91, 151 1, 89, 13, 122, 20, 74, 128, 11, 117, 34, 144, 30, 84, 142, 29, 137, 56, 166 40, 98, 152, Active Low (0) Reset pin which resets all of the GLB registers in the device. Dedicated Clock inputs. These clock inputs are connected to one of the clock inputs of all the GLBs on the device. Input - Dedicated in-system programming enable input pin. This pin is brought low to enable the programming mode. The MODE, SDI, SDO and SCLK options become active. Input - This pin performs two functions. When ispEN is logic low, it functions as an input pin to load programming data into the device. SDI is also used as one of the two control pins for the isp state machine. When ispEN is high, it functions as a dedicated input pin. Input - This pin performs two functions. When ispEN is logic low, it functions as a clock pin for the Serial Shift Register. When ispEN is high, it functions as a dedicated input pin. Input - This pin performs two functions. When ispEN is logic low, it functions as pin to control the operation of the isp state machine. When ispEN is high, it functions as a dedicated input pin. Output/Input - This pin performs two functions. When ispEN is logic low, it functions as the pin to read the isp data. When ispEN is high, it functions as a dedicated input pin. 25 104 is SE SDO/IN 62 Dedicated input pins to the device. Global Output Enable input pins. 24 26 S GOE 0, GOE 1 R 106, 107, 112, 113 33, Input/Output Pins - These are the general purpose I/O pins 39, used by the logic array. 45, 51, 58, 63, 70, 76, 82, 88, 94, 101, 115, 123, 129, 134, 140, 147, 153, 159, 165, 171, 2, 7, 15, D ES IG N 32, 38, 44, 50, 57, 62, 68, 75, 81, 87, 93, 99, 105, 121, 127, 133, 139, 146, 151, 158, 164, 170, 176, 6, 14, 97, 98, 102, 103 30, 36, 41, 47, 53, 58, 64, 69, 75, 80, 86, 92, 105, 112, 117, 122, 128, 134, 139, 145, 150, 156, 2, 7, 14, EW 31, 37, 43, 48, 55, 61, 67, 73, 80, 86, 92, 97, 104, 120, 126, 132, 138, 145, 150, 156, 163, 169, 175, 5, 12, 18 IN 2 - IN 5 29, 35, 40, 46, 52, 57, 62, 68, 74, 79, 85, 90, 96, 110, 116, 121, 127, 133, 138, 144, 149, 155, 160, 6, 13, DESCRIPTION N 28, 36, 42, 47, 53, 60, 66, 72, 79, 85, 91, 96, 103, 119, 125, 131, 136, 143, 149, 155, 161, 168, 174, 4, 9, 17, 25, 32, 37, 42, 48, 54, 59, 65, 70, 76, 82, 87, 93, 106, 113, 118, 123, 129, 135, 140, 146, 152, 157, 3, 8, 15, FO 28, 34, 39, 44, 50, 56, 61, 67, 73, 78, 84, 89, 95, 109, 115, 120, 126, 132, 137, 142, 148, 154, 159, 5, 11, 17 27, 35, 41, 46, 52, 59, 65, 71, 77, 83, 90, 95, 102, 116, 124, 130, 135, 141, 148, 154, 160, 167, 173, 3, 8, 16, I/O 0 - I/O 4 I/O 5 - I/O 9 I/O 10 - I/O 14 I/O 15 - I/O 19 I/O 20 - I/O 24 I/O 25 - I/O 29 I/O 30 - I/O 34 I/O 35 - I/O 39 I/O 40 - I/O 44 I/O 45 - I/O 49 I/O 50 - I/O 54 I/O 55 - I/O 59 I/O 60 - I/O 64 I/O 65 - I/O 69 I/O 70 - I/O 74 I/O 75 - I/O 79 I/O 80 - I/O 84 I/O 85 - I/O 89 I/O 90 - I/O 94 I/O 95 - I/O 99 I/O 100 - I/O 104 I/O 105 - I/O 109 I/O 110 - I/O 114 I/O 115 - I/O 119 I/O 120 - I/O 124 I/O 125 - I/O 127 E 26, 33, 38, 43, 49, 55, 60, 66, 72, 77, 83, 88, 94, 108, 114, 119, 124, 130, 136, 141, 147, 153, 158, 4, 9, 16, TQFP PIN NUMBERS 28 NAME 49, 69, Ground (GND) 157 78, 100, VCC (+5V) 54, 64, No Connect. 108, 118 162, 172 1. NC pins are not to be connected to any active signals, VCC or GND. 2. Pins have dual function capability. 9 Table 2-0002/2128 Specifications ispLSI 2128/A Pin Configuration EW 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 21 28 E FO R Top View N ispLSI 2128/A 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 I/O 77 I/O 76 I/O 75 I/O 74 I/O 73 I/O 72 I/O 71 I/O 70 I/O 69 VCC I/O 68 I/O 67 I/O 66 GND I/O 65 I/O 64 SDO/IN 61 IN 5 IN 4 Y2 GOE 0 GOE 1 IN 3 IN 2 I/O 63 I/O 62 I/O 61 I/O 60 I/O 59 VCC I/O 58 I/O 57 I/O 56 I/O 55 I/O 54 I/O 53 I/O 52 I/O 51 I/O 50 GND SE is I/O 14 I/O 15 I/O 16 I/O 17 GND I/O 18 I/O 19 I/O 20 I/O 21 I/O 22 VCC I/O 23 I/O 24 I/O 25 I/O 26 I/O 27 I/O 28 I/O 29 I/O 30 I/O 31 I/O 32 I/O 33 GND I/O 34 I/O 35 I/O 36 I/O 37 I/O 38 I/O 39 I/O 40 VCC I/O 41 I/O 42 I/O 43 I/O 44 I/O 45 I/O 46 I/O 47 I/O 48 I/O 49 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 pL SI GND I/O 114 I/O 115 I/O 116 I/O 117 I/O 118 I/O 119 I/O 120 I/O 121 GND I/O 122 VCC I/O 123 I/O 124 I/O 125 I/O 126 I/O 127 Y0 Y1 RESET ispEN 1SDI/IN 7 1 SCLK/IN 0 1MODE/IN 1 I/O 0 I/O 1 GND I/O 2 I/O 3 I/O 4 VCC I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 D ES IG N S 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 I/O 113 I/O 112 I/O 111 I/O 110 I/O 109 I/O 108 I/O 107 I/O 106 I/O 105 VCC I/O 104 I/O 103 I/O 102 I/O 101 I/O 100 I/O 99 I/O 98 GND I/O 97 I/O 96 I/O 95 I/O 94 I/O 93 I/O 92 I/O 91 I/O 90 I/O 89 I/O 88 I/O 87 VCC I/O 86 I/O 85 I/O 84 I/O 83 I/O 82 GND I/O 81 I/O 80 I/O 79 I/O 78 ispLSI 2128/A 160-Pin PQFP Pinout Diagram U 1. Pins have dual function capability. 160-PQFP/2128A 10 Specifications ispLSI 2128/A Pin Configuration 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 I/O 77 I/O 76 I/O 75 I/O 74 NC1 I/O 73 I/O 72 I/O 71 I/O 70 I/O 69 VCC I/O 68 I/O 67 I/O 66 NC1 GND I/O 65 I/O 64 SDO/IN 62 IN 5 IN 4 Y2 GOE 0 GOE 1 NC1 IN 3 IN 2 I/O 63 I/O 62 I/O 61 I/O 60 I/O 59 VCC I/O 58 NC1 I/O 57 I/O 56 I/O 55 I/O 54 I/O 53 I/O 52 I/O 51 I/O 50 GND EW D ES IG N 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 SI 21 28 E FO R Top View N ispLSI 2128/A is I/O 14 I/O 15 I/O 16 I/O 17 GND I/O 18 I/O 19 I/O 20 I/O 21 1 NC I/O 22 VCC I/O 23 I/O 24 I/O 25 I/O 26 I/O 27 I/O 28 I/O 29 1NC I/O 30 I/O 31 I/O 32 I/O 33 GND I/O 34 I/O 35 I/O 36 I/O 37 1NC I/O 38 I/O 39 I/O 40 VCC I/O 41 I/O 42 I/O 43 I/O 44 I/O 45 1NC I/O 46 I/O 47 I/O 48 I/O 49 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 pL GND I/O 114 I/O 115 I/O 116 I/O 117 I/O 118 I/O 119 I/O 120 I/O 121 1NC GND I/O 122 VCC I/O 123 I/O 124 I/O 125 I/O 126 I/O 127 Y0 1NC Y1 RESET ispEN 2SDI/IN 7 2SCLK/IN 0 2MODE/IN 1 I/O 0 I/O 1 GND 1NC I/O 2 I/O 3 I/O 4 VCC I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 1NC I/O 10 I/O 11 I/O 12 I/O 13 S 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 I/O 113 I/O 112 I/O 111 I/O 110 NC1 I/O 109 I/O 108 I/O 107 I/O 106 I/O 105 VCC I/O 104 I/O 103 I/O 102 NC1 I/O 101 I/O 100 I/O 99 I/O 98 GND I/O 97 I/O 96 I/O 95 I/O 94 NC1 I/O 93 I/O 92 I/O 91 I/O 90 I/O 89 I/O 88 I/O 87 VCC I/O 86 NC1 I/O 85 I/O 84 I/O 83 I/O 82 GND I/O 81 I/O 80 I/O 79 I/O 78 ispLSI 2128/A 176-Pin TQFP Pinout Diagram SE 176-TQFP/2128A U 1. NC pins are not to be connected to any active signals, VCC or GND. 2. Pins have dual function capability. 11 Specifications ispLSI 2128/A Part Number Description ispLSI XXXXX – XXX X X X Device Family Grade Blank = Commercial I = Industrial Package Q = PQFP M = MQFP T = TQFP D ES IG N S Device Number 2128 2128A Speed 100 = 100 MHz fmax 80 = 81 MHz fmax Power L = Low EW 0212/2128A ispLSI 2128/A Ordering Information Tpd (ns) 100 10 100 10 81 81 ispLSI ispLSI 2128A-100LQ160 160-Pin PQFP ispLSI 2128A-100LT176 176-Pin TQFP 15 ispLSI 2128A-80LQ160 160-Pin PQFP 15 ispLSI 2128A-80LT176 176-Pin TQFP 10 ispLSI 2128-100LQ 160-Pin PQFP 10 ispLSI 2128-100LT 176-Pin TQFP 15 ispLSI 2128-80LQ 160-Pin PQFP 15 ispLSI 2128-80LT 176-Pin TQFP Table 2-0041A/2128A INDUSTRIAL Tpd (ns) ORDERING NUMBER PACKAGE 81 15 ispLSI 2128A-80LT176I 176-Pin TQFP 81 15 ispLSI 2128-80LTI 176-Pin TQFP Table 2-0041B/2128A U SE is ispLSI PACKAGE Fmax (MHz) pL FAMILY SI 21 81 28 81 E 100 100 ORDERING NUMBER R Fmax (MHz) FO FAMILY N COMMERCIAL 12