ETC LP2951ACDM

LP2950, LP2951
100 mA, 3.0 V, Low Power
Low Dropout Voltage
Regulator
The LP2950 and LP2951 are micropower voltage regulators that are
specifically designed to maintain proper regulation with an extremely
low input–to–output voltage differential. These devices feature a very
low quiescent bias current of 75 µA and are capable of supplying
output currents in excess of 100 mA. Internal current and thermal
limiting protection is provided.
The LP2951 has three additional features. The first is the Error
Output that can be used to signal external circuitry of an out of
regulation condition, or as a microprocessor power–on reset. The
second feature allows the output voltage to be preset to 5.0 V, 3.3 V or
3.0 V output (depending on the version) or programmed from 1.25 V
to 29 V. It consists of a pinned out resistor divider along with direct
access to the Error Amplifier feedback input. The third feature is a
Shutdown input that allows a logic level signal to turn–off or turn–on
the regulator output.
Due to the low input–to–output voltage differential and bias current
specifications, these devices are ideally suited for battery powered
computer, consumer, and industrial equipment where an extension of
useful battery life is desirable. The LP2950 is available in the three
pin case 29 and DPAK packages, and the LP2951 is available in the
eight pin dual–in–line, SO–8 and Micro–8 surface mount packages.
The ‘A’ suffix devices feature an initial output voltage tolerance
±0.5%.
LP2950 and LP2951 Features:
• Low Quiescent Bias Current of 75 µA
• Low Input–to–Output Voltage Differential of 50 mV at 100 µA and
•
•
•
•
380 mV at 100 mA
5.0 V, 3.3 V or 3.0 V ±0.5% Allows Use as a Regulator or Reference
Extremely Tight Line and Load Regulation
Requires Only a 1.0 µF Output Capacitor for Stability
Internal Current and Thermal Limiting
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TO–92
Z SUFFIX
CASE 29
1
2
Pin: 1. Output
2. Ground
3. Input
3
DPAK
DT SUFFIX
CASE 369A
1
3
PIN CONNECTIONS
1
2
Pin: 1. Input
2. Ground
3. Output
3
(Top View)
Heatsink surface (shown as terminal 4 in
case outline drawing) is connected to Pin 2.
SO–8
D SUFFIX
CASE 751
8
1
PDIP–8
N SUFFIX
CASE 626
8
1
Micro–8
DM SUFFIX
CASE 846A
LP2951 Additional Features:
• Error Output Signals an Out of Regulation Condition
• Output Programmable from 1.25 V to 29 V
• Logic Level Shutdown Input
8
1
PIN CONNECTIONS
(See Following Page for Device Information.)
Output 1
8
Input
Sense 2
7
Feedback
Shutdown 3
6
VO Tap
Gnd 4
5
Error Output
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on pages 13 and 14 of this data sheet.
 Semiconductor Components Industries, LLC, 2002
January, 2002 – Rev. 8
1
Publication Order Number:
LP2950/D
LP2950, LP2951
DEVICE INFORMATION
Output Voltage
Package
3.0V
3.3V
5.0V
Adjustable
Operating Junction
Temperature Range
TO–92
Suffix Z
LP2950CZ–3.0
LP2950ACZ–3.0
LP2950CZ–3.3
LP2950ACZ–3.3
LP2950CZ–5.0
LP2950ACZ–5.0
Not
Available
TJ = –40° to +125°C
DPAK
Suffix DT
LP2950CDT–3.0
LP2950ACDT–3.0
LP2950CDT–3.3
LP2950ACDT–3.3
LP2950CDT–5.0
LP2950ACDT–5.0
Not
Available
TJ = –40° to +125°C
SO–8
Suffix D
LP2951CD–3.0
LP2951ACD–3.0
LP2951CD–3.3
LP2951ACD–3.3
LP2951CD
LP2951ACD
LP2951CD
LP2951ACD
TJ = –40° to +125°C
Micro–8
Suffix DM
LP2951CDM–3.0
LP2951ACDM–3.0
LP2951CDM–3.3
LP2951ACDM–3.3
LP2951CDM
LP2951ACDM
LP2951CDM
LP2951ACDM
TJ = –40° to +125°C
DIP–8
Suffix N
LP2951CN–3.0
LP2951ACN–3.0
LP2951CN–3.3
LP2951ACN–3.3
LP2951CN
LP2951ACN
LP2951CN
LP2951ACN
TJ = –40° to +125°C
LP2950Cx–xx / LP2951Cxx–xx
LP2950ACx–xx / LP2951ACxx–xx
1% Output Voltage Precision at TJ = 25°C
0.5% Output Voltage Precision at TJ = 25°C
Input
Output
3
Battery or
Unregulated DC
182 k
Error Amplifier
1.23 V
Reference
Gnd
Input
Battery or
Unregulated DC
8
60 k
LP2950CZ–5.0
2
Output
1
5.0 V/100 mA
1.0 µF
1
Sense
5.0 V/100 mA
2
182 k
60 k
1.0 µF
VO Tap
6
7
From
3
CMOS/TTL
Feedback
Error
Amplifier
Shutdown
60 k
50 k
75 mV/
60 mV
Error Detection
Comparator
1.23 V
Reference
Gnd
330 k
4
Error
Output
5
To CMOS/TTL
LP2951CD or CN
This device contains 34 active transistors.
Figure 1. Representative Block Diagrams
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2
LP2950, LP2951
MAXIMUM RATINGS (TA = 25°C, unless otherwise noted.)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
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ÁÁÁÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁ
Symbol
Value
Unit
VCC
30
Vdc
PD
Internally Limited
W
RθJA
RθJC
180
45
°C/W
°C/W
RθJA
RθJC
92
6.0
°C/W
°C/W
RθJA
RθJC
160
83
°C/W
°C/W
RθJA
105
°C/W
RθJA
240
°C/W
Vfb
–1.5 to +30
Vdc
Shutdown Input Voltage
Vsd
–0.3 to +30
Vdc
Error Comparator Output Voltage
Verr
–0.3 to +30
Vdc
Operating Junction Temperature
TJ
–40 to +125
°C
Storage Temperature Range
Tstg
–65 to +150
°C
Rating
Input Voltage
Power Dissipation and Thermal Characteristics
Maximum Power Dissipation
Case 751(SO–8) D Suffix
Thermal Resistance, Junction–to–Ambient
Thermal Resistance, Junction–to–Case
Case 369A (DPAK) DT Suffix (Note 1)
Thermal Resistance, Junction–to–Ambient
Thermal Resistance, Junction–to–Case
Case 29 (TO–226AA/TO–92) Z Suffix
Thermal Resistance, Junction–to–Ambient
Thermal Resistance, Junction–to–Case
Case 626 N Suffix
Thermal Resistance, Junction–to–Ambient
Case 846A (Micro–8) DM Suffix
Thermal Resistance, Junction–to–Ambient
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
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ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁ
Feedback Input Voltage
ELECTRICAL CHARACTERISTICS (Vin = VO + 1.0 V, IO = 100 µA, CO = 1.0 µF, TJ = 25°C [Note 3], unless otherwise noted.)
Characteristic
Symbol
Output Voltage, 5.0 V Versions
Vin = 6.0 V, IO = 100 µA, TJ = 25°C
LP2950C–5.0/LP2951C
LP2950AC–5.0/LP2951AC
TJ = –40 to +125°C
LP2950C–5.0/LP2951C
LP2950AC–5.0/LP2951AC
Vin = 6.0 to 30 V, IO = 100 µA to 100 mA, TJ = –40 to +125°C
LP2950C–5.0/LP2951C
LP2950AC–5.0/LP2951AC
VO
Output Voltage, 3.3 V Versions
Vin = 4.3 V, IO = 100 µA, TJ = 25°C
LP2950C–3.3/LP2951C–3.3
LP2950AC–3.3/LP2951AC–3.3
TJ = –40 to +125°C
LP2950C–3.3/LP2951C–3.3
LP2950AC–3.3/LP2951AC–3.3
Vin = 4.3 to 30 V, IO = 100 µA to 100 mA, TJ = –40 to +125°C
LP2950C–3.3/LP2951C–3.3
LP2950AC–3.3/LP2951AC–3.3
VO
Min
Typ
3
Unit
V
4.950
4.975
5.000
5.000
5.050
5.025
4.900
4.940
–
–
5.100
5.060
4.880
4.925
–
–
5.120
5.075
V
3.267
3.284
3.300
3.300
3.333
3.317
3.234
3.260
–
–
3.366
3.340
3.221
3.254
–
–
3.379
3.346
Output Voltage, 3.0 V Versions
VO
Vin = 4.0 V, IO = 100 µA, TJ = 25°C
LP2950C–3.0/LP2951C–3.0
2.970
3.000
LP2950AC–3.0/LP2951AC–3.0
2.985
3.000
TJ = –40 to +125°C
LP2950C–3.0/LP2951C–3.0
2.940
–
LP2950AC–3.0/LP2951AC–3.0
2.964
–
Vin = 4.0 to 30 V, IO = 100 µA to 100 mA, TJ = –40 to +125°C
LP2950C–3.0/LP2951C–3.0
2.928
–
LP2950AC–3.0/LP2951AC–3.0
2.958
–
1. The Junction–to–Ambient Thermal Resistance is determined by PC board copper area per Figure 27.
2. ESD data available upon request.
3. Low duty pulse techniques are used during test to maintain junction temperature as close to ambient as possible.
4. VO(nom) is the part number voltage option.
5. Noise tests on the LP2951 are made with a 0.01 µF capacitor connected across Pins 7 and 1.
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Max
V
3.030
3.015
3.060
3.036
3.072
3.042
LP2950, LP2951
ELECTRICAL CHARACTERISTICS (continued) (Vin = VO + 1.0 V, IO = 100 µA, CO = 1.0 µF, TJ = 25°C [Note 8], unless
otherwise noted.)
Symbol
Characteristic
Min
Typ
Max
–
–
0.08
0.04
0.20
0.10
–
–
0.13
0.05
0.20
0.10
–
–
30
350
80
450
–
–
93
4.0
120
12
µA
mA
ICCdropout
–
110
170
µA
ILimit
–
220
300
mA
Regthermal
–
0.05
0.20
%/W
–
–
126
56
–
–
1.210
1.220
1.235
1.235
1.260
1.250
1.200
1.200
–
–
1.270
1.260
Line Regulation (Vin = VO(nom) +1.0 V to 30 V) (Note 9)
LP2950C–XX/LP2951C/LP2951C–XX
LP2950AC–XX/LP2951AC/LP2951AC–XX
Regline
Load Regulation (IO = 100 µA to 100 mA)
LP2950C–XX/LP2951C/LP2951C–XX
LP2950AC–XX/LP2951AC/LP2951AC–XX
Regload
Dropout Voltage
IO = 100 µA
IO = 100 mA
VI – VO
Supply Bias Current
IO = 100 µA
IO = 100 mA
%
%
mV
ICC
Dropout Supply Bias Current (Vin = VO(nom) – 0.5 V,
IO = 100 µA) (Note 9)
Current Limit (VO Shorted to Ground)
Thermal Regulation
Output Noise Voltage (10 Hz to 100 kHz) (Note 10)
CL = 1.0 µF
CL = 100 µF
Unit
µVrms
Vn
LP2951A/LP2951AC ONLY
Reference Voltage (TJ = 25°C)
LP2951C/LP2951C–XX
LP2951AC/LP2951AC–XX
Vref
Reference Voltage (TJ = –40 to +125°C)
LP2951C/LP2951C–XX
LP2951AC/LP2951AC–XX
Vref
Reference Voltage (TJ = –40 to +125°C)
IO = 100 µA to 100 mA, Vin = 23 to 30 V
LP2951C/LP2951C–XX
LP2951AC/LP2951AC–XX
Vref
Feedback Pin Bias Current
V
V
V
1.185
1.190
–
–
1.285
1.270
IFB
–
15
40
Output Leakage Current (VOH = 30 V)
Ilkg
–
0.01
1.0
µA
Output Low Voltage (Vin = 4.5 V, IOL = 400 µA)
VOL
–
150
250
mV
Upper Threshold Voltage (Vin = 6.0 V)
Vthu
40
45
–
mV
Lower Threshold Voltage (Vin = 6.0 V)
Vthl
–
60
95
mV
Hysteresis (Vin = 6.0 V)
Vhy
–
15
–
mV
0
2.0
–
–
0.7
30
–
–
35
450
50
600
–
3.0
10
nA
ERROR COMPARATOR
SHUTDOWN INPUT
Input Logic Voltage
Logic “0” (Regulator “On”)
Logic “1” (Regulator “Off”)
Vshtdn
Shutdown Pin Input Current
Vshtdn = 2.4 V
Vshtdn = 30 V
Ishtdn
Regulator Output Current in Shutdown Mode
(Vin = 30 V, Vshtdn = 2.0 V, VO = 0, Pin 6 Connected to Pin 7)
Ioff
V
µA
6. The Junction–to–Ambient Thermal Resistance is determined by PC board copper area per Figure 27.
7. ESD data available upon request.
8. Low duty pulse techniques are used during test to maintain junction temperature as close to ambient as possible.
9. VO(nom) is the part number voltage option.
10. Noise tests on the LP2951 are made with a 0.01 µF capacitor connected across Pins 7 and 1.
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4
µA
LP2950, LP2951
DEFINITIONS
Output Noise Voltage – The rms ac voltage at the output,
with constant load and no input ripple, measured over a
specified frequency range.
Leakage Current – Current drawn through a bipolar
transistor collector–base junction, under a specified
collector voltage, when the transistor is “off”.
Upper Threshold Voltage – Voltage applied to the
comparator input terminal, below the reference voltage
which is applied to the other comparator input terminal,
which causes the comparator output to change state from a
logic “0” to “1”.
Lower Threshold Voltage – Voltage applied to the
comparator input terminal, below the reference voltage
which is applied to the other comparator input terminal,
which causes the comparator output to change state from a
logic “1” to “0”.
Hysteresis – The difference between Lower Threshold
voltage and Upper Threshold voltage.
Dropout Voltage – The input/output voltage differential
at which the regulator output no longer maintains regulation
against further reductions in input voltage. Measured when
the output drops 100 mV below its nominal value (which is
measured at 1.0 V differential), dropout voltage is affected
by junction temperature, load current and minimum input
supply requirements.
Line Regulation – The change in output voltage for a
change in input voltage. The measurement is made under
conditions of low dissipation or by using pulse techniques
such that average chip temperature is not significantly
affected.
Load Regulation – The change in output voltage for a
change in load current at constant chip temperature.
Maximum Power Dissipation – The maximum total
device dissipation for which the regulator will operate
within specifications.
Bias Current – Current which is used to operate the
regulator chip and is not delivered to the load.
6.0
1.0
0.1
0.01
0.1
1.0
10
3.0
RL = 50 Ω
2.0
1.0
1.0
0
2.0
3.0
4.0
5.0
IL, LOAD CURRENT (mA)
Vin, INPUT VOLTAGE (V)
Figure 2. Quiescent Current
Figure 3. Dropout Characteristics
6.0
5.00
Vout , OUTPUT VOLTAGE (V)
200
0.1 mA Load Current
150
100
No Load
50
0
RL = 50 k
4.0
0
100
250
BIAS CURRENT (µ A)
LP2951C
TA = 25°C
5.0
Vout , OUTPUT VOLTAGE (V)
LP2950/LP2951 BIAS CURRENT (mA)
10
0
5.0
10
15
20
4.99
4.98
4.97
4.96
LP2951C
4.95
-50
25
0
50
100
150
Vin, INPUT VOLTAGE (V)
TA, AMBIENT TEMPERATURE (°C)
Figure 4. Input Current
Figure 5. Output Voltage versus Temperature
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5
200
TA = 25°C
250
200
150
100
50
0
0.1
1.0
10
55
500
50
450
40
400
350
0
IO, OUTPUT CURRENT (mA)
Vin , INPUT VOLTAGE (V)
Vin Decreasing
Vin Increasing
2.0
1.0
4.74
4.78
4.82
4.86
2.0
7.0
0
Vout
-2.0
6.5
TA = 25°C
CL = 1.0 µF
IL = 1.0 mA
VO = 5.0 V
6.0
0
100
200
300
-4.0
400
500
600
700
Vin, INPUT VOLTAGE (V)
t, TIME (µs)
Figure 8. Error Comparator Output
Figure 9. Line Transient Response
7.0
CL = 1.0 µF
Vout = 5.0 V
IL = 400 A to 75 mA
TA = 25°C
150
5.0
4.0
2.0
1.0
Shutdown Input
0
400
TA = 25°C
IL = 10 mA
Vin = 8.0 V
Vout = 5.0 V
200
Vout
100
CL = 10 µF
3.0
-6.0
800
200
CL = 1.0 µF
6.0
-1.0
-100
4.0
Vin
7.5
5.5
4.90
LOAD CURRENT (mA)
Vout , OUTPUT VOLTAGE (V)
SHUTDOWN AND OUTPUT VOLTAGE (V)
8.0
LP2951C
RL = 330 k
TA = 25°C
3.0
30
150
100
Figure 7. Dropout Voltage versus Temperature
5.0
0
4.70
50
T, TEMPERATURE (°C)
Figure 6. Dropout Voltage versus Output Current
4.0
35
RL = 50 k
300
-50
100
45
RL = 50
OUTPUT VOLTAGE CHANGE (mV)
300
550
0
50
-200
ILoad
0
-400
0
100
200
300
400
-50
0
0.5
1
1.5
2
2.5
3
3.5
t, TIME (µs)
t, TIME (ms)
Figure 10. LP2951 Enable Transient
Figure 11. Load Transient Response
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6
4
OUTPUT VOLTAGE CHANGE (mV)
DROPOUT VOLTAGE (mV)
350
DROPOUT VOLTAGE (mV) R L= 50
400
DROPOUT VOLTAGE (mV) R L= 50 k
LP2950, LP2951
LP2950, LP2951
4.0
VOLTAGE NOISE (µ V/√ Hz)
60
IL= 0.1 mA
40
20
0
1.0
TA = 25°C
CL = 1.0 µF
Vin = 6.0 V
Vout = 5.0 V
10
1.0 k
100
10 k
CL = 1.0 µF
3.0
2.0
CL = 100 µF
1.0
0
100
100 k
1.0 k
f, FREQUENCY (Hz)
10 k
100 k
f, FREQUENCY (Hz)
Figure 12. Ripple Rejection
Figure 13. Output Noise
1.8
100
Vout , OUTPUT CURRENT (mA)
SHUTDOWN THRESHOLD VOLTAGE (V)
IL= 100 mA
TA = 25°C
VO = 5.0 V
LP2951C
1.6
1.4
Output Off"
1.2
Output On"
1.0
0.8
-40 -20
0
20
40
60
80
100
120
140
TA = 25°C
80
0
40
-2.0
20
-4.0
LP2951CN
0
5.0
10
15
20
25
30
t, TEMPERATURE (°C)
Vin, INPUT VOLTAGE (V)
Figure 14. Shutdown Threshold Voltage
versus Temperature
Figure 15. Maximum Rated
Output Current
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7
2.0
TA = 75°C
60
0
160
4.0
35
-6.0
40
OUTPUT VOLTAGE CHANGE (mV)
RIPPLE REJECTION (dB)
80
LP2950, LP2951
APPLICATIONS INFORMATION
Introduction
to the LP2951 is ramped up and down. The ERROR signal
becomes valid (low) at about 1.3 V input. It goes high when
the input reaches about 5.0 V (Vout exceeds about 4.75 V).
Since the LP2951’s dropout voltage is dependent upon the
load current (refer to the curve in the Typical Performance
Characteristics), the input voltage trip point will vary with
load current. The output voltage trip point does not vary
with load.
The error comparator output is an open collector which
requires an external pull–up resistor. This resistor may be
returned to the output or some other voltage within the
system. The resistance value should be chosen to be
consistent with the 400 µA sink capability of the error
comparator. A value between 100 k and 1.0 MΩ is
suggested. No pull–up resistance is required if this output is
unused.
When operated in the shutdown mode, the error
comparator output will go high if it has been pulled up to an
external supply. To avoid this invalid response, the error
comparator output should be pulled up to Vout (see
Figure 16).
The LP2950/LP2951 regulators are designed with
internal current limiting and thermal shutdown making them
user–friendly. Typical application circuits for the LP2950
and LP2951 are shown in Figures 18 through 26.
These regulators are not internally compensated and thus
require a 1.0 µF (or greater) capacitance between the
LP2950/LP2951 output terminal and ground for stability.
Most types of aluminum, tantalum or multilayer ceramic
will perform adequately. Solid tantalums or appropriate
multilayer ceramic capacitors are recommended for
operation below 25°C.
At lower values of output current, less output capacitance
is required for output stability. The capacitor can be reduced
to 0.33 µF for currents less than 10 mA, or 0.1 µF for currents
below 1.0 mA. Using the 8–pin versions at voltages less than
5.0 V operates the error amplifier at lower values of gain, so
that more output capacitance is needed for stability. For the
worst case operating condition of a 100 mA load at 1.23 V
output (Output Pin 1 connected to the feedback Pin 7) a
minimum capacitance of 3.3 µF is recommended.
The LP2950 will remain stable and in regulation when
operated with no output load. When setting the output
voltage of the LP2951 with external resistors, the resistance
values should be chosen to draw a minimum of 1.0 µA.
A bypass capacitor is recommended across the
LP2950/LP2951 input to ground if more than 4 inches of
wire connects the input to either a battery or power supply
filter capacitor.
Input capacitance at the LP2951 Feedback Pin 7 can
create a pole, causing instability if high value external
resistors are used to set the output voltage. Adding a 100 pF
capacitor between the Output Pin 1 and the Feedback Pin 7
and increasing the output filter capacitor to at least 3.3 µF
will stabilize the feedback loop.
5.0 V
4.75 V
Output
Voltage
ERROR
Not
Valid
Not
Valid
4.75 V + Vdropout
Input
Voltage
4.70 V
1.3 V
Pull-Up
to Ext
Pull-Up
to Vout
4.70 V + Vdropout
1.3 V
Error Detection Comparator
The comparator switches to a positive logic low whenever
the LP2951 output voltage falls more than approximately
5.0% out of regulation. This value is the comparator’s
designed–in offset voltage of 60 mV divided by the 1.235 V
internal reference. As shown in the representative block
diagram. This trip level remains 5.0% below normal
regardless of the value of regulated output voltage. For
example, the error flag trip level is 4.75 V for a normal 5.0
V regulated output, or 9.50 V for a 10 V output voltage.
Figure 2 is a timing diagram which shows the ERROR
signal and the regulated output voltage as the input voltage
Figure 16. ERROR Output Timing
Programming the Output Voltage (LP2951)
The LP2951CX may be pin–strapped for the nominal
fixed output voltage using its internal voltage divider by
tying Pin 1 (output) to Pin 2 (sense) and Pin 7 (feedback) to
Pin 6 (5.0 V tap). Alternatively, it may be programmed for
any output voltage between its 1.235 reference voltage and
its 30 V maximum rating. An external pair of resistors is
required, as shown in Figure 17.
http://onsemi.com
8
LP2950, LP2951
Vin
100 k
Error
Output
5
8
Vin
Error
Vout
SNS
Shutdown
Input
3
1
2
Gnd
4
FB
Vout
1.23 to 30 V
NC
6 NC
VO T
SD
for reducing noise on the 3 lead LP2950. However,
increasing the capacitor from 1.0 µF to 220 µF only
decreases the noise from 430 µV to 160 µVrms for a 100 kHz
bandwidth at the 5.0 V output.
Noise can be reduced fourfold by a bypass capacitor
across R1, since it reduces the high frequency gain from 4
to unity. Pick
R1
0.01 µF
C
3.3 µF
Bypass
1
2R1 x 200 Hz
or about 0.01 µF. When doing this, the output capacitor must
be increased to 3.3 µF to maintain stability. These changes
reduce the output noise from 430 µV to 126 µVrms for a
100 kHz bandwidth at 5.0 V output. With bypass
capacitor added, noise no longer scales with output voltage
so that improvements are more dramatic at higher output
voltages.
7
R2
Figure 17. Adjustable Regulator
Unregulated
Input
The complete equation for the output voltage is:
V
V (1 R1R2) I
R1
out
ref
1.0 µF
FB
where Vref is the nominal 1.235 V reference voltage and IFB
is the feedback pin bias current, nominally –20 nA. The
minimum recommended load current of 1.0 µA forces an
upper limit of 1.2 MΩ on the value of R2, if the regulator
must work with no load. IFB will produce a 2% typical error
in Vout which may be eliminated at room temperature by
adjusting R1. For better accuracy, choosing R2 = 100 k
reduces this error to 0.17% while increasing the resistor
program current to 12 µA. Since the LP2951 typically draws
75 µA at no load with Pin 2 open circuited, the extra 12 µA
of current drawn is often a worthwhile tradeoff for
eliminating the need to set output voltage in test.
Error
Output
Shutdown
Input
MTB23P06E
10 k
5 Error
3
0.01 µF
8
Vin
Vout
5.0 V ±1.0%
0 to 1.0 A
Vout
SNS
LP2951CN
SD
Gnd
4
VO T
FB
7
1
2
6
220 µF
0.002 µF
1.0 M
2.0 k
Output Noise
In many applications it is desirable to reduce the noise
present at the output. Reducing the regulator bandwidth by
increasing the size of the output capacitor is the only method
Figure 18. 1.0 A Regulator with 1.2 V Dropout
http://onsemi.com
9
LP2950, LP2951
TYPICAL APPLICATIONS
+V = 2.0 to 30 V
IL
8
NC
5 Error
Vin
Vout
1N4001
1
2
NC
SNS
0.1 µF LP2951CN
3
6 NC
SD
VO T
Gnd
4
FB
330 pF
2.2 µF
7
Error
Output
4.2 V ±0.025 V
2.0 M
1.0%
806 k
1.0%
Shutdown
Input
IL = 1.23/R
Load
Unregulated Input
6.0 to 10 Vdc
5
Error
8
Vin
0.1 µF
Vout
1
2
SNS
LP2951CN
3
6
SD
VO T
Gnd
4
Lithium Ion
Rechargeable
Cell
FB
50 k
7
1.0 µF
R
Gnd
Figure 19. Lithium Ion Battery Cell Charger
Figure 20. Low Drift Current Sink
+Vin
+Vin
470 k
2N3906
5
470 k
Reset
Normally
Closed
Error
8
Vin
Vout
SNS
LP2951CN
3
SD
Gnd
4
CMOS
Gate
*Sleep
Input
VO T
FB
1
2
Vout
NC
6 NC
Error
Output
R1
1.0 µF
7
8
Vin
47 k
5
Error
470 k
Vout
SNS
LP2951CN
Shutdown
Input
3
SD
Gnd
4
R2
Error flag occurs when Vin is too
low to maintain Vout, or if Vout is
reduced by excessive load current.
VO T
FB
2
Vout
2N3906
1
NC
200 k
6 NC
3.3 µF
100 k 100 pF
7
100 k
Figure 21. Latch Off When Error Flag Occurs
Figure 22. 5.0 V Regulator with 2.5 V Sleep Function
http://onsemi.com
10
LP2950, LP2951
+Vin
5
NC
Error
8
Vin
Vout
2
SNS
LP2951CN
#1
3
6
SD
VO T
Gnd
4
FB
D2
1
D1
Memory
V+
1.0 µF
20
3.6 V
NiCad
7
27 k
Early Warning
D3
All diodes are 1N4148.
Reset
Q1
2.7 M
D4
VDD
2N3906
330 k
5
Error
8
Vin
Main output latches off at lower input voltages.
Battery backup on auxiliary output.
Vout
1
FB
Operation: Regulator #1’s Vout is programmed one
diode drop above 5.0 V. Its error flag becomes active
when Vin < 5.7 V. When Vin drops below 5.3 V, the
error flag of regulator #2 becomes active and via Q1
latches the main output “off”. When Vin again exceeds
5.7 V, regulator #1 is back in regulation and the early
warning signal rises, unlatching regulator #2 via D3.
Main
Output
2
SNS
LP2951CN
3
#2
6
SD
VO T
Gnd
4
Early Warning flag on low input voltage.
µP
1.0 µF
7
Figure 23. Regulator with Early Warning and Auxiliary Output
+Vin
Current Limit
Section
0.05
470
680
2N3906
2N3906
.33 µF
10 k
4.7 M
Error
Flag
5
220
Error
Vout
SNS
LP2951CN
3
SD
VO T
Gnd
4
20 k
8
Vin
FB
7
1000 µF
MJE2955
1
2
NC
6 NC
.01 µF
Vout @ 2.0 A
47
4.7 µF
Tant
100 µF
R1
R2
0.033 µF
Vout = 1.25V (1.0 + R1/R2)
For 5.0 V output, use internal resistors. Wire Pin 6 to 7,
and wire Pin 2 to +Vout Bus.
Figure 24. 2.0 A Low Dropout Regulator
http://onsemi.com
11
LP2950, LP2951
+5.0 V
4.7 k
4
20 mA
5
NC
3
NC
1N4001
1
0.1 µF
Error
8
Vin
Vout
SNS
LP2951CN
SD
VO T
Gnd
4
FB
1
2
2
4
NC
6
Output*
5
* High for
IL < 3.5 mA
NC
7
1N457
360
1N457
1N457
Figure 25. Open Circuit Detector for 4.0 to 20 mA Current Loop
100 k
31.6 k
2
NC
1
5
Error
8
Vin
Vout
SNS
LP2951CN
3
3
SD
VO T
Gnd
4
FB
1
Main V+
2
Memory V+
6
1.0 µF
NC
20
NiCad Backup
Battery
7
NC
Figure 26. Low Battery Disconnect
JUNCTIONTOAIR (° C/W)
R θ JA, THERMAL RESISTANCE
100
90
80
Minimum
Size Pad
70
60
50
40
2.4
PD(max) for TA = 50°C
Free Air
Mounted
Vertically
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
2.0 oz. Copper
L
1.6
L
1.2
RθJA
0
5.0
10
15
20
2.0
25
30
0.8
0.4
0
L, LENGTH OF COPPER (mm)
Figure 27. DPAK Thermal Resistance and Maximum
Power Dissipation versus P.C.B. Copper Length
http://onsemi.com
12
PD, MAXIMUM POWER DISSIPATION (W)
MC34164P–5
6.0 V Lead-Acid
Battery
2N3906
LP2950, LP2951
ORDERING INFORMATION (LP2950)
Output Voltage
(Volts)
Tolerance (%)
Package
Shipping
LP2950CZ–3.0
3.0
1.0
TO–92
2000 Units / Bag
LP2950ACZ–3.0
3.0
0.5
TO–92
2000 Units / Bag
LP2950CZ–3.3
3.3
1.0
TO–92
2000 Units / Bag
LP2950ACZ–3.3
3.3
0.5
TO–92
2000 Units / Bag
LP2950CZ–3.3RA
3.3
1.0
TO–92
2000 Units / Tape & Reel
LP2950ACZ–3.3RA
3.3
0.5
TO–92
2000 Units / Tape & Reel
LP2950CZ–5.0
5.0
1.0
TO–92
2000 Units / Bag
LP2950ACZ–5.0
5.0
0.5
TO–92
2000 Units / Bag
LP2950CZ–5.0RA
5.0
1.0
TO–92
2000 Units / Tape & Reel
LP2950CZ–5.0RP
5.0
1.0
TO–92
2000 Units / Ammo Pack
LP2950ACZ–5.0RA
5.0
0.5
TO–92
2000 Units / Tape & Reel
LP2950CDT–3.0
3.0
1.0
DPAK
75 Units / Rail
LP2950CDT–3.0RK
3.0
1.0
DPAK
2500 Units / Tape & Reel
LP2950ACDT–3.0
3.0
0.5
DPAK
75 Units / Rail
LP2950CDT–3.3
3.3
1.0
DPAK
75 Units / Rail
LP2950CDT–3.3RK
3.3
1.0
DPAK
2500 Units / Tape & Reel
LP2950ACDT–3.3
3.3
0.5
DPAK
75 Units / Rail
LP2950CDT–5.0
5.0
1.0
DPAK
75 Units / Rail
LP2950CDT–5.0RK
5.0
1.0
DPAK
2500 Units / Tape & Reel
LP2950ACDT–5.0
5.0
0.5
DPAK
75 Units / Rail
LP2950ACDT–5.0RK
5.0
0.5
DPAK
2500 Units / Tape & Reel
Part Number
http://onsemi.com
13
LP2950, LP2951
ORDERING INFORMATION (LP2951)
Output Voltage
(Volts)
Tolerance (%)
Package
Shipping
LP2951CD–3.0
3.0 or Adj.
1.0
SO–8
98 Units / Rail
LP2951CD–3.0R2
3.0 or Adj.
1.0
SO–8
2500 Units / Tape & Reel
LP2951ACD–3.0
3.0 or Adj.
0.5
SO–8
98 Units / Rail
LP2951ACD–3.0R2
3.0 or Adj.
0.5
SO–8
2500 Units / Tape & Reel
LP2951CD–3.3
3.3 or Adj.
1.0
SO–8
98 Units / Rail
LP2951CD–3.3R2
3.3 or Adj.
1.0
SO–8
2500 Units / Tape & Reel
LP2951ACD–3.3
3.3 or Adj.
0.5
SO–8
98 Units / Rail
LP2951ACD–3.3R2
3.3 or Adj.
0.5
SO–8
2500 Units / Tape & Reel
LP2951CD
5.0 or Adj.
2.0
SO–8
98 Units / Rail
LP2951CDR2
5.0 or Adj.
2.0
SO–8
2500 Units / Tape & Reel
LP2951ACD
5.0 or Adj.
1.2
SO–8
98 Units / Rail
LP2951ACDR2
5.0 or Adj.
1.2
SO–8
2500 Units / Tape & Reel
LP2951CDM–3.0R2
3.0 or Adj.
1.0
Micro–8
2500 Units / Tape & Reel
LP2951ACDM–3.0R2
3.0 or Adj.
0.5
Micro–8
2500 Units / Tape & Reel
LP2951CDM–3.3R2
3.3 or Adj.
1.0
Micro–8
2500 Units / Tape & Reel
LP2951ACDM–3.3R2
3.3 or Adj.
0.5
Micro–8
2500 Units / Tape & Reel
LP2951CDMR2
5.0 or Adj.
2.0
Micro–8
2500 Units / Tape & Reel
LP2951ACDMR2
5.0 or Adj.
1.2
Micro–8
2500 Units / Tape & Reel
LP2951CN–3.0
3.0 or Adj.
1.0
DIP–8
50 Units / Rail
LP2951ACN–3.0
3.0 or Adj.
0.5
DIP–8
50 Units / Rail
LP2951CN–3.3
3.3 or Adj.
1.0
DIP–8
50 Units / Rail
LP2951ACN–3.3
3.3 or Adj.
0.5
DIP–8
50 Units / Rail
LP2951CN
5.0 or Adj.
2.0
DIP–8
50 Units / Rail
LP2951ACN
5.0 or Adj.
1.2
DIP–8
50 Units / Rail
Part Number
http://onsemi.com
14
LP2950, LP2951
PACKAGE DIMENSIONS
TO–226AA/TO–92
Z SUFFIX
PLASTIC PACKAGE
CASE 29–11
ISSUE AL
A
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. CONTOUR OF PACKAGE BEYOND DIMENSION R
IS UNCONTROLLED.
4. LEAD DIMENSION IS UNCONTROLLED IN P AND
BEYOND DIMENSION K MINIMUM.
B
R
P
L
SEATING
PLANE
K
DIM
A
B
C
D
G
H
J
K
L
N
P
R
V
D
X X
G
J
H
V
C
SECTION X–X
1
N
INCHES
MIN
MAX
0.175
0.205
0.170
0.210
0.125
0.165
0.016
0.021
0.045
0.055
0.095
0.105
0.015
0.020
0.500
--0.250
--0.080
0.105
--0.100
0.115
--0.135
---
MILLIMETERS
MIN
MAX
4.45
5.20
4.32
5.33
3.18
4.19
0.407
0.533
1.15
1.39
2.42
2.66
0.39
0.50
12.70
--6.35
--2.04
2.66
--2.54
2.93
--3.43
---
N
DPAK
DT SUFFIX
PLASTIC PACKAGE
CASE 369A–13
ISSUE AB
–T–
C
B
V
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
SEATING
PLANE
E
R
4
Z
A
S
1
2
3
U
K
F
J
L
H
D
G
2 PL
0.13 (0.005)
M
T
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15
DIM
A
B
C
D
E
F
G
H
J
K
L
R
S
U
V
Z
INCHES
MIN
MAX
0.235
0.250
0.250
0.265
0.086
0.094
0.027
0.035
0.033
0.040
0.037
0.047
0.180 BSC
0.034
0.040
0.018
0.023
0.102
0.114
0.090 BSC
0.175
0.215
0.020
0.050
0.020
--0.030
0.050
0.138
---
MILLIMETERS
MIN
MAX
5.97
6.35
6.35
6.73
2.19
2.38
0.69
0.88
0.84
1.01
0.94
1.19
4.58 BSC
0.87
1.01
0.46
0.58
2.60
2.89
2.29 BSC
4.45
5.46
0.51
1.27
0.51
--0.77
1.27
3.51
---
LP2950, LP2951
PACKAGE DIMENSIONS
PDIP–8
N SUFFIX
PLASTIC PACKAGE
CASE 626–05
ISSUE L
8
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5
–B–
1
4
DIM
A
B
C
D
F
G
H
J
K
L
M
N
F
–A–
NOTE 2
L
C
J
–T–
MILLIMETERS
MIN
MAX
9.40
10.16
6.10
6.60
3.94
4.45
0.38
0.51
1.02
1.78
2.54 BSC
0.76
1.27
0.20
0.30
2.92
3.43
7.62 BSC
--10
0.76
1.01
INCHES
MIN
MAX
0.370
0.400
0.240
0.260
0.155
0.175
0.015
0.020
0.040
0.070
0.100 BSC
0.030
0.050
0.008
0.012
0.115
0.135
0.300 BSC
--10
0.030
0.040
N
SEATING
PLANE
D
M
K
G
H
0.13 (0.005)
M
T A
M
B
M
SO–8
D SUFFIX
PLASTIC PACKAGE
CASE 751–07
ISSUE W
–X–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
A
8
5
0.25 (0.010)
S
B
1
M
Y
M
4
K
–Y–
G
C
N
X 45 SEATING
PLANE
–Z–
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
S
http://onsemi.com
16
J
DIM
A
B
C
D
G
H
J
K
M
N
S
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0
8
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0
8
0.010
0.020
0.228
0.244
LP2950, LP2951
PACKAGE DIMENSIONS
Micro–8
DM SUFFIX
PLASTIC PACKAGE
CASE 846A–02
ISSUE E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
–A–
–B–
K
PIN 1 ID
G
D 8 PL
0.08 (0.003)
–T–
M
T B
S
A
S
SEATING
PLANE
0.038 (0.0015)
C
H
J
L
http://onsemi.com
17
DIM
A
B
C
D
G
H
J
K
L
MILLIMETERS
MIN
MAX
2.90
3.10
2.90
3.10
--1.10
0.25
0.40
0.65 BSC
0.05
0.15
0.13
0.23
4.75
5.05
0.40
0.70
INCHES
MIN
MAX
0.114
0.122
0.114
0.122
--0.043
0.010
0.016
0.026 BSC
0.002
0.006
0.005
0.009
0.187
0.199
0.016
0.028
LP2950, LP2951
Notes
http://onsemi.com
18
LP2950, LP2951
Notes
http://onsemi.com
19
LP2950, LP2951
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or
death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold
SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable
attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
Literature Fulfillment:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada
Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada
Email: [email protected]
JAPAN: ON Semiconductor, Japan Customer Focus Center
4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031
Phone: 81–3–5740–2700
Email: [email protected]
ON Semiconductor Website: http://onsemi.com
For additional information, please contact your local
Sales Representative.
N. American Technical Support: 800–282–9855 Toll Free USA/Canada
http://onsemi.com
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