ETC NAD10105-18

PRELIMINARY PRODUCT SPECIFICATION
10-Bit 105MSPS Sampling
Analog-to-Digital Converter
nAD10105-18
FEATURES
APPLICATIONS
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1.8V power supply
SNR typ 59dB for (fin = 10MHz)
Low power (65mW @ 1.8V and
105MSPS)
Frequency dependent biasing
Internal Sample/Hold
Differential input
Low input capacitance
Power Down and Sleep Mode
Imaging
Test equipment
Computer scanners
Wireless communication
Powerline communication
Set top boxes
Video products
GENERAL DESCRIPTION
The nAD10105-18 is a compact, high-speed, low power 10-bit monolithic analog-todigital converter, implemented in a 0.18µm single poly CMOS process with MiM
capacitor option. The converter includes a high bandwidth sample and hold. Using
internal references, the full scale range is ±0.75V. The full scale range can be set
between ±0.5V and ±0.75V using external references. It operates from a single 1.8V
supply. Its low distortion and high dynamic range offers the performance needed for
demanding imaging, multimedia, telecommunications and instrumentation
applications. The bias current level for the ADC is automatically adjusted based on
the clock input frequency. Hence, the power dissipation of the device is continuously
minimised for the current operation frequency.
QUICK REFERENCE DATA
Symbol
VDD
IDD
PD
PD
DNL
INL
fS
N
Parameter
Conditions
Supply voltage
Supply current
(105 MSPS)
Power dissipation
(10 MSPS)
Power dissipation
(1050 MSPS)
Differential
nonlinearity
Integral nonlinearity
Conversion rate
Resolution
Min.
Typ.
Max.
Unit
1.6
1.8
36.1
2.0
V
mA
Except digital
output drivers
Except digital
output drivers
fIN=0.9991MHz
8
mW
65
mW
fIN=0.9991MHz
±0.5
LSB
±0.75
LSB
MHz
bit
105
10
Table 1. Quick reference data
Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989
Revision: 1.2
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PRELIMINARY PRODUCT SPECIFICATION
nAD10105-18 10 Bit 105 MSPS Sampling ADC IP
GENERAL DESCRIPTION (Continued)
The nAD10105-18 has a pipelined architecture - resulting in low input capacitance.
Digital error correction of the 9 most significant bits ensures good linearity for input
frequencies approaching Nyquist. The nAD10105-18 is compact. The core occupies
less than 0.9mm2 of die area in a standard single poly 0.18µm CMOS process. The
fully differential architecture makes it insensitive to substrate noise. Thus it is ideal as
a mixed signal ASIC macro cell.
BLOCK DIAGRAM
REFP
REFN
EXTREF
BIAS0
BIAS1
ANALOG
INN
CLOCK
ANCLOCK
CK0
CK0B
CK2
CK2B
CLOCKBUF
INP
VCM
CKBUS<3:0>
IN_CORR<17:0>
CKCORR<1:0>
CORR_LOG
BIT<9:0>
Figure 1. Block diagram nAD10105-18
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Revision: 1.2
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PRELIMINARY PRODUCT SPECIFICATION
nAD10105-18 10 Bit 105 MSPS Sampling ADC IP
ELECTRICAL SPECIFICATIONS
(At TA = 25°C, VDD = 1.8V, Sampling Rate = 105MHz, Input frequency = 10MHz, Differential input
signal, 50% duty cycle clock unless otherwise noted )
Symbol Parameter (condition)
DNL
INL
VOS
CMRR
εG
SNR
SINAD
SFDR
VFSR
VCMI
CINA
VREFNI
VREFPI
VREFNO
VREFPO
VREFP-VREFN
VCM
FS
tAP
th
td
tAP
th
td
DC Accuracy
Differential Nonlinearity
fIN = 0.9991 MHz
Integral Nonlinearity
fIN = 0.9991 MHz
Midscale offset
Common Mode Rejection Ratio
Gain Error
Dynamic Performance
Signal to Noise Ratio (without
harmonics)
fIN = 10 MHz
fIN = 40 MHz
Signal to Noise and Distortion Ratio
fIN = 10 MHz
Spurious Free Dynamic Range
fIN = 10 MHz
fIN = 40 MHz
Analog Input
Input Voltage Range (differential)
Common mode input voltage
Input Capacitance (from each input to
ground)
Reference Voltages
Internal reference voltage on pin 10
Internal reference voltage on pin 11
Internal reference voltage drift
Negative Input Voltage
Positive Input Voltage
Reference input voltage range 1)
Common mode output voltage
Switching Performance
Conversion Rate
Pipeline Delay
Aperture delay, IP
Output hold time, IP
Output delay time, IP
Aperture delay, with bonding pad
Output hold time, with bonding pad
Output delay time, with bonding pad
Test
Level
Min.
Typ.
Max.
Units
IV
±0.5
LSB
IV
±0.75
±1
-59
±1
LSB
%FS
dB
%FS
59
58.5
dBFS
dBFS
IV
58
dBFS
IV
IV
70
57
dB
dB
IV
IV
±0.75
0.9
1.5
V
V
pF
IV
IV
0.525
1.275
IV
IV
IV
IV
0.525
1.275
0.75
0.9
V
V
ppm/°C
V
V
V
V
IV
IV
V
V
V
V
V
V
105
6
0.9
0.5
2.5
1.0
1.0
4.0
MSPS
Clocks
ns
ns
ns
ns
ns
ns
IV
IV
56
55
100
Digital Inputs
VIL
VIH
IIL
IIH
CIND
Logic “0” voltage
Logic “1” voltage
Logic “0” current (VI=VSS)
Logic “1” current (VI=VDD)
Input Capacitance
IV
IV
IV
IV
IV
0.4
AVDD -0.4
±10
±10
5
V
V
µA
µA
pF
(table continued on next page)
Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989
Revision: 1.2
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PRELIMINARY PRODUCT SPECIFICATION
nAD10105-18 10 Bit 105 MSPS Sampling ADC IP
VOL
VOH
VDD
IDD
VSS
PD
PD
PD
PD
AVDDDVDD1
OVDD
T
Digital Outputs
Logic “0” voltage (I = 2 mA)
Logic “1” voltage (I = 2 mA)
Power Supply
Supply voltage
Supply current (except digital output)
Supply voltage
Power dissipation (except digital output)
(10 MSPS)
Power dissipation (except digital output)
(80 MSPS)
Power dissipation (except digital output)
2)
Power Down Mode
Power dissipation (except digital output)
Sleep Mode
Analog power – digital power pins
IV
IV
V
IV
0.2
85% OVDD 90% OVDD
V
V
2.0
V
mA
IV
1.8
36.1
GND
8
IV
65
mW
IV
45
µW
IV
655
µW
Output driver supply voltage
Ambient operating temperature
1.6
0.4
-0.2
1.6
-40
1.8
mW
+0.2
V
2.0
+85
V
°C
Table 2. Electrical specifications
1)
See Figure 5.
2)
Power Down Mode is only available for IP version of nAD10105-18.
Test Levels
Test Level I: 100% production tested at +25°C
Test Level II: 100% production tested at +25°C and sample tested at specified
temperatures
Test Level III: Sample tested only
Test Level IV: Parameter is guaranteed by design and characterization testing
Test Level V: Parameter is typical value only
Test Level VI: 100% production tested at +25°C. Guaranteed by design and
characterization testing for industrial temperature range
ABSOLUTE MAXIMUM RATINGS
Supply voltages
AVDD ............................- 0.2V to +2.2V
DVDD1 ..................- 0.2V to VDD + 0.2V
OVDD ...................- 0.2V to VDD + 0.2V
Temperatures
Operating Temperature ….-40 to +85°C
Storage Temperature.. ... - 65 to +125°C
Input voltages
Analog In.......... - 0.2V to AVDD + 0.2V
Digital In..............- 0.2V to VDD + 0.2V
REFP ................. - 0.2V to AVDD + 0.2V
REFN................. - 0.2V to AVDD + 0.2V
CLOCK ...............- 0.2V to VDD + 0.2V
Note: Stress above one or more of the limiting values may cause permanent damage
to the device.
Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989
Revision: 1.2
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PRELIMINARY PRODUCT SPECIFICATION
nAD10105-18 10 Bit 105 MSPS Sampling ADC IP
PIN FUNCTIONS
Pin Name
Description
INP INN
REFP REFN
Differential input signal pins. Common mode voltage: 0.9V
Reference input pins. Bypass with 100nF capacitors close to the pins. See Application
Information below.
BIAS0, BIAS1
Digital inputs for max. sampling rate programming.
BIAS1=0, BIAS0=0: Sleep mode (power save)
BIAS1=0, BIAS0=1: - 12.5% bias
BIAS1=1, BIAS0=0: +12.5% bias
BIAS1=1, BIAS0=1: Typ. Bias
CLOCK
VCM
BIT9 - BIT0
OR
OUTEN
EXTREF
PD
VDD
VSS
OVDD
The bias setting is automatically performed based on the clock input frequency. This
function should be used ONLY if another bias setting than typical must be used.
Clock input
Common mode voltage output
Digital outputs ( MSB to LSB)
OverRange. High if all outputs are zeros or ones. Available on IP.
Enable digital outputs (Keep low for active outputs)
Disable internal references (Keep low for internal references)
Power Down (Keep low for normal operation) Available on IP or with bonding option.
Power pins for on chip power
Ground pins
Power pins for output drivers
Table 3. Pin functions
PIN ASSIGNMENT
BIT9
1
28 OUTEN
BIT8
2
27
CLOCK
BIT7
3
26
BIAS1
BIT6
4
25
BIAS0
BIT5
5
24
INP
OVDD
6
23
INN
OVDD
7
22
VDD
VSS
8
21
VSS
VSS
9
20
VCM
BIT4 10
BIT3 11
nAD10105-18
19 EXTREF
18
REFP
BIT2 12
17
REFN
BIT1 13
16
VDD
BIT0 14
15
VSS
28 PIN SSOP
Figure 2. Pin assignment for the 28 pin package used for samples
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Revision: 1.2
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PRELIMINARY PRODUCT SPECIFICATION
nAD10105-18 10 Bit 105 MSPS Sampling ADC IP
BIAS0
BIAS1
EXTREF
INP
INN
VCM
IP BLOCK LAYOUT
AVSS
AVSS
AVDD
AVDD
REFP
REFN
VDD
CLOCK
Y
X
AVDD
AVSS
AVSS
OR
BIT9
:
BIT0
AVDD
Figure 3. Size and pin placement for nAD10105-18.
The height and width of the layout is X =1208µm and Y=711µm respectively in the
0.18µm CMOS process.
TIMING DIAGRAM
CLOCK
S
A
M N-1
P
L
E
DATA
S
A
M N
P
L
E
S
A
M N+1
P
L
E
tAP
S
A
M N+2
P
L
E
t
t
h
Data
N-1
d
Data
N
Data
N+1
Figure 4. Timing diagram
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Revision: 1.2
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PRELIMINARY PRODUCT SPECIFICATION
nAD10105-18 10 Bit 105 MSPS Sampling ADC IP
INPUT SIGNAL RANGE
VREFP
VINP
VCM
VINN
VRR
VREFN
+VRR
VFSR
VINP-VINN
-VRR
Figure 5. Definition of full scale range
DEFINITIONS
Data sheet status
Objective product specification
Preliminary product
specification
Product specification
This datasheet contains target specifications for product development.
This datasheet contains preliminary data; supplementary data may be
published from Nordic VLSI ASA later.
This datasheet contains final product specifications.
Limiting values
Stress above one or more of the limiting values may cause permanent damage to the device. These are stress
ratings only and operation of the device at these or at any other conditions above those given in the
Specifications sections of the specification is not implied. Exposure to limiting values for extended periods may
affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Table 4. Definitions
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems
where malfunction of these products can reasonably be expected to result in personal
injury. Nordic VLSI ASA customers using or selling these products for use in such
applications do so at their own risk and agree fully indemnify Nordic VLSI ASA for
any damages resulting from such improper use or sale.
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Revision: 1.2
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PRELIMINARY PRODUCT SPECIFICATION
nAD10105-18 10 Bit 105 MSPS Sampling ADC IP
APPLICATION INFORMATION
References
The nAD10105-18 has a differential analog input. The input range is determined by
the voltages VREFP and VREFN applied to reference pins REFP and REFN respectively,
and is equal to ±(VREFP-VREFN). Externally generated reference voltages connected to
REFP and REFN should be symmetrical around 0.9V. The input range can be defined
between ±0.5V and ±0.75V. The references should be bypassed as close to the
converter pins as possible using 100nF capacitors in parallel with smaller capacitors
(e.g. 1nF) (to ground).
Analog input
The input of the nAD10105-18 can be configured in various ways - dependent upon
whether a single ended or differential, AC- or DC-coupled input is wanted.
AC-coupled input is most conveniently implemented using a transformer with a center
tapped secondary winding. The center tap is connected to the CM-node, as shown in
figure 6. In order to obtain low distortion, it is important that the selected transformer
does not exhibit core saturation at full-scale. Excellent results are obtained with the
Mini Circuits T1-6T or T1-1T. Proper termination of the input is important for input
signal purity. A small capacitor across the inputs attenuates kickback-noise from the
sample and hold. Series resistors as shown in Figure 6 may be advantageous to
improve linearity. The VCM-node should be bypassed to ground as closed to the
converter pin as possible using 100nF capacitors in parallel with a small one.
Vin
Mini Circuits
T1-6T
50Ω
ADC
INP
51Ω
22pF
VCM
INN
50Ω
Figure 6. Example of AC coupled input using transformer configuration
If a DC-coupled single ended input is wanted, a solution based on operational
amplifiers - as shown in Figure 7, is usually preferred. The AD826 is suggested for
low distortion and video bandwidth. Lower cost operational amplifiers may be used if
the demands are less strict. A good alternative for high performance applications is to
use AD8138 single ended to differential amplifier.
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Revision: 1.2
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PRELIMINARY PRODUCT SPECIFICATION
nAD10105-18 10 Bit 105 MSPS Sampling ADC IP
51Ω
470Ω
AD826
Input
offset
Video
in
470Ω
ADC
51Ω
100Ω
AD826
INP
15pF
100Ω
INN
51Ω
51Ω
470Ω
AD826
470Ω
470Ω
Figure 7. DC-coupled single ended to differential conversion (power supplies and
bypassing not shown)
Clock
In order to preserve accuracy at high input frequency, it is important that the clock has
low jitter and steep edges. Rise/fall times should be kept shorter than 2ns whenever
possible. Overshoot should be avoided. Low jitter is especially important when
converting high frequency input signals. Jitter causes the noise floor to rise
proportionally to input signal frequency. Jitter may be caused by crosstalk on the PCB.
It is therefore recommended that the clock trace on the PCB is made as short as
possible.
Digital outputs
The digital output data appears in offset binary code at CMOS logic levels. Full-scale
negative input results in output code 000...0. Full-scale positive input results in output
code 111...1. Output data are available 6 clock cycles after the data are sampled. The
analog input is sampled one aperture delay (tAP) after the high to low clock transition.
Output data should be sampled as shown in the timing diagram.
PCB layout and decoupling
A well designed PCB is necessary to get good spectral purity from any high
performance ADC. A multilayer PCB with a solid ground plane is recommended for
optimum performance. If the system has a split analog and digital ground plane, it is
recommended that all ground pins on the ADC are connected to the analog ground
plane. It is our experience that this gives the best performance. The power supply pins
should be bypassed using 100nF surface mounted capacitors as close to the package
pins as possible. Analog and digital supply pins should be separately filtered.
Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989
Revision: 1.2
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PRELIMINARY PRODUCT SPECIFICATION
nAD10105-18 10 Bit 105 MSPS Sampling ADC IP
Dynamic testing
Careful testing using high quality instrumentation is necessary to achieve accurate test
results on high speed A/D-converters. It is important that the clock source and signal
source has low jitter. A spectrally pure, low noise RF signal generator - such as the
HP8662A or HP8644B is recommended for the test signal. Low pass filtering or band
pass filtering of the input signal is usually necessary to obtain the required spectral
purity (SFDR > 75dB). The clock signal can be obtained from either a crystal
oscillator or a low-jitter pulse generator. Alternatively, a low-jitter RF-generator can
be used as a clock source. At Nordic VLSI, the Marconi Instruments 2041A is used.
The sinewave clock must then be applied to an ultra high-speed comparator (e.g.
AD9696) and a TTL to CMOS level shifter (e.g. 74LV04) before application to the
converter. The most consistent results are obtained if the clock signal is phase locked
to the input signal. Phase locking allows testing without windowing of output data. A
logic analyzer with deep memory - such as the HP16500-series, is recommended for
test data acquisition.
Power Down Mode and Sleep Mode
The nAD10105-18 has both Power Down Mode and Sleep Mode. The Power Down
Mode can be used when the ADC should be put to ‘zero current consumption’ state
and when a somewhat longer startup time is allowed. The Sleep Mode can be used to
put the ADC in an ‘idle’ state and when the application require a quick startup. The
two different power consumption saving schemes can be activated through the PD,
BIAS0 and BIAS1 pins/connections in the following manner:
Power Down Mode: PD=1, BIAS0=0, BIAS1=0
Sleep Mode: PD=0, BIAS0=0, BIAS1=0
The actual startup time from these modes are dependent on the external decopling
configuration.
Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989
Revision: 1.2
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September 10th 2001
PRELIMINARY PRODUCT SPECIFICATION
nAD10105-18 10 Bit 105 MSPS Sampling ADC IP
DESIGN CENTER
Nordic VLSI ASA
Vestre Rosten 81
N-7075 TILLER
NORWAY
Telephone:
+47 72898900
Telefax:
+47 72898989
E-mail: For further information regarding our state of the art data converters, please email us at [email protected]
World Wide Web/Internet: Visit our site at http://www.nvlsi.no.
ORDERING INFORMATION
Type number
nAD10105-18-IC
nAD10105-18-EVB
Description
nAD10105-18 sample in SSOP28
package (limited availability)
nAD10105-18 evaluation board
including characterisation report and
user guide
Price
USD 50
USD 300
Available
January 15th,
2002
January 15th,
2002
Table 5. Ordering information
Product Specification. Revision Date: September 10th, 2001
All rights reserved ®. Reproduction in whole or in part is prohibited without the prior
written permission of the copyright holder. Company and product names referred to in
this datasheet belong to their respective copyright/trademark holders.
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Revision: 1.2
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September 10th 2001