ETC NAD1210-25

PRELIMINARY PRODUCT SPECIFICATION
12-Bit 10MSPS Sampling
Analog-to-Digital Converter IP
nAD1210-25
FEATURES
APPLICATIONS
•
•
•
•
•
•
•
•
•
•
•
•
•
•
2.5V power supply
SNR typ 67dB for (fin = 10MHz)
Low power ([email protected])
Sample rate:10MSPS
Frequency dependent biasing
Internal/sample hold
Differential input
Low input capacitance
Imaging
Test equipment
Computer scanners
Communications
Set top boxes
Video products
GENERAL DESCRIPTION
The nAD1210-25 is a compact, high-speed, low power 12-bit monolithic analog-todigital converter, implemented in the TSMC Mixed-Signal MiM CMOS process. It
has 12-bit resolution with more than 10 effective bits, and close to 11 bit dynamic
range for video frequency signals. The converter includes a high bandwidth sample
and hold. The full scale range is ±1V. The full scale range can be set between ±0.5V
and ±1V. It operates from a single 2.5V supply. Its low distortion and high dynamic
range offers the performance needed for demanding imaging, multimedia,
telecommunications and instrumentation applications.
The bias current level for the ADC is automatically adjusted based on the clock input
frequency. Hence, the power dissipation of the device is continuously minimised for
the current operation frequency.
QUICK REFERENCE DATA
Symbol
Parameter
VDD
IDD
supply voltage
supply current
(10 MSPS)
power dissipation
(10 MSPS)
power dissipation
(sleep mode)
differential nonlinearity
integral nonlinearity
conversion rate
resolution
PD
PD
DNL
INL
fS
N
Conditions
Min.
Typ.
Max.
Unit
2.25
2.5
12
2.75
V
mA
Except digital
output drivers
Except digital
output drivers
fIN=0.9991MHz
fIN=0.9991MHz
30
mW
1.5
mW
±1
±3
10
20
12
LSB
LSB
MHz
bit
Table 1. Quick reference data
Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989
Revision: 1.0
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September 4th, 2001
PRELIMINARY PRODUCT SPECIFICATION
nAD1210-25 12 Bit 10 MSPS Sampling ADC IP
GENERAL DESCRIPTION (Continued)
The nAD1210-25 has a pipelined architecture - resulting in low input capacitance.
Digital error correction of the 11 most significant bits ensures good linearity for input
frequencies approaching Nyquist. The nAD1210-25 is compact. The core occupies
less than 1,5mm2 of die area in TSMC Mixed Signal MiM 0.25µm CMOS process.
The fully differential architecture makes it insensitive to substrate noise. Thus it is
ideal as a mixed signal ASIC macro cell.
BLOCK DIAGRAM
REFP
REFN
EXTREF
BIAS0
BIAS1
ANALOG
INN
CLK
ANCLOCK
CK0
CK0B
CK2
CK2B
CLOCKBUF
INP
CM
CKBUS<3:0>
IN_CORR<17:0>
CKCORR<1:0>
CORR_LOG
BIT<11:0>
Figure 1. Block diagram nAD1210-25
Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989
Revision: 1.0
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PRELIMINARY PRODUCT SPECIFICATION
nAD1210-25 12 Bit 10 MSPS Sampling ADC IP
ELECTRICAL SPECIFICATIONS
(At TA = 25°C, VDD = 2.5V, Sampling Rate = 10MHz, Input frequency = 10MHz dBFS, Differential
input signal, 50% duty cycle clock unless otherwise noted).
Symbol Parameter (condition)
DC Accuracy
Differential Nonlinearity
fIN = 0.9991 MHz
INL
Integral Nonlinearity
fIN = 0.9991 MHz
VOS
Midscale offset
CMRR
Common Mode Rejection Ratio (of VOS)
Dynamic Performance
SINAD
Signal to Noise and Distortion Ratio
fIN = 10 MHz
fIN = 40 MHz
SNR
Signal to Noise Ratio (without
harmonics)
fIN = 10 MHz
SFDR
Spurious Free Dynamic Range
fIN = 10 MHz
fIN = 40 MHz
PSRR
Power Supply Rejection Ratio (of VOS)
Analog Input
VFSR
Input Voltage Range (differential)
VCMI
Common mode input voltage
CINA
Input Capacitance (differential)
Reference Voltages
VREFN
Negative Input Voltage
VREFP
Positive Input Voltage
1
VRR
Reference input voltage range
VCM
Common mode output voltage
Digital Inputs
VIL
Logic “0” voltage
VIH
Logic “1” voltage
IIL
Logic “0” current (VI=VSS)
IIH
Logic “1” current (VI=VDD)
CIND
Input Capacitance
Digital Outputs
VOL
Logic “0” voltage (I = 2 mA)
VOH
Logic “1” voltage (I = 2 mA)
tH
Output hold time
tD
Output delay time
(table continued on next page)
Test
Level
Min.
Typ.
Max.
Units
III
±0.5
±1.0
LSB
III
III
±1.0
TBD
TBD
±3.0
LSB
mV
dB
III
III
66
60
dBFS
dBFS
III
67
dBFS
III
III
III
76
70
-55
dBFS
dBFS
dB
DNL
1
IV
III
III
III
III
III
+0.5
1
0.5
III
IV
IV
IV
IV
IV
IV
IV
V
V
±1.0
1.2
2.5
0.7
1.7
1
1.35
1.05
1.2
±10
±10
5
0.2
85% OVDD 90% OVDD
1.9
4.8
V
V
V
V
0.4
AVDD -0.4
V
V
pF
0.4
V
V
µA
µA
pF
V
V
ns
ns
See “Input Signal Range” section
Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989
Revision: 1.0
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PRELIMINARY PRODUCT SPECIFICATION
nAD1210-25 12 Bit 10 MSPS Sampling ADC IP
fS
σAP
tAP
VDD
IDD
PD
PD
VSS
AVDDDVDD1
OVDD
T
Switching Performance
Conversion Rate
Pipeline Delay
Aperture jitter
Aperture delay
Power Supply
supply voltage
supply current (except digital output)
power dissipation (except digital output)
(10 MSPS)
power dissipation (except digital output)
1)
(sleep mode)
supply voltage
analog power – digital power pins
Output driver supply voltage
Ambient operating temperature
V
IV
V
V
V
IV
IV
10
7
TBD
1.4
2.25
IV
2.5
12
30
MSPS
Clocks
ps
ns
2.75
1.5
V
mA
mW
mW
GND
-0.2
III
IV
2.25
-40
2.5/3.0
+0.2
V
3.3
+85
V
°C
Table 3. Electrical specifications
1)
Power Down Mode (“zero” power dissipation) available for IP version of nAD1210-25
Test Levels
Test Level I: 100% production tested at +25°C
Test Level II: 100% production tested at +25°C and sample tested at specified
temperatures
Test Level III: Sample tested only
Test Level IV: Parameter is guaranteed by design and characterisation testing
Test Level V: Parameter is typical value only
Test Level VI: 100% production tested at +25°C. Guaranteed by design and
characterisation testing for industrial temperature range
ABSOLUTE MAXIMUM RATINGS
Supply voltages
AVDD ...............................- 0.3V to +3V
DVDD1 ..................- 0.3V to VDD + 0.3V
OVDD ...................- 0.3V to VDD + 0.3V
Temperatures
Operating Temperature....-40 to +85°C
Storage Temperature…..-65 to +125°C
Input voltages
Analog In.......... - 0.3V to AVDD + 0.3V
Digital In..............- 0.3V to VDD + 0.3V
REFP ................. - 0.3V to AVDD + 0.3V
REFN................. - 0.3V to AVDD + 0.3V
CLOCK ...............- 0.3V to VDD + 0.3V
Note: Stress above one or more of the
limiting values may cause permanent
damage to the device.
Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989
Revision: 1.0
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PRELIMINARY PRODUCT SPECIFICATION
nAD1210-25 12 Bit 10 MSPS Sampling ADC IP
PIN FUNCTIONS
Pin Name
Description
INP INN
REFP REFN
Differential input signal pins. Common mode voltage: 1.2V
Reference input pins. Bypass with 100nF || 1nF capacitors close to the pins. See
Application Information below.
Digital inputs for max. sampling rate programming.
BIAS1=0, BIAS0=0: Sleep mode (power save)
BIAS1=0, BIAS0=1: - 12.5% bias
BIAS1=1, BIAS0=0: +12.5% bias
BIAS1=1, BIAS0=1: Typ. Bias
BIAS0, BIAS1
CLK
CM
BIT11 - BIT0
PD
EXTREF
VDD
VSS
OVDD
The bias current is automatically scaled based on the clock input frequency.
Clock input
Common mode voltage output
Digital outputs ( MSB to LSB)
Power Down. Tie to Vss for normal operation.
Disable internal references
Power pins for chip core
Ground pins
Power pins for output drivers
Table 4. Pin functions
IP BLOCK OUTLINE
The height and width of the layout is X =1875µm and Y=800µm respectively
(PRELIMINARY).
Figure 2. IP block outline and pin placement for nAD1210-25
Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989
Revision: 1.0
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PRELIMINARY PRODUCT SPECIFICATION
nAD1210-25 12 Bit 10 MSPS Sampling ADC IP
TIMING DIAGRAM
Figure 4. Timing diagram
INPUT SIGNAL RANGE
Figure 5. Definition of full scale range
Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989
Revision: 1.0
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PRELIMINARY PRODUCT SPECIFICATION
nAD1210-25 12 Bit 10 MSPS Sampling ADC IP
DEFINITIONS
Data sheet status
Objective product specification
Preliminary product
specification
Product specification
This datasheet contains target specifications for product development.
This datasheet contains preliminary data; supplementary data may be
published from Nordic VLSI ASA later.
This datasheet contains final product specifications.
Limiting values
Stress above one or more of the limiting values may cause permanent damage to the device. These are stress
ratings only and operation of the device at these or at any other conditions above those given in the
Specifications sections of the specification is not implied. Exposure to limiting values for extended periods may
affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Table 5. Definitions
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems
where malfunction of these products can reasonably be expected to result in personal
injury. Nordic VLSI ASA customers using or selling these products for use in such
applications do so at their own risk and agree to fully indemnify Nordic VLSI ASA
for any damages resulting from such improper use or sale.
Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989
Revision: 1.0
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PRELIMINARY PRODUCT SPECIFICATION
nAD1210-25 12 Bit 10 MSPS Sampling ADC IP
APPLICATION INFORMATION
References
The nAD1210-25 has a differential analog input. The input range is determined by the
voltages on the reference pins REFP and REFN respectively, and is equal to
±(VREFP-VREFN). Externally generated reference voltages connected to REFP and
REFN should be symmetric around 1.2V. The input range can be defined between
±0.5V and ±1.0V. The references should be bypassed as close to the converter pins as
possible using 100nF capacitors in parallel with smaller capacitors (e.g. 1nF) (to
ground). There should be decoupling between the reference, and from each reference
to ground.
Analog input
The input of the nAD1210-25 can be configured in various ways - dependent upon
whether a single ended or differential, AC- or DC-coupled input is wanted.
AC-coupled input is most conveniently implemented using a transformer with a centre
tapped secondary winding. The centre tap is connected to the CM-node, as shown in
figure 6. In order to obtain low distortion, it is important that the selected transformer
does not exhibit core saturation at full-scale. Excellent results are obtained with the
Mini Circuits T1-6T or T1-1T. Proper termination of the input is important for input
signal purity. A small capacitor (typ. 21pF) across the inputs attenuates kickbacknoise from the sample and hold. The CM-pin should be decoupled as close to the
package as possible with a 100nF capacitor in parallel with a 1nF capacitor.
21pF
Vin
ADC
Mini Circuits
T1-6T
INP
51Ω
CM
INN
Figure 6. AC coupled input using transformer
If a DC-coupled single ended input is wanted, a solution based on operational
amplifiers - as shown in Figure 7, is usually preferred. The AD826 is suggested for
low distortion and video bandwidth. Lower cost operational amplifiers may be used if
the demands are less strict. A good alternative for high performance applications is to
use AD8138 single ended to differential amplifier.
Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989
Revision: 1.0
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PRELIMINARY PRODUCT SPECIFICATION
nAD1210-25 12 Bit 10 MSPS Sampling ADC IP
51Ω
470Ω
AD826
Input
offset
Video
in
470Ω
ADC
51Ω
100Ω
AD826
INP
15pF
100Ω
INN
51Ω
51Ω
470Ω
AD826
470Ω
470Ω
Figure 7. DC-coupled single ended to differential conversion (power supplies and
bypassing not shown)
Clock
In order to preserve accuracy at high input frequency, it is important that the clock has
low jitter and steep edges. Rise/fall times should be kept shorter than 2ns whenever
possible. Overshoot should be avoided. Low jitter is especially important when
converting high frequency input signals. Jitter causes the noise floor to rise
proportionally to input signal frequency. Jitter may be caused by crosstalk on the PCB.
It is therefore recommended that the clock trace on the PCB is made as short as
possible.
Digital outputs
The digital output data appears in offset binary code. Full-scale negative input results
in output code 000...0. Full-scale positive input results in output code 111...1. Output
data are available 7 clock cycles after the data are sampled. The analog input is
sampled one aperture delay (tAP) after the high to low clock transition. Output data
should be sampled as shown in the timing diagram.
Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989
Revision: 1.0
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PRELIMINARY PRODUCT SPECIFICATION
nAD1210-25 12 Bit 10 MSPS Sampling ADC IP
PCB layout and decoupling
A well designed PCB is necessary to get good spectral purity from any high
performance ADC. A multilayer PCB with a solid ground plane is recommended for
optimum performance. If the system has a split analog and digital ground plane, it is
recommended that all ground pins on the ADC are connected to the analog ground
plane. It is our experience that this gives the best performance. The power supply pins
should be bypassed using 100nF || 1nF surface mounted capacitors as close to the
package pins as possible. Analog and digital supply pins should be separately filtered.
Dynamic testing
Careful testing using high quality instrumentation is necessary to achieve accurate test
results on high speed A/D-converters. It is important that the clock source and signal
source has low jitter. A spectrally pure, low noise RF signal generator - such as the
HP8662A or HP 8644B is recommended for the test signal. Low pass filtering or band
pass filtering of the input signal is usually necessary to obtain the required spectral
purity (SFDR > 75dB). The clock signal can be obtained from either a crystal
oscillator or a low-jitter pulse generator. Alternatively, a low-jitter RF-generator can
be used as a clock source. At Nordic VLSI, the Marconi Instruments 2041A is used.
The sinewave clock must then be applied to an ultra high-speed comparator (e.g.
MAX961) before application to the converter. The most consistent results are
obtained if the clock signal is phase locked to the input signal. Phase locking allows
testing without windowing of output data. A logic analyser with deep memory - such
as the HP16500-series, is recommended for test data acquisition.
Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989
Revision: 1.0
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PRELIMINARY PRODUCT SPECIFICATION
nAD1210-25 12 Bit 10 MSPS Sampling ADC IP
DESIGN CENTER
Nordic VLSI ASA
Vestre Rosten 81
N-7075 TILLER
NORWAY
Telephone:
+47 72898900
Telefax:
+47 72898989
E-mail: For further information regarding our state of the art data converters, please email us at [email protected]
World Wide Web/Internet: Visit our site at http://www.nvlsi.no.
ORDERING INFORMATION
Type number
nAD1210-25-IC
nAD1210-25-EVB
Description
nAD1210-25 sample in SSOP28
package (limited availability)
nAD1210-25 evaluation board
including characterisation report and
user guide
Table 6. Ordering information
Price
USD 50
USD 300
Available
March 15th,
2002
March 15th,
2002
Revision Date: September 4th 2001.
All rights reserved ®. Reproduction in whole or in part is prohibited without the prior
written permission of the copyright holder. Company and product names referred to in
this datasheet belong to their respective copyright/trademark holders.
Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989
Revision: 1.0
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