OBJECTIVE PRODUCT SPECIFICATION 12-Bit 20MSPS Sampling Analog-to-Digital Converter nAD1220-18T FEATURES APPLICATIONS • • • • • • • • • • • • • • • 3.3V power supply SINAD min 63.2dB for fin = 50MHz Low power (119mW @ 3.3V and 20MSPS) Frequency dependent biasing Internal, wideband Track/Hold Differential input Low input capacitance Power Down and Sleep Mode Imaging Test equipment Computer scanners Wireless communication Powerline communication Set top boxes Video products GENERAL DESCRIPTION The nAD1220-18T is a compact, high-speed, low power 12-bit monolithic analog-todigital converter, implemented in a 0.18µm single poly CMOS process with MiM capacitors and thick oxide transistor option. It has 12-bit resolution with 11 effective bits at low input frequencies, and close to 12 bit dynamic range for video frequency signals. The converter includes a high bandwidth track and hold. Using internal references, the full scale range is ±1V. The full scale range can be set between ±0.75V and ±1.0V using external references. It operates from a single 3.3V supply, while I/O is biased with 1.8V. Its low distortion and high dynamic range offers the performance needed for demanding imaging, multimedia, telecommunications and instrumentation applications. The bias current level for the ADC is automatically adjusted based on the clock input frequency. Hence, the power dissipation of the device is continuously minimised for the current operation frequency. QUICK REFERENCE DATA Symbol VDD IDD PD PD DNL INL fS N Parameter Supply voltage Supply current (30 MSPS) Power dissipation (15 MSPS) Power dissipation (20 MSPS) Differential nonlinearity Integral nonlinearity Conversion rate Resolution Conditions Except digital output drivers Except digital output drivers fIN=0.9991MHz fIN=0.9991MHz Min. Typ. Max. Unit 2.97 3.3 36 80 3.63 V mA mW 119 mW ±0.5 ±1.0 20 12 LSB LSB MHz bit Table 1. Quick reference data Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.3 Page 1 of 11 September 11th , 2001 OBJECTIVE PRODUCT SPECIFICATION nAD1220-18T 12 Bit 20 MSPS Sampling ADC IP GENERAL DESCRIPTION (Continued) The nAD1220-18T has a pipelined architecture - resulting in low input capacitance. Digital error correction of the 11 most significant bits ensures good linearity for input frequencies approaching Nyquist. The nAD1220-18T is compact. The core occupies less than 4mm2 of die area in the TSMC MiM 0.18µm CMOS process with thick oxide option. The fully differential architecture makes it insensitive to substrate noise. Thus it is ideal as a mixed signal ASIC macro cell. BLOCK DIAGRAM REF_HI REF_LO REF_SEL BIAS0 BIAS1 SCR_EN IN_N IN_P CK2 CK2B CKBUS<3:0> IN_CORR<19:0> CKCORR<1:0> CORR_LOG BIT<11:0> OR_LO CK0B OR_HI ADC_CLK ANCLOCK CK0 CLOCKBUF CM Figure 1. Block diagram nAD1220-18T Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.3 Page 2 of 11 September 11th , 2001 OBJECTIVE PRODUCT SPECIFICATION nAD1220-18T 12 Bit 20 MSPS Sampling ADC IP ELECTRICAL SPECIFICATIONS (At TA = 25°C, VDD = 3.3V, Sampling Rate = 20MHz, Input frequency = 15MHz, Differential input signal, 50% duty cycle clock unless otherwise noted ) Symbol Parameter (condition) DNL INL VOS CMRR εG SNR SINAD SFDR VFSR VCMI CINA VREFNO VREFPO VREFP-VREFN VCM FS tAP th td tAP th td DC Accuracy Differential Nonlinearity fIN = 0.9991 MHz Integral Nonlinearity fIN = 0.9991 MHz Midscale offset Common Mode Rejection Ratio Gain Error Dynamic Performance Signal to Noise Ratio (without harmonics) fIN = 10 MHz fIN = 50 MHz Signal to Noise and Distortion Ratio fIN = 10 MHz fIN = 50 MHz Spurious Free Dynamic Range fIN = 10 MHz fIN = 50 MHz Analog Input Input Voltage Range (differential) Common mode input voltage Input Capacitance (from each input to ground) Reference Voltages Internal reference voltage drift Negative Input Voltage Positive Input Voltage Reference input voltage range 1) Common mode output voltage Switching Performance Conversion Rate Pipeline Delay Aperture delay, IP Output hold time, IP Output delay time, IP Aperture delay, with bonding pad Output hold time, with bonding pad Output delay time, with bonding pad Test Level Min. Typ. IV IV ±1 TBD ±2 Max. Units ±0.5 LSB ±1.0 LSB %FS dB %FS ±5 IV IV 69 63.2 dBFS dBFS IV IV 67 63.2 dBFS IV IV 75 70 dB dB IV IV IV IV IV IV ±0.75 1.05 TBD 0.75 TBD IV IV V V V V V V ±1.0 1.65 1.15 2.15 0.75 1.65 TBD 150 V V FF 100 TBD 2.25 TBD TBD ppm/°C V V V V 20 6 0.3 2.0 2.7 TBD TBD TBD MSPS Clocks ns ns ns ns ns ns Digital Inputs VIL VIH IIL IIH CIND Logic “0” voltage Logic “1” voltage Logic “0” current (VI=VSS) Logic “1” current (VI=VDD) Input Capacitance IV IV IV IV IV 1.62 1.8 TBD 0.4 1.98 ±10 ±10 V V µA µA pF (table continued on next page) Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.3 Page 3 of 11 September 11th , 2001 OBJECTIVE PRODUCT SPECIFICATION nAD1220-18T 12 Bit 20 MSPS Sampling ADC IP VOL VOH VDD IDD VSS PD PD PD PD AVDDDVDD1 OVDD T Digital Outputs Logic “0” voltage (I = 2 mA) Logic “1” voltage (I = 2 mA) Power Supply Supply voltage Supply current (except digital output) Supply voltage Power dissipation (except digital output) (15 MSPS) Power dissipation (except digital output) (30 MSPS) Power dissipation (except digital output) 2) Power Down Mode Power dissipation (except digital output) Sleep Mode Analog power – digital power pins IV IV V IV 0.2 85% OVDD 90% OVDD V V 3.63 V mA IV 3.3 36 GND 80 IV 119 mW IV TBD µW IV TBD µW Output driver supply voltage Ambient operating temperature 2.97 0.4 -0.2 1.62 -40 1.8 mW +0.2 V 1.98 +85 V °C Table 2. Electrical specifications 1) See Figure 5. 2) Power Down Mode is only available for IP version of nAD1220-18T. Test Levels Test Level I: 100% production tested at +25°C Test Level II: 100% production tested at +25°C and sample tested at specified temperatures Test Level III: Sample tested only Test Level IV: Parameter is guaranteed by design and characterization testing Test Level V: Parameter is typical value only Test Level VI: 100% production tested at +25°C. Guaranteed by design and characterization testing for industrial temperature range ABSOLUTE MAXIMUM RATINGS Supply voltages AVDD ............................- 0.2V to +2.2V DVDD1 ..................- 0.2V to VDD + 0.2V OVDD ...................- 0.2V to VDD + 0.2V Input voltages Analog In.......... - 0.2V to AVDD + 0.2V Digital In..............- 0.2V to VDD + 0.2V REFP ................. - 0.2V to AVDD + 0.2V REFN ................ - 0.2V to AVDD + 0.2V CLOCK ............... - 0.2V to VDD + 0.2V Temperatures Operating Temperature ….-40 to +85°C Storage Temperature.. ... - 65 to +125°C Note: Stress above one or more of the limiting values may cause permanent damage to the device. Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.3 Page 4 of 11 September 11th , 2001 OBJECTIVE PRODUCT SPECIFICATION nAD1220-18T 12 Bit 20 MSPS Sampling ADC IP PIN FUNCTIONS Pin Name Description INP INN REFHI REFLO Differential input signal pins. Common mode voltage: 2.5V Reference input pins. Bypass with 100nF capacitors close to the pins. See Application Information below. BIAS0, BIAS1 Digital inputs for max. sampling rate programming. BIAS1=0, BIAS0=0: Sleep mode (power save) BIAS1=0, BIAS0=1: - 12.5% bias BIAS1=1, BIAS0=0: +12.5% bias BIAS1=1, BIAS0=1: Typ. Bias ADC_CLK CM BIT11 - BIT0 SCR_EN REF_SEL OR_HI, OR_LO VDD VSS OVDD The bias setting is automatically performed based on the clock input frequency. This function should be used ONLY if another bias setting than typical must be used. Clock input Common mode voltage output Digital outputs ( MSB to LSB) Enable scrambling algorithm Disable internal references Overflow HIGH input Overflow LOW input Power pins for on chip power Ground pins Power pins for output drivers Table 3. Pin functions PIN ASSIGNMENT (TBD) Figure 2. Pin assignment for the package used for samples IP BLOCK LAYOUT (TBD) Figure 3. Size and pin placement for nAD1220-18T. The height and width of the layout is X =2000µm and Y=1550µm respectively in the 0.18µm CMOS process. Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.3 Page 5 of 11 September 11th , 2001 OBJECTIVE PRODUCT SPECIFICATION nAD1220-18T 12 Bit 20 MSPS Sampling ADC IP TIMING DIAGRAM CLOCK S A M N-1 P L E S A M N P L E S A M N+1 P L E tAP S A M N+2 P L E t t h d Data N-1 DATA Data N Data N+1 Figure 4. Timing diagram IP version INPUT SIGNAL RANGE VREFP VINP VINN VCM VRR VREFN +VRR VINP-VINN VFSR -VRR Figure 5. Definition of full scale range Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.3 Page 6 of 11 September 11th , 2001 OBJECTIVE PRODUCT SPECIFICATION nAD1220-18T 12 Bit 20 MSPS Sampling ADC IP DEFINITIONS Data sheet status Objective product specification Preliminary product specification Product specification This datasheet contains target specifications for product development. This datasheet contains preliminary data; supplementary data may be published from Nordic VLSI ASA later. This datasheet contains final product specifications. Limiting values Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Specifications sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. Table 4. Definitions LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Nordic VLSI ASA customers using or selling these products for use in such applications do so at their own risk and agree fully indemnify Nordic VLSI ASA for any damages resulting from such improper use or sale. Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.3 Page 7 of 11 September 11th , 2001 OBJECTIVE PRODUCT SPECIFICATION nAD1220-18T 12 Bit 20 MSPS Sampling ADC IP APPLICATION INFORMATION References The nAD1220-18T has a differential analog input. The input range is determined by the voltages VREFP and VREFN applied to reference pins REFP and REFN respectively, and is equal to ±(VREFP-VREFN). Externally generated reference voltages connected to REFP and REFN should be symmetrical around 1.65V. The input range can be defined between ±0.5V and ±0.75V. The references should be bypassed as close to the converter pins as possible using 100nF capacitors in parallel with smaller capacitors (e.g. 1nF) (to ground). Analog input The input of the nAD1220-18T can be configured in various ways - dependent upon whether a single ended or differential, AC- or DC-coupled input is wanted. AC-coupled input is most conveniently implemented using a transformer with a center tapped secondary winding. The center tap is connected to the CM-node, as shown in figure 6. In order to obtain low distortion, it is important that the selected transformer does not exhibit core saturation at full-scale. Excellent results are obtained with the Mini Circuits T1-6T or T1-1T. Proper termination of the input is important for input signal purity. A small capacitor across the inputs attenuates kickback-noise from the sample and hold. Series resistors as shown in Figure 6 may be advantageous to improve linearity. The VCM-node should be bypassed to ground as closed to the converter pin as possible using 100nF capacitors in parallel with a small one. Vin Mini Circuits T1-6T 50Ω ADC INP 51Ω 22pF VCM INN 50Ω Figure 6. Example of AC coupled input using transformer configuration If a DC-coupled single ended input is wanted, a solution based on operational amplifiers - as shown in Figure 7, is usually preferred. The AD826 is suggested for low distortion and video bandwidth. Lower cost operational amplifiers may be used if the demands are less strict. A good alternative for high performance applications is to use AD8138 single ended to differential amplifier. Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.3 Page 8 of 11 September 11th , 2001 OBJECTIVE PRODUCT SPECIFICATION nAD1220-18T 12 Bit 20 MSPS Sampling ADC IP 51Ω 470Ω AD826 Input offset Video in 470Ω ADC 51Ω 100Ω AD826 INP 15pF 100Ω INN 51Ω 51Ω 470Ω AD826 470Ω 470Ω Figure 7. DC-coupled single ended to differential conversion (power supplies and bypassing not shown) Clock In order to preserve accuracy at high input frequency, it is important that the clock has low jitter and steep edges. Rise/fall times should be kept shorter than 2ns whenever possible. Overshoot should be avoided. Low jitter is especially important when converting high frequency input signals. Jitter causes the noise floor to rise proportionally to input signal frequency. Jitter may be caused by crosstalk on the PCB. It is therefore recommended that the clock trace on the PCB is made as short as possible. Digital outputs The digital output data appears in offset binary code at CMOS logic levels. Full-scale negative input results in output code 000...0. Full-scale positive input results in output code 111...1. Output data are available 6 clock cycles after the data are sampled. The analog input is sampled one aperture delay (tAP) after the high to low clock transition. Output data should be sampled as shown in the timing diagram. PCB layout and decoupling A well designed PCB is necessary to get good spectral purity from any high performance ADC. A multilayer PCB with a solid ground plane is recommended for optimum performance. If the system has a split analog and digital ground plane, it is recommended that all ground pins on the ADC are connected to the analog ground plane. It is our experience that this gives the best performance. The power supply pins should be bypassed using 100nF surface mounted capacitors as close to the package pins as possible. Analog and digital supply pins should be separately filtered. Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.3 Page 9 of 11 September 11th , 2001 OBJECTIVE PRODUCT SPECIFICATION nAD1220-18T 12 Bit 20 MSPS Sampling ADC IP Dynamic testing Careful testing using high quality instrumentation is necessary to achieve accurate test results on high speed A/D-converters. It is important that the clock source and signal source has low jitter. A spectrally pure, low noise RF signal generator - such as the HP8662A or HP8644B is recommended for the test signal. Low pass filtering or band pass filtering of the input signal is usually necessary to obtain the required spectral purity (SFDR > 75dB). The clock signal can be obtained from either a crystal oscillator or a low-jitter pulse generator. Alternatively, a low-jitter RF-generator can be used as a clock source. At Nordic VLSI, the Marconi Instruments 2041A is used. The sinewave clock must then be applied to an ultra high-speed comparator (e.g. AD9696) and a TTL to CMOS level shifter (e.g. 74LV04) before application to the converter. The most consistent results are obtained if the clock signal is phase locked to the input signal. Phase locking allows testing without windowing of output data. A logic analyzer with deep memory - such as the HP16500-series, is recommended for test data acquisition. Power Down Mode and Sleep Mode The nAD1220-18T has both Power Down Mode and Sleep Mode. The Power Down Mode can be used when the ADC should be put to ‘zero current consumption’ state and when a somewhat longer startup time is allowed. The Sleep Mode can be used to put the ADC in an ‘idle’ state and when the application require a quick startup. The two different power consumption saving schemes can be activated through the PD, BIAS0 and BIAS1 pins/connections in the following manner: Power Down Mode: (TBD) Sleep Mode: (TBD) The actual startup time from these modes are dependent on the external decopling configuration. Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.3 Page 10 of 11 September 11th , 2001 OBJECTIVE PRODUCT SPECIFICATION nAD1220-18T 12 Bit 20 MSPS Sampling ADC IP DESIGN CENTER Nordic VLSI ASA Vestre Rosten 81 N-7075 TILLER NORWAY Telephone: +47 72898900 Telefax: +47 72898989 E-mail: For further information regarding our state of the art data converters, please email us at [email protected]. World Wide Web/Internet: Visit our site at http://www.nvlsi.no. ORDERING INFORMATION Type number nAD1220-18T-IC nAD1220-18T-EVB Description nAD1220-18T sample in SSOP28 package (limited availability) nAD1220-18T evaluation board including characterisation report and user guide Table 5. Ordering information Price USD 50 USD 300 Available January 15th, 2002 January 15th, 2002 Product Specification. Revision Date: September 11th, 2001 All rights reserved ®. Reproduction in whole or in part is prohibited without the prior written permission of the copyright holder. Company and product names referred to in this datasheet belong to their respective copyright/trademark holders. Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.3 Page 11 of 11 September 11th , 2001