NSL12TT1 High Current Surface Mount PNP Silicon Low VCE(sat) Transistor for Battery Operated Applications http://onsemi.com 12 VOLTS 1.0 AMPS PNP TRANSISTOR MAXIMUM RATINGS (TA = 25°C) Rating Symbol Max Unit Collector-Emitter Voltage VCEO –12 Vdc Collector-Base Voltage VCBO –20 Vdc Emitter-Base Voltage VEBO –4.0 Vdc IC –1.0 –0.5 Adc Collector Current – Peak Collector Current – Continuous Electrostatic Discharge ESD COLLECTOR 3 1 BASE HBM Class 3B MM Class C 2 EMITTER THERMAL CHARACTERISTICS Characteristic Total Device Dissipation TA = 25°C Derate above 25°C Thermal Resistance, Junction to Ambient Total Device Dissipation TA = 25°C Derate above 25°C Symbol Max Unit PD (Note 1) 210 mW 1.7 mW/°C RθJA (Note 1) 595 °C/W 1 PD (Note 2) 365 mW 2.9 mW/°C CASE 463 SOT–416/SC–75 STYLE 1 Thermal Resistance, Junction to Ambient RθJA (Note 2) 340 °C/W Thermal Resistance, Junction to Lead #3 RθJL 205 °C/W Junction and Storage Temperature Range TJ, Tstg –55 to +150 °C 3 2 DEVICE MARKING L2 1. FR–4 @ Minimum Pad 2. FR–4 @ 1.0 X 1.0 inch Pad L2 = Specific Device Code ORDERING INFORMATION Device NSL12TT1 Semiconductor Components Industries, LLC, 2002 February, 2002 – Rev. 2 1 Package Shipping SOT–416 3000/Tape & Reel Publication Order Number: NSL12TT1/D NSL12TT1 ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Characteristic Symbol Min Typical Max –12 –18 – –20 –28 – –4.0 –7.0 – – –0.03 –0.1 – –0.03 –0.1 – –0.01 –0.1 150 150 100 200 200 150 – – – – – – – – – – –0.070 –0.110 –0.190 –0.165 –0.300 –0.210 –0.410 –0.110 –0.150 –0.240 – –0.370 – – – –0.81 –0.90 – –0.81 –0.875 – 52 – – 30 – – 50 – – 80 – Unit OFF CHARACTERISTICS Collector–Emitter Breakdown Voltage (IC = –10 mAdc, IB = 0) V(BR)CEO Collector–Base Breakdown Voltage (IC = –0.1 mAdc, IE = 0) V(BR)CBO Emitter–Base Breakdown Voltage (IE = –0.1 mAdc, IC = 0) V(BR)EBO Collector Cutoff Current (VCB = –12 Vdc, IE = 0) ICBO Collector–Emitter Cutoff Current (VCES = –9 Vdc) ICES Emitter Cutoff Current (VEB = –4.0 Vdc) IEBO Vdc Vdc Vdc Adc Adc Adc ON CHARACTERISTICS DC Current Gain (Note 3) (IC = –100 mA, VCE = –1.0 V) (IC = –100 mA, VCE = –2.0 V) (IC = –500 mA, VCE = –2.0 V) hFE Collector–Emitter Saturation Voltage (Note 3) (IC = –50 mA, IB = –0.5 mA) (IC = –100 mA, IB = –1.0 mA) (IC = –250 mA, IB = –2.5 mA) (IC = –250 mA, IB = –5.0 mA) (IC = –500 mA, IB = –5.0 mA) (IC = –500 mA, IB = –50 mA) (IC = –1.0 A, IB = –100 mA) VCE(sat) Base–Emitter Saturation Voltage (Note 3) (IC = –150 mA, IB = –20 mA) VBE(sat) Base–Emitter Turn–on Voltage (Note 3) (IC = –150 mA, VCE = –3.0 V) VBE(on) Input Capacitance (VEB = 0 V, f = 1.0 MHz) Cibo Output Capacitance (VCB = 0 V, f = 1.0 MHz) Cobo Turn–On Time (IBI = –50 mA, IC = –500 mA, RL = 3.0 Ω) ton Turn–Off Time (IB1 = IB2 = –50 mA, IC = –500 mA, RL = 3.0 Ω) toff 3. Pulsed Condition: Pulse Width = 300 sec, Duty Cycle ≤ 2% Figure 1. http://onsemi.com 2 V V V pF pF ns ns NSL12TT1 0.1 1 VCE(sat), COLLECTOR EMITTER SATURATION VOLTAGE (V) VCE(sat), COLLECTOR EMITTER SATURATION VOLTAGE (V) 1 IC/IB = 200 100 50 0.01 10 TA = 25°C 0.001 0.001 0.01 0.1 –55°C 0.1 TA = 125°C Figure 1. Collector Emitter Saturation Voltage vs. Collector Current Figure 2. Collector Emitter Saturation Voltage vs. Collector Current 1 VCE(sat), COLLECTOR EMITTER SATURATION VOLTAGE (V) 125°C 400 300 25°C 200 TA = –55°C 100 0.01 0.001 0.1 IC/IB = 50 25°C 0.1 –55°C TA = 125°C 0.01 0.001 1 IC, COLLECTOR CURRENT (AMPS) 0.1 1 Figure 4. Collector Emitter Saturation Voltage vs. Collector Current 1 1.2 VBE(sat), BASE EMITTER SATURATION VOLTAGE (V) TA = 25°C 0.9 VCE(sat), COLLECTOR EMITTER SATURATION VOLTAGE (V) 0.01 IC, COLLECTOR CURRENT (AMPS) Figure 3. DC Current Gain 0.8 IC = 1.0 A 0.7 0.6 0.5 0.4 500 mA 50 mA 250 mA 0.2 0.1 1 IC, COLLECTOR CURRENT (AMPS) 500 0.3 0.1 0.01 IC, COLLECTOR CURRENT (AMPS) VCE = 1.0 V hFE, DC CURRENT GAIN 25°C 0.01 0.001 1 600 0 IC/IB = 100 10 mA 5.0 mA 0 0.00001 0.0001 1 –55°C 0.8 25°C TA = 125°C 0.6 0.4 0.2 100 mA 0.001 0.01 0.1 1 0 0.001 IB, BASE CURRENT (AMPS) 0.01 0.1 IC, COLLECTOR CURRENT (AMPS) Figure 5. Collector Emitter Saturation Voltage vs Base Current Figure 6. Base Emitter Saturation Voltage vs. Collector Current http://onsemi.com 3 1 NSL12TT1 55 VCE = 3.0 V 1 Cibo, INPUT CAPACITANCE VBE(on), BASE EMITTER TURN–ON VOLTAGE (V) 1.2 –55°C 0.8 25°C 0.6 TA = 125°C 0.4 0.2 0 0.001 0.01 0.1 1 f = 1 MHz IC = 0 A TA = 25°C 50 45 40 35 30 25 20 0 1 2 3 4 IC, COLLECTOR CURRENT (AMPS) VEB, EMITTER BASE VOLTAGE Figure 7. Base Emitter Turn–On Voltage vs. Collector Current Figure 8. Input Capacitance 5 6 Cobo, OUTPUT CAPACITANCE 35 f = 1 MHz IE = 0 A TA = 25°C 30 25 20 15 10 0 2 4 6 8 10 12 14 VCB, COLLECTOR BASE VOLTAGE r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) Figure 9. Output Capacitance 1 D = 0.50 D = 0.20 P(pk) D = 0.10 0.1 D = 0.05 t1 t2 DUTY CYCLE, D = t1/t2 D = 0.01 Copper Area = 0.048 square inches RθJA = 505.7 °C/W SINGLE PULSE 0.01 0.0001 0.001 0.01 0.1 t1, TIME (s) 1 Figure 10. Normalized Thermal Response http://onsemi.com 4 10 100 1000 NSL12TT1 INFORMATION FOR USING THE SOT–416 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ 0.5 min. (3x) Unit: mm 1 TYPICAL SOLDERING PATTERN 0.5 0.5 min. (3x) 1.4 SOT–416/SC–90 POWER DISSIPATION The power dissipation of the SOT–416/SC–90 is a function of the pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RθJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet, PD can be calculated as follows. PD = the equation for an ambient temperature TA of 25°C, one can calculate the power dissipation of the device which in this case is 125 milliwatts. PD = 150°C – 25°C 833°C/W = 150 milliwatts The 833°C/W assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 150 milliwatts. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Clad. Using a board material such as Thermal Clad, a higher power dissipation can be achieved using the same footprint. TJ(max) – TA RθJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into SOLDERING PRECAUTIONS • The soldering temperature and time should not exceed The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. • Always preheat the device. • The delta temperature between the preheat and soldering should be 100°C or less.* • When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference should be a maximum of 10°C. • • • 260°C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient should be 5°C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 5 NSL12TT1 SOLDER STENCIL GUIDELINES The stencil opening size for the surface mounted package should be the same as the pad size on the printed circuit board, i.e., a 1:1 registration. Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. A solder stencil is required to screen the optimum amount of solder paste onto the footprint. The stencil is made of brass or stainless steel with a typical thickness of 0.008 inches. TYPICAL SOLDER HEATING PROFILE The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177–189°C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating “profile” for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 11 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. STEP 1 PREHEAT ZONE 1 RAMP" 200°C 150°C STEP 5 STEP 4 HEATING HEATING ZONES 3 & 6 ZONES 4 & 7 SPIKE" SOAK" STEP 2 STEP 3 VENT HEATING SOAK" ZONES 2 & 5 RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES 205° TO 219°C PEAK AT SOLDER JOINT 170°C 160°C 150°C 140°C 100°C 100°C 50°C STEP 6 STEP 7 VENT COOLING SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 11. Typical Solder Heating Profile http://onsemi.com 6 NSL12TT1 PACKAGE DIMENSIONS SC–75/SOT–416 CASE 463–01 ISSUE B –A– S NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 2 3 D 3 PL 0.20 (0.008) G –B– 1 M B K J 0.20 (0.008) A C L DIM A B C D G H J K L S MILLIMETERS MIN MAX 0.70 0.80 1.40 1.80 0.60 0.90 0.15 0.30 1.00 BSC --0.10 0.10 0.25 1.45 1.75 0.10 0.20 0.50 BSC STYLE 1: PIN 1. BASE 2. EMITTER 3. COLLECTOR H http://onsemi.com 7 INCHES MIN MAX 0.028 0.031 0.055 0.071 0.024 0.035 0.006 0.012 0.039 BSC --0.004 0.004 0.010 0.057 0.069 0.004 0.008 0.020 BSC NSL12TT1 Thermal Clad is a trademark of the Bergquist Company. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATION Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada Email: [email protected] JAPAN: ON Semiconductor, Japan Customer Focus Center 4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031 Phone: 81–3–5740–2700 Email: [email protected] ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative. N. American Technical Support: 800–282–9855 Toll Free USA/Canada http://onsemi.com 8 NSL12TT1/D