DS90LV004 4-Channel LVDS Buffer/Repeater with Pre-Emphasis General Description Features The DS90LV004 is a four channel 1.5 Gbps LVDS buffer/repeater. High speed data paths and flow-through pinout minimize internal device jitter and simplify board layout, while configurable pre-emphasis overcomes ISI jitter effects from lossy backplanes and cables. The differential inputs interface to LVDS, and Bus LVDS signals such as those on National's 10-, 16-, and 18- bit Bus LVDS SerDes, as well as CML and LVPECL. The differential inputs and outputs are internally terminated with a 100Ω resistor to improve performance and minimize board space. The repeater function is especially useful for boosting signals for longer distance transmission over lossy cables and backplanes. ■ 1.5 Gbps data rate per channel ■ Configurable pre-emphasis drives lossy backplanes and ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ cables Low output skew and jitter Hot plug protection LVDS/CML/LVPECL compatible input, LVDS output On-chip 100Ω input and output termination 15 kV ESD protection on LVDS inputs and outputs Single 3.3V supply Very low power consumption Industrial -40 to +85°C temperature range Small TQFP Package Footprint Evaluation Kit Available See SCAN90004 for JTAG-enabled version Typical Application 20146620 © 2007 National Semiconductor Corporation 201466 www.national.com DS90LV004 4-Channel LVDS Buffer/Repeater with Pre-Emphasis October 2007 DS90LV004 Block and Connection Diagrams 20146601 DS90LV004 Block Diagram 20146602 TQFP Pinout - Top View www.national.com 2 DS90LV004 Pin Descriptions Pin Name TQFP Pin Number I/O, Type Description DIFFERENTIAL INPUTS IN0+ IN0− 13 14 I, LVDS Channel 0 inverting and non-inverting differential inputs. IN1+ IN1− 15 16 I, LVDS Channel 1 inverting and non-inverting differential inputs. IN2+ IN2− 19 20 I, LVDS Channel 2 inverting and non-inverting differential inputs. IN3+ IN3− 21 22 I, LVDS Channel 3 inverting and non-inverting differential inputs. DIFFERENTIAL OUTPUTS OUT0+ OUT0− 48 47 O, LVDS Channel 0 inverting and non-inverting differential outputs. (Note 1) OUT1+ OUT1− 46 45 O, LVDS Channel 1 inverting and non-inverting differential outputs. (Note 1) OUT2+ OUT2− 42 41 O, LVDS Channel 2 inverting and non-inverting differential outputs. (Note 1) OUT3+ OUT3- 40 39 O, LVDS Channel 3 inverting and non-inverting differential outputs. (Note 1) DIGITAL CONTROL INTERFACE PWDN 12 I, LVTTL A logic low at PWDN activates the hardware power down mode. PEM0 PEM1 1 2 I, LVTTL Pre-emphasis Control Inputs (affects all Channels) VDD 3, 4, 5, 7, 10, 11, 27, 28, 29, 32, 33, 34 I, Power VDD = 3.3V, ±5% GND 8, 9, 17, 18, 23, 24, 25, 26, 37, 38, 43, 44 I, Power Ground reference for LVDS and CMOS circuitry. N/C 6, 30, 31, 35, 36 POWER No Connect Note 1: The LVDS outputs do not support a multidrop (BLVDS) environment. The LVDS output characteristics of the DS90LV004 device have been optimized for point-to-point backplane and cable applications. 3 www.national.com DS90LV004 Absolute Maximum Ratings (Note 2) Supply Voltage (VDD) CMOS Input Voltage LVDS Receiver Input Voltage (Note 3) LVDS Driver Output Voltage LVDS Output Short Circuit Current Junction Temperature Storage Temperature Lead Temperature (Solder, 4sec) Max Pkg Power Capacity @ 25°C EIAJ, 0Ω, 200pF Charged Device Model −0.3V to +4.0V −0.3V to (VDD+0.3V) Recommended Operating Conditions −0.3V to (VDD+0.3V) −0.3V to (VDD+0.3V) -90 mA +150°C −65°C to +150°C 260°C 1.64W Thermal Resistance (θJA) Package Derating above +25°C ESD Last Passing Voltage HBM, 1.5kΩ, 100pF 250V 1000V Supply Voltage (VCC) Input Voltage (VI) (Note 3) Output Voltage (VO) Operating Temperature (TA) Industrial 3.15V to 3.45V 0V to VCC 0V to VCC −40°C to +85°C Note 2: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of products outside of recommended operation conditions. 76°C/W 13.2mW/°C 15 kV Note 3: VID max < 2.4V Electrical Characteristics Over recommended operating supply and temperature ranges unless other specified. Symbol Parameter Conditions Min Typ (Note 4) Max Units VDD V LVTTL DC SPECIFICATIONS (PWDN, PEM0, PEM1) VIH High Level Input Voltage VIL Low Level Input Voltage GND 0.8 V IIH High Level Input Current VIN = VDD = VDDMAX −10 +10 µA IIL Low Level Input Current VIN = VSS, VDD = VDDMAX −10 +10 µA CIN1 Input Capacitance Any Digital Input Pin to VSS VCL Input Clamp Voltage ICL = −18 mA 2.0 −1.5 3.5 pF −0.8 V LVDS INPUT DC SPECIFICATIONS (INn±) VTH Differential Input High Threshold VCM = 0.8V to 3.4V, (Note 5) VDD = 3.45V VTL Differential Input Low Threshold VCM = 0.8V to 3.4V, (Note 5) VDD = 3.45V VID Differential Input Voltage VCM = 0.8V to 3.4V, VDD = 3.45V 100 2400 mV VCMR Common Mode Voltage Range VID = 150 mV, VDD = 3.45V 0.05 3.40 V CIN2 Input Capacitance IN+ or IN− to VSS IIN Input Current VIN = 3.45V, VDD = VDDMAX −10 +10 µA VIN = 0V, VDD = VDDMAX −10 +10 µA www.national.com 0 −100 100 0 mV 3.5 4 mV pF Parameter Conditions Min Typ (Note 4) Max Units 250 500 600 mV 35 mV 1.475 V 35 mV −90 mA LVDS OUTPUT DC SPECIFICATIONS (OUTn±) RL = 100Ω external resistor between OUT+ and OUT− VOD Differential Output Voltage, 0% Pre-emphasis (Note 5) ΔVOD Change in VOD between Complementary States −35 VOS Offset Voltage (Note 6) 1.05 ΔVOS Change in VOS between Complementary States −35 IOS Output Short Circuit Current OUT+ or OUT− Short to GND −60 COUT2 Output Capacitance OUT+ or OUT− to GND when TRI-STATE 5.5 All inputs and outputs enabled and active, terminated with differential load of 100Ω between OUT+ and OUT-, 0% pre-emphasis 117 140 mA 2.7 6 mA 210 300 ps 210 300 ps 2.0 3.2 ns 2.0 3.2 ns 25 80 ps 50 125 ps 1.1 ns 1.18 pF SUPPLY CURRENT (Static) ICC ICCZ Supply Current Supply Current - Power Down Mode PWDN = L, 0% pre-emphasis SWITCHING CHARACTERISTICS—LVDS OUTPUTS tLHT Differential Low to High Transition Time Use an alternating 1 and 0 pattern at 200 Mbps, measure between 20% and 80% of VOD. (Note 11) tHLT Differential High to Low Transition Time tPLHD Differential Low to High Propagation Delay tPHLD Differential High to Low Propagation Delay tSKD1 Pulse Skew tSKCC Output Channel to Channel Skew Difference in propagation delay (tPLHD or tPHLD) among all output channels. (Note 11) tSKP Part to Part Skew Common Edge, parts at same temp and VCC (Note 11) tJIT Jitter (0% Pre-emphasis) (Note 7) RJ - Alternating 1 and 0 at 750 MHz (Note 8) 1.1 1.5 psrms DJ - K28.5 Pattern, 1.5 Gbps (Note 9) 43 62 psp-p TJ - PRBS 223-1 Pattern, 1.5 Gbps (Note 10) 35 85 psp-p Use an alternating 1 and 0 pattern at 200 Mbps, measure at 50% VOD between input to output. |tPLHD–tPHLD| (Note 11) tON LVDS Output Enable Time Time from PWDN to OUT± change from TRISTATE to active. 300 ns tOFF LVDS Output Disable Time Time from PWDN to OUT± change from active to TRI-STATE. 12 ns Note 4: Typical parameters are measured at VDD = 3.3V, TA = 25°C. They are for reference purposes, and are not production-tested. Note 5: Differential output voltage VOD is defined as ABS(OUT+–OUT−). Differential input voltage VID is defined as ABS(IN+–IN−). Note 6: Output offset voltage VOS is defined as the average of the LVDS single-ended output voltages at logic high and logic low states. Note 7: Jitter is not production tested, but guaranteed through characterization on a sample basis. Note 8: Random Jitter, or RJ, is measured RMS with a histogram including 1500 histogram window hits. The input voltage = VID = 500mV, 50% duty cycle at 750MHz, tr = tf = 50ps (20% to 80%). Note 9: Deterministic Jitter, or DJ, is measured to a histogram mean with a sample size of 350 hits. The input voltage = VID = 500mV, K28.5 pattern at 1.5 Gbps, tr = tf = 50ps (20% to 80%). The K28.5 pattern is repeating bit streams of (0011111010 1100000101). Note 10: Total Jitter, or TJ, is measured peak to peak with a histogram including 3500 window hits. Stimulus and fixture Jitter has been subtracted. The input voltage = VID = 500mV, 223-1 PRBS pattern at 1.5 Gbps, tr = tf = 50ps (20% to 80%). Note 11: Not production tested. Guaranteed by a statistical analysis on a sample basis at the time of characterization. 5 www.national.com DS90LV004 Symbol DS90LV004 INPUT FAILSAFE BIASING External pull up and pull down resistors may be used to provide enough of an offset to enable an input failsafe under open-circuit conditions. This configuration ties the positive LVDS input pin to VDD thru a pull up resistor and the negative LVDS input pin is tied to GND by a pull down resistor. The pull up and pull down resistors should be in the 5kΩ to 15kΩ range to minimize loading and waveform distortion to the driver. The common-mode bias point ideally should be set to approximately 1.2V (less than 1.75V) to be compatible with the internal circuitry. Please refer to application note AN-1194 “Failsafe Biasing of LVDS Interfaces” for more information. Feature Descriptions INTERNAL TERMINATIONS The DS90LV004 has integrated termination resistors on both the input and outputs. The inputs have a 100Ω resistor across the differential pair, placing the receiver termination as close as possible to the input stage of the device. The LVDS outputs also contain an integrated 100Ω ohm termination resistor, this resistor is used to reduce the effects of Near End Crosstalk (NEXT) and does not take the place of the 100 ohm termination at the inputs to the receiving device. The integrated terminations improve signal integrity and decrease the external component count resulting in space savings. OUTPUT CHARACTERISTICS The output characteristics of the DS90LV004 have been optimized for point-to-point backplane and cable applications, and are not intended for multipoint or multidrop signaling. POWERDOWN MODE The PWDN input activates a hardware powerdown mode. When the powerdown mode is active (PWDN=L), all input and output buffers and internal bias circuitry are powered off and disabled. Outputs are tri-stated in powerdown mode. When exiting powerdown mode, there is a delay associated with turning on bandgap references and input/output buffer circuits as indicated in the LVDS Output Switching Characteristics PRE-EMPHASIS Pre-emphasis dramatically reduces ISI jitter from long or lossy transmission media. Two pins are used to select the preemphasis level for all outputs: off, low, medium, or high. Pre-emphasis Control Selection Table PEM1 PEM0 0 0 Off 0 1 Low 1 0 Medium 1 1 High www.national.com Pre-Emphasis 6 20146631 Typical LVDS Driver DC-Coupled Interface to DS90LV004 Input 20146632 Typical CML Driver DC-Coupled Interface to DS90LV004 Input 20146633 Typical LVPECL Driver DC-Coupled Interface to DS90LV004 Input 7 www.national.com DS90LV004 drivers (i.e. LVPECL, LVDS, CML). The following three figures illustrate typical DC-coupled interface to common differential drivers. Note that the DS90LV004 inputs are internally terminated with a 100Ω resistor. INPUT INTERFACING The DS90LV004 accepts differential signals and allow simple AC or DC coupling. With a wide common mode range, the DS90LV004 can be DC-coupled with all common differential DS90LV004 and assumes that the receivers have high impedance inputs. While most differential receivers have a common mode input range that can accomodate LVDS compliant signals, it is recommended to check respective receiver's data sheet prior to implementing the suggested interface implementation. OUTPUT INTERFACING The DS90LV004 outputs signals that are compliant to the LVDS standard. Their outputs can be DC-coupled to most common differential receivers. The following figure illustrates typical DC-coupled interface to common differential receivers 20146634 Typical DS90LV004 Output DC-Coupled Interface to an LVDS, CML or LVPECL Receiver www.national.com 8 DS90LV004 Typical Performance Characteristics Power Supply Current vs. Bit Data Rate Total Jitter (TJ) vs. Bit Data Rate 20146641 20146642 Dynamic power supply current was measured while running a clock or PRBSTotal Jitter measured at 0V differential while running a PRBS 223-1 pattern with 223-1 pattern with all 4 channels active. VCC = 3.3V, TA = +25°C, VID = 0.5V,a single channel active. VCC = 3.3V, TA = +25°C, VID = 0.5V, 0% Pre-emphasis VCM = 1.2V Total Jitter (TJ) vs. Temperature Positive Edge Transition vs. Pre-emphasis Level 20146644 20146643 Total Jitter measured at 0V differential while running a PRBS 223-1 pattern with a single channel active. VCC = 3.3V, VID = 0.5V, VCM = 1.2V, 1.5 Gbps data rate, 0% Pre-emphasis 9 www.national.com DS90LV004 Physical Dimensions inches (millimeters) unless otherwise noted 48-TQFP NS Package Number VBC48a Order Number DS90LV004TVS (250 piece Tray) www.national.com 10 DS90LV004 Notes 11 www.national.com DS90LV004 4-Channel LVDS Buffer/Repeater with Pre-Emphasis Notes THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. NATIONAL MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE ACCURACY OR COMPLETENESS OF THE CONTENTS OF THIS PUBLICATION AND RESERVES THE RIGHT TO MAKE CHANGES TO SPECIFICATIONS AND PRODUCT DESCRIPTIONS AT ANY TIME WITHOUT NOTICE. NO LICENSE, WHETHER EXPRESS, IMPLIED, ARISING BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. TESTING AND OTHER QUALITY CONTROLS ARE USED TO THE EXTENT NATIONAL DEEMS NECESSARY TO SUPPORT NATIONAL’S PRODUCT WARRANTY. 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