PI6C9911 & PI6C9911E 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 5V High-Speed Programmable Skew Clock Buffers - SuperClock Product Features Description • Four pairs of programmable skew outputs • User-selectable output functions: − Selectable skews − Inverted and noninverted − Operation at ½ and ¼ input frequency − Operation at 2X and 4X input frequency • Low skew <100ps typical same pair, 250ps max. • Allow REF clock input to have Spread Spectrum modulation for EMI reduction • 2X, 4X, ½ and ¼ outputs • 3-level inputs for skew and output frequency control • External feedback, internal loop filter • Low cycle-to-cycle Jitter: <25ps RMS • Duty cycle of output clock signals: 45% min. 55% max. • Same pinout as Cypress CY7B9911 • Available in 32-pin PLCC Package (J) • Output Operation 3.75 to 100 MHz for PI6C9911 3.75 to 125 MHz for PI6C9911E The PI6C9911 and PI6C9911E are low-skew, low jitter, 5V phaselock-loop (PLL) programmable skew clock drivers, for high-performance computing and networking applications. These parts offer user-selectable skew-control of 4 output pairs, providing the timing delays necessary to optimize high-performance clock-distribution circuits. Each output can be hardwired to one of nine delay or function configurations. Delay increments are determined by the input clock frequency and the configurations selected by the user. The PI6C9911 and PI6C9911E allow the REF clock input to have Spread Spectrum modulation for EMI reduction. Both buffers are pin-compatable with Cypresss RoboClock CY7B9911, but with improved AC/DC characteristics. The PI6C9911 and PI6C9911E also have the same pinout as Cypresss CY7B9911and with balanced output drive. Logic Block Diagram Powered by ICminer.com Electronic-Library Service CopyRight 2003 REF GND TEST 2F1 30 2F0 4F0 6 28 GND 4F1 7 27 1F1 VCCQ 8 26 1F0 3Q0 VCCN 9 25 VCCN 3Q1 4Q1 10 24 1Q0 4Q0 11 23 1Q1 GND 12 22 GND GND 13 14 15 16 17 18 19 21 20 GND 2Q0 2Q1 1Q0 1Q1 1 32-Pin J 2Q0 1F0 1F1 31 2Q1 MATRIX 32 VCCN 2F0 2F1 1 29 4Q1 SELECT 2 FB Three Level Select Inputs 3F0 3F1 3 5 4Q0 SKEW 4 3F1 FS 4F0 4F1 VCCQ Vco and Time Unit Generator VCCN Filter 3Q0 REF Phase Freq Det 3Q1 FB FS TEST 3F0 Pin Configuration PS8451 01/27/00 PI6C9911 & PI6C9911E 5V High Speed Programmable Skew Clock Buffers - SuperClock 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Pin Definitions Signal Name I/O D e s cription REF Reference frequency input. This input supplies the frequency and timing reference which all functional variation is measured. FB PLL feedback input (typically connected to one of the eight outputs). FS Three- level frequency range select. See Table 1. 1F0, 1F1 I Three- level function select inputs for output pair 1 (1Q 0, 1Q 1). See Table 2. 2F0, 2F1 Three- level function select inputs for output pair 2 (2Q 0, 2Q 1). See Table 2. 3F0, 3F1 Three- level function select inputs for output pair 3 (3Q 0, 3Q 1). See Table 2. 4F0, 4F1 Three- level function select inputs for output pair 4 (4Q 0, 4Q 1). See Table 2. TEST Three- level select. See test mode section under the block diagram descriptions. 1Q 0, 1Q 1 O utput pair 1. See Table 2. 2Q 0, 2Q 1 3Q 0, 3Q 1 O O utput pair 2. See Table 2. O utput pair 3. See Table 2. 4Q 0, 4Q 1 O utput pair 4. See Table 2. VCCN Power supply for output drivers. VCCQ GND PWR Power supply for internal circuitry. Ground Block Diagram Description Phase Frequency Detector and Filter Skew Select Matrix These two blocks accept input signals from the reference frequency (REF) input and the feedback (FB) input and generate correction information to control the frequency of the Voltage-Controlled Oscillator (VCO). These blocks, along with the VCO, form a PhaseLocked Loop (PLL) that tracks the incoming REF signal. The skew select matrix is comprised of four independent sections. Each section has two low-skew, high-fanout drivers (xQ0, xQ1), and two corresponding three-level function select (xF0, xF1) inputs. Table 2 shows the nine possible output functions for each section as determined by the function select inputs. All times are measured with respect to the REF input assuming that the output connected to the FB input has 0tU selected. VCO and Time Unit Generator The VCO accepts analog control inputs from the PLL filter block and generates a frequency that is used by the time unit generator to create discrete time units that are selected in the skew mix matrix. The operational range of the VCO is determined by the FS control pin. The time unit (tU) is determined by the operating frequency of the device and the level of the FS pin as shown in Table 1. Powered by ICminer.com Electronic-Library Service CopyRight 2003 2 PS8451 01/27/00 PI6C9911 & PI6C9911E 5V High Speed Programmable Skew Clock Buffers - SuperClock 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Table 1. Frequency Range Select and tU Calculation(1) tU = 1 fNOM x N where N= Approximate Fre que ncy (M Hz) at which tU = 1.0ns 1F1, 2F1, 3F1, 4F1 LOW M in. M ax. LOW 15 30 44 22.7 MID 25 50 26 38.5 HIGH 40 100 16 62.5 LOW 20 40 44 22.7 MID 35 70 26 38.5 PI6C9911 PI6C9911E Function Se le cts MID HIGH t0 +5tU t0 +4tU t0 +3tU t0 +2tU t0 +1tU t0 t0 -1tU 62.5 t0 -2tU t0 -3tU 16 t0 -4tU 125 t0 -5tU 60 t0 -6tU HIGH Output Functions 1F0, 2F0, 1Q0, 1Q1, 3F0, 4F0 2Q0, 2Q1 3Q0, 3Q1 4Q0, 4Q1 LOW - 4tU Divide by 2 MID - 3tU - 6tU HIGH - 2tU - 4tU LOW - 1tU - 2tU MID - 0tU HIGH +1tU +2tU LOW +2tU +4tU MID +3tU +6tU HIGH +4tU Divide by 4 Inverted t0 +6tU FS(2,3) fNOM(M Hz) Table 2. Programmable Skew Configurations(1) FB Input 1Fx 3Fx REF Input 2Fx 4Fx (N/A) LM -6tU LL LH -4tU LM (N/A) -3tU LH ML ML (N/A) -1tU MM MM 0tU MH (N/A) +1tU HL MH HM (N/A) +3tU HH HL -2tU +2tU +4tU (N/A) HM +6tU (N/A) LL/HH DIVIDED (N/A) HH INVERT Figure 1. Typical Outputs with FB Connected to a Zero-Skew Output(4) Powered by ICminer.com Electronic-Library Service CopyRight 2003 3 PS8451 01/27/00 PI6C9911 & PI6C9911E 5V High Speed Programmable Skew Clock Buffers - SuperClock 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Test Mode Maximum Ratings The TEST input is a three-level input. In normal system operation, this pin is connected to ground, allowing the PI6C9911 to operate as explained briefly above (for testing purposes, any of the three-level inputs can have a removable jumper to ground, or be tied LOW through a 100Ω resistor. This will allow an external tester to change the state of these pins). (Above which the useful life may be impaired) Storage Temperature ............................................ 65ºC to +150ºC Ambient Temperature with Power Applied .............................................. 55ºC to +125ºC Supply Voltage to Ground Potential ....................... 0.5V to +7.0V DC Input Voltage .................................................... 0.5V to +7.0V Output Current into Outputs (LOW) ................................... 64mA Static Discharge Voltage (per MIL-STD-883, Method 3015) ................................. >2001V Latch-Up Current ............................................................ >200mA If the TEST input is forced to its MID or HIGH state, the device will operate with its internal phase locked loop disconnected, and input levels supplied to REF will directly control all outputs. Relative output to output functions are the same as in normal mode. In contrast with normal operation (TEST tied LOW). All outputs will function based only on the connection of their own function select inputs (xF0 and xF1) and the waveform characteristics of the REF input. Operating Range Range Ambie nt Te mpe rature Commercial 0ºC to +70ºC Industrial 40ºC to +85ºC VCC 5V ±10% Notes for Tables on Pages 3 through 7: 1. For all three-state inputs, HIGH indicates a connection to V CC, LOW indicates a connections to GND, and MID indicates an open connection. Internal termination circuitry holds an unconnected input to VCC/2. 2. The level to be set on FS is determined by the normal operating frequency (fNOM) of the VCO and the Time Unit Generator (see Logic Block Diagram). Nominal frequency (f NOM) always appears at 1Q0 and the other outputs when they are operated in their undivided modes (see Table 2). The frequency appearing at the REF and FB inputs will be f NOM when the output connected to FB is undivided. The frequency of the REF and FB inputs will be fNOM/2 or f NOM /4 when the part is configured for a frequency multiplication by using a divided output as the FB input. 3. When the FS pin is selected HIGH, the REF input must not transition upon power-up untill VCC has reached 4.3V. 4. FB connected to an output selected for zero skew (ie., xF1 = xF0 = MID). 6. These inputs are normally wired to VCC, GND, or left unconnected (actual threshhold voltages vary as a percentage of VCC). Internal termination resistors hols unconnected inputs at VCC/2. If these inputs are switched, the function and timing of the outputs may glitch and the PLL may require an additional tLOCK time before all datasheet limits are achieved. 10. Test measurement levels are TTL levels (1.5V to 1.5V). Test conditions assume signal transition times of 2ns or less and output loading as shown in the AC Test Loads and Waveforms unless specified. 11. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters. 12. Skew is defined as the time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with 30pF and terminated with 50Ω to 2.06V. 13. tSKEWPR is defined as the skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0tU. 14. tSKEW0 is defined as the skew between outputs when they are selected for 0tU. Other outputs are divided or inverted but not shifted. 15. There are three classes of outputs: Nominal (multiple of tU delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH), and Divided (3Qx and 4Qx only in Divide-by-2 or Divide-by-4 mode). 16. tDEV is the output-to-output skew between any two devices operating under the same conditions (VCC ambient temperature, air flow, etc.). 17. tODCV is the deviation of the output from a 50% duty cycle. Output pulse width variations are included in tSKEW2 and tSKEW4 specifications. 18. Specified with outputs loaded with 30pF. Devices are terminated through 50Ω to 2.06V. 19. tPWH is measured at 2.0V. TPWL is measured at 0.8V 20. tORISE and tOFALL measured between 0.8V and 2.0V. 21. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits. Powered by ICminer.com Electronic-Library Service CopyRight 2003 4 PS8451 01/27/00 PI6C9911 & PI6C9911E 5V High Speed Programmable Skew Clock Buffers - SuperClock 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 DC Characteristics Over the Operating Range Symbol Parameter Test Condition Min. Max. V OH Output HIGH Voltage Vcc = Min., IOH = –16mA V OL Output LOW Voltage Vcc = Min., IOL = 46mA VIH Input HIGH Voltage of REF, FB inputs 2.0 V CC VIL Input LOW Voltage of REF, FB inputs –0.5 0.8 VIH3 Input HIGH Voltage of 3-level inputs TEST, FS, xFn(6) VCC–0.85V V CC VIM3 Input MID Voltage of 3-level inputs TEST, FS, xFn(6) VCC/2 –0.5 VCC/2 +0 . 5 VIL3 Input LOW Voltage of 3-level inputs TEST, FS, xFn(6) IIN Input Leakage Current of REF, FB inputs I3 3-Level Input DC Current (TEST, FS, nF 1:0) 2.4 0.45 Min ≤VCC ≤ Max 10 VIN = VCC (HIGH level) 200 VIN = VCC/2 (MID level) 50 VIN = GND (LOW level) 200 Short Circuit Current VCC = Max. VOUT = GND (25° only) –250 ICCQ Operating Current usd by Internal Circuitry VCCN = VCCQ = Max. All Inputs Select Open ICCN Output Buffer Current per Output Pair VCCN = VCCQ = Max, IOUT = 0mA Input Selects Open, fMAX PD Power Dissipation per Output Pair V 0.85 VIN = VCC or GND, VCC = Max IOS Units 85 µΑ mA 14 78 mW Capacitance at REF and FB Parame te r De s cription Te s t Conditions M ax. Units CIN Input Capacitance TA = 25ºC, f = 1 MHz, VCC = 5.0V 10 pF AC Test Loads and Waveforms (PI6C9911) 5V 3.0V R1 CL CL = 30pF R2 2.0V R1 = 130Ω R2 = 91Ω (Includes fixture Vth = 1.5V 0.8V 0.0V and probe capacitance) ≤1ns (16) ≤1ns TTL Input Test Waveform TTL AC Test Load Powered by ICminer.com Electronic-Library Service CopyRight 2003 2.0V Vth = 1.5V 0.8V 5 PS8451 01/27/00 PI6C9911 & PI6C9911E 5V High Speed Programmable Skew Clock Buffers - SuperClock 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Switching Characteristics over the Operating Range(2,10,11) Parame te r Operating clock Frequency in MHz M in. 15 30 FS = MID 25 FS = HIGH(1,2,3) 40 (1,2) (1,2) tRPW H REF Pulse Width HIGH tRPW L REF Pulse Width LOW tU Programmable Skew Unit tS K EW PR M in. Typ. PI6C9911-5 M ax. FS = LOW FNOM PI6C9911-2 De s cription M ax. M in. 15 30 15 30 50 25 50 25 50 100 40 100 40 100 4.0 Typ. PI6C9911 4.0 Typ. M ax. 4.0 See Table 1 (12,13) Zero Output Matched- Pair Skew (xQ0, xQ1) (12,14) 0.05 0.20 0.1 0.25 0.1 0.25 tS K EW 0 Zero Output Skew (All Outputs) 0.10 0.25 0.25 0.5 0.3 0.75 tS K EW 1 Output Skew (Rise- Rise, Fall- Fall, Same Class Outputs)(12,15) 0.25 0.5 0.6 0.7 0.6 1.0 tS K EW 2 Output Skew (Rise- Fall, Nominal- Inverted, DividedDivided)(12,15) 0.30 0.5 0.50 1.2 1.0 1.5 tS K EW 3 Output Skew (Rise- Rise, Fall- Fall, Different Class Outputs)(12,15) 0.25 0.5 0.50 0.9 0.7 1.2 tS K EW 4 Output Skew (Rise- Fall, Nominal- Divided, DividedInverted)(12,15) 0.50 0.9 0.50 1.2 1.2 1.7 tDEV Device- to- Device Skew(11,16) tP D Propagation Delay, REF Rise to FB Rise 0.25 0 0.25 0.5 0 0.5 0.7 0.0 +0.7 t O DC V Output Duty Cycle Variation(17) 0.65 0 0.65 1.0 0 1.0 1.2 0.0 +1.2 tP W H 0.75 2.0 2.0 3.0 (18,19) 1.5 2.5 3.5 tP W L Output LOW Time Deviation from 50% tO RIS E Output Rise Time(18,20) (18,20) Output Fall Time t LO C K PLL Lock Time(21) tJ R Cycle- to Cycle Output Jitter RMS(11) Peak- to- Peak 1.65 (18,19) Output HIGH Time Deviation from 50% tO FALL 1.25 (11) Powered by ICminer.com Electronic-Library Service CopyRight 2003 6 0.15 1.0 1.2 0.15 1.0 1.5 0.15 1.5 2.5 0.15 1.0 1.2 0.15 1.0 1.5 0.15 1.5 2.5 0.5 0.5 0.5 25 25 25 200 200 200 PS8451 01/27/00 PI6C9911 & PI6C9911E 5V High Speed Programmable Skew Clock Buffers - SuperClock 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Switching Characteristics over the Operating Range(2,10,11) Parame te r Operating clock Frequency in MHz M in. 20 40 FS = MID 35 FS = HIGH(1,2,3) 60 (1,2) (1,2) tRPW H REF Pulse Width HIGH tRPW L REF Pulse Width LOW tU Programmable Skew Unit tS K EW PR M in. Typ. PI6C9911E-5 M ax. FS = LOW FNOM PI6C9911E-2 De s cription M ax. M in. 20 40 20 40 70 35 70 35 70 125 60 125 60 125 4.0 Typ. PI6C9911E 4.0 Typ. M ax. 4.0 See Table 1 (12,13) Zero Output Matched- Pair Skew (xQ0, xQ1) (12,14) 0.05 0.20 0.1 0.25 0.1 0.25 tS K EW 0 Zero Output Skew (All Outputs) 0.10 0.25 0.25 0.5 0.3 0.75 tS K EW 1 Output Skew (Rise- Rise, Fall- Fall, Same Class Outputs)(12,15) 0.25 0.5 0.6 0.7 0.6 1.0 tS K EW 2 Output Skew (Rise- Fall, Nominal- Inverted, DividedDivided)(12,15) 0.30 0.5 0.50 1.2 1.0 1.5 tS K EW 3 Output Skew (Rise- Rise, Fall- Fall, Different Class Outputs)(12,15) 0.25 0.5 0.50 0.9 0.7 1.2 tS K EW 4 Output Skew (Rise- Fall, Nominal- Divided, DividedInverted)(12,15) 0.50 0.9 0.50 1.2 1.2 1.7 tDEV Device- to- Device Skew(11,16) tP D Propagation Delay, REF Rise to FB Rise 0.25 0 0.25 0.5 0 0.5 0.7 0.0 +0.7 t O DC V Output Duty Cycle Variation(17) 0.65 0 0.65 1.0 0 1.0 1.2 0.0 +1.2 0.75 1.25 1.65 tP W H (18,19) Output HIGH Time Deviation from 50% 2.0 2.0 3.0 tP W L Output LOW Time Deviation from 50%(18,19) 1.5 2.5 3.5 tO RIS E Output Rise Time(18,20) (18,20) tO FALL Output Fall Time t LO C K PLL Lock Time(21) tJ R Cycle- to Cycle Output Jitter RMS(11) Peak- to- Peak (11) Powered by ICminer.com Electronic-Library Service CopyRight 2003 7 0.15 1.0 1.2 0.15 1.0 1.5 0.15 1.5 2.5 0.15 1.0 1.2 0.15 1.0 1.5 0.15 1.5 2.5 0.5 0.5 0.5 25 25 25 200 200 200 PS8451 01/27/00 PI6C9911 & PI6C9911E 5V High Speed Programmable Skew Clock Buffers - SuperClock 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 AC Timing Diagrams t REF t t RPWL RPWH REF t t PD ODCV t ODCV FB t JR Q t t SKEWPR, SKEWPR, t t SKEW0,1 SKEW0,1 OTHER Q t SKEW2 t SKEW2 INVERTED Q t t SKEW3,4 SKEW3,4 t SKEW3,4 REF DIVIDED BY 2 t t SKEW3,4 SKEW2,4 REF DIVIDED BY 4 Powered by ICminer.com Electronic-Library Service CopyRight 2003 8 PS8451 01/27/00 PI6C9911 & PI6C9911E 5V High Speed Programmable Skew Clock Buffers - SuperClock 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Package Diagram 32-Pin PLCC (J) .045 1.143 .050 1.27 BSC Typ. Pin 1 .025 .585 .547 .595 .553 14.859 13.894 15.113 14.046 0.635 Typ. .045 Typ. 1.143 .490 .530 .026 12.446 .032 13.462 0.661 0.812 .447 .453 11.354 11.506 .485 .495 12.319 12.573 .100 2.450 .140 3.556 .013 0.331 .021 0.533 .065 1.524 .095 2.413 X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS .015 0.381 Min. .390 9.906 .430 10.922 Ordering Information Part Numbe r Accuracy Package Ope rating Te mpe rature PI6C9911- 2 PI6C9911- 5 PI6C9911 250ps 500ps 750ps Commercial PI6C9911- 2I PI6C9911- 5I PI6C9911I 200ps 500ps 750ps Industrial PI6C9911E- 2 PI6C9911E- 5 PI6C9911E 250ps 500ps 750ps Commercial PI6C9911E- 2I PI6C9911E- 5I PI6C9911EI 200ps 500ps 750ps Industrial J32 Pericom Semiconductor Corporation 2380 Bering Drive San Jose, CA 95131 1-800-435-2336 Fax (408) 435-1100 http://www.pericom.com Powered by ICminer.com Electronic-Library Service CopyRight 2003 9 PS8451 01/27/00