ETC PI74ALVCH16835K

PI74ALVCH16835
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18-Bit Universal Bus Driver
with 3-STATE Outputs
Product Features
Product Description
• PI74ALVCH16835 is designed for low voltage operation
Pericom Semiconductor’s PI74ALVCH series of logic circuits are
produced using the Company’s advanced 0.5 micron CMOS
technology, achieving industry leading speed.
• VCC = 2.3V to 3.6V
• Hysteresis on all inputs
• Typical VOLP (Output Ground Bounce)
< 0.8V at VCC = 3.3V, TA = 25°C
• Typical VOHV (Output VOH Undershoot)
< 2.0V at VCC = 3.3V, TA = 25°C
• Bus Hold retains last active bus state during 3-STATE,
eliminating the need for external pullup resistors
• Industrial operation at –40°C to +85°C
• Packages available:
– 56-pin 240 mil wide plastic TSSOP (A)
– 56-pin 300 mil wide plastic SSOP (V)
– 56-pin 173 mil wide plastic TVSOP (K)
The 18-bit PI74ALVCH16835 universal bus driver is designed for
2.3V to 3.6V Vcc operation.
Data flow from A to Y is controlled by Output Enable (OE). The
device operates in the transparent mode when LE is HIGH. The A
data is latched if CLK is held at a high or low logic level. If LE is
LOW, the A-bus is stored in the latch/flip-flop on the low-to-high
transition of CLK. When OE is HIGH, the outputs are in the highimpedance state.
To ensure the high-impedance state during power up or power
down, OE should be tied to Vcc through a pullup resistor; the
minimum value of the resistor is determined by the current-sinking
capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data
inputs at a valid logic level.
Logic Block Diagram
OE
CLK
27
30
28
LE
A1
54
1D
3
C1
Y1
CLK
TO 17 OTHER CHANNELS
1
PS8169A
07/30/98
PI74ALVCH16835
18-Bit Universal Bus Driver
with 3-State Outputs
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Product Pin Description
Pin Name
OE
LE
CLK
A
Y
GND
VCC
Truth Table(1)†
Description
Output Enable Input (Active LOW)
Latch Enable
Clock Input
Data Input
Data Output
Ground
Power
Inputs
Product Pin Configuration
NC
NC
Y1
1
2
56
55
GND
NC
54
53
52
A1
GND
3
4
Y2
5
Y3
6
7
8
51
50
49
A3
VCC
9
10
48
47
A5
Y6
GND
11
Y7
12
13
45
14
15
16
43
42
A9
41
A11
17
18
40
39
A12
19
20
21
38
37
36
22
23
24
35
34
33
25
26
32
31
27
28
30
29
Y4
Y5
Y8
Y9
Y10
Y11
Y12
GND
Y13
Y14
Y15
VCC
Y16
Y17
GND
Y18
OE
LE
56-Pin
A, V 46
44
OE
LE
CLK
A
Outputs
Y
H
X
X
X
Z
L
H
X
L
L
L
H
X
H
H
L
L
­
L
L
L
L
­
H
H
L
L
H
X
Yo(2 )
L
L
L
X
Yo(3 )
Note:
1. H = High Signal Level
L = Low Signal Level
Z = High Impedance
↑ = Transition LOW-to-HIGH
X= Irrelevant
2. Output level before the indicated steady-state input
conditions were established, provided that CLK is high
before LE goes low.
3. Output level before the indicated steady-state input
conditions were established.
GND
A2
VCC
A4
A6
GND
A7
A8
A10
GND
A13
A14
A15
VCC
A16
A17
GND
A18
CLK
GND
2
PS8169A
07/30/98
PI74ALVCH16835
18-Bit Universal Bus Driver
with 3-State Outputs
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Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ............................................................ –65°C to +150°C
Ambient Temperature with Power Applied .......................... –40°C to +85°C
Input Voltage Range, VIN .................................................... –0.5V to VCC +0.5V
Output Voltage Range, VOUT ............................................. –0.5V to VCC +0.5V
DC Input Voltage ................................................................... –0.5V to +5.0V
DC Output Current .............................................................................. 100 mA
Power Dissipation ................................................................................... 1.0W
Note:
Stresses greater than those listed under MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
Recommended Operating Conditions(1)
Parame te rs
De s cription
VCC
Supply Voltage
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
VIN
Input Voltage
0
VCC
VOUT
Output Voltage
0
VCC
IOH
IOL
TA
High- level Output Current
Low- level Output Current
Te s t Conditions
M in.
Typ.
2.3
VCC = 2.3V to 2.7V
1.7
VCC = 2.7V to 3.6V
2.0
M ax.
3.6
VCC = 2.3V to 2.7V
0.7
VCC = 2.7V to 3.6V
0.8
VCC = 2.3V
- 12
VCC = 2.7V
- 12
VCC = 3.0V
- 24
VCC = 2.3V
12
VCC = 2.7V
12
VCC = 3.0V
24
Operating Free- Air Temperature
- 40
Units
85
V
mA
°C
Note:
1. Unused control inputs must be held HIGH or LOW to prevent them from floating.
3
PS8169A
07/30/98
PI74ALVCH16835
18-Bit Universal Bus Driver
with 3-State Outputs
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DC Electrical Characteristics (Over the Operating Range, TA = –40°C to +85°C, VCC = 3.3V ± 10%)
Parame te rs
VCC(1)
Te s t Conditions
IOH = - 100 mA
IOH = - 6 MA
VOH
IOH = - 12 mA
IOH = - 24 MA
VOL
IOL = 12 MA
IOL = 24 mA
II
VIH = 1.7V
2.3V
2.0
VIH = 1.7V
2.3V
1.7
VIH = 2.0V
2.7V
2.2
VIH = 2.0V
3.0V
2.4
VIH = 2.0V
3.0V
2.0
M ax. Units
V
Min. to Max.
0.2
VIL = 0.7V
2.3V
0.4
VIL = 0.7V
2.3V
0.7
VIL = 0.8V
2.7V
0.4
VIL = 0.8V
3.0V
0.55
3.6V
±5
VI = VCC or GND
VI = 0.7V
2.3V
VI = 1.7V
II (Hold)(3)
Typ.(2)
Min. to Max. VCC - 0.2
IOL = 100 mA
IOL = 6 mA
M in.
VI = 0.8V
3.0V
VI = 2.0V
45
- 45
75
- 75
mA
VI = 0 to 3.6V
3.6V
±500
IOZ(4)
VO = VCC or GND
3.6V
±10
ICC
VI = VCC or GND
3.6V
40
3V to 3.6V
750
DICC
IO = 0
One input at VCC - 0.6V, Other inputs at VCC or GND
CI Control Inputs VI = VCC or GND
3.3V
3.5
Data Input
VO = VCC or GND
3.3V
6
CO Outputs
VO = VCC or GND
3.3V
7
pF
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device typ e.
2. Typical values are at VCC = 3.3V, +25°C ambient and maximum loading.
3. Bus Hold maximum dynamic current required to switch the input from one state to another.
4. For I/O ports, the IOZ includes the input leakage current.
4
PS8169A
07/30/98
PI74ALVCH16835
18-Bit Universal Bus Driver
with 3-State Outputs
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Timing Requirements over Operating Range
Parame te rs
VCC = 2.5 V ± 0.2V
De s cription
VCC = 2.7V
VCC = 3.3V ± 0.3V
M in.
M ax.
M in.
M ax.
M in.
M ax.
0
150
0
150
0
150
fCLOCK
Clock frequency
tW Pulse
Duration
LE high
3.3
3.3
3.3
CLK high or low
3.3
3.3
3.3
Data before CLK↑
2.2
2.1
1.7
tSU Setup time Data before LE↓ , CLK High
1.9
1.6
1.5
Data before LE↓ , CLK Low
1.3
1.1
1
Data after CLK↑
0.6
0.6
0.7
Data after LE↓ , CLK High or Low
1.4
1.7
1.4
tH Hold time
∆t/∆v(1)
Input Transition Rise or Fall
0
10
0
10
Units
MHz
ns
0
10
ns/V
Note:
1. Unused control inputs must be held HIGH or LOW to prevent them from floating.
Switching Characteristics Over Operating Range(1)
Parame te rs
From
(Input)
VCC = 2.5V ± 0.2V
To (Output)
M in.(2)
M ax.
150
fMAX
VCC = 2.7V
M in.(2)
VCC = 3.3 V ± 0.3V
M in.(2)
M ax.
150
Units
M ax.
150
MHz
tPD
A
Y
1
4.2
4.2
1
3.6
tPD
LE
Y
1.3
5
4.9
1.3
4.2
tPD
CLK
Y
1.4
5.5
5.2
1.4
4.5
tEN
OE
Y
1.4
5.5
5.6
1.1
4.6
tDIS
OE
Y
1
4.5
4.3
1.3
3.9
ns
Notes:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
Switching Characteristics, from 0ºC to 65ºC, CL = 50pF
Parame te r
From (Input)
To (Output)
tPD
CLK
Y
VCC = 3.3V ± 0.15V
M in.
M ax.
1.7
4.5
Units
ns
Operating Characteristics, TA = 25ºC
VCC = 2.5V ± 0.2V
Parame te r
CPD Power Dissipation
Capacitance
Typical
Te s t Conditions
O utputs Enabled
O utputs Disabled
CL = 50pF,
f = 10 MHz
VCC = 3.3V ± 0.3V
Units
26
31
12
14
pF
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
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PS8169A
07/30/98