LM5102 High Voltage Half-Bridge Gate Driver with Programmable Delay General Description The LM5102 High Voltage Gate Driver is designed to drive both the high side and the low side N-Channel MOSFETs in a synchronous buck or a half bridge configuration. The floating high-side driver is capable of working with supply voltages up to 100V. The outputs are independently controlled. The rising edge of each output can be independently delayed with a programming resistor. An integrated high voltage diode is provided to charge the high side gate drive bootstrap capacitor. A robust level shifter operates at high speed while consuming low power and providing clean level transitions from control logic to the high side gate driver. Under-voltage lockout is provided on both the low side and the high side power rails. This device is available in the standard MSOP-10 pin and the LLP-10 pin packages. n n n n n n Bootstrap supply voltage range up to 118V DC Fast turn-off propagation delay (25 ns typical) Drives 1000 pF loads with 15 ns rise and fall times Supply rail under-voltage lockout Low power consumption Timer can be terminated midway through sequence Typical Applications n n n n n Current Fed push-pull power converters Half and Full Bridge power converters Synchronous Buck converters Two switch forward power converters Forward with Active Clamp converters Package Features n Drives both a high side and low side N-channel MOSFET n Independently programmable high and low side rising edge delay n MSOP-10 n LLP-10 (4 mm x 4 mm) Simplified Block Diagram 20088902 FIGURE 1. © 2004 National Semiconductor Corporation DS200889 www.national.com LM5102 High Voltage Half-Bridge Gate Driver with Programmable Delay January 2004 LM5102 Connection Diagram 20088901 10-Lead MSOP, LLP See NS Numbers MUB10A and SDC10A FIGURE 2. Ordering Information Package Type NSC Package Drawing Supplied As LM5102MM Ordering Number MSOP-10 MUB10A 1000 shipped as Tape & Reel LM5102MMX MSOP-10 MUB10A 3500 shipped as Tape & Reel LM5102SD LLP-10 SDC10A 1000 shipped as Tape & Reel LM5102SDX LLP-10 SDC10A 4500 shipped as Tape & Reel Pin Descriptions Pin Name Description Application Information MSOP-10 LLP-10 1 1 VDD Positive gate drive supply Locally decouple to VSS using low ESR/ESL capacitor, located as close to IC as possible. 2 2 HB High side gate driver bootstrap rail Connect the positive terminal of bootstrap capacitor to the HB pin and connect negative terminal of bootstrap capacitor to HS. The Bootstrap capacitor should be placed as close to IC as possible. 3 3 HO High side gate driver output Connect to gate of high side MOSFET with short low inductance path. 4 4 HS High side MOSFET source Connect bootstrap capacitor negative terminal and source of high connection side MOSFET. 5 5 RT1 High side output edge delay programming Resistor from RT1 to ground programs the leading edge delay of the high side gate driver. The resistor should be placed close to the IC to minimize noise coupling from adjacent traces. 6 6 RT2 Low side output edge delay programming Resistor from RT2 to ground programs the leading edge delay of the low side gate driver. The resistor should be placed close to the IC to minimize noise coupling from adjacent traces. 7 7 HI High side driver control input TTL compatible thresholds. Unused inputs should be tied to ground and not left open. 8 8 LI Low side driver control input TTL compatible thresholds. Unused inputs should be tied to ground and not left open. 9 9 VSS Ground return All signals are referenced to this ground. 10 10 LO Low side gate driver output Connect to the gate of the low side MOSFET with a short low inductance path. Note: For LLP-10 package, it is recommended that the exposed pad on the bottom of the LM5100 / LM5101 be soldered to ground plane on the PC board, and the ground plane should extend out from beneath the IC to help dissipate the heat.. www.national.com 2 Storage Temperature Range If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. ESD Rating HBM (Note 2) VDD to VSS –0.3V to +18V VHB to VHS –0.3V to +18V LI or HI Inputs to VSS –0.3V to VDD + 0.3V LO Output –0.3V to VDD + 0.3V HO Output VHS – 0.3V to VHB + 0.3V VHS to VSS −1V to +100V VHB to VSS 118V RT1 & RT2 to VSS 2 kV Recommended Operating Conditions VDD +9V to +14V HS –1V to 100V HB VHS + 8V to VHS + 14V < 50V/ns HS Slew Rate Junction Temperature –0.3V to 5V Junction Temperature –55˚C to +150˚C –40˚C to +125˚C +150˚C Electrical Characteristics Specifications in standard typeface are for TJ = +25˚C, and those in boldface type apply over the full operating junction temperature range. Unless otherwise specified, VDD = VHB = 12V, VSS = VHS = 0V, RT1 = RT2 = 100kΩ. No Load on LO or HO. Symbol Parameter Conditions Min Typ Max Units SUPPLY CURRENTS IDD VDD Quiescent Current LI = HI = 0V 0.4 0.6 mA IDDO VDD Operating Current f = 500 kHz 1.5 3 mA IHB Total HB Quiescent Current LI = HI = 0V 0.06 0.2 mA IHBO Total HB Operating Current f = 500 kHz 1.3 3 mA IHBS HB to VSS Current, Quiescent VHS = VHB = 100V 0.05 10 IHBSO HB to VSS Current, Operating f = 500 kHz 0.08 µA mA INPUT PINS VIL Low Level Input Voltage Threshold VIH High Level Input Voltage Threshold RI Input Pulldown Resistance 0.8 100 1.8 V 1.8 2.2 V 200 500 kΩ TIME DELAY CONTROLS VRT Nominal Voltage at RT1, RT2 IRT RT Pin Current Limit Vth Timer Termination Threshold TDL1, TDH1 TDL2, TDH2 2.7 3 3.3 V 0.75 1.5 2.25 mA Rising edge turn-on delay, RT = 10 kΩ 75 105 150 ns Rising edge turn-on delay, RT = 100 kΩ 530 630 750 ns 6.9 7.4 V RT1 = RT2 = 0V 1.8 V UNDER VOLTAGE PROTECTION VDDR VDD Rising Threshold VDDH VDD Threshold Hysteresis VHBR HB Rising Threshold VHBH HB Threshold Hysteresis 6.0 0.5 5.7 6.6 V 7.1 V 0.4 V BOOT STRAP DIODE VDL Low-Current Forward Voltage IVDD-HB = 100 µA 0.60 0.9 V VDH High-Current Forward Voltage IVDD-HB = 100 mA 0.85 1.1 V RD Dynamic Resistance IVDD-HB = 100 mA 0.8 1.5 Ω LO GATE DRIVER VOLL Low-Level Output Voltage ILO = 100 mA 0.25 0.4 V VOHL High-Level Output Voltage ILO = –100 mA, VOHL = VDD – VLO 0.35 0.55 V IOHL Peak Pullup Current VLO = 0V 1.6 A IOLL Peak Pulldown Current VLO = 12V 1.8 A IHO = 100 mA 0.25 HO GATE DRIVER VOLH Low-Level Output Voltage 3 0.4 V www.national.com LM5102 Absolute Maximum Ratings (Note 1) LM5102 Electrical Characteristics Specifications in standard typeface are for TJ = +25˚C, and those in boldface type apply over the full operating junction temperature range. Unless otherwise specified, VDD = VHB = 12V, VSS = VHS = 0V, RT1 = RT2 = 100kΩ. No Load on LO or HO. (Continued) Symbol Parameter Typ Max Units IHO = –100 mA, VOHH = VHB – VHO 0.35 0.55 V Peak Pullup Current VHO = 0V 1.6 A Peak Pulldown Current VHO = 12V 1.8 A MSOP 200 ˚C/W LLP-10 (Note 3) 40 VOHH High-Level Output Voltage IOHH IOLH Conditions Min THERMAL RESISTANCE θJA Junction to Ambient Switching Characteristics Specifications in standard typeface are for TJ = +25˚C, and those in boldface type apply over the full operating junction temperature range. Unless otherwise specified, VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO . Typ Max Units tLPHL Symbol Lower Turn-Off Propagation Delay LM5102 (LI Falling to LO Falling) Parameter Conditions Min 27 56 ns tHPHL Upper Turn-Off Propagation Delay LM5102 (HI Falling to HO Falling) 27 56 ns tRC, tFC Either Output Rise/Fall Time CL = 1000 pF 15 ns t R , tF Either Output Rise/Fall Time (3V to 9V) CL = 0.1 µF 0.6 µs tBS Bootstrap Diode Turn-Off Time IF = 20 mA, IR = 200 mA 50 ns Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical Characteristics tables. Note 2: The human body model is a 100 pF capacitor discharged through a 1.5kΩ resistor into each pin. 2 kV for all pins except Pin 2, Pin 3 and Pin 4 which are rated at 500V. Note 3: 4 layer board with Cu finished thickness 1.5/1/1/1.5 oz. Maximum die size used. 5x body length of Cu trace on PCB top. 50 x 50mm ground and power planes embedded in PCB. See Application Note AN-1187. Note 4: Min and Max limits are 100% production tested at 25˚C. Limits over the operating temperature range are guaranteed through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate National’s Average Outgoing Quality Level (AOQL). Note 5: The θJA is not a given constant for the package and depends on the printed circuit board design and the operating environment. www.national.com 4 LM5102 Typical Performance Characteristics IDD vs Frequency Operating Current vs Temperature 20088910 20088911 Quiescent Current vs Supply Voltage Quiescent Current vs Temperature 20088913 20088912 IHB vs Frequency HO & LO Peak Output Current vs Output Voltage 20088917 20088916 5 www.national.com LM5102 Typical Performance Characteristics (Continued) Diode Forward Voltage Undervoltage Threshold Hysteresis vs Temperature 20088918 20088915 LO & HO Gate Drive — High Level Output Voltage vs Temperature Undervoltage Rising Threshold vs Temperature 20088919 20088920 LO & HO Gate Drive — Low Level Output Voltage vs Temperature Turn Off Propagation Delay vs Temperature 20088921 www.national.com 20088922 6 (Continued) Turn On Delay vs RT Resistor Value Turn On Delay vs Temperature (RT = 10k) 20088926 20088914 Turn On Delay vs Temperature (RT = 100k) 20088927 7 www.national.com LM5102 Typical Performance Characteristics LM5102 LM5102 Waveforms 20088903 (a) 20088904 (b) FIGURE 3. Application Timing Waveforms tance. In addition, each RT pin is monitored by a comparator that will bypass the turn-on delay if the RT pin is pulled below the timer elimination threshold (1.8V typical). Grounding the RT pins programs the LM5102 to drive both outputs with minimum turn-on delay. Operational Notes The LM5102 offers a unique flexibility with independently programmable delay of the rising edge for both high and low side driver outputs independently. The delays are set with resistors at the RT1 and RT2 pins, and can be adjusted from 100 ns to 600 ns. This feature reduces component count, board space and cost compared to discrete solutions for adjusting driver dead time. The wide delay programming range provides the flexibility to optimize drive signal timing for a wide range of MOSFETs and applications. The RT pins are biased at 3V and current limited to 1 mA maximum programming current. The time delay generator will accommodate resistor values from 5k to 100k with turn-on delay times that are proportional to the RT resiswww.national.com STARTUP AND UVLO Both top and bottom drivers include under-voltage lockout (UVLO) protection circuitry which monitors the supply voltage (VDD) and bootstrap capacitor voltage (VHB – VHS) independently. The UVLO circuit inhibits each driver until sufficient supply voltage is available to turn-on the external MOSFETs, and the built-in hysteresis prevents chattering during supply voltage transitions. When the supply voltage is applied to VDD pin of LM5102, the top and bottom gates are 8 POWER DISSIPATION CONSIDERATIONS (Continued) The total IC power dissipation is the sum of the gate driver losses and the bootstrap diode losses. The gate driver losses are related to the switching frequency (f), output load capacitance on LO and HO (CL), and supply voltage (VDD) and can be roughly calculated as: PDGATES = 2 • f • CL • VDD2 There are some additional losses in the gate drivers due to the internal CMOS stages used to buffer the LO and HO outputs. The following plot shows the measured gate driver power dissipation versus frequency and load capacitance. At higher frequencies and load capacitance values, the power dissipation is dominated by the power losses driving the output loads and agrees well with the above equation. This plot can be used to approximate the power losses due to the gate drivers. held low until VDD exceeds UVLO threshold, typically about 6.9V. Any UVLO condition on the bootstrap capacitor will disable only the high side output (HO). LAYOUT CONSIDERATIONS The optimum performance of high and low side gate drivers cannot be achieved without taking due considerations during circuit board layout. Following points are emphasized. 1. A low ESR/ESL capacitor must be connected close to the IC, and between VDD and VSS pins and between HB and HS pins to support high peak currents being drawn from VDD during turn-on of the external MOSFET. 2. To prevent large voltage transients at the drain of the top MOSFET, a low ESR electrolytic capacitor must be connected between MOSFET drain and ground (VSS). 3. In order to avoid large negative transients on the switch node (HS) pin, the parasitic inductances in the source of top MOSFET and in the drain of the bottom MOSFET (synchronous rectifier) must be minimized. 4. Gate Driver Power Dissipation (LO + HO) VCC = 12V, Neglecting Diode Losses Grounding considerations: a) The first priority in designing grounding connections is to confine the high peak currents from charging and discharging the MOSFET gate in a minimal physical area. This will decrease the loop inductance and minimize noise issues on the gate terminal of the MOSFET. The MOSFETs should be placed as close as possible to the gate driver. b) The second high current path includes the bootstrap capacitor, the bootstrap diode, the local ground referenced bypass capacitor and low side MOSFET body diode. The bootstrap capacitor is recharged on the cycle-by-cycle basis through the bootstrap diode from the ground referenced VDD bypass capacitor. The recharging occurs in a short time interval and involves high peak current. Minimizing this loop length and area on the circuit board is important to ensure reliable operation. 5. 20088905 The bootstrap diode power loss is the sum of the forward bias power loss that occurs while charging the bootstrap capacitor and the reverse bias power loss that occurs during reverse recovery. Since each of these events happens once per cycle, the diode power loss is proportional to frequency. Larger capacitive loads require more current to recharge the bootstrap capacitor resulting in more losses. Higher input voltages (VIN) to the half bridge result in higher reverse recovery losses. The following plot was generated based on calculations and lab measurements of the diode recovery time and current under several operating conditions. This can be useful for approximating the diode power dissipation. The resistors on the RT1 and RT2 timer pins must be placed very close to the IC and seperated from high current paths to avoid noise coupling to the time delay generator which could disrupt timer operation. 9 www.national.com LM5102 Operational Notes LM5102 Operational Notes The total IC power dissipation can be estimated from the above plots by summing the gate drive losses with the bootstrap diode losses for the intended application. Because the diode losses can be significant, an external diode placed in parallel with the internal bootstrap diode (refer to Figure 4) and can be helpful in removing power from the IC. For this to be effective, the external diode must be placed close to the IC to minimize series inductance and have a significantly lower forward voltage drop than the internal diode. (Continued) Diode Power Dissipation VIN = 80V 20088906 Diode Power Dissipation VIN = 40V 20088907 www.national.com 10 LM5102 Operational Notes (Continued) LM5102 Driving MOSFETs Connected in Half-Bridge Configuration 20088908 FIGURE 4. 11 www.national.com LM5102 Physical Dimensions inches (millimeters) unless otherwise noted Notes: Unless otherwise specified 1. 2. 3. Standard lead finish to be 200 microinches/5.00 micrometers minimum tin/lead (solder) on copper. Pin 1 identification to have half of full circle option. No JEDEC registration as of Feb. 2000. LLP-10 Outline Drawing NS Package Number SDC10A www.national.com 12 inches (millimeters) unless otherwise noted (Continued) Notes: Unless otherwise specified 1. For solder thickness and composition, see “Solder Information” in the packaging section of the National Semiconductor web page (www.national.com). 2. Maximum allowable metal burr on lead tips at the package edges is 76 microns. 3. No JEDEC registration as of May 2003. MSOP-10 Outline Drawing NS Package Number MUB10A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. 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