PI74SSTVF32852 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 24-Bit to 48-Bit Registered Buffer Product Features Product Description • PI74 SSTVF32852 is designed for low-voltage operation, 2.5V for PC1600 ~ PC2700; 2.6V for PC3200 • Supports SSTL_2 Class I specifications on outputs • All Inputs are SSTL_2 Compatible, except RESET which is LVCMOS. • Designed for DDR Memory • Packaging: 114-Ball LFBGA (Lead-free package available) Pericom Semiconductor’s PI74SSTVF32852 logic circuit is produced using the Company’s advanced sub-micron CMOS technology, achieving industry leading speed. All inputs are compatible with the JEDEC standard for SSTL_2, except the LVCMOS reset (RESET) input. All outputs are SSTL_2, Class II compatible. The device operates from a differential clock (CK and CK). Data registered at the crossing of CK going HIGH, and CK going LOW. The PI74SSTVF32852 supports low-power standby operation. When RESET is LOW, the differential input receivers are disabled, and undriven (floating) data, clock and reference voltage (VREF) inputs are allowed. In addition, when RESET is LOW, all registers are reset, and all outputs are forced LOW. The LVCMOS RESET input must always be held at a valid logic HIGH or LOW level. Logic Block Diagram RESET D1 VREF A3 A4 A2 R3 R V CLK CLK T2 R4 CLK D Q1A A5 To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the LOW state during power up. Q1B In the DDR DIMM application, RESET is specified to be completely asynchronous with respect to CK and CK. Therefore, no timing relationship can be guaranteed between the two. When entering RESET, the register will be cleared and the outputs will be driven LOW quickly, relative to the time to disable the differential input receivers, thus ensuring no glitches on the output. However, when coming out of RESET, the register will become active quickly, relative to the time to enable the differential input receivers. When the data inputs are LOW, and the clock is stable, during the time from the LOW-to-HIGH transition of RESET until the input receivers are fully enabled, the design must ensure that the outputs will remain LOW. TO 23 OTHER CHANNELS Product Pin Description Pin Name RESET Description Reset (Active Low) LVCMOS CLK Clock Input, Positive Differential Input CLK Clock Input, Negative Differential Input D Data Input Q Data Output GND Ground VDD Core Supply Voltage, 2.5V Nominal VDDQ Output Supply Voltage, 2.5V Nominal VREF Input Reference Voltage, 1.25V Nominal Pericom’s PI74SSTVF32852 is characterized for operation from 0° to 70°C. Truth Table(1) Inputs Outputs RESET CLK CLK D Q L X or Floating X or Floating X or Floating L H ↑ ↓ H H Η ↑ ↓ L L H L or H L or H X Qo(2) Notes: 1. H= High Signal Level; L = Low Signal Level; ↑ = Transition LOW-to-HIGH; ↓ = Transition HIGH-to-LOW X = Irrelevant or floating 2. Output level before the indicated steady state input conditions were established. 1 PS8658A 04/08/03 PI74SSTVF32852 24-Bit to 48-Bit Registered Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Product Pin Configuration 1 2 3 4 5 6 A Q2A Q1A CLK CLK Q1B Q2B B Q3A VDDQ GND GND VDDQ Q3B C Q5A Q4A VDDQ VDDQ Q4B Q5B D Q7A Q6A GND GND Q6B Q7B E Q8A GND VDDQ VDDQ GND Q8B F Q10A Q9A VDDQ VDDQ Q9B Q10B G Q12A Q11A GND GND Q11B Q12B H Q13A VCC VDDQ VDDQ VCC Q13B J Q14A Q15A GND GND Q15B Q14B K Q17A Q16A VDDQ VDDQ Q16B Q17B L Q18A Q19A GND GND Q19B Q18B M Q20A VDDQ GND GND VDDQ Q20B N Q22A Q21A VDDQ VDDQ Q21B Q22B P Q23A VDDQ GND GND VDDQ Q23B R Q24A VCC RESET VREF VCC Q24B T D2 D1 D6 D18 D13 D14 U D4 D3 D10 D22 D15 D16 V D5 D7 D11 D23 D19 D17 W D8 D9 D12 D24 D21 D20 NB Package (Top View) 1 2 3 4 5 6 A B C D E F G H J K L M N P R T U V W 2 PS8658A 04/08/03 PI74SSTVF32852 24-Bit to 48-Bit Registered Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Item Symbol/Conditions Ratings Units Tstg –65 to 150 °C VDD or VDDQ –0.5 to 3.6 VI –0.5 to VDD +0.5 VO –0.5 to VDDQ +0.5 Input clamp current IIK , VI <0 or VI >VDD –50 Output clamp current IOK , VO <0 or VO >VDDQ ±50 IO , VO = 0 to VDDQ ±50 IDD, IDDQ or IGND ±100 θJA 36 Storage temperature Supply voltage Input voltage(1,2) Output voltage(1,2) Continuous output current VDD, VDDQ or GND current/pin Package Thermal Impedance(3) V mA °C/W Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 1. The input and output negative voltage ratings may be excluded if the input and output clamp ratings are observed. 2. This value is limited to 3.6V Maximum. 3. The package thermal impedance is calculated in accordance with JESD 51-7. Recommended Operating Conditions(4) Parameters VDD/VDDQ VREF VTT Description Core Output Supply Voltage Reference Voltage VREF = 0.5X VDDQ Min. Nom. Max. PC1600 PC2700 2.3 2.5 2.7 PC3200 2.5 2.6 2.7 PC1600 PC2700 1.15 1.25 1.35 PC3200 1.25 1.3 1.35 VREF –0.04 VREF VREF +0.04 Termination Voltage VI Input Voltage VIH AC High -Level Input Voltage VIL AC Low -Level Input Voltage VIH DC High -Level Input Voltage VIL DC Low -Level Input Voltage VIH High -Level Input Voltage VIL Low -Level Input Voltage VICR Common-mode input range VID Differential Input Voltage IOH High-Level Output Current –16 IOL Low-Level Output Current 16 TA Operating Free-Air Temperature 0 VDD V VREF +310mV Data Inputs Units VREF – 310mV VREF +150mV VREF –150mV Reset CK, CK 1.7 0.7 0.97 1.53 360 0 70 mA ºC Note: 4. The RESET input of the device must be held at VDD or GND to ensure proper device operation. The differential inputs must not be floating, unless RESET is LOW. 3 PS8658A 04/08/03 PI74SSTVF32852 24-Bit to 48-Bit Registered Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 DC Electrical Characteristics for PC1600 ~ PC2700 (Over the Operating Range, TA = 0°C to +70°C, VDD = 2.5V ± 200mV, VDDQ = 2.5V ± 200mV) Parameters Typ. (1) Max. IOH = –100µA 2.3V-2.7V VDD –0.2V IOH = –8mA 2.3V 1.95 IOL = 100µA 2.3V-2.7V 0.2 IOH = 8mA 2.3V 0.35 All Inputs, VI = VDD or GND 2.7V ±5 Standby (Static) RESET = GND 10 Operating Static RESET = VDD VI = VIH (AC) or VI (AC) 35 Dynamic Operating - Clock only RESET = VDD VI = VIH(AC) or VIL(AC), CK and CK switching 50% duty cycle Dynamic Operating -per each data input RESET = VDD VI = VIH (AC) or VIL(AC), CK and CK switching 50% duty cycle. One data input switching at half clock frequency, 50% duty cycle VOL IDDD CI Min. 2.3V VOH IDD VCC II = –18mA VIK II Test Conditions IO = 0 Data inputs VI = VREF ± 310mV CK and CK VICR= 1.25V, VI(PP) = 360mV RESET VI = VCC or GND –1.2 V µA mA 46 µA/ clock MHz 12 µA/ clock MHz Data 2.7V 2.5V Units 3.0 4.0 5.5 6.5 8.0 9.5 3.5 4.35 5.0 pF Note: 1. All typical values are at VDD = 2.5V, T A = 25°C. 4 PS8658A 04/08/03 PI74SSTVF32852 24-Bit to 48-Bit Registered Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 DC Electrical Characteristics for PC3200 (Over the Operating Range, TA = 0°C to +70°C, VDD = 2.6V ± 100mV, VDDQ = 2.6V ± 100mV) Parameters VIK Typ.(1) Max. IOH = –100µA 2.5V-2.7V VDD –0.2V IOH = –8mA 2.5V 1.95 IOL = 100µA 2.5V-2.7V 0.2 IOH = 8mA 2.5V 0.35 All Inputs, VI = VDD or GND 2.7V ±5 Standby (Static) RESET = GND 10 Operating Static RESET = VDD VI = VIH (AC) or VI (AC) 35 Dynamic Operating - Clock only RESET = VDD VI = VIH(AC) or VIL(AC), CK and CK switching 50% duty cycle Dynamic Operating -per each data input RESET = VDD VI = VIH (AC) or VIL(AC), CK and CK switching 50% duty cycle. One data input switching at half clock frequency, 50% duty cycle IDDD CI Min. 2.5V VOL IDD VCC II = –18mA VOH II Test Conditions IO = 0 Data inputs VI = VREF ± 350mV CK and CK VICR= 1.25V, VI(PP) = 360mV RESET VI = VCC or GND –1.2 V µA mA 46 µA/ clock MHz 12 µA/ clock MHz Data 2.7V 2.6V Units 3.0 4.0 5.5 6.5 8.0 9.5 3.5 4.35 5.0 pF Note: 1. All typical values are at VDD = 2.5V, T A = 25°C. 5 PS8658A 04/08/03 PI74SSTVF32852 24-Bit to 48-Bit Registered Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Timing Requirements (over recommended operating free-air temperature range, unless otherwise noted) fclock VDD=2.5V ±0.2V VDD=2.6V ±0.1V Min. Min. Clock Frequency Max. 270 Pulse Duration, CLK, CLK High or Low 2.5 2.5 tact Differential inputs active time, data inputs must be low after RESET High 22 22 tinact Differential Inputs inactive time, data and clock inputs must be held at valid levels (not floating) after RESET Low 22 22 0.75 0.75 0.9 0.9 0.75 0.75 0.9 0.9 tSU Setup time, slow slew rate (6,7) Hold time, fast slew rate (5,7) th Hold time, slow slew rate (6,7) Data before CK↑ ,CK ↑ ↑ Data before CK ↑ ,CK Units 270 tW Setup time, fast slew rate (5,7) Max. MHz ns Notes: 5. Data signal input slew rate ≥ 1 V/ns 6. Data signal input slew rate ≥ 0.5V/ns and <1V/ns 7. CLK, CLK input slew rates are ≥ 1 V/ns. Switching Characteristics for PC1600 ~ PC2700 (over recommended operating free-air temperature range, unless otherwise noted.) (See test circuits and switching waveforms). Parameter From (Input) VDD = 2.5V ±0.2V To (Output) Min. Typ. Units Max. 210 fmax tpd CLK, CLK Q tphl RESET Q MHz 1.1 2.5 ns 5.0 Switching Characteristics for PC3200 (over recommended operating free-air temperature range, unless otherwise noted.) (See test circuits and switching waveforms). Parameter From (Input) VDD = 2.6V ±0.1V To (Output) Min. fmax Typ. Units Max. 210 tpd CLK, CLK Q tphl RESET Q 1.1 MHz 2.5 ns 5.0 6 PS8658A 04/08/03 PI74SSTVF32852 24-Bit to 48-Bit Registered Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Test Circuit and Switching Waveforms LVCMOS RESET Input VDD VDD/2 0V t inact From Output Under Test Test Point tact IDD(9) 500Ω CL = 30pF(8) IDDH 90% 10% Load Circuit IDDL Voltage and Current Waveforms Input Active and Inactive Times Timing Input VICR tw VIH Input VREF Output VREF VICR VI(PP) t PLH t PHL VTT VTT VOL VIL Voltage Waveforms - Propagation Delay Times Voltage Waveforms - Pulse Duration Timing Input VICR tsu LVCMOS RESET Input VI(PP) VREF VIH VDD/2 VIL t PHL th VIH Input VOH VOH VTT Output VREF VOL VIL Voltage Waveforms - Propagation Delay Times Voltage Waveforms - Setup and Hold Times Parameter Measurement Information Notes: 8. CL includes probe and jig capacitance. 9. IDD tested with clock and data inputs held at VDD or GND, and IO = 0mA. 10. All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50 ohms. Input slew rate = 1V/ns ±20% (unless otherwise specified). 11. The outputs are measured one at a time with one transition per measurement. 12. VTT = VREF = VDDQ/2 13. VIH = VREF + 310mV (ac voltage levels) for SSTL inputs. VIH = VDD for LVCMOS input. 14. VIL = VREF + 310mV (ac voltage levels) for SSTL inputs. VIL = GND for LVCMOS input. 15. tPLH and tPHL are the same as tpd. 7 PS8658A 04/08/03 PI74SSTVF32852 24-Bit to 48-Bit Registered Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 114-Ball LFBGA (NB) Package 0.80 0.39 ± 0.05 0.75 0.31 BSC 0.87mm. Min. (2 layer) 0.90mm. Min. (4 layer) 1.40 Max. (2 layer) 1.45 Max. (4 layer) Ordering Information Ordering Code Package Type Operating Temperature Range PI74SSTVF32852NB 114-Ball LFBGA 0°C to 70°C PI74SSTVF32852NBE Pb-free 114-Ball LFBGA 0°C to 70°C Pericom Semiconductor Corporation 2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com 8 PS8658A 04/08/03