QL4058 - QuickRAMTM 58,000 Usable PLD Gate QuickRAM ESP Combining Performance, Density, and Embedded RAM QL4058 - QuickRAM DEVICE HIGHLIGHTS Device Highlights High Performance & High Density ■ 58,000 Usable PLD Gates with 252 I/Os ■ 300 MHz 16-bit Counters, 400 MHz Datapaths, 160+ MHz FIFOs ■ 0.35µm four-layer metal non-volatile CMOS process for smallest die sizes High Speed Embedded SRAM ■ 18 dual-port RAM modules, organized in user-configurable 1,152 bit blocks ■ 5ns access times, each port independently accessible ■ Fast and effecient for FIFO, RAM, and ROM functions Easy to Use / Fast Development Cycles ■ 100% routable with 100% utilization and complete pin-out stability ■ Variable-grain logic cells provide high performance and 100% utilization ■ Comprehensive design tools include high quality Verilog/VHDL synthesis Advanced I/O Capabilities ■ Interfaces with both 3.3 volt and 5.0 bolt devices ■ PCI compliant with 3.3V and 5.0V busses for -1/-2/-3/-4 speed grades ■ Full JTAG boundary scan ■ Registered I/O cells with individually controlled clocks and output enables } 1,008 High Speed Logic Cells 18 RAM Blocks Interface FIGURE 1. QuickRAM Block Diagram ARCHITECTURE OVERVIEW Architecture Overview The QuickRAM family of ESPs (Embedded Standard Products) offers FPGA logic in combination with DualPort SRAM modules. The QL4058 is a 58,000 usable PLD gate member of the QuickRAM family of ESPs. QuickRAM ESPs are fabricated on a 0.35mm four-layer metal process using QuickLogic’s patented ViaLinkTM technology to provide a unique combination of high performance, high density, low cost, and extreme ease-of-use. The QL4058 contains 1,008 logic cells and 18 dual port RAM modules (see Figure 1). Each RAM module has 1,152 RAM bits, for a total of 20,736 bits. RAM Modules are Dual Port (one read port, one write port) and can be configured into one of four modes: 64 (deep) x18 (wide), 128x9, 256x4, or 512x2 (see Figure 2). With a maximum of 204 I/Os, the QL4058 is available in 208-pin PQFP, 240-pin PQFP and 456pin PBGA packages. Designers can cascade multiple RAM modules to increase the depth or width allowed in single modules by connecting corresponding address lines together and dividing the words between modules (see Figure 3). This approach allows up to 512-deep configurations as large as 16 bits wide in the smallest QuickRAM device and 44 bits wide in the largest device. 6-43 QL4058 Rev G QL4058 - QuickRAMTM PRODUCT SUMMARY Product Summary Product Summary Total of 252 I/O Pins ■ 244 bi-directional input/output pins, PCI-compliant for 5.0 volt and 3.3 volt buses for -1/-2/-3/-4 speed grades ■ 8 high-drive input/distributed network pins Eight Low-Skew Distributed Networks ■ Two array clock/controlnetworks available to the logic cell flip-flop clock, set and reset inputs - each driven by and input-only pin ■ Six global clock/control networks available to the logic cell F1, clock, set and reset inputs and the input and I/O register clock, reset and enable inputs as well as the output enable control - each driven by an input-only or I/O pin, or any logic cell output or I/O cell feedback FIGURE 2. QuickRAM Module Software support for the complete QuickRAM family, including the QL4016, is available through two basic packages. The turnkey QuickWorksTM package provides the most complete ESP software solution from design entry to logic synthesis, to place and route, to simulation. The QuickToolsTM for Worksattions package provides a solution for designers who use Cadence, Exemplar, Mentor, Syn-opsys, Synplicity, Viewlogic, Veribest, or other third-party tools for design entry, synthesis, or simulation. High Performance ■ Input + logic cell + output total delays under 6 ns ■ Data path speeds over 400 MHz ■ Counter speeds over 300 MHz ■ FIFO speeds over 160+ MHz The QuickLogic variable grain logic cell features up to 16 simultaneous inputs and 5 outs within a cell that can be fragmented into 5 independent cells. Each cell has a fan-in of 29 including register and control lines (see Figure 4). WDATA WADDR RAM Module (1,152 bits) QS RDATA RADDR (1,152 bits) OS OP B1 B2 C1 C2 MP MS OZ QZ D1 D2 E1 E2 NP NS NZ FZ QC QR RDATA FIGURE 3. QuickRAM Module bits 6-44 44 AZ F1 F2 F3 F4 F5 F6 RAM Module WDATA A1 A2 A3 A4 A5 A6 Preliminary FIGURE 4. Logic Cell QL4058 - QuickRAMTM Pin #157 Pin #1 QuickRAM QL4058-1PQ208C Pin #105 Pin #53 208 Pin PQFP Pinout Diagram Pin #181 Pin #1 QuickRAM QL4058-1PQ240C Pin #121 Pin #61 240 Pin PQFP Pinout Diagram 6-45 QL4058 - QuickRAMTM PQFP 208/240 PINOUT TABLE PQFP 208/240 Pinout Table 240 PQFP 208 PQFP Function 240 PQFP 208 PQFP Function 240 PQFP 208 PQFP Function 240 PQFP 208 PQFP Function 240 PQFP 208 PQFP Function 1 208 I/O 51 43 GND 98 84 I/O 145 125 I/O 194 168 I/O 2 1 I/O 52 44 I/O 99 85 I/O 146 126 I/O 195 169 I/O 3 2 I/O 53 45 I/O 100 86 I/O 147 127 GND 196 NC I/O 4 3 I/O 54 46 I/O 101 87 I/O 148 128 I/O 197 170 I/O 5 4 I/O 55 47 I/O 102 88 I/O 149 NC I/O 198 171 I/O 6 5 I/O 56 48 I/O 103 89 I/O 150 129 GLCK/I 199 172 I/O 7 NC I/O 57 NC I/O 104 90 I/O 151 130 ACLK/I 200 173 I/O 8 6 I/O 58 49 I/O 105 91 I/O 152 131 VCC 201 174 I/O 9 7 I/O 59 50 I/O 106 92 I/O 153 132 GLCK/I 202 175 I/O 10 8 I/O 60 51 I/O 107 NC I/O 154 133 GLCK/I 203 NC I/O 11 9 I/O NC 52 I/O 108 93 I/O 155 134 VCC 204 176 I/O 12 10 VCC NC 53 I/O 109 94 I/O 156 135 I/O 205 177 GND 13 11 I/O 61 54 TDI 110 95 GND 157 136 I/O 206 178 I/O 14 12 GND 62 NC I/O NC 96 I/O 158 NC I/O 207 179 I/O 15 13 I/O 63 NC I/O 111 97 VCC 159 137 I/O 208 NC I/O 16 14 I/O 64 55 I/O NC 98 I/O 160 NC GND 209 180 I/O 17 NC I/O 65 56 I/O NC 99 I/O 161 138 I/O 210 181 I/O 18 15 I/O 66 NC I/O 112 100 I/O 162 139 I/O 211 182 GND 19 16 I/O 67 57 I/O 113 NC I/O 163 140 I/O 212 NC VCC 20 17 I/O 68 58 I/O 114 101 I/O 164 141 I/O 213 183 I/O 21 18 I/O 69 59 GND 115 NC I/O 165 142 I/O 214 184 I/O 22 19 I/O 70 60 I/O 116 102 I/O 166 NC I/O 215 185 I/O 23 20 I/O 71 61 VCC 117 NC I/O 167 143 I/O 216 186 I/O 24 NC I/O 72 62 I/O 118 NC I/O 168 144 I/O 217 187 VCCIO 25 21 I/O 73 63 I/O 119 103 TRSTB 169 145 VCC 218 188 I/O 26 22 I/O 74 64 I/O 120 104 TMS 170 NC I/O 219 NC I/O 27 23 GND 75 NC I/O 121 105 I/O 171 146 I/O 220 189 I/O 28 24 I/O 76 65 I/O 122 NC I/O 172 147 GND 221 190 I/O 29 25 GCLK/I 77 66 I/O 123 106 I/O 173 148 I/O 222 191 I/O 30 26 ACLK/I 78 67 I/O 124 107 I/O 174 149 I/O 223 192 I/O 31 27 VCC 79 NC I/O 125 108 I/O 175 150 I/O 224 193 I/O 32 28 GCLK/I 80 68 I/O 126 109 I/O 176 151 I/O 225 194 I/O 33 29 GCLK/I 81 69 I/O 127 NC I/O 177 152 I/O 226 NC I/O 34 30 VCC 82 70 I/O 128 110 I/O 178 153 I/O 227 195 I/O 35 31 I/O 83 NC I/O 129 111 I/O 179 154 I/O 228 196 I/O 36 32 I/O NC 71 I/O 130 112 I/O 180 155 I/O 229 197 I/O 37 NC GND 84 NC I/O 131 113 I/O NC 156 I/O 230 198 I/O 38 33 I/O 85 72 I/O 132 114 VCC 181 157 TCK 231 NC I/O 39 NC I/O 86 73 GND 133 115 I/O 182 158 STM 232 199 GND 40 34 I/O 87 74 I/O 134 116 GND 183 NC I/O 233 200 I/O 41 35 I/O 88 NC VCC 135 117 I/O 184 159 I/O 234 201 VCC 42 36 I/O 89 75 I/O 136 NC I/O 185 160 I/O 235 202 I/O 43 NC I/O 90 76 I/O 137 118 I/O 186 161 I/O 236 203 I/O 44 37 I/O 91 77 I/O 138 119 I/O 187 162 I/O 237 204 I/O 45 38 I/O 92 78 GND 139 120 I/O 188 163 GND 238 205 I/O 46 39 I/O 93 79 I/O 140 121 I/O 189 164 I/O 239 206 I/O 47 NC I/O 94 80 I/O 141 NC I/O 190 165 VCC 240 207 TDO 48 40 I/O 95 81 I/O 142 122 I/O 191 166 I/O 49 41 VCC 96 82 I/O 143 123 I/O 192 NC I/O 50 42 I/O 97 83 VCCIO 144 124 I/O 193 167 I/O TABLE 1: PQFP 208/240 Pinout Table 6-46 46 Preliminary QL4058 - QuickRAMTM PINOUT DIAGRAM Pinout Diagram QuickRAM QL4058-1PB456C 456 Pin PBGA TOP PIN A1 CORNER Bottom 6-47 QL4058 - QuickRAMTM PBGA 456 PINOUT TABLE PBGA 456 Pinout Table 456 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 Function I/O I/O I/O I/O I/O I/O I/O I/O NC I/O I/O VCCIO I/O I/O NC I/O NC I/O I/O I/O NC I/O NC I/O I/O I/O I/O NC I/O NC NC NC NC NC I/O NC NC I/O I/O NC I/O I/O I/O I/O I/O I/O I/O I/O NC I/O I/O 456 B26 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 Function STM I/O I/O I/O TDO I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC NC I/O I/O I/O I/O I/O I/O TCK NC I/O I/O I/O GND NC NC I/O I/O GND I/O I/O GND I/O I/O GND I/O I/O GND I/O NC NC I/O GND I/O 456 D25 D26 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 F1 F2 F3 F4 F5 F22 F23 F24 F25 F26 G1 G2 G3 G4 G5 G22 G23 G24 G25 G26 H1 H2 H3 Function I/O I/O I/O I/O I/O I/O GND VCC GND NC GND I/O GND GND VCC GND GND GND NC GND NC GND VCC GND I/O I/O I/O I/O I/O I/O NC NC VCC VCC NC I/O I/O I/O I/O I/O I/O I/O NC GND NC I/O I/O I/O NC I/O NC 456 H4 H5 H22 H23 H24 H25 H26 J1 J2 J3 J4 J5 J22 J23 J24 J25 J26 K1 K2 K3 K4 K5 K22 K23 K24 K25 K26 L1 L2 L3 L4 L5 L11 L12 L13 L14 L15 L16 L22 L23 L24 L25 L26 M1 M2 M3 M4 M5 M11 M12 M13 Function I/O NC NC NC I/O NC I/O I/O I/O I/O NC GND NC NC I/O I/O I/O NC NC I/O I/O VCC GND I/O I/O NC I/O I/O I/O I/O I/O NC GND/THERM GND/THERM GND/THERM GND/THERM GND/THERM GND/THERM NC I/O I/O NC I/O ACLK / I GCLK/I I/O NC GND GND/THERM GND/THERM GND/THERM 456 M14 M15 M16 M22 M23 M24 M25 M26 N1 N2 N3 N4 N5 N11 N12 N13 N14 N15 N16 N22 N23 N24 N25 N26 P1 P2 P3 P4 P5 P11 P12 P13 P14 P15 P16 P22 P23 P24 P25 P26 R1 R2 R3 R4 R5 R11 R12 R13 R14 R15 R16 (continued next page) Note: NC pins must be left unconnected on printed circuit board. 6-48 48 Preliminary Function GND/THERM GND/THERM GND/THERM NC NC I/O I/O I/O GCLK/I I/O I/O GCLK/I VCC GND/THERM GND/THERM GND/THERM GND/THERM GND/THERM GND/THERM GND I/O I/O NC I/O I/O I/O NC I/O NC GND/THERM GND/THERM GND/THERM GND/THERM GND/THERM GND/THERM NC GCLK / I GCLK / I NC ACLK / I NC I/O I/O NC NC GND/THERM GND/THERM GND/THERM GND/THERM GND/THERM GND/THERM QL4058 - QuickRAMTM PBGA 456 Pinout Table (continued from previous page) 456 R22 R23 R24 R25 R26 T1 T2 T3 T4 T5 T11 T12 T13 T14 T15 T16 T22 T23 T24 T25 T26 U1 U2 U3 U4 U5 U22 U23 U24 U25 U26 V1 V2 V3 V4 V5 V22 V23 V24 V25 V26 W1 W2 W3 W4 W5 W22 W23 W24 W25 W26 Function VCC NC NC I/O GCLK / I I/O I/O I/O I/O VCC GND/THERM GND/THERM GND/THERM GND/THERM GND/THERM GND/THERM GND I/O I/O NC I/O NC I/O I/O I/O GND NC I/O I/O I/O I/O I/O I/O NC NC NC GND NC I/O NC I/O I/O I/O I/O I/O NC NC I/O I/O I/O NC 456 Y1 Y2 Y3 Y4 Y5 Y22 Y23 Y24 Y25 Y26 AA1 AA2 AA3 AA4 AA5 AA22 AA23 AA24 AA25 AA26 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25 AB26 AC1 AC2 AC3 AC4 AC5 Function NC I/O NC I/O I/O GND I/O NC I/O I/O I/O I/O NC NC VCC VCC NC I/O I/O I/O NC I/O I/O I/O GND VCC NC NC NC VCC GND NC I/O GND VCC I/O NC VCC GND NC VCC GND I/O NC I/O I/O I/O I/O NC GND NC 456 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AE1 AE2 AE3 AE4 Function NC NC NC NC NC I/O NC I/O VCCIO NC NC NC NC I/O I/O I/O NC GND NC I/O I/O I/O NC I/O I/O I/O I/O I/O I/O NC I/O NC I/O I/O I/O I/O I/O I/O I/O NC NC I/O I/O TRSTB NC I/O I/O TDI I/O I/O I/O 456 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC NC TMS I/O I/O I/O NC I/O NC I/O I/O I/O I/O I/O I/O NC I/O I/O NC NC I/O I/O I/O NC I/O I/O I/O I/O I/O I/O I/O Note: NC pins must be left unconnected on printed circuit board. 6-49 QL4058 - QuickRAMTM PIN DESCRIPTION Pin Description Pin TDI/RSI Function Test Data In for JTAG / RAM init. Serial Data In TRSTB/RRO Active low Reset for JTAG / RAM init. reset out TMS Test Mode Select for JTAG TCK Test Clock for JTAG TDO/RCO Test data out for JTAG / RAM init. clock out STM Special Test Mode I/ACLK Can be configured as either or both. I High-drive input and/or array network driver High-drive input and/or global network driver High-drive input I/O Input/Output pin Can be configured as an input and/or output. VCC Power supply pin Connect to 3.3V supply. VCCIO Input voltage tolerance pin GND Ground pin Connect to 5.0 volt supply if 5 volt input tolerance is required, otherwise connect to 3.3V supply. Connect to ground. GND/THERM Ground/Thermal pin I/GCLK Description Hold HIGH during normal operation. Connects to serial PROM data in for RAM initialization. Connect to VCC if unused. Hold LOW during normal operation. Connects to serial PROM reset for RAM initialization. Connect to GND if unused. Hold HIGH during normal operation. Connect to VCC if not used for JTAG. Hold HIGH or LOW during normal operation. Connect to VCC or ground if not used for JTAG. Connect to serial PROM clock for RAM initialization. Must be left unconnected if not used for JTAG or RAM initialization. Must be grounded during normal operation. Can be configured as either or both. Use for input signals with high fanout. Available on 456-PBGA only. Connect to ground plane on PCB if heat sinking desired. Otherwise may be left unconnected. Ordering Information QL 4058 - 1 PQ208 C QuickLogic device Operating Range C = Commercial I = Industrial M = Military QuickRAM device part number Speed Grade 0 = quick 1 = fast 2 = faster 3 = faster *4 = wow Package Code PQ208 = 208-pin PQFP PQ240 = 240-pin PQFP PB456 = 456-pin PBGA * Contact QuickLogic regarding availability. 6-50 50 Preliminary QL4058 - QuickRAMTM Absolute Maximum Ratings VCC Voltage..................................-0.5 to 4.6V VCCIO Voltage ...................................-0.5 to 7.0V Input Voltage ......................... -0.5 to VCCIO+0.5V Latch-up Immunity .................................. ±200mA DC Input Current.................................. ±20 mA ESD Pad Protection .............................. ±2000V Storage Temperature .............. -65°C to +150°C Lead Temperature ........................... .......300°C Operating Range Symbol Parameter VCC VCCIO TA TC Supply Voltage I/O Input Tolerance Voltage Ambient Temperature Case Temperature -0 Speed Grade Delay Factor -1 Speed Grade -2 Speed Grade -3 Speed Grade -4 Speed Grade K Military Min Max 3.0 3.6 3.0 5.5 -55 125 0.42 2.03 0.42 1.64 0.42 1.37 N/A N/A N/A N/A Industrial Min Max 3.0 3.6 3.0 5.5 -40 85 Commercial Min Max 3.0 3.6 3.0 5.25 0 70 0.43 0.43 0.43 0.43 0.43 0.46 0.46 0.46 0.46 0.46 1.90 1.54 1.28 0.90 0.82 Unit V V °C °C 1.85 1.50 1.25 0.88 0.80 DC Characteristics Symbol VIH VIL VOH Parameter Input HIGH Voltage Input LOW Voltage Output HIGH Voltage VOL Output LOW Voltage II IOZ CI IOS I or I/O Input Leakage Current 3-State Output Leakage Current Input Capacitance [2] Output Short Circuit Current [3] ICC ICCIO D.C. Supply Current [4] D.C. Supply Current on VCCIO Conditions Min Max Unit 0.5VCC VCCIO+0.5 V -0.5 0.3VCC V IOH = -12 mA 2.4 V 0.9VCC V IOH = -500 µA IOL = 16 mA [1] 0.45 V IOL = 1.5 mA 0.1VCC V VI = VCCIO or GND -10 10 µA VI = VCCIO or GND -10 10 µA 10 pF VO = GND -15 -180 mA VO = VCC 40 210 mA VI, VIO = VCCIO or GND 0.50 (typ) 2 mA 0 100 µA Notes: [1] Applies only to -1/-2/-3/-4 commercial grade devices. These speed grades are also PCI-compliant. All other devices have 8 mA IOL specifications. [2]Capacitance is sample tested only. Clock pins are 12 pF maximum. [3]Only one output at a time. Duration should not exceed 30 seconds. [4]For -1/-2/-3/-4 commercial grade devices only. Maximum ICC is 3 mA for -0 commercial grade and all industrial grade devices, and 5 mA for all military grade devices. For AC conditions, contact QuickLogic customer engineering. 6-51 QL4058 - QuickRAMTM AC CHARACTERISTICS at VCC = 3.3V, TA = 25°C (K = 1.00) (To calculate delays, multiply the appropriate K factor in the "Operating Range" section by the following numbers.) Logic Cells Symbol tPD tSU tH tCLK tCWHI tCWLO tSET tRESET tSW tRW Parameter Combinatorial Delay [6] Setup Time [6] Hold Time Clock to Q Delay Clock High Time Clock Low Time Set Delay Reset Delay Set Width Reset Width 1 1.4 1.7 0.0 0.7 1.2 1.2 1.0 0.8 1.9 1.8 Propagation Delays (ns) Fanout [5] 2 3 4 1.7 1.9 2.2 1.7 1.7 1.7 0.0 0.0 0.0 1.0 1.2 1.5 1.2 1.2 1.2 1.2 1.2 1.2 1.3 1.5 1.8 1.1 1.3 1.6 1.9 1.9 1.9 1.8 1.8 1.8 8 3.2 1.7 0.0 2.5 1.2 1.2 2.8 2.6 1.9 1.8 RAM Cell Synchronous Write Timing Symbol TSWA THWA TSWD THWD TSWE THWE TWCRD Parameter WA Setup Time to WCLK WA Hold Time to WCLK WD Setup Time to WCLK WD Hold Time to WCLK WE Setup Time to WCLK WE Hold Time to WCLK WCLK to RD (WA=RA) [5] 1 1.0 0.0 1.0 0.0 1.0 0.0 5.0 Propagation Delays (ns) Fanout 2 3 4 1.0 1.0 1.0 0.0 0.0 0.0 1.0 1.0 1.0 0.0 0.0 0.0 1.0 1.0 1.0 0.0 0.0 0.0 5.3 5.6 5.9 8 1.0 0.0 1.0 0.0 1.0 0.0 7.1 Notes: [5]Stated timing for worst case Propagation Delay over process variation at VCC=3.3V and TA=25°C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating Range. [6]These limits are derived from a representative selection of the slowest paths through the QuickRAM logic cell including typical net delays. Worst case delay values for specific paths should be determined from timing analysis of your particular design. 6-52 52 Preliminary QL4058 - QuickRAMTM RAM Cell Synchronous Read Timing Symbol TSRA THRA TSRE THRE TRCRD Propagation Delays (ns) Fanout 2 3 4 1.0 1.0 1.0 0.0 0.0 0.0 1.0 1.0 1.0 0.0 0.0 0.0 4.3 4.6 4.9 Parameter 1 1.0 0.0 1.0 0.0 4.0 RA Setup Time to RCLK RA Hold Time to RCLK RE Setup Time to RCLK RE Hold Time to RCLK RCLK to RD [5] 8 1.0 0.0 1.0 0.0 6.1 RAM Cell Asynchronous Read Timing Symbol RPDRD Propagation Delays (ns) Fanout 2 3 4 3.3 3.6 3.9 Parameter 1 3.0 RA to RD [5] 8 5.1 Input-Only/Clock Cells Symbol Propagation Delays (ns) Fanout [5] Parameter 1 2 3 4 8 12 24 TIN TINI TISU TIH TlCLK TlRST TlESU High Drive Input Delay High Drive Input, Inverting Delay Input Register Set-Up Time Input Register Hold Time Input Register Clock To Q Input Register Reset Delay Input Register Clock Enable Setup Time 1.5 1.6 3.1 0.0 0.7 0.6 2.3 1.6 1.7 3.1 0.0 0.8 0.7 2.3 1.8 1.9 3.1 0.0 1.0 0.9 2.3 1.9 2.0 3.1 0.0 1.1 1.0 2.3 2.4 2.5 3.1 0.0 1.6 1.5 2.3 2.9 3.0 3.1 0.0 2.1 2.0 2.3 4.4 4.5 3.1 0.0 3.6 3.5 2.3 TlEH Input Register Clock Enable Hold Time 0.0 0.0 0.0 0.0 0.0 0.0 0.0 Clock Cells Symbol tACK tGCKP tGCKB Parameter Array Clock Delay Global Clock Pin Delay Global Clock Buffer Delay 1 1.2 0.7 0.8 Propagation Delays (ns) Loads per Half Column [7] 2 3 4 8 10 1.2 1.3 1.3 1.5 1.6 0.7 0.7 0.7 0.7 0.7 0.8 0.9 0.9 1.1 1.2 11 1.7 0.7 1.3 Notes: [7]The array distributed networks consist of 40 half columns and the global distributed networks consist of 44 half columns, each driven by an independent buffer. The number of half columns used does not affect clock buffer delay. The array clock has up to 8 loads per half column. The global clock has up to 11 loads per half column. 6-53 QL4058 - QuickRAMTM I/O Cell Input Delays Symbol tI/O TISU TIH TlOCLK TlORST TlESU TlEH Propagation Delays (ns) Fanout [5] Parameter Input Delay (bidirectional pad) Input Register Set-Up Time Input Register Hold Time Input Register Clock To Q Input Register Reset Delay Input Register clock Enable Set-Up Time Input Register Clock Enable Hold Time 1 2 3 4 8 10 1.3 3.1 0.0 0.7 0.6 2.3 0.0 1.6 3.1 0.0 1.0 0.9 2.3 0.0 1.8 3.1 0.0 1.2 1.1 2.3 0.0 2.1 3.1 0.0 1.5 1.4 2.3 0.0 3.1 3.1 0.0 2.5 2.4 2.3 0.0 3.6 3.1 0.0 3.0 2.9 2.3 0.0 I/O Cell Output Delays Symbol TOUTLH TOUTHL TPZH TPZL TPHZ TPLZ Propagation Delays (ns) Output Load Capacitance (pF) Parameter Output Delay Low to High Output Delay High to Low Output Delay Tri-state to High Output Delay Tri-state to Low Output Delay High to Tri-State [8] Output Delay Low to Tri-State [8] 30 50 75 100 150 2.1 2.2 1.2 1.6 2.0 1.2 2.5 2.6 1.7 2.0 3.1 3.2 2.2 2.6 3.6 3.7 2.8 3.1 4.7 4.8 3.9 4.2 Notes: [8]The following loads are used for tPXZ tPHZ 1KΩ 5 pF 1KΩ tPLZ 5 pF 6-54 54 Preliminary