RF1K49093 Data Sheet January 2002 2.5A, 12V, 0.130 Ohm, Logic Level, Dual P-Channel LittleFET™ Power MOSFET Features • 2.5A, 12V This Dual P-Channel power MOSFET is manufactured using an advanced MegaFET process. This process, which uses feature sizes approaching those of LSI integrated circuits, gives optimum utilization of silicon, resulting in outstanding performance. It is designed for use in applications such as switching regulators, switching converters, motor drivers, relay drivers, and low voltage bus switches. This product achieves full rated conduction at a gate bias in the 3V - 5V range, thereby facilitating true on-off power control directly from logic level (5V) integrated circuits. • rDS(ON) = 0.130Ω • Temperature Compensating PSPICE® Model • On-Resistance vs Gate Drive Voltage Curves • Peak Current vs Pulse Width Curve • UIS Rating Curve • Related Literature - TB334 “Guidelines for Soldering Surface Mount Components to PC Boards” Formerly developmental type TA49093. Symbol Ordering Information PART NUMBER RF1K49093 PACKAGE MS-012AA D1 (8) D1 (7) BRAND RF1K49093 S1 (1) G1 (2) NOTE: When ordering, use the entire part number. For ordering in tape and reel, add the suffix 96 to the part number, i.e., RF1K4909396. D2 (6) D2 (5) S2 (3) G2 (4) Packaging JEDEC MS-012AA BRANDING DASH 5 1 2 3 ©2002 Fairchild Semiconductor Corporation 4 RF1K49093 Rev. B RF1K49093 Absolute Maximum Ratings TA = 25oC Unless Otherwise Specified RF1K49093 UNITS Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20kΩ, Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR -12 V -12 V Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS ±10 V Drain Current Continuous (Pulse width = 5s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed (Figure 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM 2.5 Refer to Peak Current Curve A Pulsed Avalanche Rating (Figure 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Refer to UIS Curve Power Dissipation TA = 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0.016 W W/oC -55 to 150 oC 300 260 oC oC Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC. Electrical Specifications TA = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Drain to Source Breakdown Voltage BVDSS ID = 250µA, VGS = 0V, (Figure 13) -12 - - V Gate Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA, (Figure 12) -1 - -2 V - - -1 µA - - -50 µA VGS = ±10V - - ±100 nA ID = 2.5A, VGS = -5V, (Figure 9, 11) - - 0.130 Ω VDD = -6V, ID ≈ 2.5A, RL = 2.40Ω, V GS = -5V, RGS = 25Ω (Figure 10) - - 115 ns - 25 - ns - 65 - ns td(OFF) - 40 - ns tf - 45 - ns tOFF - - 110 ns - 19 24 nC - 10 14 nC - 0.8 1.1 nC - 775 - pF - 550 - pF - 150 - pF Zero Gate Voltage Drain Current Gate to Source Leakage Current Drain to Source On Resistance Turn-On Time IDSS IGSS rDS(ON) tON Turn-On Delay Time Rise Time td(ON) tr Turn-Off Delay Time Fall Time Turn-Off Time VDS = -12V, VGS = 0V Total Gate Charge Qg(TOT) VGS = 0V to -10V Gate Charge at -5V Qg(-5) VGS = 0V to -5V Threshold Gate Charge Qg(TH) VGS = 0V to -1V Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS Thermal Resistance Junction-to-Ambient RθJA TA = 25oC TA = 150oC VDD = -9.6V, ID = 2.5A, RL = 3.84Ω (Figure 15) VDS = -10V, VGS = 0V, f = 1MHz (Figure 14) - - 62.5 oC/W MIN TYP MAX UNITS ISD = -2.5A - - -1.25 V ISD = -2.5A, dISD/dt = -100A/µs - - 55 ns Pulse width = 1s Device mounted on FR-4 material Source to Drain Diode Ratings and Specifications PARAMETER Source to Drain Diode Voltage Reverse Recovery Time ©2002 Fairchild Semiconductor Corporation SYMBOL VSD trr TEST CONDITIONS RF1K49093 Rev. B RF1K49093 1.2 -3.0 1.0 -2.5 ID, DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER Typical Performance Curves 0.8 0.6 0.4 -2.0 -1.5 -1.0 -0.5 0.2 0.0 0 25 50 75 100 125 TA , AMBIENT TEMPERATURE (oC) 0 25 150 FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT TEMPERATURE ZθJA, NORMALIZED THERMAL IMPEDANCE 10 1 50 75 100 125 TA, AMBIENT TEMPERATURE (oC) 150 FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs AMBIENT TEMPERATURE DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 0.1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJA x RθJA + TA SINGLE PULSE 0.01 10-3 10-2 10-1 100 101 t, RECTANGULAR PULSE DURATION (s) 102 103 FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE TJ = MAX RATED, TA = 25oC ID, DRAIN CURRENT (A) VDSS MAX = -12V -10 5ms 10ms -1 100ms 1s -0.1 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) -0.01 -0.1 -1 DC -10 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 4. FORWARD BIAS SAFE OPERATING AREA ©2002 Fairchild Semiconductor Corporation -100 -200 IDM, PEAK CURRENT CAPABILITY (A) -100 FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: -100 I VGS = -10V = I25 150 - TA 125 TA = 25oC VGS = -5V -10 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION -1 10-5 10-4 10-3 10-2 10-1 100 101 t, PULSE WIDTH (s) FIGURE 5. PEAK CURRENT CAPABILITY RF1K49093 Rev. B RF1K49093 Typical Performance Curves (Continued) -25 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX TA = 25oC VGS = -10V -10 ID, DRAIN CURRENT (A) IAS, AVALANCHE CURRENT (A) -20 STARTING TJ = 25oC STARTING TJ = 150oC If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R ≠ 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] -1 0.1 -20 VGS = -5V -15 VGS = -4.5V -10 VGS = -4V -5 VGS = -3V 1 10 tAV, TIME IN AVALANCHE (ms) 0 100 0 -1 -2 -3 -4 VDS, DRAIN TO SOURCE VOLTAGE (V) -5 NOTE: Refer to Fairchild Application Notes AN9321 and AN9322. FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY FIGURE 7. SATURATION CHARACTERISTICS 500 VDD = -6V -55oC rDS(ON) , ON-STATE RESISTANCE (mΩ) ID(ON), ON-STATE DRAIN CURRENT (A) -25 150oC -20 25oC -15 -10 -5 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 0 0.0 400 ID = -2.5A 200 100 0 -2.5 -3.5 -3.0 -4.0 -4.5 -5.0 FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT 120 2.0 NORMALIZED DRAIN TO SOURCE ON RESISTANCE VDD = -6V, ID = -2.5A, RL= 2.40Ω tr 100 SWITCHING TIME (ns) ID = -0.5A VGS, GATE TO SOURCE VOLTAGE (V) FIGURE 8. TRANSFER CHARACTERISTICS 80 tf 60 tD(OFF) 40 tD(ON) 20 0 ID = -6.0A 300 -7.5 -1.5 -3.0 -4.5 -6.0 VGS, GATE TO SOURCE VOLTAGE (V) PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VDD = -10V ID = -1.5A 0 20 30 40 10 RGS, GATE TO SOURCE RESISTANCE (Ω) FIGURE 10. SWITCHING TIME AS A FUNCTION OF GATE RESISTANCE ©2002 Fairchild Semiconductor Corporation 50 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VGS = -5V, ID = -2.5A 1.5 1.0 0.5 0 -80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC) FIGURE 11. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE RF1K49093 Rev. B RF1K49093 Typical Performance Curves (Continued) 2.0 2.0 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 1.0 0.5 0.0 -80 -40 0 40 80 120 TJ, JUNCTION TEMPERATURE (oC) C, CAPACITANCE (pF) 1200 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS = CDS + CGD 900 CISS COSS 600 300 CRSS 1.5 1.0 0.5 0.0 -80 160 FIGURE 12. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE ID = -250µA -40 0 40 80 120 TJ , JUNCTION TEMPERATURE (oC) FIGURE 13. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE -5.00 -12 VDD = BVDSS VDD = BVDSS -3.75 -9 -6 -2.50 0.75 BVDSS 0.50 BVDSS 0.25 BVDSS -3 -1.25 RL = 3.84Ω IG(REF) = -0.5mA VGS = -5V 0.00 0 0 0 -2 -4 -6 -8 I G ( REF ) -10 20 ---------------------I G ( ACT ) VDS, DRAIN TO SOURCE VOLTAGE (V) NOTE: FIGURE 14. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE 160 VGS , GATE-SOURCE VOLTAGE (V) 1.5 VDS , DRAIN-SOURCE VOLTAGE (V) NORMALIZED GATE THRESHOLD VOLTAGE VGS = VDS, ID = -250µA t, TIME (µs) I G ( REF ) 80 ---------------------I G ( ACT ) Refer to Fairchild Application Notes AN7254 and AN7260. FIGURE 15. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT Test Circuits and Waveforms VDS tAV L VARY tP TO OBTAIN REQUIRED PEAK IAS 0 - RG + 0V VGS DUT tP IAS VDD IAS VDS tP 0.01Ω FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT ©2002 Fairchild Semiconductor Corporation VDD BVDSS FIGURE 17. UNCLAMPED ENERGY WAVEFORMS RF1K49093 Rev. B RF1K49093 Test Circuits and Waveforms (Continued) tON tOFF td(OFF) td(ON) tf tr 0 - DUT VGS VDS VDD RG 90% 90% VGS 0 + 10% 10% RL 10% 50% 50% PULSE WIDTH 90% FIGURE 19. RESISTIVE SWITCHING WAVEFORMS FIGURE 18. SWITCHING TIME TEST CIRCUIT -VDS (ISOLATED SUPPLY) CURRENT REGULATOR DUT 12V BATTERY 0.2µF VDS Qg(TH) 0 50kΩ 0.3µF VGS= -1V VGS= -5V -VGS D Qg(-5) DUT G VGS= -10V VDD 0 S Ig(REF) IG CURRENT SAMPLING RESISTOR +VDS ID CURRENT SAMPLING RESISTOR FIGURE 20. GATE CHARGE TEST CIRCUIT Soldering Precautions The soldering process creates a considerable thermal stress on any semiconductor component. The melting temperature of solder is higher than the maximum rated temperature of the device. The amount of time the device is heated to a high temperature should be minimized to assure device reliability. Therefore, the following precautions should always be observed in order to minimize the thermal stress to which the devices are subjected. 1. Always preheat the device. 2. The delta temperature between the preheat and soldering should always be less than 100oC. Failure to preheat the device can result in excessive thermal stress which can damage the device. ©2002 Fairchild Semiconductor Corporation Qg(TOT) 0 Ig(REF) FIGURE 21. GATE CHARGE WAVEFORMS 3. The maximum temperature gradient should be less than 5oC per second when changing from preheating to soldering. 4. The peak temperature in the soldering process should be at least 30 oC higher than the melting point of the solder chosen. 5. The maximum soldering temperature and time must not exceed 260oC for 10 seconds on the leads and case of the device. 6. After soldering is complete, the device should be allowed to cool naturally for at least three minutes, as forced cooling will increase the temperature gradient and may result in latent failure due to mechanical stress. 7. During cooling, mechanical stress or shock should be avoided. RF1K49093 Rev. B RF1K49093 PSPICE Electrical Model SUBCKT RF1K49093 2 1 3 ;rev 10/24/94 CA 12 8 8.75e-10 CB 15 14 8.65e-10 CIN 6 8 7.65e-10 DBODY 5 7 DBDMOD DBREAK 7 11 DBKMOD DPLCAP 10 5 DPLCAPMOD DPLCAP EBREAK 5 11 17 18 -23.75 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 8 6 1 EVTO 20 6 8 18 1 ESG MOS1 16 6 8 8 MOSMOD M = 0.99 MOS2 16 21 8 8 MOSMOD M = 0.01 2 DRAIN RDRAIN IT 8 17 1 LDRAIN 2 5 1e-9 LGATE 1 9 1.233e-9 LSOURCE 3 7 0.452e-9 LDRAIN 5 10 + GATE 1 EBREAK 16 - VTO + EVTO LGATE RGATE + 18 8 9 20 21 6 MOS1 RIN S1A 6 12 13 8 S1AMOD S1B 13 12 13 8 S1BMOD S2A 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD S1A 12 17 18 - MOS2 11 DBREAK CIN 8 RBREAK 17 18 RBKMOD 1 RDRAIN 5 16 RDSMOD 7.36e-3 RGATE 9 20 6.1 RIN 6 8 1e9 RSOURCE 8 7 RDSMOD 4.56e-2 RVTO 18 19 RVTOMOD 1 DBODY + 6 8 RSOURCE 7 LSOURCE 3 SOURCE S2A 13 8 S1B RBREAK 15 14 13 17 18 S2B RVTO 13 CB CA EGS - 14 + + 6 8 EDS - 5 8 IT 19 VBAT + VBAT 8 19 DC 1 VTO 21 6 -0.558 .MODEL DBDMOD D (IS = 3.0e-13 RS = 4.4e-2 TRS1 = 1.0e-3 TRS2 = -7.37e-6 CJO = 1.27e-9 TT = 2.2e-8) .MODEL DBKMOD D (RS = 7.84e-2 TRS1 = -4.27e-3 TRS2 = 5.77e-5) .MODEL DPLCAPMOD D (CJO = 2.85e-10 IS = 1e-30 N = 10) .MODEL MOSMOD PMOS (VTO = -2.1423 KP = 9.206 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL RBKMOD RES (TC1 = 9.61e- 4TC2 = -1.09e-6) .MODEL RDSMOD RES (TC1 = 2.10e-3 TC2 = 6.99e-6) .MODEL RVTOMOD RES (TC1 = -1.82e- 3TC2 = 1.47e-7) .MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 5.47 VOFF= 3.47) .MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 3.47 VOFF= 5.47) .MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 1.05 VOFF= -3.95) .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3.95 VOFF= 1.05) .ENDS NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991. ©2002 Fairchild Semiconductor Corporation RF1K49093 Rev. B TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx™ Bottomless™ CoolFET™ CROSSVOLT™ DenseTrench™ DOME™ EcoSPARK™ E2CMOSTM EnSignaTM FACT™ FACT Quiet Series™ FAST FASTr™ FRFET™ GlobalOptoisolator™ GTO™ HiSeC™ ISOPLANAR™ LittleFET™ MicroFET™ MicroPak™ MICROWIRE™ OPTOLOGIC™ OPTOPLANAR™ PACMAN™ POP™ Power247™ PowerTrench QFET™ QS™ QT Optoelectronics™ Quiet Series™ SILENT SWITCHER SMART START™ STAR*POWER™ Stealth™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TinyLogic™ TruTranslation™ UHC™ UltraFET VCX™ STAR*POWER is used under license DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant into support device or system whose failure to perform can the body, or (b) support or sustain life, or (c) whose be reasonably expected to cause the failure of the life failure to perform when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. H4