TPS3820-xx-Q1, TPS3823-xx-Q1, TPS3824-xx-Q1, TPS3825-xx-Q1, TPS3828-xx-Q1 PROCESSOR SUPERVISORY CIRCUITS SGLS143A – DECEMBER 2002 – REVISED JANUARY 2003 TPS3820, TPS3823, TPS3828 . . . DBV PACKAGE features (TOP VIEW) D Qualification in Accordance With D D D D D D D D D D AEC-Q100† Qualified for Automotive Applications Customer-Specific Configuration Control Can Be Supported Along With Major-Change Approval† ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Using Human Body Model (C = 100 pF, R = 1500 Ω) Power-On Reset Generator With Fixed Delay Time of 200 ms (TPS3823/4/5/8) or 25 ms (TPS3820) Manual Reset Input (TPS3820/3/5/8) Reset Output Available in Active-Low (TPS3820/3/4/5), Active-High (TPS3824) and Open-Drain (TPS3828) Supply Voltage Supervision Range 2.5 V, 3 V, 3.3 V, 5 V Watchdog Timer (TPS3820/3/4/8) Supply Current of 15 µA (Typ) SOT23-5 Package RESET 1 GND 2 MR 3 5 VDD 4 WDI TPS3824 . . . DBV PACKAGE (TOP VIEW) RESET 1 GND 2 RESET 3 5 VDD 4 WDI TPS3825 . . . DBV PACKAGE (TOP VIEW) RESET 1 GND 2 RESET 3 5 VDD 4 MR typical application applications 3.3 V D Applications Using Automotive DSPs, D D D D D D Microcontrollers, or Microprocessors Industrial Equipment Programmable Controls Automotive Systems Battery-Powered Equipment Intelligent Instruments Wireless Communications Systems † Contact factory for details. Q100 qualification data available on request. 100 nF VDD RESET VDD RESET TPS3823-33 MR WDI GND MSP430C325 I/O GND description The TPS382x family of supervisors provides circuit initialization and timing supervision, primarily for DSP and processor-based systems. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2002 – 2003, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TPS3820-xx-Q1, TPS3823-xx-Q1, TPS3824-xx-Q1, TPS3825-xx-Q1, TPS3828-xx-Q1 PROCESSOR SUPERVISORY CIRCUITS SGLS143A – DECEMBER 2002 – REVISED JANUARY 2003 description (continued) During power-on, RESET is asserted when supply voltage VDD becomes higher than 1.1 V. Thereafter, the supply voltage supervisor monitors VDD and keeps RESET active as long as VDD remains below the threshold voltage VIT–. An internal timer delays the return of the output to the inactive state (high) to ensure proper system reset. The delay time, td, starts after VDD has risen above the threshold voltage VIT–. When the supply voltage drops below the threshold voltage VIT–, the output becomes active (low) again. No external components are required. All the devices of this family have a fixed-sense threshold voltage VIT– set by an internal voltage divider. The TPS3820/3/5/8 devices incorporate a manual reset input, MR. A low level at MR causes RESET to become active. The TPS3824/5 devices include a high-level output RESET. TPS3820/3/4/8 have a watchdog timer that is periodically triggered by a positive or negative transition at WDI. When the supervising system fails to retrigger the watchdog circuit within the time-out interval, ttout, RESET becomes active for the time period td. This event also reinitializes the watchdog timer. Leaving WDI unconnected disables the watchdog. In applications where the input to the WDI pin may be active (transitioning high and low) when the TPS3820/3/4/8 is asserting RESET, the TPS3820/3/4/8 does not return to a non-reset state when the input voltage is above Vt. If the application requires that input to WDI is active when RESET is asserted, WDI must be decoupled from the active signal. This can be accomplished by using an N-channel FET in series with the WDI pin, with the gate of the FET connected to the RESET output as shown in Figure 1. TPS3824 WDI WDI External RESET Figure 1 The product spectrum is designed for supply voltages of 2.5 V, 3 V, 3.3 V, and 5 V. The circuits are available in a 5-pin SOT23-5 package. The TPS382x-xxQ-Q1 devices are characterized for operation over a temperature range of –40°C to 125°C, and are qualified in accordance with AEC-Q100 stress test qualification for integrated circuits. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS3820-xx-Q1, TPS3823-xx-Q1, TPS3824-xx-Q1, TPS3825-xx-Q1, TPS3828-xx-Q1 PROCESSOR SUPERVISORY CIRCUITS SGLS143A – DECEMBER 2002 – REVISED JANUARY 2003 PACKAGE INFORMATION DEVICE NAME TPS3820-33QDBVRQ1† TPS3820-50QDBVRQ1† THRESHOLD VOLTAGE MARKING 2.93 V PDEQ 4.55 V PDDQ TPS3823-25QDBVRQ1† TPS3823-30QDBVRQ1† 2.25 V PAPQ 2.63 V PAQQ TPS3823-33QDBVRQ1† TPS3823-50QDBVRQ1† 2.93 V PARQ 4.55 V PASQ TPS3824-25QDBVRQ1† TPS3824-30QDBVRQ1† 2.25 V PATQ 2.63 V PAUQ TPS3824-33QDBVRQ1† TPS3824-50QDBVRQ1† 2.93 V PAVQ 4.55 V PAWQ TPS3825-33QDBVRQ1† TPS3825-50QDBVRQ1† 2.93 V PDGQ 4.55 V PDFQ TPS3828-33QDBVRQ1† TPS3828-50QDBVRQ1† 2.93 V PDIQ 4.55 V † The DBVR package indicates tape and reel of 3000 parts. PDHQ FUNCTION/TRUTH TABLE INPUTS MR‡ OUTPUTS RESET RESET§ L VDD>VIT 0 L H L 1 L H H 0 L H H 1 H L ‡ TPS3820/3/5/8 § TPS3824/5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 TPS3820-xx-Q1, TPS3823-xx-Q1, TPS3824-xx-Q1, TPS3825-xx-Q1, TPS3828-xx-Q1 PROCESSOR SUPERVISORY CIRCUITS SGLS143A – DECEMBER 2002 – REVISED JANUARY 2003 functional block diagram VDD Watchdog Timer Logic Reset† Reset Logic Reset 52 kΩ + _ MR‡ 40 kΩ Vref Transition Detector WDI †TPS3824/5 ‡TPS3820/3/5/8 timing diagram VIT VDD 1.1 V td td tt(out) td undefined undefined RESET WDI 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS3820-xx-Q1, TPS3823-xx-Q1, TPS3824-xx-Q1, TPS3825-xx-Q1, TPS3828-xx-Q1 PROCESSOR SUPERVISORY CIRCUITS SGLS143A – DECEMBER 2002 – REVISED JANUARY 2003 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V RESET, RESET, MR, WDI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to (VDD + 0.3 V) Maximum low output current, IOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA Maximum high output current, IOH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –5 mA Input clamp current range, IIK (VI < 0 or VI > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA Output clamp current range, IOK (VO < 0 or VO > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 125°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C Soldering temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to GND. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING OPERATING FACTOR ABOVE TA = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING TA = 125°C POWER RATING DBV 437 mW 3.5 mW/°C 280 mW 227 mW 87 mW recommended operating conditions Supply voltage, VDD Input voltage, VI MIN MAX 1.1 5.5 V VDD + 0.3 V 0 0.7 × VDD High-level input voltage at MR and WDI, VIH Low-level input voltage, VIL Input transition rise and fall rate at MR or WDI, ∆t/∆V Operating free-air temperature range, TA –40 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT V 0.3 × VDD V 100 ns/V 125 °C 5 TPS3820-xx-Q1, TPS3823-xx-Q1, TPS3824-xx-Q1, TPS3825-xx-Q1, TPS3828-xx-Q1 PROCESSOR SUPERVISORY CIRCUITS SGLS143A – DECEMBER 2002 – REVISED JANUARY 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS RESET VOH High-level output voltage TPS382x-25 VDD = VIT– + 0.2 V IOH = –20 µA TPS382x-30 TPS382x-33 VDD = VIT– + 0.2 V IOH = –30 µA TPS382x-50 VDD = VIT– + 0.2 V IOH = –120 µA TPS3824-25 TPS3825-25 VDD ≥ 1.8 V, IOH = –100 µA TPS3824-30 TPS3825-30 RESET TPS3824-33 TPS3825-33 VDD ≥ 1.8 V, IOH = –150 µA MIN TYP MAX UNIT 0 8 × VDD 0.8 V VDD – 1.5 V 0 8 × VDD 0.8 V TPS3824-50 TPS3825-50 TPS3824-25 TPS3825-25 TPS3824-30 TPS3825-30 RESET VOL Low-level output voltage TPS3824-33 TPS3825-33 VDD = VIT– + 0.2 V IOL = 1.2 mA TPS3824-50 TPS3825-50 VDD = VIT– + 0.2 V IOL = 3 mA TPS382x-25 VDD = VIT– – 0.2 V IOL = 1 mA TPS382x-30 RESET VDD = VIT– + 0.2 V IOL = 1 mA TPS382x-33 TPS382x-50 VDD = VIT– –0.2 0.2 V IOL = 1.2 mA TPS382x-25 V 0.4 V 2.25 2.30 2.59 2.63 2.69 2.88 2.93 3 TPS382x-50 4.49 4.55 4.64 TPS382x-25 2.19 2.25 2.30 TPS382x-30 2.55 2.63 2.69 2.84 2.93 3 4.44 4.55 4.65 TPS382x-33 Negative-going Negative going input in ut threshold voltage (see Note 3) 0 45 0.45 2.21 TPS382x-30 VIT– V VDD = VIT– – 0.2 V IOL = 3 mA VDD ≥ 1.1 V, IOL = 20 µA Power-up reset voltage (see Note 2) 04 0.4 TPS382x-33 TA = 0°C to 85°C TA = – 40°C to 125°C TPS382x-50 V V TPS382x-25 TPS382x-30 Vhys Hysteresis at VDD input 30 TPS382x-33 TPS382x-50 mV 50 NOTES: 2. The lowest supply voltage at which RESET becomes active. tr, VDD ≥ 15 µs/V 3. To ensure best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1 µF) should be placed near the supply terminals. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS3820-xx-Q1, TPS3823-xx-Q1, TPS3824-xx-Q1, TPS3825-xx-Q1, TPS3828-xx-Q1 PROCESSOR SUPERVISORY CIRCUITS SGLS143A – DECEMBER 2002 – REVISED JANUARY 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued) PARAMETER IIH(AV) TEST CONDITIONS IIH High-level input current IIL Low level input current Low-level MAX UNIT µA 120 WDI = 0.3 V, VDD = 5.5 V time average (dc = 12%) –15 WDI WDI = VDD 140 190 MR MR = VDD × 0.7, VDD = 5.5 V –40 –60 WDI Average low-level input current TYP WDI = VDD, time average (dc = 88%) Average high-level input current IIL(AV) MIN WDI MR WDI = 0.3 V, VDD = 5.5 V MR = 0.3 V, VDD = 5.5 V 140 190 –110 –160 TPS382x-25 IOS Output short-circuit Out ut short circuit current (see Note 4) TPS382x-30 RESET TPS382x-33 –400 400 VDD = VIT, max + 0.2 V, VO = 0 V TPS382x-50 IDD –800 WDI and MR unconnected, Outputs unconnected Supply current A µA 15 Internal pullup resistor at MR 25 52 µA kΩ Ci Input capacitance at MR, WDI VI = 0 V to 5.5 V 5 NOTE 4: The RESET short-circuit current is the maximum pullup current when RESET is driven low by a µP bidirectional reset pin. pF timing requirements at RL = 1 MΩ, CL = 50 pF, TA = 25°C PARAMETER TEST CONDITIONS at VDD tw Pulse width at MR VDD = VIT– + 0.2 V, VDD ≥ VIT– + 0.2 V, VDD = VIT- - 0.2 V VIL = 0.3 x VDD, at WDI VDD ≥ VIT– + 0.2 V, VIL = 0.3 x VDD, MIN VIH = 0.7 x VDD VIH = 0.7 x VDD MAX UNIT 6 µs 1 µs 100 ns switching characteristics at RL = 1 MΩ, CL = 50 pF, TA = 25°C PARAMETER TEST CONDITIONS TPS3820 ttout Watchdog time out TPS3823/4/8 TPS3820 td tPHL tPLH Delay time Propagation (delay) time, high-to-low-level output Propagation (delay) time, low to high level output low-to-high-level TPS3823/4/5/8 MIN TYP MAX UNIT VDD ≥ VIT– + 0.2 V, See Timing Diagram 112 200 310 ms 0.9 1.6 2.5 s VDD ≥ VIT– + 0.2 V, See timing diagram 15 25 37 120 200 300 MR to RESET delay (TPS3820/3/5/8) VDD ≥ VIT– + 0.2 V, VIL = 0.3 x VDD, VIH = 0.7 x VDD 0.1 VDD to RESET delay VIL = VIT- - 0.2 V, VIH = VIT- + 0.2 V 25 MR to RESET delay (TPS3824/5) VDD to RESET delay (TPS3824/5) POST OFFICE BOX 655303 VDD ≥ VIT– + 0.2 V, VIL = 0.3 x VDD, VIH = 0.7 x VDD VIL = VIT- - 0.2 V, VIH = VIT- + 0.2 V • DALLAS, TEXAS 75265 ms µs 0.1 µs 25 7 TPS3820-xx-Q1, TPS3823-xx-Q1, TPS3824-xx-Q1, TPS3825-xx-Q1, TPS3828-xx-Q1 PROCESSOR SUPERVISORY CIRCUITS SGLS143A – DECEMBER 2002 – REVISED JANUARY 2003 NORMALIZED INPUT THRESHOLD VOLTAGE vs FREE-AIR TEMPERATURE AT VDD SUPPLY CURRENT vs SUPPLY VOLTAGE 1.001 19 MR = Open WDI = Open TA = 25°C 17 1 15 I DD– Supply Current – µ A Normalized Input Threshold Voltage – VIT (TA), VIT (25 °C) TYPICAL CHARACTERISTICS 0.999 0.998 0.997 13 TPS382x-33 11 9 7 5 3 0.996 1 0.995 –40 –15 10 60 35 –1 –0.5 85 0.5 1.5 TA – Free-Air Temperature – °C Figure 2 VOL – Low-Level Output Voltage – V 0 I I – Input Current – µ A 5.5 6.5 3 VDD = 2.66 V WDI = Open MR = Open VDD = 5.5 V WDI = Open –40°C –100 85°C –150 0 1 2 3 4 5 6 VI – Input Voltage at MR – V 2.5 2 1.5 85°C 1 –40°C 0.5 0 0 2 1 3 4 5 Figure 5 POST OFFICE BOX 655303 6 7 8 IOL – Low-Level Output Current – mA Figure 4 8 4.5 LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 50 –200 –1 3.5 Figure 3 INPUT CURRENT vs INPUT VOLTAGE AT MR –50 2.5 VDD – Supply Voltage – V • DALLAS, TEXAS 75265 9 10 TPS3820-xx-Q1, TPS3823-xx-Q1, TPS3824-xx-Q1, TPS3825-xx-Q1, TPS3828-xx-Q1 PROCESSOR SUPERVISORY CIRCUITS SGLS143A – DECEMBER 2002 – REVISED JANUARY 2003 TYPICAL CHARACTERISTICS HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT 6 3 VOH – High-Level Output Voltage – V VDD = 3.2 V WDI = Open MR = Open 2.5 –40°C 2 1.5 85°C 1 0.5 0 0 –50 –100 –150 –200 VDD = 5.5 V WDI = Open MR = Open 5 4 –40°C 3 85°C 2 1 0 –250 0 IOH – High-Level Output Current – µA –100 –200 –300 –400 –500 –600 –700 IOH – High-Level Output Current – µA Figure 6 Figure 7 MINIMUM PULSE DURATION AT VDD vs VDD THRESHOLD OVERDRIVE 10 t w – Minimum Pulse Duration at VDD – µs VOH – High-Level Output Voltage – V 3.5 WDI = Open MR = Open 8 6 4 2 0 0 200 400 600 800 1000 VDD – Threshold Overdrive – mV Figure 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 TPS3820-xx-Q1, TPS3823-xx-Q1, TPS3824-xx-Q1, TPS3825-xx-Q1, TPS3828-xx-Q1 PROCESSOR SUPERVISORY CIRCUITS SGLS143A – DECEMBER 2002 – REVISED JANUARY 2003 MECHANICAL DATA DBV (R-PDSO-G5) PLASTIC SMALL-OUTLINE 0,95 5X 5 0,50 0,20 M 0,30 4 1,70 1,50 1 0,15 NOM 3,00 2,60 3 Gage Plane 3,00 2,80 0,25 0°–8° 0,55 0,35 Seating Plane 1,45 0,95 0,05 MIN 0,10 4073253-4/G 01/02 NOTES: A. B. C. D. 10 All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion. Falls within JEDEC MO-178 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. 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