UCC1580-1,-2,-3,-4 UCC2580-1,-2,-3,-4 UCC3580-1,-2,-3,-4 Single Ended Active Clamp/Reset PWM FEATURES DESCRIPTION • Provides Auxiliary Switch Activation Complementary to Main Power Switch Drive The UCC3580 family of PWM controllers is designed to implement a variety of active clamp/reset and synchronous rectifier switching converter topologies. While containing all the necessary functions for fixed frequency, high performance pulse width modulation, the additional feature of this design is the inclusion of an auxiliary switch driver which complements the main power switch, and with a programmable deadtime or delay between each transition. The active clamp/reset technique allows operation of single ended converters beyond 50% duty cycle while reducing voltage stresses on the switches, and allows a greater flux swing for the power transformer. This approach also allows a reduction in switching losses by recovering energy stored in parasitic elements such as leakage inductance and switch capacitance. • Programmable deadtime (Turn-on Delay) Between Activation of Each Switch • Voltage Mode Control with Feedforward Operation • Programmable Limits for Both Transformer Volt- Second Product and PWM Duty Cycle • High Current Gate Driver for Both Main and Auxiliary Outputs • Multiple Protection Features with Latched Shutdown and Soft Restart The oscillator is programmed with two resistors and a capacitor to set switching frequency and maximum duty cycle. A separate synchronized ramp provides a voltage feedforward pulse width modulation and a programmed maximum volt-second limit. The generated clock from the oscillator contains both frequency and maximum duty cycle information. • Low Supply Current (100µA Startup, 1.5mA Operation) (continued) BLOCK DIAGRAM Pin Numbers refer to DIL-16 and SOIC-16 packages SLUS292A - FEBRUARY 1999 - REVISED JANUARY 2002 UDG-95069-2 UCC1580-1,-2,-3,-4 UCC2580-1,-2,-3,-4 UCC3580-1,-2,-3,-4 DESCRIPTION (cont.) The main gate drive output (OUT1) is controlled by the pulse width modulator. The second output (OUT2) is intended to activate an auxiliary switch during the off time of the main switch, except that between each transition there is deadtime where both switches are off, programmed by a single external resistor. This design offers two options for OUT2, normal and inverted. In the -1 and -2 versions, OUT2 is normal and can be used to drive PMOS FETs. In the -3 and -4 versions, OUT2 is inverted and can be used to drive NMOS FETs. In all versions, both the main and auxiliary switches are held off prior to startup and when the PWM command goes to zero duty cycle. During fault conditions, OUT1 is held off while OUT2 operates at maximum duty cycle with a guaranteed off time equal to the sum of the two deadtimes. Undervoltage lockout monitors supply voltage (VDD), the precision reference (REF), input line voltage (LINE), and the shutdown comparator (SHTDWN). If after any of these four have sensed a fault condition, recovery to full operation is initiated with a soft start. VDD thresholds, on and off, are 15V and 8.5V for the -2 and -4 versions, 9V and 8.5V for the -1 and -3 versions. The UCC1580-x is specified for operation over the military temperature range of −55°C to 125°C. The UCC2580-x is specified from −40°C to 85°C. The UCC3580-x is specified from 0°C to 70°C. Package options include 16-pin surface mount or dual in-line, and 20-pin plastic leadless chip carrier. ABSOLUTE MAXIMUM RATINGS CONNECTION DIAGRAMS VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16V IVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25mA LINE, RAMP . . . . . . . . . . . . . . . . . . . . . . . . −0.3V to VDD + 1V ILINE, IRAMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3V IDELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −5mA IOUT1 (tpw < 1µs and Duty Cycle < 10%) . . . . . . . −0.6A to 1.2A IOUT2 (tpw < 1µs and Duty Cycle < 10%) . . . . . . . −0.4A to 0.4A ICLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −100mA to 100mA OSC1, OSC2, SS, SHTDWN, EAIN . . . . . −0.3V to REF + 0.3V IEAOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −5mA to 5mA IREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −30mA PGND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.2V to 0.2V Storage Temperature . . . . . . . . . . . . . . . . . . . −65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . −55°C to +150°C Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . . +300°C DIL-16, SOIC-16 (Top View) J, N, or D Packages All voltages are with respect to ground unless otherwise stated. Currents are positive into, negative out of the specified terminal. Consult Packaging Section of Databook for thermal limitations and considerations of packages. PLCC-20 (Top View) Q Packages ORDER INFORMATION 2 UCC1580-1,-2,-3,-4 UCC2580-1,-2,-3,-4 UCC3580-1,-2,-3,-4 ELECTRICAL CHARACTERISTICS Unless otherwise stated, all specifications are over the full temperature range, VDD = 12V, R1 = 18.2k, R2 = 4.41k, CT = 100pF, R3 = 100k, COUT1 = 0, COUT2 = 0. TA = 0°C to 70°C for the UCC3580, −40°C to 85°C for the UCC2580, −55°C to 125°C for the UCC1580, TA = TJ. PARAMETER Oscillator Section Frequency CLK Pulse Width CLK VOH CLK VOL TEST CONDITIONS ICLK = −3mA ICLK = 3mA Ramp Generator Section Ramp VOL Flux Comparator Vth IRAMP = 100µA Pulse Width Modulator Section Minimum Duty Cycle Maximum Duty Cycle PWM Comparator Offset OUT1, EAOUT = VOL OUT1, EAIN = 2.6V Error Amplifier Section EAIN IEAIN EAOUT, VOL EAOUT, VOH AVOL Gain Bandwidth Product Softstart/Shutdown Section Start Duty Cycle SS VOL SS Restart Threshold ISS SHTDWN VTH ISHTDWN Undervoltage Lockout Section VDD On VDD Off LINE On LINE Off ILINE EAOUT = EAIN EAOUT = EAIN EAIN = 2.6V, IEAOUT = 100µA EAIN = 2.4V, IEAOUT = −100µA f = 100kHz (Note 1) MIN TYP 370 650 4.3 400 750 4.7 0.3 430 850 0.5 kHz ns V V 3.16 50 3.33 100 3.50 mV V 63 0.1 66 0.4 0 69 0.9 % % V 2.44 2.5 150 0.3 5 80 6 2.56 400 0.5 5.5 V nA V V dB MHz 4 70 2 EAIN = 2.4V ISS = 100µA 0 100 400 –20 0.5 50 350 550 –35 0.6 150 % mV mV µA V nA 14 8 7.5 4.7 4.2 15 9 8.5 5 4.5 50 16 10 9.5 5.3 4.8 150 V V V V V nA 14 15 160 2.5 16 250 3.5 V µA mA 0.4 0.4 0.4 0.4 20 40 20 1.0 1.0 1.0 1.0 50 80 50 V V V V ns ns ns 0.4 UCC3580-2,-4 UCC3580-1,-3 LINE = 6V Supply Section VDD Clamp IVDD Start IVDD Operating IVDD = 10mA VDD < VDD On No Load Output Drivers Section OUT1 VSAT High OUT1 VSAT Low OUT2 VSAT High OUT2 VSAT Low OUT1 Fall Time OUT1 Rise Time OUT2 Fall Time IOUT1 = −50mA IOUT1 =100mA IOUT2 = −30mA IOUT2 = 30mA COUT1 = 1nF, RS = 3Ω COUT1 = 1nF, RS = 3Ω COUT2 = 300pF, RS = 10Ω 3 MAX UNITS UCC1580-1,-2,-3,-4 UCC2580-1,-2,-3,-4 UCC3580-1,-2,-3,-4 ELECTRICAL CHARACTERISTICS Unless otherwise stated, all specifications are over the full temperature range, VDD = 12V, R1 = 18.2k, R2 = 4.41k, CT = 100pF, R3 = 100k, COUT1 = 0, COUT2 = 0. TA = 0°C to 70°C for the UCC3580, −40°C to 85°C for the UCC2580, −55°C to 125°C for the UCC1580, TA = TJ. PARAMETER Output Drivers Section (cont.) OUT2 Rise Time Delay 1 OUT2 to OUT1 Delay 2 OUT1 to OUT2 Reference Section REF Load Regulation Line Regulation TEST CONDITIONS MIN TYP COUT2 = 300pF, RS = 10Ω R3 = 100k, COUT1 = COUT2 = 15pF TA = TJ = 25°C R3 = 100k, COUT1 = COUT2 = 15pF TA = TJ = 25°C 90 100 110 140 20 120 120 170 170 40 160 140 250 200 ns ns ns ns ns 5 1 1 5.125 20 20 V mV mV IREF = 0 IREF = 0mA to 1mA VDD = 10V to 14V 4.875 MAX UNITS Note 1: Guaranteed by design. Not 100% tested in production. PIN DESCRIPTIONS CLK: Oscillator clock output pin from a low impedance CMOS driver. CLK is high during guaranteed off time. CLK can be used to synchronized up to five other UCC3580 PWMs. Maximum Duty Cycle = Maximum Duty Cycle for OUT1 will be slightly less due to Delay1 which is programmed by R3. DELAY: A resistor from DELAY to GND programs the nonoverlap delay between OUT1 and OUT2. The delay times, Delay1 and Delay2, are shown in Figure 1 and are as follows: OUT1: Gate drive output for the main switch capable of sourcing up to 0.5A and sinking 1A. OUT2: Gate drive output for the auxiliary switch with ± 0.3A drive current capability. Delay 1 = 11 . pF • R 3 PGND: Ground connection for the gate drivers. Connect PGND to GND at a single point so that no high frequency components of the output switching currents are in the ground plane on the circuit board. Delay2 is designed to be larger than Delay1 by a ratio shown in Figure 2. EAIN: Inverting input to the error amplifier. The noninverting input of the error amplifier is internally set to 2.5V. EAIN is used for feedback and loop compensation. RAMP: A resistor (R4) from RAMP to the input voltage and a capacitor (CR) from RAMP to GND programs the feedforward ramp signal. RAMP is discharged to GND when CLK is high and allowed to charge when CLK is low. RAMP is the line feedforward sawtooth signal for the PWM comparator. Assuming the input voltage is much greater than 3.3V, the ramp is very linear. A flux comparator compares the ramp signal to 3.3V to limit the maximum allowable volt-second product: EAOUT: Output of the error amplifier and input to the PWM comparator. Loop compensation components connect from EAOUT to EAIN. GND: Signal Ground. LINE: Hysteretic comparator input. Thresholds are 5.0V and 4.5V. Used to sense input line voltage and turn off OUT1 when the line is low. Volt-Second Product Clamp = 3.3 • R4 • CR. OSC1 & OSC2: Oscillator programming pins. A resistor connects each pin to a timing capacitor. The resistor connected to OSC1 sets maximum on time. The resistor connected to OSC2 controls guaranteed off time. The combined total sets frequency with the timing capacitor. Frequency and maximum duty cycle are approximately given by: Frequency = R1 R1 + 1.25 • R2 REF: Precision 5.0V reference pin. REF can supply up to 5mA to external circuits. REF is off until VDD exceeds 9V (–1 and –3 versions) or activates the 15V clamp (–2 and –4 versions) and turns off again when VDD droops below 8.5V. Bypass REF to GND with a 1µF capacitor. SHTDWN: Comparator input to stop the chip. The threshold is 0.5V. When the chip is stopped, OUT1 is low and OUT2 continues to oscillate with guaranteed off time equal to two non-overlap delay times. 1 (R1 + 1.25 • R2) • CT 4 UCC1580-1,-2,-3,-4 UCC2580-1,-2,-3,-4 UCC3580-1,-2,-3,-4 PIN DESCRIPTIONS (cont.) 9V to start and remain above 8.5V to continue running. A shunt clamp from VDD to GND limits the supply voltage to 15V. The –2 and –4 versions do not start until the shunt clamp threshold is reached and operation continues as long as VDD is greater than 8.5V. SS: A capacitor from SS to ground programs the soft start time. During soft start, EAOUT follows the amplitude of SS’s slowly increasing waveform until regulation is achieved. VDD: Chip power supply pin. VDD should be bypassed to PGND. The –1 and –3 versions require VDD to exceed APPLICATION INFORMATION UDG-95070-2 Note: Waveforms are not to scale. Figure 1. Output time relationships. this clamp must be activated as an indication of reaching the UVLO on threshold. The internal reference (REF) is brought up when the UVLO on threshold is crossed. The startup logic ensures that LINE and REF are above and SHTDWN is below their respective thresholds before outputs are asserted. LINE input is useful for monitoring actual input voltage and shutting off the IC if it falls below a programmed value. A resistive divider should be used to connect the input voltage to the LINE input. This feature can protect the power supply from excessive currents at low line voltages. UVLO and Startup For self biased off-line applications, -2 and -4 versions (UVLO on and off thresholds of 15V and 8.5V typical) are recommended. For all other applications, -1 and -3 versions provide the lower on threshold of 9V. The IC requires a low startup current of only 160µA when VDD is under the UVLO threshold, enabling use of a large trickle charge resistor (with corresponding low power dissipation) from the input voltage. VDD has an internal clamp at 15V which can sink up to 10mA. Measures should be taken not to exceed this current. For -2 and -4 versions, 5 UCC1580-1,-2,-3,-4 UCC2580-1,-2,-3,-4 UCC3580-1,-2,-3,-4 APPLICATION INFORMATION (cont.) The soft start pin provides an effective means to start the IC in a controlled manner. An internal current of 20µA begins charging a capacitor connected to SS once the startup conditions listed above have been met. The voltage on SS effectively controls maximum duty cycle on OUT1 during the charging period. OUT2 is also controlled during this period (see Figure 1). Negation of any of the startup conditions causes SS to be immediately discharged. Internal circuitry ensures full discharge of SS (to 0.3V) before allowing charging to begin again, provided all the startup conditions are again met. Delay Times 1400 1.80 Delay Ratio 1200 1.70 1.60 Delay [ns] Delay2 800 1.50 600 1.40 Delay1 400 Delay2/Delay1 Ratio 1000 1.30 Oscillator 200 1.20 0 0 100 200 300 400 500 600 700 800 900 Simplified oscillator block diagram and waveforms are shown in Figure 3. OSC1 and OSC2 pins are used to program the frequency and maximum duty cycle. Capacitor CT is alternately charged through R1 and discharged through R2 between levels of 1V and 3.5V. The charging and discharging equations for CT are given by 1.10 1000 R3 ProgrammingResistor [kΩ] Figure 2. Delay times. VC(charge) = REF – 4.0 • e VC(discharge) = 3.5 • e - t t τ1 τ2 where τ1 = R1 • CT and τ2 = R2 • CT. The charge time and discharge time are given by tCH = R1 • CT and tDIS = 1.25 • R2 • CT The CLK output is high during the discharge period. It blanks the output to limit the maximum duty cycle of OUT1. The frequency and maximum duty cycle are given by Frequency = 1 (R1 +1.25 • R2) • CT Maximum Duty Cycle = R1 R1 +1.25 • R2 Maximum Duty Cycle for OUT1 will be slightly less due to Delay1 which is programmed by R3. Voltage Feedforward and Volt-Second Clamp UCC3580 has a provision for input voltage feedforward. As shown in Figure 3, the ramp slope is made proportional to input line voltage by converting it into a charging current for CR. This provides a first order cancellation of the effects of line voltage changes on converter performance. The maximum volt-second clamp is provided to protect against transient saturation of the transformer core. It terminates the OUT1 pulse when the RAMP voltage exceeds 3.3V. If the feedforward feature is not used, the ramp can be generated by tying R4 to REF. However, the linearity of ramp suffers and in this case the maximum volt-second clamp is no longer available. UDG-96016-1 Figure 3. Oscillator and ramp circuits. 6 UCC1580-1,-2,-3,-4 UCC2580-1,-2,-3,-4 UCC3580-1,-2,-3,-4 APPLICATION INFORMATION (cont.) single pin is used to program the delays between OUT1 and OUT2 on both sets of edges. Figure 1 shows the relationships between the outputs. Figure 2 gives the ratio between the two delays. During the transition from main to auxiliary switch, the delay is not very critical for ZVS turn-on. For the first half of OUT1 off-time, the body diode of the auxiliary switch conducts and OUT2 can be turned on any time. The transition from auxiliary to main switch is more critical. Energy stored in the parasitic inductance(s) at the end of the OUT2 pulse is used to discharge the parasitic capacitance across the main switch during the delay time. The delay (Delay 1) should be optimally programmed at 1/4 the resonant period determined by parasitic capacitance and the resonant inductor (transformer leakage and/or magnetizing inductances, depending on the topology). However, depending on other circuit parasitics, the resonant behavior can change, and in some cases, ZVS turn-on may not be obtainable. It can be shown that the optimum delay time is independent of operating conditions for a specific circuit and should be determined specifically for each circuit. Output Configurations The UCC3580 family of ICs is designed to provide control functions for single ended active clamp circuits. For different implementations of the active clamp approach, different drive waveforms for the two switches (main and auxiliary) are required. The -3 and -4 versions of the IC supply complementary non-overlapping waveforms (OUT1 and OUT2) with programmable delay which can be used to drive the main and auxiliary switches. Most active clamp configurations will require one of these outputs to be transformer coupled to drive a floating switch (e.g. Figure 5). The -1 and -2 versions have the phase of OUT2 inverted to give overlapping waveforms. This configuration is suitable for capacity coupled driving of a ground referenced p-channel auxiliary switch with the OUT2 drive while OUT1 is directly driving an n-channel main switch (e.g. Figure 4). The programmable delay can be judiciously used to get zero voltage turn-on of both the main and auxiliary switches in the active clamp circuits. For the UCC3580, a UDG-95071-2 Figure 4. Active clamp forward converter. 7 UCC1580-1,-2,-3,-4 UCC2580-1,-2,-3,-4 UCC3580-1,-2,-3,-4 APPLICATION INFORMATION (cont.) UDG-96017-1 Figure 5. Off-line active clamp flyback converter. The use of active reset in a flyback power converter topology may be covered by U.S. Patent No. 5,402,329 owned by Technical Witts, Inc., and for which Unitrode offers users a paid up license for application of the UCC1580 product family. 8 UCC1580-1,-2,-3,-4 UCC2580-1,-2,-3,-4 UCC3580-1,-2,-3,-4 APPLICATION INFORMATION (cont.) UDG-96018-1 Figure 6. UCC3580 used in a synchronous rectifier application. UNITRODE CORPORATION 7 CONTINENTAL BLVD. • MERRIMACK, NH 03054 TEL. (603) 424-2410 FAX (603) 424-3460 9 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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