SLUS311A – JULY 1999 – REVISED AUGUST 2000 D 5-Bit Digital-to-Analog Converter (DAC) D D D D D D D D D D D, J, N AND PW PACKAGES (TOP VIEW) supports Intel Pentium II Microprocessor VID Codes Compatible with 5-V or 12-V Systems 1% Output Voltage Accuracy Ensured Drives 2 N-Channel MOSFETs Programmable Frequency to 800 kHz Power Good OV / UV / OVP Voltage Monitor Undervoltage Lockout and Softstart Functions Short Circuit Protection Low Impedance MOSFET Drivers Chip Disable VSENSE ISNS SS/ENBL D0 D1 D2 D3 D4 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 RT VCC DRVLO DRVHI GND PWRGOOD VFB COMP AVAILABLE OPTIONS PACKAGED DEVICES TJ 0°C TO 70°C D, 16-PIN J, 16-PIN N, 16-PIN PW, 16-PIN UCC3588D UCC3588J UCC3588N UCC3588PW description The UCC3588 synchronous step-down (Buck) regulator provides accurate high efficiency power conversion. Using few external components, the UCC1588 converts 5V to an adjustable output ranging from 3.5 VDC to 2.1 VDC in 100-mV steps and 2.05 VDC to 1.3 VDC in 50-mV steps with 1% dc system accuracy. A high level of integration and novel design allow this 16-pin controller to provide a complete control solution for today’s demanding microcontroller power requirements. Typical applications include on board or VRM based power conversion for Intel Pentium II microprocessors, as well as other processors from a variety of manufacturers. High efficiency is obtained through the use of synchronous rectification. The softstart function provides a controlled ramp up of the system output voltage. Overcurrent circuitry detects a hard (or soft) short on the system output voltage and invokes a timed softstart/shutdown cycle to reduce the PWM controller on time to 5%. The oscillator frequency is externally programmed with RT and operates over a range of 50 kHz to 800 kHz. The gate drivers are low impedance totem pole output stages capable of driving large external MOSFETs. Cross conduction is eliminated by fixed delay times between turn off and turn on of the external high side and synchronous MOSFETs. The chip includes undervoltage lockout circuitry which assures the correct logic states at the outputs during power up and power down. This device is available in 16-pin surface mount, plastic and ceramic DIP, and TSSOP packages. The UCC3588 is specified for operation from 0°C to 70°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2000, Texas Instruments Incorporated ! "#$ ! %#&'" ( $) (#" ! " !%$"" ! %$ *$ $! $+! ! #$ ! ! (( , -) (#" %"$!!. ($! $"$!!'- "'#($ $! . '' %$ $!) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SLUS311A – JULY 1999 – REVISED AUGUST 2000 application diagram 12 V IN 5 V IN + C15 150 µF C16 10 µF R1 10 k R4 3Ω UCC3588 + + C1 D0 C2 + C3 15 VCC DRVHI 13 11 PWRGOODDRVLO 14 + C4 C1–C4 500 µF D1 D2 D3 D4 C5 33 nF 4 D0 ISNS 2 5 D1 VSENSE 1 6 D2 VFB 10 7 D3 COMP 9 8 D4 3 SS/ENBL RT 16 R5 3Ω Q1 IRL3103 L1 1.6 µH R6 0.003Ω C8–C12 1500 µF VOUT Q2 IRL3103 + C6 R3 200 k 220 pF C8 + C9 + + + C10 C11 C12 + C14 150 µF C7 22 pF GND D1 12 R7 15 k R2 47 k D2 R8 20 k C13 1 nF RTN RTN UDG-98158 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V Gate drive current, 50% duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 A Input voltage, VSENSE, VFB, SS, COMMAND, COMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 V Input voltage, D0, D1, D2, D3, D4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V Input current, RT, COMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ‡ Currents are positive into, negative out of the specified terminal. Consult Packaging Section of Databook for thermal limitations and considerations of packages. All voltages are referenced to GND. thermal data Plastic DIP package, thermal resistance junction to leads, Θjc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45°C/W thermal resistance junction to ambient, Θja . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90°C/W Ceramic DIP package, thermal resistance junction to leads, Θjc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28°C/W thermal resistance junction to ambient, Θja . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W Standard surface mount package, thermal resistance junction to leads, Θjc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35°C/W thermal resistance junction to ambient, Θja . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W NOTE The above numbers for Θja and Θjc are maximums for the limiting thermal resistance of the package in a standard mounting configuration. The Θja numbers are meant to be guidelines for the thermal performance of the device and PC board system. All of the above numbers assume no ambient airflow, see the packaging section of Unitrode Product Data Handbook for more details. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLUS311A – JULY 1999 – REVISED AUGUST 2000 electrical characteristics, TA = 0°C to 70°C. TA = TJ. VCC = 12 V, RT = 49 k, (unless otherwise stated) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Supply Current Section Supply current, on VCC = 12 V, VRT = 2 V 4.5 5.5 mA 10.05 10.50 10.85 350 450 550 mV –0.025 –0.050 mA UVLO Section VCC UVLO turnon threshold UVLO threshold hysteresis V Voltage Error Amplifier Section Input bias current Open loop gain Output voltage high Output voltage low Output source current Output sink current VCM = 2.0 V See Note 5 77 ICOMP = –500 mA ICOMP = 500 mA VVFB = 2 V, VVFB = 3 V, 3.5 dB 3.6 0.2 V 0.5 V VCOMMAND = VCOMP = 2.5 V –400 –500 mA VCOMMAND = VCOMP = 2.5 V 5 10 mA Oscillator/PWM Section Initial accuracy 0°C < TA < 70°C 250 270 290 kHz Ramp amplitude (p–p) 1.85 V Ramp valley voltage 0.65 V PWM max duty cycle COMP = 3 V See Note 5 100 % PWM min duty cycle COMP = 0. 3 V See Note 5 0 % PWM delay to outputs (high to low) COMP = 1.5 V See Note 5 150 ns PWM delay to outputs (low to high) COMP = 1.5 V See Note 5 150 ns Transient Window Comparator Section Detection range high (duty cycle = 0) % Over VCOMMAND, See Note 1 3 % Detection range low (duty cycle = 1) % Under VCOMMAND, See Note 1 –3 % Propagation delay (VSENSE to outputs) 150 200 nS –12 mA Soft Start/ Shutdown Section SS charge current (normal start-up) Measured on SS –6 SS charge current (short circuit fault condition) Measured on SS –60 –100 –120 mA SS discharge current (during timeout sequence) Measured on SS 1 2.5 5 mA Shutdown threshold Measured on SS 4.1 4.2 4.3 V Restart threshold Measured on SS 0.4 0.5 0.6 V Soft start complete threshold (normal start– up) Measured on SS 3.5 3.7 3.9 V NOTES: 1. This percentage is measured with respect to the ideal command voltage programmed by the VID (D0,....,D4) pins and applies to all DAC codes from 1.3 V to 3.5 V. 2. Reference and error amplifier offset trimmed while the voltage amplifier is set in unity gain mode. 3. Deadtime delay is measured from the 50% point of DRVHI falling to the 50% point of DRVLO rising, and vice-verse. 4. This time is dependent on the value of CSS. 5. Ensured by design. Not 100% production tested. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SLUS311A – JULY 1999 – REVISED AUGUST 2000 electrical characteristics, TA = 0°C to 70°C. TA = TJ. VCC = 12 V, RT = 49 k, (unless otherwise stated) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS DAC / Reference Section COMMAND voltage accuracy 10.8 V < VCC < 13.2 V, 0°C < TA < 70°C, measured on COMP, See Note 2 –1.0 1.0 % D0 to D4 voltage high 5.5 6 6.5 V D0 to D4 voltage threshold 2.5 3.0 3.5 V –80 –100 D0 to D4 voltage input bias current V(D4,...,D0) < 0.5 V mA Overvoltage Comparator Section Trip point % Over VCOMMAND, See Note 1 Hysteresis 8 10 20 12 % 35 mV Undervoltage Comparator Section Trip point % Under VCOMMAND, See Note 1 Hysteresis –8.0 10 –12.0 20 % 35 mV 470 W 20 % PWRGOOD Signal Section Output impedance VCC = 12 V, IPWRGOOD = 1 mA Overvoltage Protection Section Trip point % Over VCOMMAND, See Note 1 15 17.5 20 35 mV –8 –12 –16 mA 10.8 11.5 Hysteresis VSENSE input bias current OV, OVP, UV combined Gate Drivers (DRVHI, DRVLO) Section Output high voltage Output low voltage IGATE = 100 mA, VCC = 12 V IGATE =–100 mA, VCC = 12 V V 0.5 0.8 V Driver non-overlap time (DRVHI– to DRVLO+) See Note 3 90 120 150 ns Driver non-overlap time (DRVLO– to DRVHI+) See Note 3 50 80 120 ns Driver rise time 3 nF capacitive load 80 100 ns Driver fall time 3 nF capacitive load 80 100 ns Start of quick charge to shutdown threshold VISNS = VSENSE + 75 mV, CSS = 10 nF, See Note 4, See Note 5 50 Current limit threshold voltage VTHRESHOLD = VISNS – VVSENSE Current Limit Section ISNS input bias current ms 40 54 70 mV –8 –12 –16 mA NOTES: 6. This percentage is measured with respect to the ideal command voltage programmed by the VID (D0,....,D4) pins and applies to all DAC codes from 1.3 V to 3.5 V. 7. Reference and error amplifier offset trimmed while the voltage amplifier is set in unity gain mode. 8. Deadtime delay is measured from the 50% point of DRVHI falling to the 50% point of DRVLO rising, and vice-verse. 9. This time is dependent on the value of CSS. 10. Ensured by design. Not 100% production tested. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLUS311A – JULY 1999 – REVISED AUGUST 2000 block diagram COMP 9 VOLTAGE AMPLIFIER – + VFB 10 D4 7 D2 6 D1 5 D0 4 SS/ENBL 3 S R COMMAND 8 D3 PWM COMP. Q TURN ON DELAY OV/UV DAC 14 DRVLO SHUTDOWN ANTI CROSS– CONDUCTION OVP TURN ON DELAY SHUTDOWN 13 DRVHI SHUTDOWN COMMAND DUTY=1 –3% SOFTSTART TO VREF VSENSE DUTY=0 OVER– CURRENT OSC VBIAS CURRENT LIMIT BLOCK COMMAND +3% VCC – + + 2 1 ISNS VSENSE 11 UVLO + 10.5 V – 15 VCC VREF 12 GND 16 UDG-98152 PWRGOOD RT pin assignments COMP: (Voltage Amplifier Output) The system voltage compensation network is applied between COMP and VFB. D0, D1, D2, D3, D4: These are the digital input control codes for the DAC. The DAC is comprised of two ranges set by D4, with D0 representing the least significant bit (LSB) and D3, the most significant bit (MSB). A bit is set low by being connected the pin to GND; a bit is set high by floating the pin. Each control pin is pulled up to approximately 6 V by an internal pull-up. If one of the low voltage codes is commanded on the DAC inputs, the outputs will be disabled. The outputs will also be disabled for all 1’s, the NO CPU command. DRVHI: (PWM Output, MOSFET Driver) This output provides a low Impedance totem-pole driver. Use a series resistor between this pin and the gate of the external MOSFET to prevent excessive overshoot. Minimize circuit trace length to prevent DRVHI from ringing below GND. DRVHI is disabled during UVLO conditions. DRVHI has a typical output impedance of 5 Ω for a VCC voltage of 12 V. DRVLO: (synchronous rectifier output, MOSFET driver) This output provides a low Impedance totem-pole driver to drive the low-side synchronous external MOSFET. Use a series resistor between this pin and the gate of the external MOSFET to prevent excessive overshoot. Minimize circuit trace length to prevent DRVLO from ringing below GND. DRVLO is disabled during UVLO conditions. DRVLO has a typical output impedance of 5 Ω for a VCC voltage of 12 V. GND: (Ground) All voltages measured with respect to ground. VCC should be bypassed directly to GND with a 0.1-µF or larger ceramic capacitor. The timing capacitor discharge current also returns to this pin, so the lead from the oscillator timing to GND should be as short and direct as possible. ISNS: (Current Limit Sense Input) A resistance connected between this sense connection and VSENSE sets up the current limit threshold (54-mV typical voltage threshold). PWRGOOD: This pin is an open drain output which is driven low to reset the microprocessor when VSNS rises above or falls below its nominal value by 8.5%(typ). The on resistance of the open-drain switch is no higher than 470 Ω. This output should be pulled up to a logic level voltage and should be programmed to sink 1 mA or less. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SLUS311A – JULY 1999 – REVISED AUGUST 2000 pin assignments (continued) RT: (Oscillator Charging Current) This pin is a low impedance voltage source set at ~1.25 V. A resistor from RT to GND is used to program the internal PWM oscillator frequency. The equation for RT follows: ǒ Ǔ 1 * 800 67.2 pF) R + T (f (1) SS/ENBL: (Soft Start/Shut Down) A low leakage capacitor connected between SS and GND will provide a softstart function for the converter. The voltage on this capacitor will slowly charge on start-up via an internal current source (10 mA typ.) and ultimately clamp at approximately 3.7 V. The output of the voltage error amplifier (COMP) tracks this voltage thereby limiting the controller duty ratio. If a short circuit is detected, the clamp is released and the cap on SS charges with a 100 mA (typ) current source. If the SS voltage exceeds 4.2 V, the converter shuts down, and the 100-mA current source is switched off. The SS cap will then be discharged with a 2.5-mA (typ) current sink. When the voltage on SS falls below 0.5 V, a new SS cycle is started. The equation for softstart time follows: T SS ǒ Ǔ + 3.7 C SS 10 mA (2) Shutdown is accomplished by pulling SS/SD below 0.5 V. VCC: (Positive Supply Voltage) This pin is normally connected to a 12-V ±10% system voltage. The UCC1588 will commence normal operation when the voltage on VCC exceeds 10.5 V (typ). Bypass VCC directly to GND with a 0.1-µF (minimum) ceramic capacitor to supply current spikes required to charge external MOSFET gate capacitances. VFB: (Voltage Amplifier Inverting Input) This is normally connected to a compensation network and to the power converter output through a divider network. VSENSE: (Direct Output Voltage Connection) This pin is a direct kelvin connection to the output voltage used for over voltage, under voltage, and current sensing. APPLICATION INFORMATION Figure 1 shows a synchronous regulator using the UCC3588. It accepts 5 V and 12 V as input, and delivers a regulated dc output voltage. The value of the output voltage is programmable via a 5-bit DAC code to a value between 1.3 V and 3.5 V. The example given here is for a 12-A regulator, running from a 10% tolerance source, and operating at 300 kHz. The design of the power stage is straightforward buck regulator design. Assuming an output noise requirement of 50 mV, and an output ripple current of 20% of full load, the value of the output inductor should be calculated at the highest input voltage and lowest output voltage that the regulator is likely to see. This insures that the ripple current will decrease as the input voltage and output voltage differential decreases. The minimum duty cycle, dmin, should also be calculated under this condition. 1) The current sense resistor is chosen to allow current limit to occur at 1.4 times the full load current. R6 + 6 V ǒ1.4 TRIP I OUT Ǔ + 50 mV + 3 mW 16.8 A (3) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLUS311A – JULY 1999 – REVISED AUGUST 2000 APPLICATION INFORMATION 2) To properly approximate the full load duty cycle operating range, assumptions are made regarding the MOSFETs’ RDS(on), and the output inductor’s dc resistance. Q1 and Q2 are IRF3103s, each with an RDS(on) of 0.014 Ω. The output inductor is allowed to dissipate one watt under full load, giving a dc resistance of 6.9 mW, and R6 is 3 mΩ. The resulting duty cycle at the operating extremes is then: V d MIN + MIN + )I ǒR6 ) RDS on ) RȏǓ ǒ OUT V V d OUTǒIOǓ OUTǒHIǓ )I Ǔ INǒHIǓ ǒ V 1.8 ) (12 0.024) + 0.379 5.5 (4) ǒR6 ) RDS on ) RȏǓ OUT + Ǔ INǒLOǓ + 3.5 ) (12 0.024) + 0.842 4.5 (5) 3) The value of the output inductor is chosen at the worst case ripple current point. L+ ǒ V INǒHIǓ *V DV OUTǒLOǓ Ǔ + (5.5 * 1.8) OUT 0.379 2.4 3.333 m + 1.9 mH (6) Four turns of #16 on a micrometals T51-52C core has an inductance of 1.9 µH, has a dc resistance of 6.6 mΩ, and will dissipate about 1 W under full load conditions. With an output inductor value of 1.9 µH, the ripple current will be 1750 mA under the low-input-high-output condition. 4) To meet the output noise voltage requirement, the output capacitor(s) must be chosen so that the ripple voltage induced across the ESR of the capacitors by the output ripple current is less than 50 mV. ESR t 50 mV + 42 mW DI OUT (7) Additionally, to meet output load transient response requirements, the capacitors’ ESL and ESR must be low enough to avoid excessive voltage transient spikes. (See Application Note U-157 for a discussion of how to determine the amount and type of load capacitance.) For this example, four Sanyo MV-GX 1500-µF, 6.3-V capacitors will be used. The ESR of each capacitor is approximately 44 mΩ so the parallel combination of four results in an equivalent ESR of 11 mΩ. 5) Q1 and Q2 are chosen to be IRF3103 N-Channel MOSFETs. Each MOSFET has an RDS(on) of approximately 0.014 Ω, a gate charge requirement of 50 nC, and a turn-off time of approximately 54 ns. To calculate the losses in the upper MOSFET, Q1, first calculate the RMS current it will be conducting. ǒ I Q1 Ǔ+ RMS Ǹ DI ȡ OUT 2ȣ ) ȧ 2 12 ȧ Ȣ OUT Ȥ d I (8) Notice that with a higher output voltage, the duty cycle increases, and therefore so does the RMS current. Any heat sink design should take into account the worst case power dissipation the device will experience. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SLUS311A – JULY 1999 – REVISED AUGUST 2000 APPLICATION INFORMATION With the highest programmable output voltage of 3.5 V and the lowest possible input voltage of 4.5 V, the RMS current Q1 will conduct is 10.5 A, and the conduction loss is: P Q1 + CON ǒ I Q1 Ǔ 2 R RMS + 1.5 W DSǒonǓ (9) Next, the gate drive losses are found. P Q1 + Q CON G f + 0.08 W S (10) And the turn-off losses are estimated as P ǒ Q1 + 1 V ǒ Ǔ T OFFǓ 2 IN HI I ǒ Ǔ D PK tf F + 0.56 W S (11) The total loss in Q1is the sum of the three components, or about 2.1 W. The gate drive losses in Q2 will be the same as in Q1, but the turn-off losses will be associated with the reverse recovery of the body diode, instead of the turn-off of the channel. This is due to the UCC3588’s delay built into the switching of the upper and lower MOSFET’s drive. For example, when Q1 is turned-off, the turn-on of Q2 is delayed for about 100 ns, insuring that the circuit has time to commutate and that current has begun to flow in the body diode of Q2. When Q2 is turned-off, current is diverted from the channel of Q2 into the body diode of Q2, resulting in virtually no power dissipation. When Q1 is turned ON 100ns later however, the circuit is forced to commutate again. This time causing reverse recovery loss in the body diode of Q2 as its polarity is reversed. The loss in the diode is expressed as: P Q2 + 1 RR 2 Q V RR INǒHIǓ F + 0.26 W S (12) Where QRR, the reverse recovery of the body diode, is 310 nC. 100 ns before the turn-on of Q2, and 100 ns after the turn-off of Q2, current flows through Q2’s intrinsic body diode. The power dissipation during this interval is: P COM Q2 DIODE +I OUT V 200 ns + 12 3.33 ms DIODE 1.4 0.06 + 1 W (13) During the ON period of Q2, current flows through the RDS(on) of the device. Where the highest RMS current in Q1 was at the low-input and high-output condition, the highest RMS current in Q2 is found when the input is at its highest, and the output is at its lowest. The equation for the RMS current in Q2 is: ǒ I Q2 P Ǔ RMS Ǹǒ Ǔ 1*d * 200 ns MIN 3.33 ms + ǒ Q2 + 1 Q2 CON RMS Ǔ 2 R DSǒonǓ ȡ 2 IOUT2ȣ ȧIOUT ) D 12 ȧ+ 8.7 A Ȣ Ȥ + 1.06 W The worst case loss in Q2 comes to about 2.4 W. 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 (14) (15) SLUS311A – JULY 1999 – REVISED AUGUST 2000 APPLICATION INFORMATION 6) Repeating the preceding procedure for various input and output voltage combinations yields a table of operating conditions. Table 1. Regulator Operating Conditions VIN= 4.5 5.0 5.5 VOUT = 3.5 Pd Q1 Pd Q2 Pd L Pd total Average input Duty cycle 2.20 1.50 0.95 5.10 10.5 0.84 2.10 1.60 0.95 5.20 9.50 0.76 2.00 1.80 0.95 5.40 8.70 0.69 VOUT = 1.8 Pd Q1 Pd Q2 Pd L Pd total Average input Duty cycle 1.5 2.3 0.95 5.2 6.00 0.46 1.40 2.40 0.95 5.30 5.40 0.42 1.40 2.50 0.95 5.40 4.96 0.38 7) Assuming the converter’s input current is dc, the remaining switching current drawn by Q1 must come from the input capacitors. The next step then, is to find the worst case RMS current the capacitors will experience. (Equation 16). Where IIN(avg) is the average input current. I CAP RMS + Ǹ 2 2 DI ȡ ȣ OUT ) (1 * d) ǒ Ǔ ) I * I ȧ OUT INǒavgǓ 12 ȧ Ȣ Ȥ d ǒIIN avg Ǔ ǒ 2 Ǔ (16) Repeating the above calculation over the operating range of the regulator (see Table 2.) reveals that the worst case capacitor ripple current is found at low input, and at low output voltage. A Sanyo MV-GX, 1500-µF, 6.3-V capacitor is rated to handle 1.25 A at 105°C. Derating the design to 70°C allows the use of four capacitors, each one experiencing one fourth of the total ripple current. 8) The voltage feedback loop is next. The gain and frequency response of the PWM and LC filter is shown in Equation 17. K PWM (f) + V V IN + (17) RAMP 1 ) 2pf ǒ 1 * 4p 2 f2 LC OUT ǒ R ESR C OUT Ǔ ) ǒR6 ) Rȏ ) RESRǓ POST OFFICE BOX 655303 C OUT ) • DALLAS, TEXAS 75265 L R Ǔ LOAD 9 SLUS311A – JULY 1999 – REVISED AUGUST 2000 APPLICATION INFORMATION Table 2. Regulator Operating Conditions VIN= 4.5 5.0 5.5 VOUT=3.5 Total input cap RMS current Total input cap power dissipation Total power dissipation Power train efficiency 4.40 0.21 5.10 0.89 5.20 0.29 5.30 0.88 5.60 0.34 5.40 0.87 VOUT=1.8 Total input cap RMS current Total input cap power dissipation Total power dissipation Power train efficiency 6.00 0.39 5.20 0.81 5.90 0.39 5.30 0.80 5.80 0.37 5.40 0.80 GAIN vs FREQUENCY PHASE vs FREQUENCY 20 20 10 10 0 V IN 0 = 5.5 V Phase - C Gain - dB –10 –20 –30 –10 –20 –30 VIN = 4.5 V –40 –40 –50 –50 –60 0.1 1.0 10.0 100.0 1000.0 –60 0.1 Frequency - kHz 1.0 10.0 100.0 1000.0 Frequency - kHz Figure 1 Figure 2 To compensate the loop with as high a bandwidth as practical, additional gain is added to the loop with the voltage error amplifier. 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLUS311A – JULY 1999 – REVISED AUGUST 2000 APPLICATION INFORMATION C2 R2 C3 RF C1 RI V IN VREF + VOUT Figure 3. Voltage Error Amplifier Configuration The equation for the gain of the voltage amplifier in this configuration is: (1 ) s(C1Rf)) K EA + ǒ1 ) sǒC3ǒRI ) R2ǓǓǓ ǒ R s 2C1C2Rf ) s(C1 ) C2) I Ǔ (1 ) s(C3R2)) (18) For good transient response, select the RF-C1 zero at 5 kHz. Add additional phase margin by placing the RI-C3 zero also at 5 kHz. To roll off the gain at high frequency, selece the R2-C3 pole to be at 10 kHz, and the final C2-RF pole at 40 kHz. Results are RI = 20 k, RF = 200 k, R2 = 15 k, C1 = 220 pF, C2 = 20 pF, C3 = 1000 pF. The Gain - phase plots of the voltage error amplifier and the overall loop are plotted below. 9) The value of RT is given by: RT + ǒ 1 F S 67.2 pF Ǔ * 800 + 48 kW (19) 10) The value of the soft start capacitor is given by: C SS t SS V 3.7 + 10 m (20) Where tSS is the desired soft start time. To insure that soft start is long enough so that the converter does not enter current limit during startup, the minimum value of soft start may be determined by: C SS w ǒ C V R OUT LIM Ǔ SENSE I V CH V *I IN RAMP OUT (21) Where COUT is the output capacitance, Ich is the soft start charging current (10 mA typ), VLIM is the current limit trip voltage (54 mV typ), IOUT is the load current, VIN is the 5-V supply, and VRAMP is the internal oscillator ramp voltage (1.85 V typ). For this example, CSS must be greater than 35 nF, and the resulting soft start time will be 13 ms. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 SLUS311A – JULY 1999 – REVISED AUGUST 2000 APPLICATION INFORMATION 11) The output of the regulator is adjustable by programming the following codes into the D0 - D4 pins according to the table below. To program a logic zero, ground the pin. To program a logic 1, then leave the pin floating. Do not tie the pin to an external voltage source. 12) A series resistor should be placed in series with the gate of each MOSFET to prevent excessive ringing due to parasitic effects. A value of 3 Ω to 5 Ω is usually sufficient in most cases. Additionally, to prevent pins 13 and 14 from ringing more than 0.5-V below ground, a clamp schottky rectifier placed as close as possible to the IC is also recommended. GAIN vs FREQUENCY PHASE vs FREQUENCY 60 180 160 40 Error Amp 140 120 Phase - C Gain - dB 20 VIN = 5.5 V 0 VIN = 4.5 V 100 80 60 40 –20 20 –40 0.1 1 0 10 100 1000 0.1 Frequency - kHz 10 Frequency - kHz Figure 4 12 1 Figure 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 100 1000 SLUS311A – JULY 1999 – REVISED AUGUST 2000 APPLICATION INFORMATION Table 3. VID Codes and Resulting Regulator Output Voltage D4 D3 D2 D1 D0 0 1 1 1 1 VOUT 1.30 0 1 1 1 0 1.35 0 1 1 0 1 1.40 0 1 1 0 0 1.45 0 1 0 1 1 1.50 0 1 0 1 0 1.55 0 1 0 0 1 1.60 0 1 0 0 0 1.65 0 0 1 1 1 1.70 0 0 1 1 0 1.75 0 0 1 0 1 1.80 0 0 1 0 0 1.85 0 0 0 1 1 1.90 0 0 0 1 0 1.95 0 0 0 0 1 2.00 0 0 0 0 0 2.05 1 1 1 1 1 No outputs 1 1 1 1 0 2.10 1 1 1 0 1 2.20 1 1 1 0 0 2.30 1 1 0 1 1 2.40 1 1 0 1 0 2.50 1 1 0 0 1 2.60 1 1 0 0 0 2.70 1 0 1 1 1 2.80 1 0 1 1 0 2.90 1 0 1 0 1 3.00 1 0 1 0 0 3.10 1 0 0 1 1 3.20 1 0 0 1 0 3.30 1 0 0 0 1 3.40 1 0 0 0 0 3.50 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 SLUS311A – JULY 1999 – REVISED AUGUST 2000 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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