DATA SHEET MOS INTEGRATED CIRCUIT µPD17P709A 4-BIT SINGLE-CHIP MICROCONTROLLER WITH DEDICATED HARDWARE FOR DIGITAL TUNING SYSTEM DESCRIPTION The µPD17P709A is produced by replacing the on-chip mask ROM of the µPD17704A, 17705A, 17707A, 17708A, and 17709A with a one-time PROM. The µPD17P709A allows programs to be written once, so the µPD17P709A is suitable for preproduction in µPD17704A, 17705A, 17707A, 17708A, or 17709A system development or low-volume production. When reading this document, also refer to the publications on the µPD17704A, 17705A, 17707A, 17708A, or 17709A. The electrical characteristics (including power supply current) and PLL analog characteristics of the µPD17P709A differ from those of the µPD17704A, 17705A, 17707A, 17708A, and 17709A. In high-volume application set production, be sure to carefully check these differences. FEATURES • Compatible with the µPD17704A, 17705A, 17707A, 17708A, and 17709A • On-chip one-time PROM: 32 KB (16384 × 16 bits) • Supply voltage: VDD = 5 V ±10% ORDERING INFORMATION Part Number Package µPD17P709AGC-3B9 80-pin plastic QFP (14 × 14) The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. U15723EJ1V0DS00 (1st edition) Date Published October 2001 N CP(K) Printed in Japan © 2001 µPD17P709A FUNCTIONAL OUTLINE (1/2) Part Number µ PD17704A µ PD17705A µ PD17707A µ PD17708A µ PD17709A µ PD17P709A Program memory (ROM) 8192 × 16 bits (mask ROM) 12288 × 16 bits (mask ROM) General-purpose data memory (RAM) 672 × 4 bits Instruction execution time 1.78 µ s (with f X = 4.5 MHz crystal oscillator) General-purpose ports • I/O ports: • Input ports: Item • Output ports: 16384 × 16 bits (mask ROM) 1120 × 4 bits 16384 × 16 bits (one-time PROM) 1176 × 4 bits 46 12 4 Stack levels • Address stack: 15 levels • Interrupt stack: 4 levels • DBF stack: 4 levels (can be manipulated via software) Interrupts • External: 6 sources (falling edge of CE pin, INT0 to INT4) • Internal: 6 sources (timers 0 to 3, serial interfaces 0 and 1) Timer 5 • • • • channels Basic timer (clock: 10, 20, 50, 100 Hz): 8-bit timer with gate counter (clock: 1 k, 2 k, 10 k, 100 kHz): 8-bit timer (clock: 1 kHz, 2 kHz, 10 kHz, 100 kHz): 8-bit timer multiplexed with PWM (clock: 440 Hz, 4.4 kHz): 1 1 2 1 channel channel channels channel A/D converter 8 bits × 6 channels (hardware mode and software mode selectable) D/A converter (PWM) 3 channels (8-bit or 9-bit resolution selectable by software) Output frequency: 4.4 kHz, 440 Hz (with 8-bit PWM selected) 2.2 kHz, 220 Hz (with 9-bit PWM selected) Serial interface 2 units (3 channels) • 3-wire serial I/O: 2 channels • 2-wire serial I/O/I 2 C bus: 1 channel PLL Division mode • Direct division mode (VCOL pin (MF mode): • Pulse swallow mode (VCOL pin (HF mode): 0.5 to 3 MHz) 10 to 40 MHz) (VCOH pin (VHF mode): 60 to 130 MHz) 2 Reference frequency 13 types selectable (1, 1.25, 2.5, 3, 5, 6.25, 9, 10, 12.5, 18, 20, 25, 50 kHz) Charge pump Two error-out output pins (EO0, EO1) Phase comparator Unlock status detectable by program Intermediate frequency counter • Intermediate frequency (IF) measurement P1C0/FMIFC pin : 10 to 11 MHz in FMIF mode 0.4 to 0.5 MHz in AMIF mode P1C1/AMIFC pin: 0.4 to 0.5 MHz in AMIF mode • External gate width measurement P2A1/FCG1, P2A0/FCG0 pin BEEP output 2 pins Output frequency: 1 kHz, 3 kHz, 4 kHz, 6.7 kHz (BEEP0 pin) 67 Hz, 200 Hz, 3 kHz, 4 kHz (BEEP1 pin) Data Sheet U15723EJ1V0DS µPD17P709A (2/2) Part Number Item µ PD17704A µ PD17705A µ PD17707A µ PD17708A µ PD17709A µ PD17P709A Reset • Power-on reset (on power application) • Reset by RESET pin • Watchdog timer reset Can be set only once on power application: 65536 instructions, 131072 instructions, or no-use selectable • Stack pointer overflow/underflow reset Can be set only once on power application: interrupt stack or address stack selectable • CE reset (CE pin low → high level) CE reset delay timing can be set. • Power failure detection function Standby • Clock stop mode (STOP) • Halt mode (HALT) Supply voltage • PLL operation: VDD = 4.5 to 5.5 V • CPU operation: V DD = 3.5 to 5.5 V Package 80-pin plastic QFP (14 × 14) Data Sheet U15723EJ1V0DS 3 µPD17P709A PIN CONFIGURATION (TOP VIEW) 80-pin plastic QFP (14 × 14) µ PD17P709AGC-3B9 P0C1 P0C0 P0A3/SDA P0A2/SCL P0A1/SCK0 P0A0/SO0 P0B3/SI0 P0B2/SCK1 P0B1/SO1 P0B0/SI1 P2D2 P2D1 P2D0 REG GND0 XIN XOUT CE VDD0 RESET (1) Normal operation mode 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 INT2 1 60 P0C2 P1A3/INT4 2 59 P0C3 P1A2/INT3 3 58 P2C0 P1A1 4 57 P2C1 P1A0/TM0G 5 56 P2C2 P3A3 6 55 P2C3 P3A2 7 54 P3D0 P3A1 8 53 P3D1 P3A0 9 52 P3D2 P3B3 10 51 P3D3 P3B2 11 50 P3C0 P3B1 12 49 P3C1 P3B0 13 48 P3C2 P2A2 14 47 P3C3 P2A1/FCG1 15 46 P2B0 P2A0/FCG0 16 45 P2B1 P1B3 17 44 P2B2 P1B2/PWM2 18 43 P2B3 P1B1/PWM1 19 42 INT0 P1B0/PWM0 20 41 INT1 Data Sheet U15723EJ1V0DS P1D0/BEEP0 P1D2 P1D1/BEEP1 P1D3 TEST EO1 EO0 GND1 VCOL VCOH VDD1 P1C0/FMIFC P1C1/AMIFC P1C2/AD4 P1C3/AD5 P0D0/AD0 P0D1/AD1 P0D2/AD2 GND2 4 P0D3/AD3 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 µPD17P709A (L) Note REG GND0 (OPEN) CLK (L) VDD0 (H) (2) PROM programming mode 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 (L) (OPEN) 1 60 2 59 3 58 D0 4 57 D1 5 56 D2 6 55 D3 7 54 D4 8 53 D5 9 52 D6 10 51 D7 11 50 12 49 13 48 14 47 15 46 16 45 17 44 18 43 19 42 20 (L) (L) 41 (L) VPP (OPEN) GND1 (L) MD0 VDD1 MD1 MD2 MD3 (L) GND2 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Note Connect to the same potential as VDD . Caution The items in parentheses indicate the processing of pins not used in the PROM programming mode. L: Independently connect to GND via a resistor (470 Ω) H: Independently connect each pin to VDD via a resistor (470 Ω) OPEN: Leave open. Data Sheet U15723EJ1V0DS 5 µPD17P709A PIN NAMES AD0 to AD5: 6 A/D converter input P2B0 to P2B3: Port 2B AMIFC: AM frequency counter input P2C0 to P2C3: Port 2C BEEP0, BEEP1: BEEP output P2D0 to P2D2: Port 2D CE: Chip enable P3A0 to P3A3: Port 3A CLK: Address update clock input P3B0 to P3B3: Port 3B D0 to D7: Data I/O P3C0 to P3C3: Port 3C EO0, EO1: Error-out output P3D0 to P3D3: Port 3D FCG0, FGC1: Frequency counter gate input REG: CPU regulator FMIFC: FM frequency counter input RESET: Reset input GND0 to GND2: Ground 0 to 2 SCK0, SCK1: 3-wire serial clock I/O INT0 to INT4: External interrupt input SCL: 2-wire serial clock I/O MD0 to MD3: Operation mode selection SDA: 2-wire serial data I/O PWM0 to PWM2: D/A converter output SI0, SI1: 3-wire serial data input P0A0 to P0A3: Port 0A SO0, SO1: 3-wire serial data output P0B0 to P0B3: Port 0B TEST: Test input P0C0 to P0C3: Port 0C TM0G: Timer 0 gate input P0D0 to P0D3: Port 0D VCOH: Local oscillation high input P1A0 to P1A3: Port 1A VCOL: Local oscillation low input P1B0 to P1B3: Port 1B V DD0, V DD1: Power supply P1C0 to P1C3: Port 1C V PP: Program voltage application P1D0 to P1D3: Port 1D X IN, X OUT: Main clock oscillation P2A0 to P2A2: Port 2A Data Sheet U15723EJ1V0DS µPD17P709A BLOCK DIAGRAM P0A0 to P0A3 4 P0B0 to P0B3 4 P0C0 to P0C3 4 P0D0 to P0D3 4 P1A0 to P1A3 4 VCOH PLL SO0/P0A0 RAM 1776 × 4 bits SCK0/P0A1 Serial interface 0 SYSREG 4 P1C0 (MD0) to P1C3 (MD3) 4 P1D0 to P1D3 4 EO0 EO1 RF P1B0 to P1B3 VCOL SCL/P0A2 SDA/P0A3 SI0/P0B3 SCK1/P0B2 Ports P2A0 to P2A2 3 P2B0 to P2B3 4 P2C0 (D0) to P2C3 (D3) 4 P2D0 to P2D2 3 Serial interface 1 SO1/P0B1 SI1/P0B0 ALU BEEP BEEP0/P1D0 BEEP1/P1D1 P3A0 to P3A3 4 P3B0 to P3B3 4 P3C0 to P3C3 4 P3D0 (D4) to P3D3 (D7) 4 Instruction decoder INT0 INT1 Interrupt control INT2 INT3/P1A2 INT4/P1A3 One-time PROM 16384 × 16 bits FCG0/P2A0 Frequency counter FCG1/P2A1 FMIFC/P1C0 AMIFC/P1C1 AD0/P0D0 AD1/P0D1 AD2/P0D2 AD3/P0D3 A/D converter 8-bit timer 0 gate counter Program counter TM0G/P1A0 AD4/P1C2 AD5/P1C3 8-bit timer 1 Stack PWM0/P1B0 PWM1/P1B1 D/A converter 8-bit timer 2 PWM2/P1B2 8-bit timer 3 CPU Peripheral OSC XIN XOUT CE Basic timer Reset RESET VDD0, VDD1 GND0 to GND2 VCPU Remark Regulator REG Pins in parentheses are used in PROM programming mode. Data Sheet U15723EJ1V0DS 7 µPD17P709A CONTENTS 1. PIN FUNCTIONS .............................................................................................................................. 1.1 Pin Function List .................................................................................................................. 1.2 PROM Programming Mode ................................................................................................. 1.3 Equivalent Circuits of Pins ................................................................................................. 1.4 Connections of Unused Pins .............................................................................................. 1.5 Cautions on Using CE, INT0 to INT4, and RESET Pins (Only in Normal Operation Mode) ...................................................................................... 1.6 Cautions on Using TEST Pin (Only in Normal Operation Mode) ..................................... 9 9 13 14 19 2. ONE-TIME PROM (PROGRAM MEMORY) WRITE, READ, AND VERIFY .................................... 2.1 Operation Modes for Program Memory Write, Read and Verify ...................................... 2.2 Program Memory Write Procedure .................................................................................... 2.3 Program Memory Read Procedure ..................................................................................... 22 23 24 25 21 21 3. ELECTRICAL SPECIFICATIONS ......................................................................................................... 26 4. PACKAGE DRAWING ..........................................................................................................................31 5. RECOMMENDED SOLDERING CONDITIONS ................................................................................... 32 APPENDIX DEVELOPMENT TOOLS ...................................................................................................... 33 8 Data Sheet U15723EJ1V0DS µPD17P709A 1. PIN FUNCTIONS 1.1 Pin Function List Pin No. Symbol Function Output Form 1 41 42 INT2 INT1 INT0 Edge-detectable vectored interrupt input pins. Rising or falling edge can be specified. – 2 3 4 5 P1A3/INT4 P1A2/INT3 P1A1 P1A0/TM0G Port 1A multiplexed with external interrupt request signal input and event signal input pins. • P1A3 to P1A0 • 4-bit input port • INT4, INT3 • Edge-detectable vectored interrupt • TM0G • Input for gate of 8-bit timer 0 – After reset 6 | 9 P3A3 | P3A0 Power-on reset WDT&SP reset Input (P1A3 to P1A0) Input (P1A3 to P1A0) With clock stopped CE reset Retained Retained 4-bit I/O port. Input or output can be specified in 4-bit units. After reset Power-on reset Input WDT&SP reset Input CMOS push-pull With clock stopped CE reset Retained Retained 10 P3B3 4-bit I/O port. CMOS | 13 | P3B0 Input or output can be specified in 4-bit units. push-pull After reset Power-on reset Input 14 15 16 P2A2 P2A1/FCG1 P2A0/FCG0 WDT&SP reset Input With clock stopped CE reset Retained Retained Port 2A multiplexed with external gate counter input pins. • P2A2 to P2A0 • 3-bit I/O port • Input or output can be specified in 1-bit units. • FCG1, FCG0 • Input for external gate counter After reset Power-on reset WDT&SP reset Input (P2A2 to P2A0) Input (P2A2 to P2A0) CMOS push-pull With clock stopped CE reset Retained (P2A2 to P2A0) Data Sheet U15723EJ1V0DS Retained (P2A2 to P2A0) 9 µPD17P709A Pin No. Symbol 17 18 | 20 P1B3 P1B2/PWM2 | P1B0/PWM0 Function Output Form Port 1B multiplexed with D/A converter output pins. • P1B3 to P1B0 • 4-bit output port • PWM2 to P2M0 • 8- or 9-bit D/A converter output After reset Power-on reset WDT&SP reset Outputs low level Outputs low level (P1B3 to P1B0) (P1B3 to P1B0) N-ch open-drain (12 V withstanding voltage) With clock stopped CE reset Retained Retained (P1B3 to P1B0) 21 33 75 GND2 GND1 GND0 Ground – 22 | 25 P0D3/AD3 | P0D0/AD0 Port 0D multiplexed with A/D converter input pins • P0D3 to P0D0 • 4-bit input port • Pull-down resistors can be connected in 1-bit units. • AD3 to AD0 • Analog input of A/D converter with 8-bit resolution – After reset 26 27 28 29 P1C3/AD5 P1C2/AD4 P1C1/AMIFC P1C0/FMIFC Power-on reset WDT&SP reset Input with pull-down resistor (P0D3 to P0D0) Input with pull-down resistor (P0D3 to P0D0) With clock stopped CE reset Retained Retained Port 1C multiplexed with A/D converter input and IF counter input pins. • P1C3 to P1C0 • 4-bit input port • AD5, AD4 • Analog input to A/D converter with 8-bit resolution • FMIFC, AMIFC • Input to frequency counter After reset 10 Power-on reset WDT&SP reset Input (P1C3 to P1C0) Input (P1C3 to P1C0) With clock stopped CE reset • P1C3/AD5, P1C2/AD4 Retained • P1C1/AMIFC, P1C0/FMIFC Input (P1C1, P1C0) Data Sheet U15723EJ1V0DS • P1C3/AD5, P1C2/AD4 Retained • P1C1/AMIFC, P1C0/FMIFC Input (P1C1, P1C0) – µPD17P709A Pin No. Symbol Function Output Form 30 79 V DD 1 V DD 0 Power supply. Supply the same voltage to these • With CPU and peripheral function operating: • With CPU operating: • With clock stopped: pins. 4.5 to 5.5 V 3.5 to 5.5 V 2.2 to 5.5 V 31 32 VCOH VCOL PLL local oscillation (VCO) frequency input. • VCOH • Active with VHF mode selected by program; otherwise, pulled down. • VCOL • Active with HF or MW mode selected by program; otherwise, pulled down. – – Because the input of these pins goes into an AC amplifier, cut the DC component of the input signal with a capacitor. 34 35 EO0 EO1 Output from charge pump of PLL frequency synthesizer. Outputs the divided frequency of local oscillation and the result of comparison of the phase difference of the reference frequency. After reset CMOS 3-state With clock stopped Power-on reset WDT&SP reset CE reset High-impedance output High-impedance output High-impendance output 36 TEST Test input pin. Be sure to connect this pin to GND. 37 38 39 40 P1D3 P1D2 P1D1/BEEP1 P1D0/BEEP0 Port 1D and BEEP output. • P1D3 to P1D0 • 4-bit I/O port • Input or output can be specified in 1-bit units. • BEEP1, BEEP0 High-impedance output – CMOS push-pull • BEEP output After reset Power-on reset 43 | 46 P2B3 | P2B0 Input Retained Retained (P1D3 to P1D0) (P1D3 to P1D0) (P1D3 to P1D0) (P1D3 to P1D0) 4-bit I/O port. Input or output can be specified in 1-bit units. After reset Input P3C3 | P3C0 CE reset Input Power-on reset 47 | 50 WDT&SP reset With clock stopped WDT&SP reset Input CMOS push-pull With clock stopped CE reset Retained Retained 4-bit I/O port. Input or output can be specified in 4-bit units. After reset Power-on reset Input WDT&SP reset Input CMOS push-pull With clock stopped CE reset Retained Data Sheet U15723EJ1V0DS Retained 11 µPD17P709A Pin No. 51 | 54 Symbol P3D3 | P3D0 Function 4-bit I/O port. Input or output can be specified in 4-bit units. Input P2C3 | P2C0 65 66 67 68 69 70 P0A1/SCK0 P0A0/SO0 P0B3/SI0 P0B2/SCK1 P0B1/SO1 P0B0/SI1 WDT&SP reset Input CE reset Retained P2D2 | P2D0 WDT&SP reset Input CMOS push-pull CE reset Retained Retained Ports P0A and P0B are multiplexed with I/O of serial interface. • P0A3 to P0A0 • 4-bit I/O port • Input or output can be specified in 1-bit units. • P0B3 to P0B0 • 4-bit I/O port • Input or output can be specified in 1-bit units. • SDA, SCL • Serial data and serial clock I/O of serial interface 0 in 2-wire serial I/O or I 2 C bus mode • SCK0, SO0, SI0 • Serial clock I/O, serial data output, and serial data input of serial interface 0 in 3-wire serial I/O mode • SCK1, SO1, SI1 • Serial clock I/O, serial data output, serial data input of serial interface 1 in 3-wire serial I/O mode WDT&SP reset CE reset Input P0A3 to P0A0, P0B3 to P0B0 Input P0A3 to P0A0, P0B3 to P0B0 Retained P0A3 to P0A0, P0B3 to P0B0 After reset Input Input CMOS push-pull Retained P0A3 to P0A0, P0B3 to P0B0 3-bit I/O port. Input or output can be specified in 1-bit units. WDT&SP reset N-ch open-drain With clock stopped Power-on reset Power-on reset 12 Retained With clock stopped After reset 71 | 73 CMOS push-pull With clock stopped After reset Input P0A3/DSA P0A2/SCL Retained 4-bit I/O port. Input or output can be specified in 4-bit units. Power-on reset 63 64 Retained After reset Input P0C3 | P0C0 Input CE reset 4-bit I/O port. Input or output can be specified in 4-bit units. Power-on reset 59 | 62 WDT&SP reset CMOS push-pull With clock stopped After reset Power-on reset 55 | 58 Output Form CMOS push-pull With clock stopped CE reset Retained Data Sheet U15723EJ1V0DS Retained µPD17P709A Pin No. Symbol Function Output Form 74 REG CPU regulator. Connect this pin to GND via 0.1 µ F capacitor. – 76 77 X OUT X IN Ground pins of crystal resonator. – 78 CE Device operation selection, CE reset, and interrupt signal input pin. • Device operation selection When CE is high, the PLL frequency synthesizer can operate. When CE is low, the PLL frequency synthesizer is automatically disabled internally. • CE reset When CE goes high, the device is reset at the rising edge of the internal basic timer setting pulse. This pin also has a reset timing delay function. • Interrupt – A vectored interrupt occurs at the falling edge of this pin. 80 RESET Reset input – 1.2 PROM Programming Mode Pin No. Symbol 26 | MD3 | 29 MD0 21 33 GND2 GND1 75 GND0 36 Function Output Form Input for operating mode selection for program memory write, read, or verify. – Ground – V PP Pin to which program voltage is applied during program memory write, read, or verify. +12.5 V is applied. – 30 V DD 1 Power supply pins. +6 V is applied during program memory write, read, or – 79 V DD 0 verify. 51 D7 8-bit data I/O for program memory write, read, or verify | 58 | D0 77 CLK Clock input for address updating during program memory write, read, or CMOS push-pull – verify Remark The pins other than those listed above are not used in PROM programming mode. For the handling of the unused pins, see PIN CONFIGURATION (2) PROM programming mode. Data Sheet U15723EJ1V0DS 13 µPD17P709A 1.3 Equivalent Circuits of Pins (1) P0A (P0A1/SCK0, P0A0/SO0) P0B (P0B3/SI0, P0B2/SCK1, P0B1/SO1, P0B0/SI1) P0C (P0C3, P0C2, P0C1, P0C0) P1D (P1D3, P1D2, P1D1/BEEP1, P1D0/BEEP0) P2A (P2A2, P2A1/FCG1, P2A0/FCG0) P2B (P2B3, P2B2, P2B1, P2B0) (I/O) P2C (P2C3, P2C2, P2C1, P2C0) P2D (P2D2, P2D1, P2D0) P3A (P3A3, P3A2, P3A1, P3A0) P3B (P3B3, P3B2, P3B1, P3B0) P3C (P3C3, P3C2, P3C1, P3C0) P3D (P3D3, P3D2, P3D1, P3D0) VDD CKSTOPNote VDD Note This is an internal signal that is output when the clock stop instruction is executed. Its circuit is designed not to increase the current consumption due to noise even if it is floated. 14 Data Sheet U15723EJ1V0DS µPD17P709A (2) P0A (P0A3/SDA, P0A2/SCL) (I/O) VDD CKSTOPNote Note This is an internal signal that is output when the clock stop instruction is executed. Its circuit is designed not to increase the current consumption due to noise even if it is floated. (3) P1B (P1B3, P1B2/PWM2, P1B1/PWM1, P1B0/PWM0) (output) (4) P0D (P0D3/AD3, P0D2/AD2, P0D1/AD1, P0D0/AD0) (input) A/D converter VDD CKSTOPNote P0DPLD flag High on-resistance Note This is an internal signal that is output when the clock stop instruction is executed. Its circuit is designed not to increase the current consumption due to noise even if it is floated. Data Sheet U15723EJ1V0DS 15 µPD17P709A (5) P1A (P1A1) (input) VDD (6) P1C (P1C3/AD5, P1C2/AD4) (input) VDD A/D converter (7) P1C (P1C1/AMIFC, P1C0/FMIFC) (input) VDD General-purpose port VDD High on-resistance VDD Frequency counter 16 Data Sheet U15723EJ1V0DS µPD17P709A (8) CE RESET INT0, INT1, INT2 (Schmitt-triggered input) P1A (P1A3/INT4, P1A2/INT3, P1A0/TM0G) VDD (9) X OUT (output), X IN (input) VDD High on-resistance VDD XIN Internal clock High onresistance XOUT (10) EO1, EO0 (output) VDD DWN UP Data Sheet U15723EJ1V0DS 17 µPD17P709A (11) VCOH, VCOL (input) VDD High on-resistance VDD High onresistance 18 Data Sheet U15723EJ1V0DS µPD17P709A 1.4 Connections of Unused Pins It is recommended to connect unused pins as follows. Table 1-1. Connections of Unused Pins (1/2) Pin Name Port pin P0D3/AD3 to P0D0/AD0 I/O Mode Recommended Connection Independently connect to GND via a resistorNote 1 . Input P1C3/AD5 P1C2/AD4 P1C1/AMIFC Note 2 Set to port mode and individually connect to V DD or GND P1C0/FMIFC Note 2 via a resistor Note 1 . P1A3/INT4 Independently connect to GND via a resistor Note 1 . P1A2/INT3 P1A1 P1A0/TM0G P1B3 N-ch open-drain P1B2/PWM2 to P1B0/PWM0 output P0A3/SDA I/O Note 3 P0A2/SCL Set to low-level output by software and leave open. Set to general-purpose input port mode by software and independently connect to V DD or GND via a resistor Note 1 . P0A1/SCK0 P0A0/SO0 P0B3/SI0 P0B2/SCK1 P0B1/SO1 P0B0/SI1 P0C3 to P0C0 P1D3 P1D2 P1D1/BEEP1 P1D0/BEEP0 P2A2 P2A1/FCG1 P2A0/FCG0 P2B3 to P2B0 P2C3 to P2C0 P2D2 to P2D0 Notes 1. If a pin is externally pulled up (connected to V DD via a resistor) or pulled down (connected to GND via a resistor) with a high resistance, the pin almost enters a high-impedance state, increasing the current (through-current) consumption of the port. Generally, the resistance of a pull-up or pulldown resistor is several 10 kΩ, although it depends on the application circuit. 2. Do not set these pins as AMIFC and FMIFC pins; otherwise, the current consumption will increase. 3. The I/O ports are set in the general-purpose input port mode at power-on reset, when reset by the RESET pin, or when reset by an overflow or underflow of the watchdog timer or the stack. Data Sheet U15723EJ1V0DS 19 µPD17P709A Table 1-1. Connections of Unused Pins (2/2) Pin Name Port pin P3A3 to P3A0 I/O Mode I/O Note 2 Recommended Connection Set in general-purpose input port mode by software and independently connect to V DD or GND via a resistor Note 1 . P3B3 to P3B0 P3C3 to P3C0 P3D3 to P3D0 Non-port pins CE Input Connect to V DD via a resistor Note 1. EO1 Output Leave open. INT0 to INT2 Input Independently connect to GND via a resistorNote 1 . RESET Input Connect to V DD via a resistor Note 1. EO0 TEST VCOH – Input Directly connect to GND. Disable PLL via software and leave open. VCOL Notes 1. If a pin is externally pulled up (connected to V DD via a resistor) or pulled down (connected to GND via a resistor) with a high resistance, the pin almost enters a high-impedance state, increasing the current (through-current) consumption of the port. Generally, the resistance of a pull-up or pulldown resistor is several 10 kΩ, although it depends on the application circuit. 2. The I/O ports are set in the general-purpose input port mode at power-on reset, when reset by the RESET pin, or when reset by an overflow or underflow of the watchdog timer or the stack. 20 Data Sheet U15723EJ1V0DS µPD17P709A 1.5 Cautions on Using CE, INT0 to INT4, and RESET Pins (Only in Normal Operation Mode) The CE, INT0 to INT4, and RESET pins have a function to set a test mode in which the internal operations of the µ PD17P709A are tested (IC test), in addition to the functions listed in 1.1 Pin Function List. When a voltage exceeding V DD is applied to any of these pins, the device is set in the test mode. If a noise exceeding V DD is superimposed during normal operation, therefore, the test mode is set by mistake, affecting the normal operation. Especially if the wiring length of pins is too long, noise is superimposed on these pins. In consequence, the above problem occurs. Therefore, keep the wiring length as short as possible to prevent noise from being superimposed. If superimposition of noise is unavoidable, connect an external component as illustrated below to suppress the noise. • Connect a diode with a low V F • Connect a capacitor between the pin and between the pin and V DD. V DD. VDD Diode with low VF VDD VDD VDD CE, INT0 to INT4, RESET CE, INT0 to INT4, RESET 1.6 Cautions on Using TEST Pin (Only in Normal Operation Mode) When V DD is applied to the TEST pin, the device is set in the test mode or program memory write/verify mode. Therefore, be sure to keep the wiring length of this pin as short as possible, and directly connect it to the GND pin. If the wiring length between the TEST pin and GND pin is too long, or if external noise is superimposed on the TEST pin, generating a potential difference between the TEST pin and GND pin, your program may not run normally. GND TEST Short Data Sheet U15723EJ1V0DS 21 µPD17P709A 2. ONE-TIME PROM (PROGRAM MEMORY) WRITE, READ, AND VERIFY The µ PD17P709A includes a 16,384 × 16-bit one-time PROM program memory. In normal operation, this PROM is accessed in 16-bit word units. During program memory write, read, and verify, the PROM is accessed in 8-bit word units. The higher 8 bits of a 16-bit word are located at an even-numbered address, and the lower 8 bits are located at an odd-numbered address. The pins used for the write, read, and verify operations of this one-time PROM are listed in Table 2-1. Clock input from the CLK pin, instead of address input, is used for updating addresses. Table 2-1. Pins Used for Program Memory Write, Read, and Verify Pin Name Function V PP Program voltage application (+12.5 V) CLK Address update clock input MD0 to MD3 Operation mode selection D0 to D7 8-bit data I/O V DD0, V DD1 Supply voltage application (+6 V) The specified PROM programmer and a dedicated programmer adapter are used for writing to the on-chip PROM. The following PROM programmers and programmer adapters are usable. PROM Programmer PG-1500 Programmer Adapter PA17P709GC + PA-17KDZ (adapter for PG-1500) Third-party PROM programmers are also available, such as the AF-9703, AF-9704, AF-9705, and AF-9706 (manufactured by Ando Electric Co., Ltd.) 22 Data Sheet U15723EJ1V0DS µPD17P709A Figure 2-1. PA-17P709GC and PA-17KDZ PA-17P709GC PA-17KDZ To PG-1500 2.1 Operation Modes for Program Memory Write, Read, and Verify When +6 V is applied to the VDD pin and +12.5 V to the VPP pin, the µPD17P709A enters the program memory write, read, and verify mode. The following operation modes can be set by setting pins MD0 to MD3 as shown below. Pins not listed in Table 2-2 should be connected to GND via a pull-down resistor (470 Ω) (refer to PIN CONFIGURATION (2) PROM programming mode). Table 2-2. Operation Mode Setting for Program Memory Write, Read, and Verify Operation Mode Setting VPP +12.5 V Remark Operation Mode VDD MD0 MD1 MD2 MD3 +6 V H L H L Program memory address 0-clear mode L H H H Write mode L L H H Write/verify mode H × H H Program inhibit mode ×: L or H Data Sheet U15723EJ1V0DS 23 µPD17P709A 2.2 Program Memory Write Procedure Program memory can be written at high speed using the following procedure. (1) Pull down unused pins to GND via a resistor. Set the CLK pin to low. (2) Supply 5 V to the V DD pin. Set the V PP pin to low. (3) Wait for 10 µ s and then supply 5 V to the V PP pin. (4) Set the mode setting pin to program memory address 0-clear mode. (5) Supply +6 V to the V DD pin and +12.5 V to the V PP pin. (6) Set the program inhibit mode. (7) Write data in the 1 ms write mode. (8) Set the program inhibit mode. (9) Set the verify mode. If the data is correct, go to step (10). If not, repeat steps (7) to (9). (10) (X: Number of write operations from steps (7) to (9)) × 1 ms additional write. (11) Set the program inhibit mode. (12) Input four pulses to the CLK pin to increment the program memory address by one. (13) Repeat steps (7) to (12) until the end address is reached. (14) Set the program memory address 0-clear mode. (15) Change the V DD and V PP pins to 5 V. (16) Turn off the power. The following figure shows steps (2) to (12). X repetitions Reset Verify Write VDD VPP Additional write Address increment VDD + 1 VDD GND VPP VDD GND CLK D0 to D7 Hi - Z Data input Hi - Z Data output MD0 MD1 MD2 MD3 24 Data Sheet U15723EJ1V0DS Hi - Z Data input Hi - Z µPD17P709A 2.3 Program Memory Read Procedure (1) Pull down unused pins to GND via a resistor. Set the CLK pin to low. (2) Supply 5 V to the V DD pin. Set the V PP pin to low. (3) Wait for 10 µ s and then supply 5 V to the VPP pin. (4) Set the mode setting pin to program memory address 0-clear mode. (5) Supply +6 V to the V DD pin and +12.5 V to the V PP pin. (6) Set the program inhibit mode. (7) Set the verify mode. Addresses are incremented by one for each 4-pulse cycle input to the CLK pin. (8) Set the program inhibit mode. (9) Set the program memory address 0-clear mode. (10) Change the V DD and V PP pins to 5 V. (11) Turn off the power. The following figure shows steps (2) to (9). Reset VDD VPP VDD + 1 VDD GND VPP VDD GND CLK D0 to D7 Hi - Z Data output Data output Hi - Z MD0 MD1 “L” MD2 MD3 Data Sheet U15723EJ1V0DS 25 µPD17P709A 3. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25°C) Parameter Symbol Conditions Ratings Unit Supply voltage VDD –0.3 to +6.0 V PROM program voltage VPP –0.3 to +13.5 V Other than CE, INT0 to INT4, and RESET pins –0.3 to VDD + 0.3 V CE, INT0 to INT4, and RESET pins –0.3 to VDD + 0.6 V –0.3 to VDD + 0.3 V Input voltage VI Output voltage VO Except P1B0 to P1B3 Output current, high IOH Per pin –8.0 mA Total of P2A0 to P2A2, P3A0 to P3A3, and P3B0 to P3B3 –15.0 mA Total of P0A0 to P0A3, P0B0 to P0B3, P0C0 to P0C3, P1D0 to P1D3, P2B0 to P2B3, P2C0 to P2C3, P2D0 to P2D2, P3C0 to P3C3, and P3D0 to P3D3 –25.0 mA Per pin for P1B0 to P1B3 12.0 mA Per pin for P1B0 to P1B3 8.0 mA Total of P2A0 to P2A2, P3A0 to P3A3, and P3B0 to P3B3 15.0 mA Total of P0A0 to P0A3, P0B0 to P0B3, P0C0 to P0C3, P1D0 to P1D3, P2B0 to P2B3, P2C0 to P2C3, P2D0 to P2D2, P3C0 to P3C3, and P3D0 to P3D3 25.0 mA Total of P1B0 to P1B3 pins 25.0 mA P1B0 to P1B3 14.0 V Output current, low Output voltage IOL VBDS Total power dissipation Pt 200 mW Operating ambient temperature TA –40 to +85 °C Storage temperature Tstg –55 to +125 °C Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Recommended Operating Range (TA = –40 to +85°C) Parameter Supply voltage Symbol Conditions MIN. TYP. MAX. Unit VDD1 When CPU and PLL are operating 4.5 5.0 5.5 V VDD2 When CPU and PLL are stopped 3.5 5.0 5.5 V MIN. TYP. MAX. Unit 12 V Recommended Output Withstanding Voltage (TA = –40 to +85°C) Parameter Output withstanding voltage 26 Symbol VBDS Conditions P1B0 to P1B3 Data Sheet U15723EJ1V0DS µPD17P709A DC Characteristics (TA = –40 to +85°C, VDD = 3.5 to 5.5 V) Parameter Supply current Data retention voltage Symbol Conditions MIN. TYP. MAX. Unit IDD1 When CPU is operating and PLL is stopped with sine wave input to XIN pin. (fIN = 4.5 MHz ±1%, VIN = VDD) 1.5 3.0 mA IDD2 When CPU and PLL are stopped with sine-wave input to XIN pin. (fIN = 4.5 MHz ±1%, VIN = VDD) With HALT instruction 0.7 1.5 mA VDDR1 Crystal oscillation 3.5 5.5 V VDDR2 Crystal oscillation Power failure detection by timer FF 2.2 5.5 V VDDR3 stopped 2.0 5.5 V IDDR1 Crystal oscillation VDD = 5 V, TA = 25°C 2.0 4.0 µA IDDR2 stopped 2.0 30.0 µA VIH1 P0A0, P0B1, P0C0 to P0C3, P1A0, P1A1, P1C0 to P1C3, P1D0 to P1D3, P2A2, P2B0 to P2B3, P2C0 to P2C3, P2D0 to P2D2, P3A0 to P3A3, P3B0 to P3B3, P3C0 to P3C3, P3D0 to P3D3 0.7VDD VDD V VIH2 P0A1 to P0A3, P0B0, P0B2, P0B3, P2A0, P2A1, CE, INT0 to INT4, RESET 0.8VDD VDD V VIH3 P0D0 to P0D3 0.55VDD VDD V VIL1 P0A0, P0B1, P0C0 to P0C3, P1A0, P1A1, P1C0 to P1C3, P1D0 to P1D3, P2A2, P2B0 to P2B3, P2C0 to P2C3, P2D0 to P2D2, P3A0 to P3A3, P3B0 to P3B3, P3C0 to P3C3, P3D0 to P3D3 0 0.3VDD V VIL2 P0A1 to P0A3, P0B0, P0B2, P0B3, P2A0, P2A1, CE, INT0 to INT4, RESET 0 0.2VDD V VIL3 P0D0 to P0D3 0 0.15VDD V IOH1 P0A0 to P0A3, P0B0 to P0B3, P0C0 to P0C3, P1D0 to P1D3, P2A0 to P2A2, P2B0 to P2B3, P2C0 to P2C3, P2D0 to P2D2, P3A0 to P3A3, P3B0 to P3B3, P3C0 to P3C3, P3D0 to P3D3 VOH = VDD – 1 V –1.0 mA IOH2 EO0, EO1 VDD = 4.5 to 5.5 V, VOH = VDD – 1 V –3.0 mA IOL1 P0A0 to P0A3, P0B0 to P0B3, P0C0 to P0C3, P1D0 to P1D3, P2A0 to P2A2, P2B0 to P2B3, P2C0 to P2C3, P2D0 to P2D2, P3A0 to PA3A, P3B0 to P3B3, P3C0 to P3C3, P3D0 to P3D3 VOL = 1 V 1.0 mA IOL2 EO0, EO1 VDD = 4.5 to 5.5 V, VOL = 1 V 3.0 mA IOL3 P1B0 to P1B3 VOL = 1 V 7.0 mA Input current, high IIH P0D0 to P0D3 pulled down VIN = VDD 5.0 Output off leakage ILO1 P1B0 to P1B3 current ILO2 EO0, EO1 Input leakage current, high ILIH Input pin Input leakage current, low ILIL Input pin Data retention current Input voltage, high Input voltage, low Output current, high Output current, low Data memory retained 150 µA 1.0 µA ±1.0 µA VIN = VDD 1.0 µA VIN = 0 V –1.0 µA VIN = 12 V VIN = VDD, VIN = 0 V Data Sheet U15723EJ1V0DS 27 µPD17P709A AC Characteristics (TA = –40 to +85°C, VDD = 5 V ±10%) Parameter Symbol Operating frequency fIN1 fIN2 Conditions MIN. TYP. MAX. Unit VCOL pin, Sine-wave input VIN = 0.15Vp-p 0.8 3 MHz MF mode Sine-wave input VIN = 0.1Vp-p 0.5 3 MHz 10 40 MHz VCOL pin, HF mode, sine-wave input VIN = 0.1Vp-pNote fIN3 VCOH pin, VHF mode, sine-wave input VIN = 0.1Vp-pNote 60 130 MHz fIN4 AMIFC pin, sine-wave input 0.4 0.5 MHz VIN = 0.15Vp-p fIN5 FMIFC pin, FMIF count mode, sine-wave input VIN = 0.20Vp-p 10 11 MHz fIN6 FMIFC pin, AMIF count mode, sine-wave input VIN = 0.15Vp-p 0.4 0.5 MHz SIO0 input frequency fIN7 External clock 1 MHz SIO1 input frequency fIN8 External clock 0.7 MHz Note The condition of sine-wave input VIN = 0.1Vp-p is the rated value when the µPD17P709A is operating alone. Where influence of noise must be taken into consideration, operation under input amplitude conditions of VIN = 0.15Vp-p is recommended. A/D Converter Characteristics (TA = –40 to +85°C, VDD = 5 V ±10%) Parameter Symbol Conditions A/D conversion total error 8 bits A/D conversion total error 8 bits MIN. TYP. MAX. Unit ±3.0 LSB ±2.5 LSB TYP. MAX. Unit 6.0 12.0 mA TA = 0 to 85°C Reference Characteristics (TA = +25°C, VDD = 5.0 V) Parameter Symbol Supply current IDD3 Conditions MIN. When CPU and PLL are operating with sine-wave input to VCOH pin (fIN = 130 MHz, VIN = 0.3Vp-p) DC Programming Characteristics (TA = 25°C, VDD = 6.0 ±0.25 V, VPP = 12.5 ±0.5 V) Parameter Symbol Input voltage, high Conditions VDD V V Pins other than CLK 0 0.2VDD V VIL2 CLK 0 0.4 V Input leakage current ILI VIN = VIL or VIH 10 µA Output voltage, high VOH IOH = –1 mA Output voltage, low VOL IOL = 1 mA VDD supply current IDD VPP supply current IPP 28 VIL1 Unit VDD 2. CLK MAX. 0.7VDD Cautions 1. Pins other than CLK TYP. VDD – 0.5 Input voltage, low VIH1 VIH2 MIN. VDD – 1.0 MD0 = VIL, MD1 = VIH Ensure that VPP does not exceed +13.5 V including overshoot. VDD must be applied before VPP, and cut after VPP. Data Sheet U15723EJ1V0DS V 1.0 V 30 mA 30 mA µPD17P709A AC Programming Characteristics (TA = 25°C, VDD = 6.0 ±0.25 V, VPP = 12.5 ±0.5 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Address setup timeNote (to MD0↓) tAS 2 µs MD1 setup time (to MD0↓) tM1S 2 µs Data setup time (to MD0↓) tDS 2 µs tAH 2 µs Data hold time (from MD0↑) tDH 2 µs Delay time from MD0↑ to data output float tDF 0 VPP setup time (to MD3↑) tVPS 2 µs VDD setup time (to MD3↑) tVDS 2 µs Initial program pulse width tPW 0.95 Additional program pulse width tOPW 0.95 MD0 setup time (to MD1↑) tM0S 2 Delay time from MD0↓ to data output tDV MD0 = MD1 = VIL MD1 hold time (from MD0↑) tM1H tM1H + tM1R ≥ 50 µs MD1 recovery time (from MD0↓) Note Address hold time (from MD0↑) 130 1.0 ns 1.05 ms 21.0 ms µs 1 µs 2 µs tM1R 2 µs Program counter reset time tPCR 10 µs CLK input high-/low-level widths tXH, tXL 0.125 µs CLK input frequency fX Initial mode setting time tI 2 µs MD3 setup time (to MD1↑) tM3S 2 µs MD3 hold time (from MD1↓) tM3H 2 µs MD3 setup time (to MD0↓) tM3SR Program memory read Delay time from addressNote to data output tDAD Program memory read Hold time from addressNote to data output tHAD Program memory read 0 MD3 hold time (from MD0↑) tM3HR Program memory read 2 Delay time from MD3↓ to data output float tDFR Program memory read Reset setup time tRES Note 4.19 µs 2 2 µs 130 ns µs 2 10 MHz µs µs The internal address signal is incremented by 1 on the 3rd fall of a four-clock input (CLK) cycle, and is not connected to a pin. Data Sheet U15723EJ1V0DS 29 µPD17P709A Program Memory Write Timing tRES tVPS VPP VPP VDD GND VDD + 1 VDD tVDS VDD tXH GND CLK tXL Data input D0-D7 tDS tI Data output tDH tDV tDF Data input Data input tDH tAH tDS tAS MD0 tPW tM0S tM1R tOPW MD1 tPCR tM1S tM1H MD2 tM3H tM3S MD3 Remark The dashed line indicates high-impedance. Program Memory Read Timing tRES tVPS VPP VPP VDD GND VDD + 1 tVDS VDD VDD tXH GND CLK tDAD tHAD tXL Hi-Z D0-D7 Hi-Z Data output Data output tDFR tDV tI tM3HR MD0 MD1 L tPCR MD2 tM3SR MD3 30 Data Sheet U15723EJ1V0DS µPD17P709A 4. PACKAGE DRAWING 80-PIN PLASTIC QFP (14x14) A B 41 40 60 61 detail of lead end S C D Q R 21 20 80 1 F G J H I M K P S N S L M NOTE ITEM Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. MILLIMETERS A 17.2±0.4 B 14.0±0.2 C 14.0±0.2 D 17.2±0.4 F 0.825 G 0.825 H I 0.30±0.10 0.13 J 0.65 (T.P.) K 1.6±0.2 0.8±0.2 L M 0.15 +0.10 −0.05 N 0.10 P 2.7±0.1 Q 0.1±0.1 R 5°±5° S 3.0 MAX. S80GC-65-3B9-6 Data Sheet U15723EJ1V0DS 31 µPD17P709A 5. RECOMMENDED SOLDERING CONDITIONS The µPD17P709A should be soldered and mounted under the following recommended conditions. For details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact an NEC sales representative. Table 5-1. Surface Mounting Type Soldering Conditions µPD17P709AGC-3B9: 80-pin plastic QFP (14 × 14) Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235°C, Time: 30 seconds MAX. (at 210°C or higher.), Count: Three times or less IR35-00-3 VPS Package peak temperature: 215°C, Time: 40 seconds MAX. (at 200°C or higher.), Count: Three times or less VP15-00-3 Wave soldering Solder bath temperature: 260°C MAX., Time: 10 seconds MAX., Count: Once, Preheating temperature: 120°C MAX. (package surface temperature) WS60-00-1 Partial heating Pin temperature: 300°C MAX., Time: 3 seconds MAX. (per pin row) Caution Do not use different soldering methods together (except for partial heating). 32 Data Sheet U15723EJ1V0DS — µPD17P709A APPENDIX DEVELOPMENT TOOLS The following development tools are available for development of programs for the µPD17P709A. Hardware Name Outline In-circuit emulator (IE-17K-ETNote 1) IE-17K-ET is an in-circuit emulator that can be used with any model in the 17K Series. IE-17K-ET is connected to a host machine, which is PC-9800 series or IBM PC/ATTM, with RS-232C. By using these in-circuit emulators with a system evaluation board (SE board) corresponding to each model, these emulators operate as emulators specific to a model. When man-machine interface software SIMPLEHOSTTM is used, a more sophisticated debugging environment can be created. SE board (SE-17709) SE-17709 is an SE board for the µPD17709A Subseries. This board can be used alone to evaluate a system, or in combination with an in-circuit emulator for debugging. Emulation probe (EP-17K80GC) EP-17K80GC is an emulation probe for the µPD17P709AGC. By using this probe with EV-9200GC80Note 2, the SE board and target system are connected. Conversion socket (EV-9200GC-80Note 2) EV-9200GC-80 is a conversion socket for 80-pin plastic QFP (14 × 14). It is used to connect the EP17K80GC and target system. PROM programmer (PG-1500) PG-1500 is a PROM programmer supporting µPD17P709A. It can program the µPD17P709A when connected with the PG-1500 adapter PA-17KDZ and programmer adapter PA-17P709GC. Programmer adapter (PA-17P709GC) PA-17P709GC is an adapter to program the µPD17P709A. It is used with PG-1500. Notes 1. External power supply type 2. One EV-9200GC-80 is supplied with the EP-17K80GC. Five EV-9200GC-80 are also available as a set. Remark Third-party PROM programmers AF-9703, AF-9704, AF-9705, and AF-9706 are available from Ando Electric Co., Ltd. Use these programmers with programmer adapter PA-17P709GC. For details, consult Ando Electric Co., Ltd. (TEL: +8-44-549-7300). Software Name 17K Series assembler (RA17K) Device file (AS17704) Outline Host Machine RA17K is an assembler that can be commonly used with 17K Series. To develop programs for the µPD17P709A, this RA17K and a device file (AS17704) are used in combination. AS17704 is a device file for the µPD17P709A. It is used with the assembler common to the 17K Series (RA17K). SIMPLEHOST is man-machine Support interface software that runs on software Windows when a program is (SIMPLEHOST) developed by using an in-circuit emulator and personal computer. OS Media Parts Number PC-9800 series Japanese WindowsTM 3.5” 2HD µSAA13RA17K IBM PC/AT Japanese Windows 3.5” 2HC µSAB13RA17K compatibles English Windows µSBB13RA17K PC-9800 series Japanese Windows 3.5” 2HD µSAA13AS17704 IBM PC/AT Japanese Windows 3.5” 2HC µSAB13AS17704 compatibles English Windows µSBB13AS17704 PC-9800 series Japanese Windows 3.5” 2HD µSAA13ID17K IBM PC/AT Japanese Windows 3.5” 2HC µSAB13ID17K compatibles English Windows µSBB13ID17K Data Sheet U15723EJ1V0DS 33 µPD17P709A NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 34 Data Sheet U15723EJ1V0DS µPD17P709A Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) • Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd. Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics Hong Kong Ltd. Velizy-Villacoublay, France Tel: 01-3067-5800 Fax: 01-3067-5899 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (France) S.A. NEC Electronics Singapore Pte. Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Madrid Office Madrid, Spain Tel: 091-504-2787 Fax: 091-504-2860 Novena Square, Singapore Tel: 253-8311 Fax: 250-3583 NEC Electronics Italiana s.r.l. NEC Electronics (Germany) GmbH Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 NEC Electronics (France) S.A. NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (UK) Ltd. NEC Electronics Taiwan Ltd. Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951 NEC do Brasil S.A. Electron Devices Division Guarulhos-SP, Brasil Tel: 11-6462-6810 Fax: 11-6462-6829 J01.2 Data Sheet U15723EJ1V0DS 35 µPD17P709A Purchase of NEC I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. SIMPLEHOST is a trademark of NEC Corporation. Windows is either a registered trademark or trademark of Microsoft Corporation in the United States and/ or other countries. PC/AT is a trademark of International Business Machines Corporation. The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. • The information in this document is current as of September, 2001. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. • NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. • Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. • While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. • NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above). 2 M8E 00. 4