DATA SHEET MOS INTEGRATED CIRCUIT µPD30200, 30210 VR4300TM, VR4305TM, VR4310TM 64-BIT MICROPROCESSOR DESCRIPTION The µPD30200-100, 30200-133 (VR4300), 30200-80 (VR4305), and 30210 (VR4310) are high-performance, 64bit RISC (Reduced Instruction Set Computer) type VR SeriesTM microprocessors employing the RISC architecture developed by MIPSTM Technologies Inc. The VR4300, VR4305, and VR4310 are intended for the high-performance embedded device field and have 32bit system interface buses. Detailed function descriptions are provided in the following user’s manual. Be sure to read this manual before designing. • VR4300, VR4305, VR4310 User’s Manual (U10504E) FEATURES • Employs 64-bit RISC MIPS architecture • High-speed operation processing • 5-stage pipeline processing • High-speed execution of integer and floating-point operations • 48 SPECint92, 36 SPECfp92, 106 MIPS, at 80 MHz operation (µPD30200-80) 60 SPECint92, 45 SPECfp92, 131 MIPS, at 100 MHz operation (µPD30200-100) 80 SPECint92, 60 SPECfp92, 177 MIPS at 133 MHz operation (µPD30200-133, µPD30210-133) 100 SPECint92, 75 SPECfp92, 221 MIPS at 167 MHz operation (µPD30210-167) • • • • Instruction set compatible with VR4000TM Series (conforms to MIPS-I/II/III) On-chip cache memory (Instruction: 16 Kbytes, Data: 8 Kbytes) 32-bit address/data multiplexed bus facilitating system design Low power consumption • µPD30200-80: 1.5 W (TYP.) (at 80 MHz operation) • µPD30200-100, 30200-133: 1.8 W (TYP.) (at 100 MHz operation), 2.4 W (TYP.) (at 133 MHz operation) • µPD30210-×××: 1.9 W (TYP.) (at 133 MHz operation), 2.4 W (TYP.) (at 167 MHz operation) • Supply voltage: 3.3 ± 0.3 V (µPD30200-80, 30200-100), 3.0 to 3.5 V (µPD30200-133, 30210-×××) Unless otherwise specified, the VR4300 (µPD30200) is treated as the representative model throughout this document. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. U10116EJ7V0DS00 (7th edition) Date Published November 2000 N CP(K) Printed in Japan The mark shows major revised points. © 1995, 1998 1994 µPD30200, 30210 APPLICATIONS • Embedded controllers • Page printer controllers • Amusement game machines, etc. ORDERING INFORMATION Part Number 2 Package Maximum Internal Operating Frequency (MHz) µ PD30200GD-80-LBB 120-pin plastic QFP (28 × 28) 80 µ PD30200GD-100-MBB 120-pin plastic QFP (28 × 28) 100 µ PD30200GD-133-MBB 120-pin plastic QFP (28 × 28) 133 µ PD30210GD-133-MBB 120-pin plastic QFP (28 × 28) 133 µ PD30210GD-167-MBB 120-pin plastic QFP (28 × 28) 167 Data Sheet U10116EJ7V0DS00 µPD30200, 30210 PIN CONFIGURATION (Top View) • 120-pin plastic QFP (28 × 28) µPD30200GD-80-LBB µPD30200GD-100-MBB µPD30200GD-133-MBB µPD30210GD-133-MBB 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 VDD GND Int2 SysAD27 SysAD28 VDD GND SysAD29 EOK SysAD30 VDD GND PValid SysAD31 VDD GND PReq SysAD0 VDD GND SysAD1 SysAD2 VDD GND SysAD3 JTDO SysAD4 JTDI VDD GND GND VDD SysAD16 SysAD15 GND VDD SysAD14 SysAD13 GND VDD SysAD12 SysAD11 GND VDD SysAD10 Int0 SysAD9 GND VDD SysAD8 SysAD7 JTMS GND VDD SysAD6 SysAD5 JTCK Int1 GND VDD VDD GND SysAD22 SysAD21 VDD GND SysAD20 VDD VDDP GNDP PLLCap0 PLLCap1 VDDP GNDP VDD (DivMode2) MasterClock GND TCIock VDD GND SyncOut SysAD19 VDD Syncln GND SysAD18 SysAD17 Int4 VDD GND 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 GND VDD Int3 SysAD23 DivMode0 SysAD24 GND VDD DivMode1 SysCmd4 ColdReset SysCmd3 GND VDD SysCmd2 EValid Reset SysCmd1 GND VDD SysCmd0 EReq SysAD25 GND VDD PMaster SysAD26 NMI GND VDD µPD30210GD-167-MBB Remark ( ): Pin name in the µPD30210-××× Data Sheet U10116EJ7V0DS00 3 µPD30200, 30210 PIN NAMES ColdReset: DivMode (1:0) : Divide Mode EOK: External OK EReq: External Request EValid: External Valid Int(4:0): Interrupt Request JTCK: JTAG Clock Input JTDI: JTAG Data In JTDO: JTAG Data Out JTMS: JTAG Command Signal MasterClock: Master Clock NMI: Non-maskable Interrupt Request PLLCap (1:0): Phase Locked Loop Capacitance PMaster: Processor Master PReq: Processor Request PValid: Processor Valid Reset: Reset SyncIn: Synchronization Clock Input SyncOut: Synchronization Clock Output SysAD(31:0): System Address/Data Bus SysCmd (4:0): System Command/Data ID Bus TClock: Transmit Clock V DD: Power Supply GND: Ground V DDP: V DD for PLL GNDP: GND for PLL Note 4 Cold Reset Note In the µPD30200-×××. DivMode (2:0) in the µPD30210-×××. Data Sheet U10116EJ7V0DS00 µPD30200, 30210 INTERNAL BLOCK DIAGRAM Data, address Control System interface Master clock Clock generator Data cache Instruction cache CP0 TLB Execution unit Instruction address Pipeline control Data Sheet U10116EJ7V0DS00 5 µPD30200, 30210 CONTENTS 1. PIN FUNCTIONS ............................................................................................................................ 7 2. ELECTRICAL SPECIFICATIONS .................................................................................................. 9 3. PACKAGE DRAWING ..................................................................................................................... 19 4. RECOMMENDED SOLDERING CONDITIONS ............................................................................... 20 DIFFERENCES BETWEEN THE VR4300, VR4305, VR4310 AND VR4100TM .............. 21 APPENDIX 6 Data Sheet U10116EJ7V0DS00 µPD30200, 30210 1. PIN FUNCTIONS Pin Name I/O Function SysAD (31:0) I/O System address/data bus. 32-bit bus for communication between processor and external agent. SysCmd (4:0) I/O System command/data ID bus. 5-bit bus for communication of commands and data identifiers between processor and external agent. EValid Input PValid Output EReq Input PReq Output Processor request. Signal used by processor to request use of system interface. If the processor detects a protocol error, this signal oscillates with the same frequency as SClock (internal), and the system interface hangs up. PMaster Output Processor master. Signal indicating processor controls system interface. EOK Input External valid. Signal indicating that external agent has transmitted valid address or data onto SysAD bus and valid command or data identifier onto SysCmd bus. Processor valid. Signal indicating that processor has transmitted valid address or data onto SysAD bus and valid command or data identifier onto SysCmd bus. External request. Signal used by external agent to request use of system interface. External OK. Signal indicating that external agent can accept processor request. Int (4:0) Input Interrupt. General-purpose processor interrupt requests, the input status of which can be confirmed by bits 14 through 10 of cause register. NMI Input Non-maskable interrupt. Interrupt request that cannot be masked. ColdReset Input Cold reset. Signal that initializes internal status of processor. It can be made active/inactive without synchronizing with the MasterClock. Reset Input Reset. Signal that generates reset exception without initializing internal status of processor. MasterClock Input Master clock. Clock input signal to processor. TClock Output Transmit-receive signal clock This is the basic clock for the system interface and is synchronized with the MasterClock. SyncOut Output Synchronization clock output. Output of synchronization clock. SyncIn Input Synchronization clock input. Input of synchronization clock. JTDI Input JTAG data input. Input of JTAG serial data. Data Sheet U10116EJ7V0DS00 7 µPD30200, 30210 Pin Name I/O Function JTDO Output JTAG data output. Output of JTAG serial data. JTMS Input JTAG command. Indicates that input serial data is command data. JTCK Input JTAG clock input. Input of JTAG serial clock. If the JTAG interface is not used, set it to low level. DivMode Input Mode setting. Sets frequency ratio of MasterClock, TClock, and PClock. • DivMode (1:0) (VR4300) Example DivMode (1:0) MasterClock PClock 00 33.3 MHz 133 MHz 01 66.7 MHz 100.0 MHz 10 50.0 MHz 100.0 MHz 11 33.3 MHz 100.0 MHz TClock 33.3 MHz 66.7 MHz 50.0 MHz 33.3 MHz Ratio 1:4:1 2:3:2 1:2:1 1:3:1 Note 1 Note 2 Notes 1. This setting is allowed with the 133 MHz model only. With the 100 MHz model, this setting is reserved. 2. This setting is allowed with the 100 MHz model only. With the 133 MHz model, this setting is reserved. • DivMode (1:0) (VR4305) Example DivMode (1:0) 00 01 10 11 MasterClock 66.7 MHz – 40 MHz 20 MHz PClock 66.7 MHz – 80 MHz 60 MHz TClock 66.7 MHz – 40 MHz 20 MHz Ratio 1:1:1 Reserved 1:2:1 1:3:1 • DivMode (2:0) (VR4310) Example DivMode (2:0) 000 001 010 011 100 101 110 111 MasterClock 26.7 MHz 22.2 MHz 66.7 MHz 33.3 MHz 33.3 MHz – 50.0 MHz 33.3 MHz PClock 133 MHz 133 MHz 167 MHz 100 MHz 133 MHz – 100 MHz 100 MHz TClock 26.7 MHz 22.2 MHz 66.7 MHz 33.3 MHz 33.3 MHz – 50.0 MHz 33.3 MHz Ratio 1:5:1 1:6:1 2:5:2 Note 1:3:1 1:4:1 Reserved 1:2:1 1:3:1 Note This setting is allowed with the 167 MHz model only. With the 133 MHz model, this setting is reserved. After power application, do not change the value of these pins; otherwise the operation is not guaranteed. 8 PLLCap (1:0) – PLL capacitor. Connect capacitor to adjust internal PLL. VDDP – PLL VDD. Power supply for internal PLL. GNDP – PLL GND. Ground for internal PLL. VDD – Positive power supply pin. GND – Ground pin. Data Sheet U10116EJ7V0DS00 µPD30200, 30210 2. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25°C) Parameter Supply voltage Input Symbol Conditions VDD voltageNote VI Pulse of less than 10 ns Ratings Unit –0.5 to +4.0 V –0.5 to VDD + 0.3 V –1.5 to VDD + 0.3 V Operating case temperature TC 0 to +85 °C Storage temperature Tstg –65 to +150 °C Note The upper limit of the input voltage (VDD + 0.3) is +4.0 V. Cautions 1. Do not short circuit two or more outputs at the same time. 2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. The specifications and conditions shown in the following DC Characteristics and AC Characteristics are the range within which the product can normally operate and the quality can be guaranteed. DC Characteristics (TC = 0 to +85°C, VDD = 3.3 ±0.3 V): µPD30200-80, 30200-100 (TC = 0 to +85°C, VDD = 3.0 to 3.5 V): Parameter Symbol µPD30200-133, 30210-××× Conditions MIN. MAX. Unit VOH IOH = –400 µA 2.4 V VOHC IOH = –400 µA 2.7 V Output voltage, low VOL IOL = 2.5 mA Input voltage, high VIH Input voltage, low VIL Output voltage, high Output voltage, highNote 1 Pulse of less than 10 ns 0.4 V 2.0 VDD + 0.3 V –0.5 +0.8 V –1.5 +0.8 V Input voltage, highNote 2 VIHC 0.8VDD VDD + 0.3 V Input voltage, lowNote 2 VILC –0.5 0.2VDD V –1.5 0.2VDD V µPD30200 at 80 MHz operation 0.60 A at 100 MHz operation 0.67 A at 133 MHz operation 0.90 A µPD30210 at 133 MHz operation 0.69 A at 167 MHz operation 0.85 A Pulse of less than 10 ns Supply current IDD Input leakage current, high ILIH VI = VDD 10 µA Input leakage current, low ILIL VI = 0 V –10 µA Output leakage current, high ILOH VO = VDD 20 µA Output leakage current, low ILOL VO = 0 V –20 µA Notes 1. Applied to the TClock pin. 2. Applied to the MasterClock pin only. Remark The operating supply current is almost proportional to the operating clock frequency. Data Sheet U10116EJ7V0DS00 9 µPD30200, 30210 Capacitance (TA = 25°C, VDD = 0 V) Parameter Symbol Conditions MIN. MAX. Unit Input capacitance CIn fC = 1 MHz 10 pF Output capacitance Cout Unmeasured pins returned to 0 V. 10 pF AC Characteristics (TC = 0 to +85°C, VDD = 3.3 ±0.3 V): µPD30200-80, 30200-100 (TC = 0 to +85°C, VDD = 3.0 to 3.5 V): µPD30200-133, 30210-××× Clock Parameters (1) µPD30200-××× Parameter Symbol Conditions µPD30200-80 MIN. MAX. µPD30200-100 µPD30200-133 MIN. MAX. MIN. Unit MAX. Master clock high-level width tMCkHigh 3.5 3.5 3.5 ns Master clock low-level width 3.5 3.5 3.5 ns Master clock tMCkLow frequencyNote Master clock cycle tMCkP DivMode = 1:1 20 66.7 – – – – MHz DivMode = 1:2 20 66.7 20 66.7 34 66.7 MHz DivMode = 2:3 – – 20 66.7 – – MHz DivMode = 1:3 20 66.7 20 66.7 24 66.7 MHz DivMode = 1:4 – – – – 20 66.7 MHz DivMode = 1:1 15 50 – – – – ns DivMode = 1:2 15 50 15 50 15 29 ns DivMode = 2:3 – – 15 50 – – ns DivMode = 1:3 15 50 15 50 15 41 ns DivMode = 1:4 – – – – 15 50 ns Clock jitter tMCJitter ±500 ±500 ±500 ps Master clock rise time tMCRise 4.0 4.0 4.0 ns Master clock fall time tMCFall 4.0 4.0 4.0 ns JTAG clock cycle tJTAGCkP Note 4 × tMCkP 4 × tMCkP 4 × tMCkP ns The operation of the internal PLL of the µPD30200-××× is guaranteed. The RP mode is supported only by µPD30200-80 and 30200-100 and guaranteed when the master clock frequency is 40 MHz or higher. 10 Data Sheet U10116EJ7V0DS00 µPD30200, 30210 (2) µPD30210-××× Parameter Symbol Conditions µPD30210-133 µPD30210-167 MIN. MIN. MAX. Unit MAX. Master clock high-level width tMCkHigh 3.5 3.5 ns Master clock low-level width 3.5 3.5 ns tMCkLow Master clock frequencyNote DivMode = 2.0 Master clock cycle tMCkP 50 66.7 50 83.3 MHz DivMode = 2.5 – – 40 66.7 MHz DivMode = 3.0 33.3 44.4 33.3 55.6 MHz DivMode = 4.0 25 33.3 25 41.7 MHz DivMode = 5.0 20 26.7 20 33.3 MHz DivMode = 6.0 20 22.2 20 27.8 MHz DivMode = 2.0 15 20 12 20 ns DivMode = 2.5 – – 15 25 ns DivMode = 3.0 22 30 18 30 ns DivMode = 4.0 30 40 24 40 ns DivMode = 5.0 37 50 30 50 ns DivMode = 6.0 45 50 36 50 ns Clock jitter tMCJitter ±500 ±500 ps Master clock rise time tMCRise 4.0 4.0 ns Master clock fall time tMCFall 4.0 4.0 ns JTAG clock cycle tJTAGCkP 4 × tMCkP 4 × tMCkP ns The operation of the internal PLL of the µPD30210-××× is guaranteed. The RP mode is not supported by Note the µPD30210-×××. System Interface Parameters (1) µPD30200-80 (TC = 0 to 85°C, VDD = 3.3 ±0.3 V) Parameter Data output delay timeNote 1 Data setup delay timeNote 1 Data hold delay Clock rise Clock fall timeNote 1 timeNote 2 timeNote 2 Clock high-level Clock low-level widthNote 2 widthNote 2 Symbol tDO Conditions CL = 50 pF At 66.7 MHz InputNote 3 At 40 MHz InputNote 3 At 33.3 MHz InputNote 3 MIN. MAX. MIN. MAX. MIN. MAX. 2.0 8.0 2.0 8.0 2.0 8.0 Unit ns tDS 3.5 3.5 3.5 ns tDH 1.5 1.5 1.5 ns tCORise CL = 50 pF tCOFall 4.0 4.0 4.0 ns 4.0 4.0 4.0 ns tCOHigh 3.5 8.5 11.0 ns tCOLow 3.5 8.5 11.0 ns Notes 1. Applied to all interface pins. 2. Applied to TClock pin. 3. Master clock frequency (example) Data Sheet U10116EJ7V0DS00 11 µPD30200, 30210 (2) µPD30200-100 (TC = 0 to 85°C, VDD = 3.3 ±0.3 V) Parameter Data output delay timeNote 1 Data setup delay timeNote 1 Data hold delay Mode data setup Clock rise Clock fall timeNote 1 timeNote 2 timeNote 3 timeNote 3 Clock high-level Clock low-level widthNote 3 widthNote 3 Symbol tDO Condition CL = 50 pF At 66.7 MHz InputNote 4 At 62.5 MHz InputNote 4 At 50 MHz InputNote 4 At 33.3 MHz InputNote 4 MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. 2.0 8.0 2.0 8.0 2.0 8.0 2.0 8.0 Unit ns tDS 3.5 3.5 3.5 3.5 ns tDH 1.5 1.5 1.5 1.5 ns tMDS 3.5 3.5 3.5 3.5 ns tCORise CL = 50 pF tCOFall 4.0 4.0 4.0 4.0 ns 4.0 4.0 4.0 4.0 ns tCOHigh 3.5 4.0 6.0 11.0 ns tCOLow 3.5 4.0 6.0 11.0 ns Notes 1. Applied to all interface pins (except DivMode (1:0) pin). 2. Applied to DivMode (1:0) pin. 3. Applied to TClock pin. 4. Master clock frequency (example) (3) µPD30200-133 (TC = 0 to 85°C, VDD = 3.0 to 3.5 V) Parameter Symbol Conditions At 66.7 MHz InputNote 4 At 44.4 MHz InputNote 4 At 33.3 MHz InputNote 4 MIN. MAX. MIN. MAX. MIN. MAX. 2.0 8.0 2.0 8.0 2.0 8.0 Unit Data output delay timeNote 1 tDO Data setup delay timeNote 1 tDS 3.5 3.5 3.5 ns Data hold delay timeNote 1 tDH 1.5 1.5 1.5 ns Mode data setup timeNote 2 tMDS 3.5 3.5 3.5 ns Clock rise timeNote 3 tCORise Clock fall timeNote 3 tCOFall Clock high-level widthNote 3 tCOHigh 3.5 7.2 11.0 ns Clock low-level widthNote 3 tCOLow 3.5 7.2 11.0 ns CL = 50 pF CL = 50 pF Notes 1. Applied to all interface pins (except DivMode (1:0) pin). 2. Applied to DivMode (1:0) pin. 3. Applied to TClock pin. 4. Master clock frequency (example) 12 Data Sheet U10116EJ7V0DS00 ns 4.0 4.0 4.0 ns 4.0 4.0 4.0 ns µPD30200, 30210 (4) µPD30210-133 (TC = 0 to 85°C, VDD = 3.0 to 3.5 V) Parameter Data output delay timeNote 1 Data setup delay timeNote 1 Data hold delay Clock rise Clock fall timeNote 1 timeNote 2 timeNote 2 widthNote 2 Clock high-level Clock low-level widthNote 2 Symbol tDO Conditions CL = 50 pF At 66.7 MHz InputNote 3 At 33.3 MHz InputNote 3 MIN. MAX. MIN. MAX. 2.0 8.0 2.0 8.0 Unit ns tDS 3.5 3.5 ns tDH 1.5 1.5 ns tCORise CL = 50 pF tCOFall 4.0 4.0 ns 4.0 4.0 ns tCOHigh 3.5 11.0 ns tCOLow 3.5 11.0 ns Notes 1. Applied to all interface pins. 2. Applied to TClock pin. 3. Master clock frequency (example) (5) µPD30210-167 (TC = 0 to 85°C, VDD = 3.0 to 3.5 V) Parameter Data output delay timeNote 1 Data setup delay timeNote 1 Data hold delay Clock rise Clock fall timeNote 1 timeNote 2 timeNote 2 Clock high-level Clock low-level widthNote 2 widthNote 2 Symbol tDO Conditions CL = 50 pF At 83.3 MHz InputNote 3 At 66.7 MHz InputNote 3 At 33.3 MHz InputNote 3 MIN. MAX. MIN. MAX. MIN. MAX. 1.5 8.0 1.5 8.0 1.5 8.0 Unit ns tDS 3.5 3.5 3.5 ns tDH 1.5 1.5 1.5 ns tCORise CL = 50 pF tCOFall 2.5 4.0 4.0 ns 2.5 4.0 4.0 ns tCOHigh 3.5 3.5 11.0 ns tCOLow 3.5 3.5 11.0 ns Notes 1. Applied to all interface pins. 2. Applied to TClock pin. 3. Master clock frequency (example) Load Coefficient Rating Parameter Symbol Conditions Unit MIN. Load coefficient CLD MAX. 2 Data Sheet U10116EJ7V0DS00 ns/25 pF 13 µPD30200, 30210 Test Conditions 1.5 V SCIock tDO All output pins 1.5 V Test Load All output pins DUT CL = 50 pF Timing Charts Clock timing tMCkP tMCkHigh 0.8VDD MasterClock 0.5VDD 0.2VDD tMCkLow tMCRise tMCFall tCOHigh 0.8VDD TClock 0.2VDD tCOLow 14 tCORise Data Sheet U10116EJ7V0DS00 tCOFall µPD30200, 30210 Clock jitter MasterClock 0.5VDD tMCJitter tMCJitter TClockNote Note 0.5VDD If SyncOut and SyncIn are connected with the shortest path, the point of TClock = 50% is the point of MasterClock = 50%. Remark To match the MasterClock edge, make the load capacitance of the SyncIn/SyncOut path the same as that of TClock. System interface edge timing SClock tDO SysAD (31:0) SysCmd (4:0) (Output) Output tDS tDH SysAD (31:0) SysCmd (4:0) (Input) Input tDO PValid, PReq, PMaster Output tDS tDH EValid, EReq, EOK, Int0 to Int4, NMI Input Data Sheet U10116EJ7V0DS00 15 µPD30200, 30210 Clocking relationships Cycle 1 2 3 4 MasterClock (Input) SyncOut (Output) PClock (Internal) SClock (Internal) TClock (Output) SysAD Driven (Output) Data Data Data Data tDO SysAD Received (Input) Data Data tDS tDH 16 Data Sheet U10116EJ7V0DS00 Data Data µPD30200, 30210 Power-on reset timing MasterClock (Input) 64000 master clocks or more tDS ColdReset (Input) 16 master clocks or more tDS tDH Reset (Input) tDH tMDSNote 2 DivMode (1:0)Note1 (Input) SyncOut (Output) Undefined TClock (Output) Undefined Notes 1. In the µPD30200-×××. DivMode (2:0) in the µPD30210-×××. 2. In the µPD30200-100 and 30200-133. tDS in the µPD30200-80 and 30210-×××. Data Sheet U10116EJ7V0DS00 17 µPD30200, 30210 Cold reset timing MasterClock (Input) 64000 master clocks or more tDS ColdReset (Input) 16 master clocks or more tDS tDH Reset (Input) tDH SyncOut (Output) Undefined TClock (Output) Undefined Software reset timing MasterClock (Input) ColdReset (Input) H tDS 16 master clocks or more tDS Reset (Input) tDH SyncOut (Output) TClock (Output) 18 Data Sheet U10116EJ7V0DS00 tDH µPD30200, 30210 3. PACKAGE DRAWING 120 PIN PLASTIC QFP (28x28) A B 90 61 91 60 detail of lead end S C D Q 120 1 R 31 30 F G H I J M P K S N S L M NOTE ITEM Each lead centerline is located within 0.15 mm of its true position (T.P.) at maximum material condition. A MILLIMETERS B 32.0±0.3 28.0±0.2 C 28.0±0.2 D 32.0±0.3 F 2.4 G 2.4 H 0.37 +0.08 −0.07 I 0.15 J 0.8 (T.P.) K 2.0±0.2 L 0.8±0.2 M 0.17 +0.08 −0.07 N 0.1 P 3.2 Q 0.1±0.1 R 5°±5° S 3.3±0.2 P120GD-80-LBB, MBB-2 Data Sheet U10116EJ7V0DS00 19 µPD30200, 30210 4. RECOMMENDED SOLDERING CONDITIONS The products should be soldered and mounted under the following recommended conditions. For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact your NEC representative. Table 4-1. Surface Mounting Type Soldering Conditions µPD30200GD-80-LBB: 120-pin plastic QFP (28 × 28) µPD30200GD-100-MBB: 120-pin plastic QFP (28 × 28) µPD30200GD-133-MBB: 120-pin plastic QFP (28 × 28) µPD30210GD-×××-MBB: 120-pin plastic QFP (28 × 28) Soldering Method Recommended Condition Symbol Soldering Conditions Infrared reflow Package peak temperature: 235°C, Time: 30 sec. max. (at 210°C or higher), Count: Two times or less, Exposure limit: 7 daysNote (after that, prebake at 125°C for 36 hours.) IR35-367-2 VPS Package peak temperature: 215°C, Time: 40 sec. max, (at 200°C or higher), Count: Two times or less, Exposure limit: 7 daysNote (after that, prebake at 125°C for 36 hours.) VP15-367-2 Wave soldering Solder bath temperature: 260°C max., Time: 10 sec. max., Count: Once, Preheating temperature: 120°C max. (package surface temperature), Exposure limit: 7 daysNote WS60-367-1 (after that, prebake at 125°C for 36 hours) Partial heating Note – After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period. Caution 20 Pin temperature: 300°C max., Time: 3 sec. max. (per pin row) Do not use different soldering methods together (except for partial heating). Data Sheet U10116EJ7V0DS00 µPD30200, 30210 DIFFERENCES BETWEEN THE VR4300, VR4305, VR4310 AND VR4100TM APPENDIX Parameter System bus VR4300 VR4305 VR4310 VR4100 Write data transfer Two buses (D/D××) Initial value setting pins at reset time DivMode (1:0) (Can be set on power application only) Block write access Sequential ordering Subblock ordering State after final data write Final data retained in transfer rate setting End of access Non-cache high-speed write Provided Provided (Set with a register) CPU Corresponding instructions MIPS I, II, and III instruction sets MIPS I, II, III instruction sets plus sum-of-products arithmetic Cache memory Data protection None Word parity (instructions), byte parity (data) JTAG interface Provided None SyncOut-SyncIn path Provided Clock interface BigEndian, Div2, HizParity None 1, 2, 3 2, 2.5 5, 6 Internal vs. bus frequency division rate 1.5Note 1, 2, 3, 4Note 2 1, 2, 3 2, 2.5Note 3, 3, 4, 5, 6 1, 2 Low-power mode Pipeline/system bus operated at a quarter of the normal rateNote4 None None Wait mode None Three types Imp = 0×0B Imp = 0×0C 1.5 , 2, 3, 4 multiplication rate Power mode DivMode (2:0) (Can be set on power application only) Note 2 Input vs. internal Note 1 Four buses (D/D×/D××/D×××) PRId register Note 3 , 3, 4, 4 Notes 1. The 1.5 times frequency setting is allowed with the 100 MHz model only. (With the 133 MHz model, this setting is reserved.) 2. The 4 times frequency setting is allowed with the 133 MHz model only. (With the 100 MHz model, this setting is reserved.) 3. The 2.5 times frequency setting is allowed with the 167 MHz model only. (With the 133 MHz model, this setting is reserved.) 4. Not supported by the 133 MHz model of the VR 4300. Data Sheet U10116EJ7V0DS00 21 µPD30200, 30210 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. The related documents indicated in this publication may include preliminary versions. preliminary versions are not marked as such. VR4000, VR4100, VR4300, VR4305, VR4310, and VR Series are trademarks of NEC Corporation. MIPS is a registered trademark of MIPS Technologies, Inc. in the United States. 22 Data Sheet U10116EJ7V0DS00 However, µPD30200, 30210 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) • Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd. Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics (France) S.A. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (France) S.A. NEC Electronics Singapore Pte. Ltd. Madrid Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860 United Square, Singapore Tel: 65-253-8311 Fax: 65-250-3583 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 NEC Electronics Hong Kong Ltd. NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.l. NEC Electronics (Germany) GmbH Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951 NEC do Brasil S.A. Electron Devices Division Guarulhos-SP Brasil Tel: 55-11-6462-6810 Fax: 55-11-6462-6829 J00.7 Data Sheet U10116EJ7V0DS00 23 µPD30200, 30210 Exporting this product or equipment that includes this product may require a governmental license from the U.S.A. for some countries because this product utilizes technologies limited by the export control regulations of the U.S.A. • The information in this document is current as of July, 2000. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. • NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. • Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. • While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. • NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above). M8E 00. 4