DATA SHEET MOS INTEGRATED CIRCUIT µPD4564441-A75, 4564841-A75 64M-bit Synchronous DRAM, 133MHz 4-bank, LVTTL Description The µPD4564441-A75, 4564841-A75 are high-speed 67,108,864-bit synchronous dynamic random-access memories, organized as 4,194,304 × 4 × 4 and 2,097,152 × 8 × 4 (word × bit × bank), respectively. The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture. All inputs and outputs are synchronized with the positive edge of the clock. The synchronous DRAMs are compatible with Low Voltage TTL (LVTTL). These products are packaged in 54-pin plastic TSOP (II). Features • Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge • Pulsed interface • Possible to assert random column address in every cycle • Quad internal banks controlled by A12 and A13 (Bank Select) • Programmable Wrap sequence (Sequential / Interleave) • Programmable burst length (1, 2, 4, 8 and full page) • /CAS latency (3) • Automatic precharge and controlled precharge • CBR (auto) refresh and self refresh • ×4, ×8 organization • Single 3.3 V ± 0.3 V power supply • LVTTL compatible inputs and outputs • 4,096 refresh cycles / 64 ms • Burst termination by Burst stop command and Precharge command Ordering Information Organization (word × bit × bank) Clock frequency MHz (MAX.) Package µPD4564441G5-A75-9JF 4M × 4 × 4 133 54-pin Plastic TSOP (II) µPD4564841G5-A75-9JF 2M × 8 × 4 Part number (10.16mm (400)) The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. M13977EJ5V0DS00 (5th edition) Date Published January 2000 NS CP (K) Printed in Japan The mark • shows major revised points. © 1998 µPD4564441-A75, 4564841-A75 Part Number [ x4, x8 ] µPD4564841G5 - A75 NEC Memory Synchronous DRAM Memory density Minimum cycle time 64 : 64M bits 75 : 7.5 ns (133 MHz) Organization 4 : x4 8 : x8 Number of banks 4 : 4 banks Low voltage Interface A : 3.3 ± 0.3 V 1 : LVTTL Package G5 : TSOP (II) 2 Data Sheet M13977EJ5V0DS00 µPD4564441-A75, 4564841-A75 Pin Configurations /xxx indicates active low signal. [µPD4564441-A75] 54-pin Plastic TSOP (II) (10.16mm (400)) 4M words × 4 bits × 4 banks VCC NC VCCQ NC DQ0 VSSQ NC NC VCCQ NC DQ1 VSSQ NC VCC NC /WE /CAS /RAS /CS A13 A12 A10 A0 A1 A2 A3 VCC A0 to A13 Note 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Vss NC VssQ NC DQ3 VccQ NC NC VssQ NC DQ2 VccQ NC Vss NC DQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 Vss : Address inputs DQ0 to DQ3 : Data inputs / outputs CLK : Clock input CKE : Clock enable /CS : Chip select /RAS : Row address strobe /CAS : Column address strobe /WE : Write enable DQM : DQ mask enable VCC : Supply voltage VSS : Ground VCCQ : Supply voltage for DQ VSSQ : Ground for DQ A0 to A9 : Column address inputs NC : No connection A12, A13 : Bank select Note A0 to A11 : Row address inputs Data Sheet M13977EJ5V0DS00 3 µPD4564441-A75, 4564841-A75 [µPD4564841-A75] 54-pin Plastic TSOP (II) (10.16mm (400)) 2M words × 8 bits × 4 banks VCC DQ0 VCCQ NC DQ1 VSSQ NC DQ2 VCCQ NC DQ3 VSSQ NC VCC NC /WE /CAS /RAS /CS A13 A12 A10 A0 A1 A2 A3 VCC A0 to A13 Note 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Vss DQ7 VssQ NC DQ6 VccQ NC DQ5 VssQ NC DQ4 VccQ NC Vss NC DQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 Vss : Address inputs DQ0 to DQ7 : Data inputs / outputs 4 CLK : Clock input CKE : Clock enable /CS : Chip select /RAS : Row address strobe /CAS : Column address strobe /WE : Write enable DQM : DQ mask enable VCC : Supply voltage VSS : Ground VCCQ : Supply voltage for DQ VSSQ : Ground for DQ A0 to A8 : Column address inputs NC : No connection A12, A13 : Bank select Note A0 to A11 : Row address inputs Data Sheet M13977EJ5V0DS00 µPD4564441-A75, 4564841-A75 Block Diagram CLK CKE Clock Generator Bank D Bank C Mode Register Row Address Buffer & Refresh Counter Row Decoder Bank B Address Bank A Data Sheet M13977EJ5V0DS00 DQM Column Decoder & Latch Circuit Data Control Circuit Input & Output Buffer /WE Column Address Buffer & Burst Counter Latch Circuit /CAS Control Logic /RAS Command Decoder Sense Amplifier /CS DQ 5 µPD4564441-A75, 4564841-A75 CONTENTS 1. Input / Output Pin Function .............................................................................................................. 8 2. Commands ......................................................................................................................................... 9 3. Simplified State Diagram ................................................................................................................ 12 4. Truth Table ....................................................................................................................................... 13 4.1 Command Truth Table............................................................................................................................. 13 4.2 DQM Truth Table ...................................................................................................................................... 13 4.3 CKE Truth Table....................................................................................................................................... 13 4.4 Operative Command Table .................................................................................................................... 14 4.5 Command Truth Table for CKE ............................................................................................................. 17 5. Initialization ...................................................................................................................................... 18 6. Programming the Mode Register ................................................................................................... 19 7. Mode Register .................................................................................................................................. 20 7.1 Burst Length and Sequence .................................................................................................................. 21 8. Address Bits of Bank-Select and Precharge ................................................................................ 22 9. Precharge ......................................................................................................................................... 23 10. Auto Precharge ................................................................................................................................ 24 10.1 Read with Auto Precharge .................................................................................................................. 24 10.2 Write with Auto Precharge .................................................................................................................. 25 11. Read / Write Command Interval ..................................................................................................... 26 11.1 Read to Read Command Interval ........................................................................................................ 26 11.2 Write to Write Command Interval ....................................................................................................... 26 11.3 Write to Read Command Interval ........................................................................................................ 27 11.4 Read to Write Command Interval ........................................................................................................ 28 12. Burst Termination ........................................................................................................................... 29 6 12.1 Burst Stop Command .......................................................................................................................... 29 12.2 Precharge Termination ........................................................................................................................ 30 12.2.1 Precharge Termination in READ Cycle .................................................................................... 30 12.2.2 Precharge Termination in WRITE Cycle .................................................................................. 31 Data Sheet M13977EJ5V0DS00 µPD4564441-A75, 4564841-A75 13. Electrical Specifications ................................................................................................................. 32 13.1 AC Parameters for Read Timing ......................................................................................................... 37 13.2 AC Parameters for Write Timing ......................................................................................................... 39 13.3 Relationship between Frequency and Latency ................................................................................. 40 13.4 Mode Register Set ................................................................................................................................ 41 13.5 Power On Sequence and CBR (Auto) Refresh .................................................................................. 42 13.6 /CS Function ......................................................................................................................................... 43 13.7 Clock Suspension during Burst Read (using CKE Function) .......................................................... 44 13.8 Clock Suspension during Burst Write (using CKE Function) .......................................................... 45 13.9 Power Down Mode and Clock Mask ................................................................................................... 46 13.10 CBR (Auto) Refresh ............................................................................................................................. 47 13.11 Self Refresh (Entry and Exit) ............................................................................................................... 48 13.12 Random Column Read (Page with Same Bank) ................................................................................ 49 13.13 Random Column Write (Page with Same Bank) ................................................................................ 50 13.14 Random Row Read (Ping-Pong Banks) ............................................................................................. 51 13.15 Random Row Write (Ping-Pong Banks) ............................................................................................. 52 13.16 Read and Write ..................................................................................................................................... 53 13.17 Interleaved Column Read Cycle .......................................................................................................... 54 13.18 Interleaved Column Write Cycle ......................................................................................................... 55 13.19 Auto Precharge after Read Burst ........................................................................................................ 56 13.20 Auto Precharge after Write Burst ....................................................................................................... 57 13.21 Full Page Read Cycle ........................................................................................................................... 58 13.22 Full Page Write Cycle ........................................................................................................................... 59 13.23 Burst Read and Single Write (Option) ................................................................................................ 60 13.24 Full Page Random Column Read ........................................................................................................ 61 13.25 Full Page Random Column Write ....................................................................................................... 62 13.26 PRE (Precharge) Termination of Burst ............................................................................................... 63 14. Package Drawing ............................................................................................................................. 64 15. Recommended Soldering Condition ............................................................................................. 65 16. Revision History .............................................................................................................................. 66 Data Sheet M13977EJ5V0DS00 7 µPD4564441-A75, 4564841-A75 1. Input / Output Pin Function Pin name Input / Output Function CLK Input CLK is the master clock input. Other inputs signals are referenced to the CLK rising edge. CKE Input CKE determine validity of the next CLK (clock). If CKE is high, the next CLK rising edge is valid; otherwise it is invalid. If the CLK rising edge is invalid, the internal clock is not issued and the µPD4564xxx suspends operation. When the µPD4564xxx is not in burst mode and CKE is negated, the device enters /CS Input /CS low starts the command input cycle. When /CS is high, commands are ignored but operations continue. /RAS, /CAS, /WE Input /RAS, /CAS and /WE have the same symbols on conventional DRAM but different functions. For details, refer to the command table. A0 - A13 Input Row Address is determined by A0 - A13 at the CLK (clock) rising edge in the active command cycle. It does not depend on the bit organization. Column Address is determined by A0 - A9 at the CLK rising edge in the read or write command cycle. It depends on the bit organization: A0 - A9 for ×4 device, A0 - A8 for ×8 device. A12 and A13 are the bank select signal (BS). In command cycle, A12 and A13 low select bank A, A12 low and A13 high select bank B, A12 high and A13 low select bank C and then A12 and A13 high select bank D. A10 defines the precharge mode. When A10 is high in the precharge command cycle, all banks are precharged; when A10 is low, only the bank selected by A12 and A13 is precharged. When A10 is high in read or write command cycle, the precharge starts automatically after the burst access. DQM Input DQM controls I/O buffers. In read mode, DQM controls the output buffers like a conventional /OE pin. DQM high and DQM low turn the output buffers off and on, respectively. The DQM latency for the read is two clocks. In write mode, DQM controls the word mask. Input data is written to the memory cell if DQM is low but not if DQM is high. The DQM latency for the write is zero. DQ0 - DQ7 Input / Output DQ pins have the same function as I/O pins on a conventional DRAM. VCC, VSS, VCCQ, VSSQ (Power supply) VCC and VSS are power supply pins for internal circuits. VCCQ and VSSQ are power supply pins for the output buffers. power down mode. During power down mode, CKE must remain low. 8 Data Sheet M13977EJ5V0DS00 µPD4564441-A75, 4564841-A75 2. Commands Fig.1 Mode register set command Mode register set command CLK (/CS, /RAS, /CAS, /WE = Low) CKE The µPD4564xxx has a mode register that defines how the device /CS operates. In this command, A0 through A13 are the data input pins. /RAS After power on, the mode register set command must be executed to /CAS initialize the device. H /WE The mode register can be set only when all banks are in idle state. During 2 CLK (tRSC) following this command, the µPD4564xxx cannot accept any other commands. A12, A13 A10 Add Fig.2 Row address strobe and Activate command bank activate command (/CS, /RAS = Low, /CAS, /WE = High) CLK The µPD4564xxx has four banks, each with 4,096 rows. This command activates the bank selected by A12 and A13 (BS) and a row address selected by A0 through A11. CKE H /CS /RAS This command corresponds to a conventional DRAM’s /RAS falling. /CAS /WE A12, A13 (Bank select) A10 Row Add Row Precharge command Fig.3 Precharge command (/CS, /RAS, /WE = Low, /CAS = High) CLK This command begins precharge operation of the bank selected by A12 and A13 (BS). When A10 is High, all banks are precharged, CKE /CS regardless of A12 and A13. When A10 is Low, only the bank selected /RAS by A12 and A13 is precharged. /CAS After this command, the µPD4564xxx can’t accept the activate command to the precharging bank during tRP (precharge to activate command period). H /WE A12, A13 (Bank select) This command corresponds to a conventional DRAM’s /RAS rising. A10 (Precharge select) Add Data Sheet M13977EJ5V0DS00 9 µPD4564441-A75, 4564841-A75 Write command Fig.4 Column address and write command (/CS, /CAS, /WE = Low, /RAS = High) CLK If the mode register is in the burst write mode, this command sets the CKE burst start address given by the column address to begin the burst write /CS operation. The first write data in burst mode can input with this /RAS command with subsequent data on following clocks. /CAS H /WE A12, A13 (Bank select) A10 Add Read command Col. Fig.5 Column address and read command (/CS, /CAS = Low, /RAS, /WE = High) CLK Read data is available after /CAS latency requirements have been met. This command sets the burst start address given by the column address. CKE H /CS /RAS /CAS /WE A12, A13 (Bank select) A10 Add CBR (auto) refresh command Fig.6 CBR (auto) refresh command (/CS, /RAS, /CAS = Low, /WE, CKE = High) CLK CKE This command is a request to begin the CBR (auto) refresh operation. The refresh address is generated internally. /CS /RAS Before executing CBR (auto) refresh, all banks must be precharged. After this cycle, all banks will be in the idle (precharged) state and ready for a row activate command. During tRC period (from refresh command to refresh or activate command), the µPD4564xxx cannot accept any other command. /CAS /WE A12, A13 (Bank select) A10 Add 10 Col. Data Sheet M13977EJ5V0DS00 H µPD4564441-A75, 4564841-A75 Self refresh entry command Fig.7 Self refresh entry command (/CS, /RAS, /CAS, CKE = Low, /WE = High) CLK CKE After the command execution, self refresh operation continues while /CS CKE remains low. When CKE goes high, the µPD4564xxx exits the self /RAS refresh mode. /CAS During self refresh mode, refresh interval and refresh operation are performed internally, so there is no need for external control. Before executing self refresh, all banks must be precharged. /WE A12, A13 (Bank select) A10 Add Burst stop command Fig.8 Burst stop command in Full Page Mode (/CS, /WE = Low, /RAS, /CAS = High) CLK This command can stop the current burst operation. CKE H /CS /RAS /CAS /WE A12, A13 (Bank select) A10 Add No operation Fig.9 No operation CLK (/CS = Low, /RAS, /CAS, /WE = High) CKE This command is not an execution command. No operations begin or terminate by this command. H /CS /RAS /CAS /WE A12, A13 (Bank select) A10 Add Data Sheet M13977EJ5V0DS00 11 µPD4564441-A75, 4564841-A75 3. Simplified State Diagram Self Refresh LF SE xit Fe L SE MRS Mode Register Set REF IDLE CBR (auto) Refresh CK E ACT CK E Power Down CKE ROW ACTIVE BS T wit h ch arg pre ite Wr CKE Read ad WRITE CKE CKE WRITEA CKE Precharge PR E( Pre cha rge ter min atio n) Write CKE POWER ON Read READ n) atio min ter rge cha Pre E( PR WRITEA SUSPEND Au WRITE SUSPEND to W T Re h wit e ad rg Re cha pre to PRE Write Au e rit e BS Active Power Down CKE CKE CKE READA CKE READ SUSPEND READA SUSPEND Precharge Automatic sequence Manual input 12 Data Sheet M13977EJ5V0DS00 µPD4564441-A75, 4564841-A75 4. Truth Table 4.1 Command Truth Table Function Symbol CKE /CS n–1 n /RAS /CAS /WE A12, A10 A13 A11, A9 - A0 Device deselect DESL H × H × × × × × × No operation NOP H × L H H H × × × Burst stop BST H × L H H L × × × Read READ H × L H L H V L V Read with auto precharge READA H × L H L H V H V Write WRIT H × L H L L V L V Write with auto precharge WRITA H × L H L L V H V Bank activate ACT H × L L H H V V V Precharge select bank PRE H × L L H L V L × Precharge all banks PALL H × L L H L × H × Mode register set MRS H × L L L L L L V Remark H = High level, L = Low level, × = High or Low level (Don't care), V = Valid data input 4.2 DQM Truth Table Function Symbol CKE DQM n–1 n Data write / output enable ENB H × L Data mask / output disable MASK H × H Remark H = High level, L = Low level, × = High or Low level (Don't care) 4.3 CKE Truth Table Current state Function Symbol CKE n–1 /CS /RAS /CAS /WE Address n Activating Clock suspend mode entry H L × × × × × Any Clock suspend mode L L × × × × × Clock suspend Clock suspend mode exit L H × × × × × Idle CBR (auto) refresh command REF H H L L L H × Idle Self refresh entry SELF H L L L L H × Self refresh Self refresh exit L H L H H H × L H H × × × × Idle Power down entry H L × × × × × Power down Power down exit L H H × × × × L H L H H H × Remark H = High level, L = Low level, × = High or Low level (Don't care) Data Sheet M13977EJ5V0DS00 13 µPD4564441-A75, 4564841-A75 4.4 Operative Command Table Current state Idle Row active Read Write 14 Note1 (1/3) /CS /RAS /CAS /WE Address Command Action Notes H × × × × DESL Nop or power down 2 L H H × × NOP or BST Nop or power down 2 L H L H BA, CA, A10 READ/READA ILLEGAL 3 L H L L BA, CA, A10 WRIT/WRITA ILLEGAL 3 L L H H BA, RA ACT Row activating L L H L BA, A10 PRE/PALL Nop L L L H × REF/SELF CBR (auto) refresh or self refresh L L L L Op-Code MRS Mode register accessing 4 H × × × × DESL Nop L H H × × NOP or BST Nop L H L H BA, CA, A10 READ/READA Begin read : Determine AP 5 L H L L BA, CA, A10 WRIT/WRITA Begin write : Determine AP 5 L L H H BA, RA ACT ILLEGAL 3 L L H L BA, A10 PRE/PALL Precharge 6 L L L H × REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL H × × × × DESL Continue burst to end → Row active L H H H × NOP Continue burst to end → Row active L H H L × BST Burst stop → Row active L H L H BA, CA, A10 READ/READA Terminate burst, new read : Determine AP 7 L H L L BA, CA, A10 WRIT/WRITA Terminate burst, start write : Determine AP 7, 8 L L H H BA, RA ACT ILLEGAL L L H L BA, A10 PRE/PALL Terminate burst, precharging L L L H × REF/SELF ILLEGAL 3 L L L L Op-Code MRS ILLEGAL H × × × × DESL Continue burst to end → Write recovering L H H H × NOP Continue burst to end → Write recovering L H H L × BST Burst stop → Row active L H L H BA, CA, A10 READ/READA Terminate burst, start read : Determine AP 7, 8 L H L L BA, CA, A10 WRIT/WRITA Terminate burst, new write : Determine AP 7 L L H H BA, RA ACT ILLEGAL 3 L L H L BA, A10 PRE/PALL Terminate burst, precharging 9 L L L H × REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL Data Sheet M13977EJ5V0DS00 µPD4564441-A75, 4564841-A75 (2/3) Current state /CS /RAS /CAS /WE Address Command Action Notes Read with auto H × × × × DESL Continue burst to end → Precharging precharge L H H H × NOP Continue burst to end → Precharging L H H L × BST ILLEGAL L H L H BA, CA, A10 READ/READA ILLEGAL 3 L H L L BA, CA, A10 WRIT/WRITA ILLEGAL 3 L L H H BA, RA ACT ILLEGAL 3 L L H L BA, A10 PRE/PALL ILLEGAL 3 L L L H × REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL H × × × × DESL Continue burst to end → Write recovering with auto precharge L H H H × NOP Continue burst to end → Write recovering with auto precharge L H H L × BST ILLEGAL L H L H BA, CA, A10 READ/READA ILLEGAL 3 L H L L BA, CA, A10 WRIT/WRITA ILLEGAL 3 L L H H BA, RA ACT ILLEGAL 3 L L H L BA, A10 PRE/PALL ILLEGAL 3 L L L H × REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL H × × × × DESL Nop → Enter idle after tRP L H H H × NOP Nop → Enter idle after tRP L H H L × BST ILLEGAL L H L H BA, CA, A10 READ/READA ILLEGAL 3 L H L L BA, CA, A10 WRIT/WRITA ILLEGAL 3 L L H H BA, RA ACT ILLEGAL 3 L L H L BA, A10 PRE/PALL Nop → Enter idle after tRP L L L H × REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL Write with auto precharge Precharging Row activating H × × × × DESL Nop → Enter bank active after tRCD L H H H × NOP Nop → Enter bank active after tRCD L H H L × BST ILLEGAL L H L H BA, CA, A10 READ/READA ILLEGAL L H L L BA, CA, A10 WRIT/WRITA ILLEGAL 3 L L H H BA, RA ACT ILLEGAL 3, 10 L L H L BA, A10 PRE/PALL ILLEGAL 3 L L L H × REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL Data Sheet M13977EJ5V0DS00 3 15 µPD4564441-A75, 4564841-A75 (3/3) Current state Write recovering /CS /RAS /CAS /WE Address Command Action Notes H × × × × DESL Nop → Enter row active after tDPL L H H H × NOP Nop → Enter row active after tDPL L H H L × BST Nop → Enter row active after tDPL L H L H BA, CA, A10 READ/READA Start read, Determine AP L H L L BA, CA, A10 WRIT/WRITA New write, Determine AP L L H H BA, RA ACT ILLEGAL 3 L L H L BA, A10 PRE/PALL ILLEGAL 3 L L L H × REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL 8 Write recovering H × × × × DESL Nop → Enter precharge after tDPL with auto precharge L H H H × NOP Nop → Enter precharge after tDPL L H H L × BST Nop → Enter precharge after tDPL L H L H BA, CA, A10 READ/READA ILLEGAL L H L L BA, CA, A10 WRIT/WRITA ILLEGAL 3 L L H H BA, RA ACT ILLEGAL 3 L L H L BA, A10 PRE/PALL ILLEGAL L L L H × REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL H × × × × DESL Nop → Enter idle after tRC L H H × × NOP/BST Nop → Enter idle after tRC L H L × × READ/WRIT ILLEGAL L L H × × ACT/PRE/PALL ILLEGAL L L L × × REF/SELF/MRS ILLEGAL Mode register H × × × × DESL Nop → Enter idle after tRSC accessing L H H H × NOP Nop → Enter idle after tRSC L H H L × BST ILLEGAL L H L × × READ/WRIT ILLEGAL L L × × × ACT/PRE/PALL/ ILLEGAL Refreshing 3, 8 REF/SELF/MRS Notes 1. All entries assume that CKE was active (High level) during the preceding clock cycle. 2. If all banks are idle, and CKE is inactive (Low level), µPD4564xxx will enter Power down mode. All input buffers except CKE will be disabled. 3. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA), depending on the state of that bank. 4. If all banks are idle, and CKE is inactive (Low level), µPD4564xxx will enter Self refresh mode. All input buffers except CKE will be disabled. 5. Illegal if tRCD is not satisfied. 6. Illegal if tRAS is not satisfied. 7. Must satisfy burst interrupt condition. 8. Must satisfy bus contention, bus turn around, and/or write recovery requirements. 9. Must mask preceding data which don't satisfy tDPL. 10. Illegal if tRRD is not satisfied. Remark H = High level, L = Low level, × = High or Low level (Don’t care), V = Valid data 16 Data Sheet M13977EJ5V0DS00 µPD4564441-A75, 4564841-A75 4.5 Command Truth Table for CKE Current State CKE /CS /RAS /CAS /WE Address Action n–1 n H × × × × × × INVALID, CLK (n-1) would exit self refresh L H H × × × × Self refresh recovery L H L H H × × Self refresh recovery L H L H L × × ILLEGAL L H L L × × × ILLEGAL L L × × × × × Maintain self refresh H H H × × × × Idle after tRC H H L H H × × Idle after tRC H H L H L × × ILLEGAL H H L L × × × ILLEGAL H L H × × × × ILLEGAL H L L H H × × ILLEGAL H L L H L × × ILLEGAL H L L L × × × ILLEGAL H × × × × × L H H × × × × L H L H H H × L L × × × × × H H H × × × Refer to operations in Operative Command Table H H L H × × Refer to operations in Operative Command Table H H L L H × Refer to operations in Operative Command Table H H L L L H × CBR (auto) refresh H H L L L L Op-Code Refer to operations in Operative Command Table H L H × × × Refer to operations in Operative Command Table H L L H × × Refer to operations in Operative Command Table H L L L H × H L L L L H × Self refresh H L L L L L Op-Code Refer to operations in Operative Command Table L × × × × × × Power down H × × × × × × Refer to operations in Operative Command Table L × × × × × × Power down Any state other than H H × × × × listed above H L × × × × × Begin clock suspend next cycle L H × × × × × Exit clock suspend next cycle L L × × × × × Maintain clock suspend Self refresh Self refresh recovery Power down All banks idle Row active Notes INVALID, CLK (n – 1) would exit power down EXIT power down → Idle Maintain power down mode Refer to operations in Operative Command Table 1 1 1 Refer to operations in Operative Command Table 2 Notes 1. Self refresh can be entered only from the all banks idle state. Power down can be entered only from all banks idle or row active state. 2. Must be legal command as defined in Operative Command Table. Remark H = High level, L = Low level, × = High or Low level (Don't care) Data Sheet M13977EJ5V0DS00 17 µPD4564441-A75, 4564841-A75 5. Initialization The synchronous DRAM is initialized in the power-on sequence according to the following. (1) To stabilize internal circuits, when power is applied, a 100 µs or longer pause must precede any signal toggling. (2) After the pause, all banks must be precharged using the Precharge command (The Precharge all banks command is convenient). (3) Once the precharge is completed and the minimum tRP is satisfied, the mode register can be programmed. After the mode register set cycle, tRSC (2 CLK minimum) pause must be satisfied as well. (4) Two or more CBR (auto) refresh must be performed. Remarks 1. The sequence of Mode register programming and Refresh above may be transposed. 2. CKE and DQM must be held high until the Precharge command is issued to ensure data-bus Hi-Z. 18 Data Sheet M13977EJ5V0DS00 µPD4564441-A75, 4564841-A75 6. Programming the Mode Register The mode register is programmed by the Mode register set command using address bits A13 through A0 as data inputs. The register retains data until it is reprogrammed or the device loses power. The mode register has four fields; Options : A13 through A7 /CAS latency : A6 through A4 Wrap type : A3 Burst length : A2 through A0 Following mode register programming, no command can be issued before at least 2 CLK have elapsed. /CAS Latency /CAS latency is the most critical of the parameters being set. It tells the device how many clocks must elapse before the data will be available. The value is determined by the frequency of the clock and the speed grade of the device. 13.3 Relationship between Frequency and Latency shows the relationship of /CAS latency to the clock period and the speed grade of the device. Burst Length Burst Length is the number of words that will be output or input in a read or write cycle. After a read burst is completed, the output bus will become Hi-Z. The burst length is programmable as 1, 2, 4, 8 or full page. Wrap Type (Burst Sequence) The wrap type specifies the order in which the burst data will be addressed. This order is programmable as either “Sequential” or “Interleave”. The method chosen will depend on the type of CPU in the system. Some microprocessor cache systems are optimized for sequential addressing and others for interleaved addressing. 7.1 Burst Length and Sequence shows the addressing sequence for each burst length using them. Both sequences support bursts of 1, 2, 4 and 8. Additionally, sequence supports the full page length. Data Sheet M13977EJ5V0DS00 19 µPD4564441-A75, 4564841-A75 7. Mode Register 13 12 11 10 9 8 7 0 0 0 0 0 0 1 13 12 11 10 9 8 7 x x x x 1 0 0 13 12 11 10 9 8 7 1 0 6 5 4 3 2 1 0 JEDEC Standard Test Set (refresh counter test) 6 5 4 LTMODE 6 5 3 2 WT 4 3 1 0 BL 2 1 Burst Read and Single Write (for Write Through Cache) 0 Use in future 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x x x x x 1 1 V V V V V V V 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 LTMODE WT Vender Specific V = Valid x = Don’t care BL Mode Register Set Burst length Bits2-0 000 001 010 011 100 101 110 111 Wrap type 0 1 Latency mode WT = 0 1 2 4 8 R R R Full page Sequential Interleave Bits6-4 000 001 010 011 100 101 110 111 Remark R : Reserved Mode Register Set Timing CLK CKE /CS /RAS /CAS /WE A0 - A13 Mode Register Set 20 Data Sheet M13977EJ5V0DS00 /CAS latency R R R 3 R R R R WT = 1 1 2 4 8 R R R R µPD4564441-A75, 4564841-A75 7.1 Burst Length and Sequence [Burst of Two] Starting address (column address A0, binary) Sequential addressing sequence (decimal) Interleave addressing sequence (decimal) 0 0, 1 0, 1 1 1, 0 1, 0 Starting address (column address A1 - A0, binary) Sequential addressing sequence (decimal) Interleave addressing sequence (decimal) 00 0, 1, 2, 3 0, 1, 2, 3 01 1, 2, 3, 0 1, 0, 3, 2 10 2, 3, 0, 1 2, 3, 0, 1 11 3, 0, 1, 2 3, 2, 1, 0 Starting address (column address A2 - A0, binary) Sequential addressing sequence (decimal) Interleave addressing sequence (decimal) 000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 001 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6 010 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5 011 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4 100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 101 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2 110 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1 111 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0 [Burst of Four] [Burst of Eight] Full page burst is an extension of the above tables of sequential addressing, with the length being 1,024 (for 16M ×4 device) and 512 (for 8M ×8 device). Data Sheet M13977EJ5V0DS00 21 µPD4564441-A75, 4564841-A75 8. Address Bits of Bank-Select and Precharge Row A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 (Activate command) A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A12 A13 Result Select Bank A “Activate” command Select Bank B “Activate” command 0 0 0 1 1 0 Select Bank C “Activate” command 1 1 Select Bank D “Activate” command A13 A10 0 0 0 0 1 (Precharge command) A12 A13 0 0 1 0 0 1 1 1 x x Result Precharge Bank A Precharge Bank B Precharge Bank C Precharge Bank D Precharge All Banks x : Don’t care 0 Col. A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 x A12 A13 1 disables Auto-Precharge (End of Burst) enables Auto-Precharge (End of Burst) (/CAS strobes) A12 22 Data Sheet M13977EJ5V0DS00 A13 Result enables Read/Write commands for Bank A enables Read/Write commands for Bank B 0 0 0 1 1 0 enables Read/Write commands for Bank C 1 1 enables Read/Write commands for Bank D µPD4564441-A75, 4564841-A75 9. Precharge The precharge command can be issued anytime after tRAS (MIN.) is satisfied. Soon after the precharge command is issued, precharge operation performed and the synchronous DRAM enters the idle state after tRP is satisfied. The parameter tRP is the time required to perform the precharge. The earliest timing in a read cycle that a precharge command can be issued without losing any data in the burst is as follows. It is depending on the /CAS latency and clock cycle time. Burst length=4 T0 T1 T2 T3 T4 T5 T6 T7 Q3 Q4 T8 CLK /CAS latency = 3 Command Read PRE DQ Q1 Q2 Hi-Z (tRAS must be satisfied) In order to write all data to the memory cell correctly, the asynchronous parameter “t DPL” must be satisfied. The tDPL (MIN.) specification defines the earliest time that a precharge command can be issued. Minimum number of clocks is calculated by dividing tDPL (MIN.) with clock cycle time. In summary, the precharge command can be issued relative to reference clock that indicates the last data word is valid. In the following table, minus means clocks before the reference; plus means time after the reference. /CAS latency Read Write 3 –2 +tDPL (MIN.) Data Sheet M13977EJ5V0DS00 23 µPD4564441-A75, 4564841-A75 10. Auto Precharge During a read or write command cycle, A10 controls whether auto precharge is selected. A10 high in the Read or Write command (Read with Auto precharge command or Write with Auto precharge command), auto precharge is selected and begins automatically. The tRAS must be satisfied with a read with auto precharge or a write with auto precharge operation. In addition, the next activate command to the bank being precharged cannot be executed until the precharge cycle ends. In read cycle, once auto precharge has started, an activate command to the bank can be issued after tRP has been satisfied. In write cycle, the tDAL must be satisfied to issue the next activate command to the bank being precharged. The timing that begins the auto precharge cycle depends on the /CAS latency programmed into the mode register and whether read or write cycle. 10.1 Read with Auto Precharge During a read cycle, the auto precharge begins two clocks earlier (/CAS latency of 3) the last data word output. Burst length = 4 T0 T1 T2 T3 T4 T5 T6 T7 QB3 QB4 T9 T8 CLK /CAS latency = 3 Command Auto precharge starts READA B Hi-Z DQ QB1 QB2 (tRAS must be satisfied) Remark READA means Read with Auto precharge 24 Data Sheet M13977EJ5V0DS00 µPD4564441-A75, 4564841-A75 10.2 Write with Auto Precharge During a write cycle, the auto precharge starts at the timing that is equal to the value of the tDPL (MIN.) after the last data word input to the device. Burst length = 4 T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK /CAS latency = 3 Command Auto precharge starts WRITA B Hi-Z DB1 DQ DB2 DB3 DB4 tDPL(MIN.) (tRAS must be satisfied) Remark WRITA means Write with Auto Precharge In summary, the auto precharge begins relative to a reference clock that indicates the last data word is valid. In the table below, minus means clocks before the reference; plus means after the reference. /CAS latency Read Write 3 –2 +tDPL (MIN.) Data Sheet M13977EJ5V0DS00 25 µPD4564441-A75, 4564841-A75 11. Read / Write Command Interval 11.1 Read to Read Command Interval During a read cycle, when new Read command is issued, it will be effective after /CAS latency, even if the previous read operation does not completed. READ will be interrupted by another READ. The interval between the commands is 1 cycle minimum. Each Read command can be issued in every clock without any restriction. Burst length = 4, /CAS latency = 3 T0 T1 T2 T3 T4 T5 T6 T7 T8 QA1 QB1 QB2 QB3 QB4 T9 CLK Command Read A Read B Hi-Z DQ 1cycle 11.2 Write to Write Command Interval During a write cycle, when a new Write command is issued, the previous burst will terminate and the new burst will begin with a new Write command. WRITE will be interrupted by another WRITE. The interval between the commands is minimum 1 cycle. Each Write command can be issued in every clock without any restriction. Burst length = 4 T0 T1 T2 T3 T4 T5 DB2 DB3 DB4 T6 CLK Command Write A Write B DA1 DB1 Hi-Z DQ 1cycle 26 Data Sheet M13977EJ5V0DS00 T7 T8 µPD4564441-A75, 4564841-A75 11.3 Write to Read Command Interval Write command and Read command interval is also 1 cycle. Only the write data before Read command will be written. The data bus must be Hi-Z at least one cycle prior to the first DOUT. Burst length = 4 T0 T1 T2 T3 T4 T5 T6 T7 T8 QB1 QB2 QB3 QB4 CLK /CAS latency = 3 Command Write A Read B Hi-Z DQ DA1 Data Sheet M13977EJ5V0DS00 27 µPD4564441-A75, 4564841-A75 11.4 Read to Write Command Interval During a read cycle, READ can be interrupted by WRITE. The Read and Write command interval is 1 cycle minimum. There is a restriction to avoid data conflict. The Data bus must be Hi-Z using DQM before WRITE. Burst length = 4 T0 T1 T2 Read Write T3 T4 T5 D2 D3 D4 T6 T7 T8 CLK Command DQM Hi-Z D1 DQ 1cycle READ can be interrupted by WRITE. DQM must be High at least 3 clocks prior to the Write command. Burst length = 8 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 D2 D3 CLK /CAS latency = 3 Command Read Write DQM DQ Q1 Q2 D1 Hi-Z is necessary 28 Data Sheet M13977EJ5V0DS00 µPD4564441-A75, 4564841-A75 12. Burst Termination There are two methods to terminate a burst operation other than using a Read or a Write command. One is the burst stop command and the other is the precharge command. 12.1 Burst Stop Command During a read cycle, when the burst stop command is issued, the burst read data are terminated and the data bus goes to Hi-Z after the /CAS latency from the burst stop command. Burst length = X T0 T1 T2 T3 T4 T5 T6 T7 CLK Command Read BST /CAS latency = 3 Hi-Z DQ Q1 Q2 Q3 Remark BST: Burst stop command During a write cycle, when the burst stop command is issued, the burst write data are terminated and data bus goes to Hi-Z at the same clock with the burst stop command. Burst length = X T0 T1 T2 T3 T4 T5 T6 T7 CLK Command Write BST /CAS latency = 3 DQ Hi-Z D1 D2 D3 D4 Remark BST: Burst stop command Data Sheet M13977EJ5V0DS00 29 µPD4564441-A75, 4564841-A75 12.2 Precharge Termination 12.2.1 Precharge Termination in READ Cycle During a read cycle, the burst read operation is terminated by a precharge command. When the precharge command is issued, the burst read operation is terminated and precharge starts. The same bank can be activated again after tRP from the precharge command. To issue a precharge command, tRAS must be satisfied. When /CAS latency is 3, the read data will remain valid until two clocks after the precharge command. Burst length = X, /CAS latency = 3 T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK Command Read PRE ACT Hi-Z DQ Q1 Q2 Q3 Q4 tRP (tRAS must be satisfied) 30 Data Sheet M13977EJ5V0DS00 µPD4564441-A75, 4564841-A75 12.2.2 Precharge Termination in WRITE Cycle During a write cycle, the burst write operation is terminated by a precharge command. When the precharge command is issued, the burst write operation is terminated and precharge starts. The same bank can be activated again after tRP from the precharge command. To issue a precharge command, tRAS must be satisfied. When /CAS latency is 3, the write data written prior to the precharge command will be correctly stored. However, invalid data may be written at the same clock as the precharge command. To prevent this from happening, DQM must be high at the same clock as the precharge command. This will mask the invalid data. Burst length = X T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK Command Write PRE ACT DQM Hi-Z DQ D1 D2 D3 D4 D5 tRP (tRAS must be satisfied) Data Sheet M13977EJ5V0DS00 31 µPD4564441-A75, 4564841-A75 13. Electrical Specifications • All voltages are referenced to VSS (GND). • After power up, wait more than 100 µs and then, execute Power on sequence and CBR (auto) Refresh before proper device operation is achieved. Absolute Maximum Ratings Parameter Symbol Rating Unit VCC, VCCQ −0.5 to +4.6 V Voltage on any pin relative to GND VT −0.5 to +4.6 V Short circuit output current IO 50 mA Power dissipation PD 1 W Operating ambient temperature TA 0 to 70 °C Storage temperature Tstg −55 to + 125 °C Voltage on power supply pin relative to GND Caution Condition Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended Operating Conditions Parameter Symbol Supply voltage Condition VCC, VCCQ High level input voltage VIH Low level input voltage VIL Operating ambient temperature TA MIN. TYP. MAX. Unit 3.0 3.3 3.6 V 2.0 −0.3 VCC+0.3 Note2 0 Note1 V +0.8 V 70 °C Notes 1. VIH(MAX.) = VCC + 1.5 V (Pulse width ≤ 5 ns) 2. VIL(MIN.) = –1.5 V (Pulse width ≤ 5 ns) Pin Capacitance (TA = 25 °C, f = 1 MHz) Parameter Input capacitance Data input / output capacitance 32 Symbol Condition MIN. TYP. MAX. Unit pF CI1 CLK 2.5 3.5 CI2 A0 - A13, CKE, /CS, /RAS, /CAS, /WE, DQM 2.5 3.8 CI/O DQ0 - DQ7 4 6.5 Data Sheet M13977EJ5V0DS00 pF µPD4564441-A75, 4564841-A75 DC Characteristics 1 (Recommended Operating Conditions unless otherwise noted) Parameter Symbol Test condition /CAS Grade Unit Notes 1 ×4 ×8 85 90 mA CKE ≤ VIL (MAX.), tCK = 15 ns 1 1 mA CKE ≤ VIL (MAX.), tCK = ∞ 1 1 CKE ≥ VIH (MIN.), tCK = 15 ns, /CS ≥ VIH (MIN.), Input signals are changed one time during 30 ns. 20 20 CKE ≥ VIH (MIN.), tCK = ∞, Input signals are stable. 6 6 CKE ≤ VIL (MAX.), tCK = 15 ns 5 5 CKE ≤ VIL (MAX.), tCK = ∞ 4 4 CKE ≥ VIH (MIN.), tCK = 15 ns, /CS ≥ VIH (MIN.), Input signals are changed one time during 30 ns. 25 25 ICC3NS CKE ≥ VIH (MIN.), tCK = ∞ , Input signals are stable. 15 15 ICC4 tCK ≥ tCK (MIN.), Io = 0 mA, latency Operating current Maximum ICC1 Burst length = 1, CL = 3 -A75 tRC ≥ tRC (MIN.), Io = 0 mA, One bank active Precharge standby current in power down mode Precharge standby current in non power down mode ICC2P ICC2PS ICC2N ICC2NS Active standby current in power down mode Active standby current in non power down mode Operating current ICC3P ICC3PS ICC3N (Burst mode) mA mA mA CL = 3 -A75 115 135 mA 2 CL = 3 -A75 140 140 mA 3 1 1 mA All banks active CBR (auto) refresh current ICC5 tRC ≥ tRC (MIN.) Self refresh current ICC6 CKE ≤ 0.2 V Notes 1. ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, ICC1 is measured condition that addresses are changed only one time during tCK (MIN.). 2. ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, ICC4 is measured condition that addresses are changed only one time during tCK (MIN.). 3. ICC5 is measured on condition that addresses are changed only one time during tCK (MIN.). Data Sheet M13977EJ5V0DS00 33 µPD4564441-A75, 4564841-A75 DC Characteristics 2 (Recommended Operating Conditions unless otherwise noted) Parameter Symbol Test condition MIN. TYP. MAX. Unit Input leakage current II (L) 0 ≤ VI ≤ VCCQ, VCCQ = VCC All other pins not under test = 0 V −1.0 +1.0 µA Output leakage current IO (L) 0 ≤ VO ≤ VCCQ, DOUT is disabled −1.5 +1.5 µA High level output voltage VOH IO = −4 mA 2.4 Low level output voltage VOL IO = +4 mA V 0.4 V AC Characteristics (Recommended Operating Conditions unless otherwise noted) Test Conditions Parameter AC high level input voltage / low level input voltage Value Unit 2.4 / 0.4 V Input timing measurement reference level Transition time (Input rise and fall time) Output timing measurement reference level 1.4 V 1 ns 1.4 V tCK tCH CLK 2.4 V 1.4 V 0.4 V tSETUP tHOLD Input 2.4 V 1.4 V 0.4 V tAC tOH Output 34 Data Sheet M13977EJ5V0DS00 tCL Note µPD4564441-A75, 4564841-A75 Synchronous Characteristics Parameter Symbol Clock cycle time /CAS latency = 3 tCK3 Access time from CLK /CAS latency = 3 tAC3 -A75 Unit MIN. MAX. 7.5 (133 MHz) ns 5.4 ns CLK high level width tCH 2.5 ns CLK low level width tCL 2.5 ns tOH3 2.7 ns tLZ 0 ns tHZ3 3 Data-in setup time tDS 1.5 ns Data-in hold time tDH 0.8 ns Address setup time tAS 1.5 ns Address hold time tAH 0.8 ns CKE setup time tCKS 1.5 ns CKE hold time tCKH 0.8 ns CKE setup time (Power down exit) tCKSP 1.5 ns Command (/CS, /RAS, /CAS, /WE, DQM) setup time tCMS 1.5 ns Command (/CS, /RAS, /CAS, /WE, DQM) hold time tCMH 0.8 ns Data-out hold time /CAS latency = 3 Data-out low-impedance time Data-out high-impedance time /CAS latency = 3 6 Note 1 1 ns Note 1. Output load Z = 50 Ω Output 50 pF Data Sheet M13977EJ5V0DS00 35 µPD4564441-A75, 4564841-A75 Asynchronous Characteristics Symbol Parameter -A75 MIN. ★ Unit MAX. ACT to REF/ACT command period (operation) tRC 67.5 ns REF to REF/ACT command period (refresh) tRC1 67.5 ns ACT to PRE command period tRAS 45 PRE to ACT command period tRP 20 ns Delay time ACT to READ/WRITE command tRCD 20 ns ACT (one) to ACT (another) command period tRRD 15 ns Data-in to PRE command period /CAS latency = 3 tDPL3 8 ns Data-in to ACT (REF) command period (Auto precharge) /CAS latency = 3 tDAL3 1 CLK + 20 ns tRSC 2 CLK tT 0.5 Mode register set cycle time Transition time Refresh time (4,096 refresh cycles) 36 tREF Data Sheet M13977EJ5V0DS00 120,000 ns 30 ns 64 ms Note 13.1 AC Parameters for Read Timing (Manual Precharge, Burst Length = 4, /CAS Latency = 3) ,,,,,, ,,,, ,, ,, ,, , ,, , , ,, , ,, ,, , ,, , , ,, , ,, ,, , ,, , , ,, , , , ,, , ,, , , ,, ,, , , ,, , ,, , , , , ,, , ,, , , , ,, , , ,, , ,, , , ,, , ,, , , ,, , , ,, , ,, , , ,, , ,, , ,, , , ,, , ,, , ,, , , ,, , ,, , ,, , , ,, , ,, , ,, , , ,, , ,, , ,, , , ,, , ,, , ,, , , ,, , ,,, ,, ,, , , ,, , T0 tCK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 CLK tCH tCL CKE tCKH tCKS tCMS tCMH /CS /RAS /CAS ,,,, ,,,, A13 A12 A10 ADD tAS tAH DQM L tAC DQ tAC tAC tAC tHZ Hi-Z tLZ tRCD tOH tOH tRAS tOH tOH tRP tRC Activate Command for Bank A Read Command for Bank A Precharge Command for Bank A Activate Command for Bank A 37 µPD4564441-A75, 4564841-A75 Data Sheet M13977EJ5V0DS00 /WE 38 AC Parameters for Read Timing (Auto Precharge, Burst Length = 4, /CAS Latency = 3) T0 tCK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 CLK ,,,,,,,,,, ,,,,,,,,,, , , , , , , ,,,,,,,,,,,, ,,,,,, ,,,,, ,,,,,, ,,, ,,,,,,,,, ,,,,,,,, ,,,,,,,,,, tCH tCL CKE tCKS Auto Precharge Start for Bank C tCMS tCMH tCKH /CS /CAS /WE A13 A10 ADD tAS tAH DQM ,, ,, , A12 L tAC DQ tAC tAC tAC tHZ Hi-Z tRCD tLZ tOH tOH tOH tOH tRAS tRRD tRC Activate Command for Bank C Read with Auto Precharge Command for Bank C Activate Command for Bank D Activate Command for Bank C µPD4564441-A75, 4564841-A75 Data Sheet M13977EJ5V0DS00 /RAS 13.2 AC Parameters for Write Timing (Burst Length = 4, /CAS Latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK ,,,,,,,,,,,, ,,,,,,,,,,,, ,,,,,,,,,,,,, , , , , , , , ,,,,,, ,,,, ,,,, ,,,, ,,,, ,,,,,,,,,, CKE Auto Precharge Start for Bank C tCKS tCMS tCMH tCKH /RAS /CAS /WE A13 A12 A10 ADD tAS tAH DQM L tDS tDH DQ Hi-Z tRCD tDAL tRC tRRD tRCD tDPL tRP tRAS tRC 39 Activate Command for Bank C Write with Activate Auto Precharge Command Command for Bank B for Bank C Write Command for Bank B Activate Precharge Command Command for Bank C for Bank B Activate Command for Bank B µPD4564441-A75, 4564841-A75 Data Sheet M13977EJ5V0DS00 ,, ,, ,, /CS µPD4564441-A75, 4564841-A75 13.3 Relationship between Frequency and Latency Speed version -A75 Clock cycle time [ns] 7.5 Frequency [MHz] 133 /CAS latency 3 [tRCD] 3 /RAS latency (/CAS latency + [tRCD]) 6 [tRC] 9 [tRC1] 9 [tRAS] 6 [tRRD] 2 [tRP] 3 [tDPL] 2 [tDAL] 4 [tRSC] 2 40 Data Sheet M13977EJ5V0DS00 13.4 Mode Register Set (Burst Length = 4, /CAS Latency = 3) tRSC H CKE ADD ADDRESS KEY DQM DQ Hi-Z Mode Register Set Command tRP Activate Command is valid 41 µPD4564441-A75, 4564841-A75 ,, ,, ,,, ,, ,,, ,, ,, , ,, , ,, , , ,, ,, , ,, , ,, , , ,, ,, , ,, , ,, , , ,, ,, , ,, , ,, , , ,, ,, , ,, , ,, , , ,, ,, , ,, , ,, , , ,, ,, , ,, , ,, , , ,, ,, , ,, , ,, , , ,, ,, , ,, , ,, , , ,, ,, , ,, , ,, , , ,, ,, , ,, , ,, , , , ,, , ,, ,, , ,, , , ,, , ,, ,, , ,, , , ,, , , ,, ,, ,, , , ,, , ,, ,, , ,, , , ,, , ,, ,, , ,, , ,, , , ,, ,, , ,, , /WE A13 A12 Data Sheet M13977EJ5V0DS00 A10 Precharge All Banks Command T21 T20 T19 T18 T17 T16 T15 T14 T13 T12 T11 T10 T9 T8 T7 T6 T5 T4 T3 T2 T1 T0 CLK 2 CLK (MIN.) /CS /RAS /CAS 42 13.5 Power On Sequence and CBR (Auto) Refresh CLK Clock cycle is necessary CKE tRSC 2 refresh cycles are necessary ,, ,,,, ,, ,, , ,, ,, , , ,, , , , ,, , ,, ,, , , , ,, , ,, , ,, , , ,, , ,, , ,, , , ,, , ,, , ,, , , ,, , , ,, ,, , , ,, , ,, ,, , , , ,, , ,, , ,, , , ,, , ,, , ,, , , ,, , ,, , ,, , , ,, , ,, , ,, ,, ,, , , , ,, , , , ,, ,, , , ,, , , , ,, , ,, ,, ,, , ,, , , ,, , ,, , ,, , , ,, , High level is necessary /CS /RAS /CAS /WE A12 A10 ADDRESS KEY ADD DQM High level is necessary Hi-Z DQ Precharge All Banks Command is necessary Mode Register Set Command is necessary tRP CBR (Auto) Refresh Command is necessary CBR (Auto) Refresh Command is necessary tRC1 Activate Command tRC1 µPD4564441-A75, 4564841-A75 Data Sheet M13977EJ5V0DS00 A13 13.6 /CS Function (Burst Length = 4, /CAS Latency = 3) Only /CS signal needs to be issued at minimum rate T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE H /CS /RAS /WE A13 L A12 L A10 RAa ADD RAa DQM CAa CAb L Hi-Z QAa1 DQ Activate Command for Bank A Read Command for Bank A QAa2 QAa3 QAa4 DAb1 Write Command for Bank A DAb2 DAb3 DAb4 Precharge Command for Bank A 43 µPD4564441-A75, 4564841-A75 Data Sheet M13977EJ5V0DS00 /CAS 44 13.7 Clock Suspension during Burst Read (using CKE Function) (Burst Length = 4, /CAS Latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE ,,, ,,,,,, ,,, , ,, ,, ,, , ,,, , ,, ,, ,, , ,,, , ,, ,, ,, , ,,, , ,, ,, ,, , ,,, , ,, ,, ,, , ,,, , ,, ,, ,, , ,,, , ,, ,, ,, , ,,, , ,, ,, ,, , ,,, , ,, ,, ,, , ,,, , ,, ,, ,, , ,,, , ,, ,, ,, , ,,, , ,, ,, ,, , ,,, , , ,, ,, ,, , ,, , ,, ,, ,, , ,,, , ,,, , , ,, ,, ,, , , ,, ,, , ,, ,,, , ,,, , ,, ,, , ,, /CS /RAS /CAS A13 A12 A10 RAa ADD RAa DQM CAa L Hi-Z QAa1 DQ Activate Command for Bank A Read Command for Bank A QAa2 1-CLOCK SUSPENDED QAa3 QAa4 2-CLOCK SUSPENDED 3-CLOCK SUSPENDED Hi-Z (turn off) at the end of burst µPD4564441-A75, 4564841-A75 Data Sheet M13977EJ5V0DS00 /WE 13.8 Clock Suspension during Burst Write (using CKE Function) (Burst Length = 4, /CAS Latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE ,,,, ,,,,, ,,, ,, , ,, ,, , ,,, ,, , ,, ,, , ,,, ,, , ,, ,, , ,,, ,, , ,, ,, , ,,, ,, , ,, ,, , ,,, ,, , ,, ,, , ,,, ,, , ,, ,, , ,, ,,, ,, , ,, ,, , ,, ,,, ,, , ,, ,, , ,, ,,, ,, , ,, ,, , ,, ,,, ,, , ,, ,, , ,, ,, ,,, ,, , ,, ,, , ,,, , , ,, ,, ,, ,, , ,, ,, ,, ,, , ,,, , , ,, ,,, , , ,, ,, ,, , ,, ,, , ,, ,,, , , ,,, ,, , ,, , ,, /CS /RAS /CAS A13 A12 A10 RAa ADD RAa DQM CAa L Hi-Z DQ DAa1 Activate Command for Bank A DAa2 Write 1-CLOCK Command SUSPENDED for Bank A DAa3 2-CLOCK SUSPENDED DAa4 3-CLOCK SUSPENDED 45 µPD4564441-A75, 4564841-A75 Data Sheet M13977EJ5V0DS00 /WE 46 13.9 Power Down Mode and Clock Mask (Burst Length = 4, /CAS Latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK tCKSP tCKSP CKE ,,,, ,, , , , , ,, , , , , ,, , , , , ,, , , , , ,, , , , ,, , , , , ,, , , , , ,, , , , , ,, , , , , ,, , , , , , , , , , ,, , , , , ,, , , , , ,, , , , , , ,, , , , , ,, VALID /CS /RAS /CAS A13 A12 A10 RAa ADD RAa DQM CAa L Hi-Z QAa1 QAa2 QAa3 DQ Activate Command for Bank A Read Command for Bank A Power Down Mode Entry Power Down Mode Exit ACTIVE STANDBY QAa4 Precharge Command for Bank A Clock Mask Start Clock Mask End Power Down Mode Entry Power Down Mode Exit PRECHARGE STANDBY µPD4564441-A75, 4564841-A75 Data Sheet M13977EJ5V0DS00 /WE 13.10 CBR (Auto) Refresh T0 T1 T2 T3 T4 T5 T6 Tn Tn + 1 Tn + 2 Tn + 3 Tn + 4 Tn + 5 Tn + 6 Tm Tm + 1 Tm + 2 Tm + 3 Tm + 4 Tm + 5 Tm + 6 Tm + 7 CLK CKE H ,,,, ,,,,, ,,, ,, , ,, ,, , ,,, ,, , ,, ,, , ,, ,, , ,, ,,, , ,, ,, , , ,,, ,, ,, ,, ,, , ,,, , ,, ,, ,, , ,,, , ,, ,, ,, , ,,, , ,, ,, ,, , ,,, , ,, ,, ,, , ,,, , ,, ,, ,, , ,,, , ,, ,, ,, , ,,, , ,, ,, ,, , ,,, , ,, ,, ,, , ,,, , ,, ,,, ,, , ,, , ,, ,,, ,, , ,, , ,, ,, , ,, ,, , ,,, ,,, ,, , ,, ,, , /CS /RAS /CAS A13 A12 A10 ADD DQM DQ L Hi-Z Q1 Precharge CBR (Auto) Refresh Command (if necessary) 47 tRP CBR (Auto) Refresh tRC1 Activate Command tRC1 Read Command µPD4564441-A75, 4564841-A75 Data Sheet M13977EJ5V0DS00 /WE 48 13.11 Self Refresh (Entry and Exit) T1 T2 T3 T4 Tn Tn + 1 Tn + 2 Tm Tm + 1 Tk Tk + 1 Tk + 2 Tk + 3 Tk + 4 ,,,, ,,,, ,, , ,, ,, , , ,, , , ,, ,, , , ,, , , , , ,, ,, ,, , , , , ,, ,,, , ,, , , , ,, ,,, , ,, , , , ,, ,,, , ,, , , , ,, , ,,, ,, , , , ,, ,, ,, , , , , ,, ,, , ,, , , , ,, ,,, , ,, , , , ,, ,,, , ,, , , , ,, , ,, ,,,,, , , , ,, ,, , , ,, , ,, , ,, , , ,, ,, , ,, , , ,, , ,, , ,, , , ,, , T0 CLK CKE /CS /RAS /CAS A13 A12 A10 ADD DQM L Hi-Z DQ Precharge Command (if necessary) Self Refresh Entry Self Refresh Self Refresh Entry Exit (or Activate Command) Self Refresh Exit Activate Command Next Clock Enable tRP tRC1 Next Clock Enable tRC1 µPD4564441-A75, 4564841-A75 Data Sheet M13977EJ5V0DS00 /WE 13.12 Random Column Read (Page with Same Bank) (Burst Length = 4, /CAS Latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 ,,,,,, , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , CLK H CKE /CS /RAS /CAS A13 A12 A10 RAa ADD RAa DQM RAa CAa CAb CAc RAa CAa Activate Command for Bank A Read Command for Bank A L Hi-Z QAa1 QAa2 DQ Activate Command for Bank A Read Command for Bank A Read Command for Bank A QAa3 QAa4 Read Command for Bank A QAb1 QAb2 QAc1 QAc2 Precharge Command for Bank A QAc3 QAc4 49 µPD4564441-A75, 4564841-A75 Data Sheet M13977EJ5V0DS00 /WE 50 13.13 Random Column Write (Page with Same Bank) (Burst Length = 4, /CAS Latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 ,,,,,, ,,,,,,,,,,,, ,,,,,,,,,,,, ,,,,,,,,,,,, ,,,,,,,,,,,, ,,,,,,,,,,,, ,,,,,,,,,,,, ,,,,,,,,,,,, ,,,,,,,,,,,, CLK CKE H /CS /RAS /CAS A13 A12 A10 RDa ADD RDa DQM DQ RDd CDa CDb CDc RDd CDd L Hi-Z Activate Command for Bank D DDa1 Write Command for Bank D DDa2 DDa3 DDa4 DDb1 DDb2 Write Command for Bank D DDc1 Write Command for Bank D DDc2 DDc3 DDc4 Precharge Command for Bank D DDd1 DDd2 Activate Command for Bank D Write Command for Bank D µPD4564441-A75, 4564841-A75 Data Sheet M13977EJ5V0DS00 /WE 13.14 Random Row Read (Ping-Pong Banks) (Burst Length = 8, /CAS Latency = 3) T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 ,,,,, ,,,, ,,, ,, , , , ,, , , ,, ,,,, , ,, , ,, , ,,, , , , ,, ,, , ,, , ,,,, , ,, , ,, , , , ,, ,, , , ,, , ,, ,,,, , ,, , ,, , , ,, , ,, ,, , , ,, ,,,, , ,, , , ,, , , ,, ,, , , ,, , ,,,, , ,, , , ,, , , ,, ,, , , ,, , ,,,, , ,, , , ,, , , ,, ,, , , , ,, ,,,, , , ,, , ,, , ,, , ,, , ,, , , ,,,, , ,, , ,, , , T0 CLK CKE H /CS /RAS /CAS A13 A12 A10 RBa ADD RBa DQM DQ RAa CBa RAa RBb CAa RBb CBb L Hi-Z Activate Command for Bank B QBa1 QBa2 Read Command for Bank B QBa3 QBa4 Activate Command for Bank A QBa5 QBa6 Read Command for Bank A QBa7 QBa8 Precharge Command for Bank B QAa1 QAa2 QAa3 QAa4 Activate Command for Bank B QAa5 QAa6 QAa7 Read Command for Bank B Precharge Command for Bank A 51 µPD4564441-A75, 4564841-A75 Data Sheet M13977EJ5V0DS00 /WE 52 13.15 Random Row Write (Ping-Pong Banks) (Burst Length = 8, /CAS Latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK ,,, ,,,,, ,,,,, , , , ,, ,, , , ,, ,,,,,, , ,, ,, , ,, ,, , ,, ,,,,,, ,, ,,,,,, ,, , ,,,, ,, , , ,, ,, , , , ,, ,, , ,,,,, , ,, , , ,, ,, , , ,, ,, , , ,,,,, ,,, , ,, ,, , ,, , , , ,, ,, ,, , ,, ,,,,, ,, ,, , ,, , , , , ,, ,, , ,, ,,,, ,,, ,, , ,, , , ,, , ,, ,, ,, , , , ,, ,,,,, , ,, ,, , , ,, , ,, , ,, , ,,,, ,,,,,, ,,, ,, , ,, CKE H /CS /RAS /CAS A13 A12 A10 RAa ADD RAa DQM DQ RAb RDa CAa RDa RAb CDa CAb L Hi-Z Activate Command for Bank A DAa1 DAa2 Write Command for Bank A DAa3 DAa4 DAa5 DAa6 DAa7 Activate Command for Bank D DAa8 DDa1 DDa2 Write Command for Bank D DDa3 Precharge Command for Bank A DDa4 DDa5 DDa6 Activate Command for Bank A DDa7 DDa8 DAb1 Write Command for Bank A DAb2 Precharge Command for Bank D µPD4564441-A75, 4564841-A75 Data Sheet M13977EJ5V0DS00 /WE 13.16 Read and Write (Burst Length = 4, /CAS Latency = 3) T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 ,,,,,,, ,, ,, , , , ,, , ,,,, , , , ,, , ,, , , , ,, , ,,,, , , , ,, , ,, , , , ,, , ,,,, , , , ,, , , ,, , , , , ,,,, , ,, , ,,, , , ,, , , , ,, , ,,,, , , , ,, , ,, , , , ,, , ,,,, , , , ,, , ,, , ,, , , , ,,,, , , , ,, , , , ,, , ,, , ,,,, , , ,, , , T0 CLK CKE H /CS /RAS /CAS A13 A12 A10 RAa ADD RAa CAb CAa CAc Write Latency = 0 DQM L Word Masking DQ Hi-Z Activate Command for Bank A QAa1 Read Command for Bank A QAa2 QAa3 QAa4 DAb1 DAb2 DAb4 Write Command for Bank A 53 Hi-Z at the end of wrap function QAc1 QAc2 Read Command for Bank A 0-Clock Latency 2-Clock Latency µPD4564441-A75, 4564841-A75 Data Sheet M13977EJ5V0DS00 /WE 54 13.17 Interleaved Column Read Cycle (Burst Length = 4, /CAS Latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 ,,,,,, ,,,,, , ,, ,, , , ,, ,, , ,,,,, ,, , ,, ,, , , ,, ,, , , ,, ,, , , ,,,,, ,, ,, , , ,, ,, , ,, , , ,,,, ,,,,,, ,, , ,, ,,, , , ,, ,, , ,, , , ,, ,, , ,, , , ,,,,, ,, ,, , ,, , ,, , , ,, ,, ,, , ,,,,, , ,, ,, ,, , ,, ,, , , ,,,,, , ,, ,, , , ,, ,, , ,, , ,, ,, , ,,,,, ,, , , ,, ,, , ,, ,,,, ,,, , ,, ,, , ,, CLK CKE H /CS /RAS /CAS A13 A12 A10 RAa ADD RAa DQM DQ RDa CAa RDa CDa CDb CAb CDc L Hi-Z Activate Command for Bank A Aa1 Read Command for Bank A Activate Command for Bank D Aa2 Read Command for Bank D Aa3 Aa4 Read Command for Bank D Da1 Da2 Read Command for Bank D Db1 Db2 Dc1 Dc2 Ab1 Ab2 Read Command for Bank A Precharge Command for Bank D Precharge Command for Bank A Ab3 Ab4 µPD4564441-A75, 4564841-A75 Data Sheet M13977EJ5V0DS00 /WE 13.18 Interleaved Column Write Cycle (Burst Length = 4, /CAS Latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 ,,,,,,,,,,, ,, ,, , , , ,,,,, ,, ,,, , , , ,, , ,, , , , , , ,,,, ,, , , , , ,, , ,, , , ,,,, ,, ,,, ,, , , , ,, , , ,, , , ,,,,, ,, ,, , , ,, , ,, , ,, , , ,,,,, ,, , , , ,, ,, , ,, , ,, , , ,,,,, ,, , ,, , , ,, ,, , ,, , ,, , ,,,,, ,, ,, , ,, , , ,, ,, , ,, ,,,, ,,,,,,, ,, , ,, CLK CKE H /CS /RAS /CAS ,, A13 A12 A10 RAa ADD RAa DQM DQ RBa CAa RBa Aa1 Aa2 CBa CBb CAb CBc CBd L Hi-Z Activate Command for Bank A 55 Write Command for Bank A Activate Command for Bank B Aa3 Aa4 Ba1 Write Command for Bank B Ba2 Bb1 Write Command for Bank B Bb2 Bc1 Write Command for Bank B Bc2 Ab1 Write Command for Bank A Ab2 Bd1 Bd2 Bd3 Bd4 Write Command for Bank B Precharge Command for Bank A Precharge Command for Bank B µPD4564441-A75, 4564841-A75 Data Sheet M13977EJ5V0DS00 /WE 56 13.19 Auto Precharge after Read Burst (Burst Length = 4, /CAS Latency = 3) T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 ,,,,,,, , ,, , , , ,,,, , , , , , ,, , , , ,,,, , , , , , ,, , , , ,,,, , , , , , ,, , , , ,,,, , , , , , ,, , , , ,,,, , , , , , ,, , , , ,,,, , , , , , ,, , , , ,,,, , , , , , , ,, , , ,,,, , , , , T0 CLK CKE H /CS /RAS /CAS A13 A12 A10 RAa ADD RAa DQM DQ RDa CAa RDa RDb CDa CAb RDb CDb L Hi-Z Activate Command for Bank A Activate Command for Bank D Read Command for Bank A Read with Auto Precharge Command for Bank D Read with Auto Precharge Command for Bank A Auto Precharge Start for Bank D Activate Command for Bank D Read with Auto Precharge Command for Bank D Auto Precharge Start for Bank A µPD4564441-A75, 4564841-A75 Data Sheet M13977EJ5V0DS00 /WE 13.20 Auto Precharge after Write Burst (Burst Length = 4, /CAS Latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK ,,, ,,,, ,,, , , ,, , ,, ,,,, , ,,, , ,, ,, , , ,, , ,, ,,,, , , ,,, ,, , ,, , , ,, , ,, , ,,,, , ,,, ,, , ,, ,, ,, , , , , ,,,, , ,,, ,, , ,, , , ,, , ,, ,,,, , ,,, ,, , ,, , , ,, , ,, ,,,, , ,,, ,, , ,, , , ,, , ,, ,,,, , ,,, ,, , ,, , , ,, , ,, ,,,, ,,, ,, , ,, , CKE H /CS /RAS /CAS A13 A12 A10 RAa ADD RAa DQM DQ RDa CAa RDa RDb CDa CAb RDb CDb L Hi-Z Activate Command for Bank A Activate Command for Bank D Write Command for Bank A 57 Write with Auto Precharge Command for Bank D Write with Auto Precharge Command for Bank A Auto Precharge Start for Bank D Activate Command for bank D Auto Precharge Start for Bank A Write with Auto Precharge Command for Bank D µPD4564441-A75, 4564841-A75 Data Sheet M13977EJ5V0DS00 /WE 58 13.21 Full Page Read Cycle (/CAS latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 Tn Tn + 1 Tn + 2 Tn + 3 Tn + 4 Tn + 5 Tn + 6 Tn + 7 Tn + 8 Tn + 9 Tn + 10 Tn + 11 Tn + 12 CLK ,,,,, ,,,,,,,,,, ,,,,,,,,, ,,,,,,,,,, ,,,,,,,,,, ,,,,,,,,,, ,,,, ,,,,,,,, ,,,,,,,,,, ,,,,,,,,,, CKE H /CS /RAS /CAS A13 A12 A10 RAa ADD RAa DQM DQ RDa CAa RDb RDa CDa RDb L Hi-Z Activate Command for Bank A Aa Read Command for Bank A Activate Command for Bank D Aa+1 Aa-3 Aa-2 Aa-1 Read Command for Bank D Aa Aa+1 Da Da+1 Da+2 Da+3 Burst Stop Command Da+4 Da+5 Precharge Command for Bank D Activate Command for Bank D µPD4564441-A75, 4564841-A75 Data Sheet M13977EJ5V0DS00 /WE 13.22 Full Page Write Cycle (/CAS Latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 Tn Tn + 1 Tn + 2 Tn + 3 Tn + 4 Tn + 5 Tn + 6 Tn + 7 Tn + 8 Tn + 9 Tn + 10 Tn + 11 Tn + 12 Tn + 13 CLK ,,,,, ,,,,,,,,,, ,,,,,,,,,, ,,,,,,,,,, ,,,,,,,,,, ,,,,,,,,,, ,,,,,,,,,, ,,,,,,,,,, ,,,,,,,,,, CKE H /CS /RAS /CAS A13 A12 A10 RAa ADD RAa DQM DQ RDa CAa RDb RDa CDa RDb L Hi-Z Activate Command for Bank A Aa Aa+1 Write Command for Bank A Aa+2 Activate Command for Bank D Aa+3 Aa-1 Aa Aa+1 Da Da+1 Da+2 Da+3 Da+4 Da+5 Precharge Command for Bank D Write Command for Bank D Burst Stop Command 59 Burst is not completed in the Full Page Mode Activate Command for Bank D µPD4564441-A75, 4564841-A75 Data Sheet M13977EJ5V0DS00 /WE 60 13.23 Burst Read and Single Write (Option) (Burst Length = 4, /CAS Latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE H ,,,,, ,,,,,,,,,, ,,,,,,,,,, ,,,,,,,,,, ,,,,,,,,,, ,,,,,,,,,, ,,,,,,,,,, ,,,,,,,,,, ,,,,,,,,,, /CS /RAS /CAS A13 A12 A10 ADD DQM DQ Hi-Z Activate Command for Bank D Qa1 Read Command for Bank D Qa2 Qa3 Qa4 D1 Single Write Command for Bank D Qb1 Single Write Command for Bank D Read Command for Bank D Qb2 Qb4 µPD4564441-A75, 4564841-A75 Data Sheet M13977EJ5V0DS00 /WE 13.24 Full Page Random Column Read (Burst Length = Full Page, /CAS Latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK ,,,,,,,,,, ,,,,,,,,,, ,,,,,,,,,, ,,,,,,,,,, ,,,,,,,,,, ,,,,,,,,,, ,,,,,,, ,,,,,,,,,, ,,,,,,,,,, CKE H /CS /RAS /CAS A13 A12 A10 RAa RDa ADD RAa RDa DQM DQ CAa CDa CAb CDb CDc CAc L Hi-Z Activate Command for Bank A QAa1 QDa1 Activate Command for Bank D Read Command for Bank A Read Command for Bank A 61 Read Command for Bank D Read Command for Bank D QAb1 QAb2 Read Command for Bank A QDb1 QDb2 QAc1 Read Command for Bank D QAc2 QAc3 QDc1 QDc2 QDc3 Precharge Command for Bank D (PRE Termination of Burst) Hi-Z µPD4564441-A75, 4564841-A75 Data Sheet M13977EJ5V0DS00 /WE 62 13.25 Full Page Random Column Write (Burst Length = Full Page, /CAS Latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 ,,,,,, ,,,,,,,,,,,, ,,,,,,,,,,,, ,,,,,,,,,,,, ,,,,,,,,,,,, ,,,,,,,,,,,, ,,,,,,,, ,,,,,,,, ,,,,,,,,,,,, CLK CKE H /CS /RAS /CAS A13 A12 A10 RAa RDa ADD RAa RDa DQM DQ CAa CDa CAb CDb CAc DDb1 DDb2 DAc1 CDc L Hi-Z Activate Command for Bank A DAa1 DDa1 Activate Command for Bank D Write Command for Bank A DAb1 Write Command for Bank A Write Command for Bank D DAb2 Write Command for Bank D Write Command for Bank A DAc2 DAc3 DDc1 Write Command for Bank D DDc2 DDc3 DDc4 Precharge Command for Bank D (PRE Termination of Burst) µPD4564441-A75, 4564841-A75 Data Sheet M13977EJ5V0DS00 /WE 13.26 PRE (Precharge) Termination of Burst (Burst Length = 8, /CAS Latency = 3) T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 ,,,, ,, ,,,,, ,, , , , ,, , ,, , ,, , , ,,,, , ,, , ,, ,, , ,, , , ,,,, , ,, , ,, , , , ,, ,, , ,, , , ,,,, , ,, ,, , , , , ,, ,, ,, , , , ,,,, , , , ,, , ,, , ,, , ,, , ,, , ,,,, , ,, , ,, , , , ,, ,, , ,, , , ,,,, , ,, , ,, , , , ,, , ,, , ,, , ,,,, , , ,, , ,, , , ,, , , ,, , ,, ,,,, , ,, , ,, , , T0 CLK CKE H /CS /RAS /CAS A13 A12 A10 RAa ADD RAa DQM RAb CAa RAb RAc CAb RAc Write Masking L Hi-Z DAa1 DQ DAa2 DAa3 DAa4 Hi-Z DAa5 Write Command for Bank A Activate Command for Bank A PRE Termination of Burst tRCD QAb3 QAb4 Read Command for Bank A Precharge Command for Bank A tDPL 63 tRAS QAb1 QAb2 Activate Command for Bank A tRP PRE Termination of Burst tRAS Activate Command for Bank A Precharge Command for Bank A µPD4564441-A75, 4564841-A75 Data Sheet M13977EJ5V0DS00 /WE µPD4564441-A75, 4564841-A75 14. Package Drawing 54-PIN PLASTIC TSOP (II) (10.16 mm (400)) 54 28 detail of lead end F P E 1 27 A H I G J S L N C D M S B K M NOTES 1. Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. 2. Dimension "A" does not include mold fiash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15 mm per side. ITEM A MILLIMETERS 22.22±0.05 B 0.91 MAX. C 0.80 (T.P.) D 0.32+0.08 −0.07 E 0.10±0.05 F 1.1±0.1 G 1.00 H 11.76±0.20 I 10.16±0.10 J 0.80±0.20 K 0.145+0.025 −0.015 L 0.50±0.10 M 0.13 N 0.10 P 3°+7° −3° S54G5-80-9JF-2 64 Data Sheet M13977EJ5V0DS00 µPD4564441-A75, 4564841-A75 15. Recommended Soldering Condition Please consult with our sales offices for soldering conditions of the µPD4564×××. Type of Surface Mount Device µPD4564×××G5: 54-pin Plastic TSOP (II) (10.16mm (400)) Data Sheet M13977EJ5V0DS00 65 µPD4564441-A75, 4564841-A75 16. Revision History Edition / Date Page Description This edition Previous edition Type of revision Location 3rd edition / p.13 p.13 Modification Power down(CKE,/CS,/RAS,/CAS,/WE, Address) April 1999 p.17 p.17 Modification Power down(CKE,/CS,/RAS,/CAS,/WE, Address) p.32 p.32 Modification CI1 (Condition, MAX.), CI2 (Condition, MAX.) p.35 p.35 Modification Note1 p.36 p.36 Modification tRC, tRC1, tRP, tRCD, tRRD, tDPL3, tDAL3 (-A75 (MIN.), Unit) tRAS (-A75 (MIN.), -A75 (MAX.), Unit, Note) p.37 Deletion Note1 Addition 13.1 AC Parameters for Read Timing p.38 13.1 AC Parameters for Read Timing p.39 13.2 AC Parameters for Write Timing p.40 Modification p.41 Addition tDPL (-A75) 13.4 Mode Register Set p.42 13.5 Power on Sequence and CBR (Auto) Refresh p.43 13.6 /CS Function p.44 13.7 Clock Suspension during Burst Read (using CKE Function) p.45 13.8 Clock Suspension during Burst Write (using CKE Function) p.46 13.9 Power Down Mode and Clock Mask p.47 13.10 CBR (Auto) Refresh p.48 13.11 Self Refresh (Entry and Exit) p.49 13.12 Random Column Read (Page with Same Bank) p.50 13.13 Random Column Write (Page with Same Bank) p.51 13.14 Random Row Read (Ping-Pong Banks) p.52 13.15 Random Row Write (Ping-Pong Banks) p.53 13.16 Read and Write p.54 13.17 Interleaved Column Read Cycle p.55 13.18 Interleaved Column Write Cycle p.56 13.19 Auto Precharge after Read Burst p.57 13.20 Auto Precharge after Write Burst p.58 13.21 Full Page Read Cycle p.59 13.22 Full Page Write Cycle p.60 13.23 Burst Read and Single Write (Option) p.61 13.24 Full Page Random Column Read p.62 13.25 Full Page Random Column Write p.63 13.26 PRE (Precharge) Termination of Burst 4th edition / p.33 p.33 Modification ICC2PS January, 2000 p.34 p.34 Modification AC Characteristics Test Conditions p.36 p.36 Modification tRP, tRCD p.36, 40 p.36, 40 Modification tDPL p.64 p.64 Modification Package Drawing p.36 p.36 Modification tDAL3 5th edition / January, 2000 66 Data Sheet M13977EJ5V0DS00 µPD4564441-A75, 4564841-A75 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet M13977EJ5V0DS00 67 µPD4564441-A75, 4564841-A75 [MEMO] • The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. • No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. • NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. • Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. • While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. • NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. M7 98. 8