ETC UPD65882

Block Library
CMOS-N5 Family
CMOS Gate Array
(5.0 V) Ver.5.0
Document No.
Date Published
A13872EJ5V0BL00 (5th edition)
December 2001 NS CP(K)
© NEC Corporation 1998
Printed in Japan
[MEMO]
Block Library A13872EJ5V0BL
Summary of Contents
Chapter 1
Interface Block .................................................................................... 1-1
Chapter 2
Function Block .................................................................................... 2-1
Chapter 3
Scan Path Block ................................................................................. 3-1
Chapter 4
Boundary Scan Block ........................................................................ 4-1
Index
................................................................................................................ Index-1
Block Library A13872EJ5V0BL
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M8E 00. 4
Block Library A13872EJ5V0BL
Regional Information
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J01.2
Block Library A13872EJ5V0BL
Major Revisions in this Edition
Page
Throughout
Description
Complete modification of organization and values.
Block Library A13872EJ5V0BL
Preface
This library contains the 5.0 V blocks of the CMOS-N5 family. For the 3.3 V blocks, please refer to CMOS-N5
Family (3.3 V) Block Library (A15895E).
When carrying out circuit design, it is requested that the CMOS-N5 Family Design Manual (A13826E) should
also be read.
Please observe all items listed in this library (general matters, cautions, and limitations).
If you don’t observe these things, degradation in the quality and performance of LSI’s or abnormal operation may
occur.
1. Introduction
The composition of this library is as follows.
(1) Preface
The usage of this library, meanings of terminologies and some information are described.
(2) Contents
This Contents is useful when searching a block from its function.
(3) Chapter 1
Interface Block
(4) Chapter 2
Function Block
(5) Chapter 3
Scan Path Block
(6) Chapter 4
Boundary Scan Block
Chapter 1 to 4 list each block by function. Each page describes a logic symbol, a truth table, I/O data and
delay time with an integrated format as explained in 2. Data Entered in the Block Library of this Preface.
(7) Index
This Index is useful when searching a block from its name.
Block Library A13872EJ5V0BL
Preface-1
2. Data Entered in the Block Library
(1)
(a) Interface Block
(3)
(2)
(4)
(8)
(5)
(7)
(6)
(b) Function Block
(1),(4)
(2)
(8)
(7)
(5)
(6)
(1) Block type
: Name of function block
(2) Function
: Function of that block
(3) Interface level
: Interface level of that block
(4) No. of int. cells
: No. of cells used (internal cell number)
(5) Logic Diagram
: Symbol of that block
(6) Truth Table
: Truth table of that block
(7) Input, Output
: Input (Name of input pin, Fan-in), Output (Name of output pin, Fan-out)
(8) Switching speed
: Delay time of that block
Furthermore, the symbols of switching speed are as follows
A
Y (H L)
(9) (10)(11)
(9) Signal path (input to output)
(10) Input signal change
(H : Rise L : Fall Z : High impedance)
(11) Output signal change (H : Rise L : Fall Z : High impedance)
Setup time, Hold time, Release time, Removal time, and Minimum pulse width;
Preface-2
MIN
: The minimum result at the minimum condition
MAX
: The minimum result at the maximum condition
Block Library A13872EJ5V0BL
3. Propagation Delay Time (tPD)
The method shown here is a simplified calculation formula. This calculation method will give comparatively
accurate results when the load matches the following conditions. The error becomes greater as the load
capacitance increases, and the results yielded from the calculation are smaller than the values obtained from the
simulator. Therefore, note beforehand that these values should be used mainly as a general guide.
Conditions
The total F/I of the front stage of the block for delay calculation shall be within 15% of the F/O limit of the front
stage drive block.
Example
Block A
Block B
Let block B be the object of the propagation calculation. The accuracy of the simplified
calculation formula is high when the sum of the F/I connected to the output of Block A is
within 15% of the block A F/O limit.
3.1 Calculating Propagation Delay Time
3.1.1 Delay time of input buffer and internal function block
The delay time of input buffer and internal function block can be estimated from the load (number of fanouts) connected to the block including the memory block and its wiring length (wiring capacitance).
tPD = tLD0 + (ΣF/O + L) × t1
tLD0
(ns)
: Delay time of block itself when F/O = 0, L = 0
ΣF/O : Number of fan-outs of output pin
L
: Wiring capacitance of output pin (see the 3.1.3 Estimated Wiring Capacitance)
t1
: Delay coefficient of output pin
3.1.2 Delay time of output buffer
The delay time of an output buffer greatly depends on the load capacitance connected to the output pin.
The dependency of delay time on load capacitance varies with the drive capability of the buffer.
The delay time(tPD) of an output buffer can be estimated for the given load capacitance(CL) using the
following formula:
tPD = tLD0 + T × CL
(ns)
tLD0
: Reference delay time (ns)
T
: Delay coefficient
CL
: Load capacitance (pF) (CL ≥ 15 pF)
The delay time of an I/O buffer is obtained as follows.
CMOS level interface
: Threshold voltage = 1/2 VDD
Block Library A13872EJ5V0BL
Preface-3
3.1.3 Estimated Wiring Capacitance
The values of estimated wiring capacitance (converted to Fan-in mode) of CMOS-N5 family are shown in
the table below.
(1/2)
Master
Pin Pairs
1
2
3
4
5
6
µ PD65880
1.621
3.266
4.911
6.556
8.200
9.845
µ PD65881
1.641
3.356
5.070
6.785
8.500
10.214
µ PD65882
1.684
3.552
5.421
7.289
9.158
11.027
µ PD65883
1.730
3.767
5.803
7.840
9.876
11.913
µ PD65884
1.757
3.892
6.026
8.161
10.295
12.430
µ PD65885
1.780
3.997
6.213
8.430
10.647
12.863
µ PD65887
1.819
4.175
6.532
8.889
11.245
13.602
µ PD65889
1.861
4.372
6.883
9.393
11.904
14.414
µ PD65890
1.904
4.569
7.233
9.897
12.562
15.226
µ PD65893
1.943
4.747
7.552
10.356
13.160
15.965
(2/2)
Master
Preface-4
Pin Pairs
7
8
9
10
11 to 15
16 to 20
µ PD65880
11.490
13.135
14.779
16.424
24.648
32.871
µ PD65881
11.929
13.644
15.358
17.073
25.647
34.220
µ PD65882
12.895
14.764
16.632
18.501
27.844
37.187
µ PD65883
13.949
15.986
18.022
20.059
30.241
40.424
µ PD65884
14.564
16.699
18.833
20.967
31.640
42.312
µ PD65885
15.080
17.297
19.513
21.730
32.813
43.897
µ PD65887
15.958
18.315
20.672
23.028
34.811
46.594
µ PD65889
16.925
19.435
21.946
24.456
37.009
49.561
µ PD65890
17.891
20.555
23.220
25.884
39.206
52.528
µ PD65893
18.769
21.574
24.378
27.182
41.204
55.226
Block Library A13872EJ5V0BL
4. Input Interface Levels
The CMOS-N5 Family gate array family has the following four types of interface levels.
(1)
CMOS level input
(2)
TTL level input
(3)
CMOS Schmitt input
(4)
TTL Schmitt input
5. Output Drive Capability
The following levels are available for output drive capability.
CMOS level output (Six types) : (3.0 mA, 6.0 mA, 9.0 mA, 12.0 mA, 18.0 mA and 24.0 mA)
6. Multifunction Buffers
6.1 Buffers with Pull-up/Pull-down Resistors
The CMOS-N5 Family have input/output/bidirectional buffers with the following on-chip pull-up/pull-down
resistors. Select one suitable for the specific application.
(1) Pull-up resistor
: 50 kΩ (TYP.)
(2) Pull-down resistor : 50 kΩ (TYP.)
(3) Pull-up resistor
: 5 kΩ (TYP.)
6.2 Low Slew-Rate Buffers
The CMOS-N5 Family have special buffers that satisfy low noise requirement by fixing slew-rate low. These
are called low slew-rate buffers. In this library, these buffers are described with a word “Low-noise” at their
function description.
Block Library A13872EJ5V0BL
Preface-5
7. Definition of Propagation Delays
(1) Input Buffer
Input
VI
Output
VI = 2.5 V (CMOS level input)
VI = 1.5 V (TTL level input)
50%
↓
tPD
(Internal supply voltage range) × 50 %
(2) Output Buffer (L→
→H, H→
→L, Z→
→H, Z→
→L)
Input
50%
Output
(Internal supply voltage range) × 50 %
↓
VO
VO = 2.5 V (CMOS level input)
tPD
• Z → H (The beginning of VO = L level)
• Z → L (The beginning of VO = H level)
(3) Output Buffer (L→
→Z, H→
→Z)
Input
(Internal supply voltage range) × 50 %
50%
↓
VO = 0.1 V × VDD (L→Z)
Output
VO = 0.9 V × VDD (H→Z)
VO
VO
Output
tPD
Preface-6
Block Library A13872EJ5V0BL
8. Measurement Load Conditions
CMOS level output buffer
RL1
• Normal Output Voltage
RL1, RL2 = ∞, CL = 15 pF
S1
S2
CL
RL2
(S1, S2 : OFF)
• 3-State Output Buffer
RL1 = 2 kΩ, RL2 = 2 kΩ, CL = 15 pF
tP(HH), tP(LL)
: S1 = OFF, S2 = OFF
tP(ZL), tP(LZ)
: S1 = ON, S2 = OFF
tP (ZH), tP(HZ)
: S1 = OFF, S2 = ON
Block Library A13872EJ5V0BL
Preface-7
9. Timing
(1) Set up time (tsu)
The data setup time required before arrival of an active edge of a clock to read data correctly.
tsu
D
Q
C
QB
Data
Clock
(2) Hold time (th)
The data hold time required after receiving an active edge of the clock to read data correctly.
th
D
Q
Data
C
QB
Clock
(3) Release time (trel)
The time required from the release of a reset (or set) signal of a latch or flip-flop until the active edge of
the next clock pulse becomes valid.
Set
trel
D
Q
Reset/Set
Clock
C
QB
Reset
Preface-8
Block Library A13872EJ5V0BL
(4) Removal time (trem)
The time required to invalidate an active edge of a clock when a reset (or set) signal of a latch or flip-flop
is released.
Set
trem
D
Q
Reset/Set
Clock
C
QB
Reset
(5) Minimum Pulse Width (tw)
The minimum pulse width of Clock/Reset/Set required to read data correctly.
Set
D
tw
Q
tw
Clock/Reset/Set
C
QB
Reset
Block Library A13872EJ5V0BL
Preface-9
Related documents
The related documents indicated in this publication may include preliminary versions. However, preliminary
versions are not marked as such.
• CMOS-N5 Family Design Manual
: A13826E
• CMOS-N5 Family Mega Macro Design Manual
: A14759E
• CMOS-N5 Family (3.3 V) Block Library
: A15895E
• CMOS-N5 Family (5.0 V) Block Library
: This manual
• CMOS-N5 Family Memory Block Library
: A14683E
• Design For Test User’s Manual
: A14357E
• SEMICONDUCTOR SELECTION GUIDE Products & Packages (CD-ROM)
: X13769E
When designing your system, be sure to use the latest documents.
Contact your local NEC sales office or distributors.
Preface-10
Block Library A13872EJ5V0BL
Contents
Chapter 1 Interface Block
1.1 CMOS Level
Function
Input Buffer
Input Buffer with failsafe
Input Buffer with EN(AND)
Input Buffer with EN(OR)
Output Buffer
Low-noise Output Buffer
Block
Description
Cells (I/O)
Page
1-4
FI01
-
3 (1)
FID1
50kΩ Pull-down
3 (1)
FIU1
50kΩ Pull-up
3 (1)
FIW1
5kΩ Pull-up
3 (1)
FIS1W
Schmitt
6 (1)
FDS1W
Schmitt 50kΩ Pull-down
6 (1)
FUS1W
Schmitt 50kΩ Pull-up
6 (1)
FWS1W
Schmitt 5kΩ Pull-up
6 (1)
FIA1
-
3 (1)
FDA1
50kΩ Pull-down
3 (1)
FIE1W
Schmitt
6 (1)
FDE1W
Schmitt 50kΩ Pull-down
6 (1)
FN11
-
6 (1)
FN21
50kΩ Pull-down
6 (1)
FN13
-
4 (1)
FN23
50kΩ Pull-down
4 (1)
FO09
3mA
4 (1)
FO04
6mA
4 (1)
FO01
9mA
4 (1)
FO02
12mA
12 (1)
FO03
18mA
12 (1)
FO06
24mA
12 (1)
FE09
3mA
5 (1)
FE04
6mA
5 (1)
FE01
9mA
5 (1)
FE02
12mA
5 (1)
FE03
18mA
5 (1)
FE06
24mA
5 (1)
Block Library A13872EJ5V0BL
1-6
1-8
1-10
1-12
1-14
Contents-1
Function
3-State Buffer
Contents-2
Block
Description
Cells (I/O)
Page
1-16
B00T
3mA
7 (1)
B0DT
3mA 50kΩ Pull-down
7 (1)
B0UT
3mA 50kΩ Pull-up
7 (1)
B0WT
3mA 5kΩ Pull-up
7 (1)
B00E
6mA
7 (1)
B0DE
6mA 50kΩ Pull-down
7 (1)
B0UE
6mA 50kΩ Pull-up
7 (1)
B0WE
6mA 5kΩ Pull-up
7 (1)
B008
9mA
7 (1)
B0D8
9mA 50kΩ Pull-down
7 (1)
B0U8
9mA 50kΩ Pull-up
7 (1)
B0W8
9mA 5kΩ Pull-up
7 (1)
B007
12mA
17 (1)
B0D7
12mA 50kΩ Pull-down
17 (1)
B0U7
12mA 50kΩ Pull-up
17 (1)
B0W7
12mA 5kΩ Pull-up
17 (1)
B009
18mA
17 (1)
B0D9
18mA 50kΩ Pull-down
17 (1)
B0U9
18mA 50kΩ Pull-up
17 (1)
B0W9
18mA 5kΩ Pull-up
17 (1)
B00H
24mA
17 (1)
B0DH
24mA 50kΩ Pull-down
17 (1)
B0UH
24mA 50kΩ Pull-up
17 (1)
B0WH
24mA 5kΩ Pull-up
17 (1)
Block Library A13872EJ5V0BL
Function
Low-noise 3-State Buffer
N-ch open drain Buffer
N-ch open drain Buffer with failsafe
Block
Description
Cells (I/O)
Page
1-20
BE0T
3mA
7 (1)
BEDT
3mA 50kΩ Pull-down
7 (1)
BEUT
3mA 50kΩ Pull-up
7 (1)
BEWT
3mA 5kΩ Pull-up
7 (1)
BE0E
6mA
7 (1)
BEDE
6mA 50kΩ Pull-down
7 (1)
BEUE
6mA 50kΩ Pull-up
7 (1)
BEWE
6mA 5kΩ Pull-up
7 (1)
BE08
9mA
7 (1)
BED8
9mA 50kΩ Pull-down
7 (1)
BEU8
9mA 50kΩ Pull-up
7 (1)
BEW8
9mA 5kΩ Pull-up
7 (1)
BE07
12mA
7 (1)
BED7
12mA 50kΩ Pull-down
7 (1)
BEU7
12mA 50kΩ Pull-up
7 (1)
BEW7
12mA 5kΩ Pull-up
7 (1)
BE09
18mA
7 (1)
BED9
18mA 50kΩ Pull-down
7 (1)
BEU9
18mA 50kΩ Pull-up
7 (1)
BEW9
18mA 5kΩ Pull-up
7 (1)
BE0H
24mA
7 (1)
BEDH
24mA 50kΩ Pull-down
7 (1)
BEUH
24mA 50kΩ Pull-up
7 (1)
BEWH
24mA 5kΩ Pull-up
7 (1)
EXT1
9mA
4 (1)
EXT3
9mA 50kΩ Pull-up
4 (1)
EXW3
9mA 5kΩ Pull-up
4 (1)
EXT9
12mA
4 (1)
EXTB
12mA 50kΩ Pull-up
4 (1)
EXWB
12mA 5kΩ Pull-up
4 (1)
EXT5
18mA
4 (1)
EXT7
18mA 50kΩ Pull-up
4 (1)
EXW7
18mA 5kΩ Pull-up
4 (1)
EXTD
24mA
4 (1)
EXTF
24mA 50kΩ Pull-up
4 (1)
EXWF
24mA 5kΩ Pull-up
4 (1)
EXO1
9mA
4 (1)
EXO9
12mA
4 (1)
EXO5
18mA
4 (1)
EXOD
24mA
4 (1)
Block Library A13872EJ5V0BL
1-24
1-26
Contents-3
Function
I/O Buffer
Contents-4
Block
Description
Cells (I/O)
Page
1-28
B00U
3mA
10 (1)
B0DU
3mA 50kΩ Pull-down
10 (1)
B0UU
3mA 50kΩ Pull-up
10 (1)
B0WU
3mA 5kΩ Pull-up
10 (1)
B00C
6mA
10 (1)
B0DC
6mA 50kΩ Pull-down
10 (1)
B0UC
6mA 50kΩ Pull-up
10 (1)
B0WC
6mA 5kΩ Pull-up
10 (1)
B003
9mA
10 (1)
B0D3
9mA 50kΩ Pull-down
10 (1)
B0U3
9mA 50kΩ Pull-up
10 (1)
B0W3
9mA 5kΩ Pull-up
10 (1)
B001
12mA
20 (1)
B0D1
12mA 50kΩ Pull-down
20 (1)
B0U1
12mA 50kΩ Pull-up
20 (1)
B0W1
12mA 5kΩ Pull-up
20 (1)
B005
18mA
20 (1)
B0D5
18mA 50kΩ Pull-down
20 (1)
B0U5
18mA 50kΩ Pull-up
20 (1)
B0W5
18mA 5kΩ Pull-up
20 (1)
B00F
24mA
20 (1)
B0DF
24mA 50kΩ Pull-down
20 (1)
B0UF
24mA 50kΩ Pull-up
20 (1)
B0WF
24mA 5kΩ Pull-up
20 (1)
Block Library A13872EJ5V0BL
Function
Low-noise I/O Buffer
Block
Description
Cells (I/O)
Page
1-34
BE0U
3mA
10 (1)
BEDU
3mA 50kΩ Pull-down
10 (1)
BEUU
3mA 50kΩ Pull-up
10 (1)
BEWU
3mA 5kΩ Pull-up
10 (1)
BE0C
6mA
10 (1)
BEDC
6mA 50kΩ Pull-down
10 (1)
BEUC
6mA 50kΩ Pull-up
10 (1)
BEWC
6mA 5kΩ Pull-up
10 (1)
BE03
9mA
10 (1)
BED3
9mA 50kΩ Pull-down
10 (1)
BEU3
9mA 50kΩ Pull-up
10 (1)
BEW3
9mA 5kΩ Pull-up
10 (1)
BE01
12mA
10 (1)
BED1
12mA 50kΩ Pull-down
10 (1)
BEU1
12mA 50kΩ Pull-up
10 (1)
BEW1
12mA 5kΩ Pull-up
10 (1)
BE05
18mA
10 (1)
BED5
18mA 50kΩ Pull-down
10 (1)
BEU5
18mA 50kΩ Pull-up
10 (1)
BEW5
18mA 5kΩ Pull-up
10 (1)
BE0F
24mA
10 (1)
BEDF
24mA 50kΩ Pull-down
10 (1)
BEUF
24mA 50kΩ Pull-up
10 (1)
BEWF
24mA 5kΩ Pull-up
10 (1)
Block Library A13872EJ5V0BL
Contents-5
Function
Schmitt I/O Buffer
Contents-6
Block
Description
Cells (I/O)
Page
1-40
BSIUW
3mA
13 (1)
BSDUW
3mA 50kΩ Pull-down
13 (1)
BSUUW
3mA 50kΩ Pull-up
13 (1)
BSWUW
3mA 5kΩ Pull-up
13 (1)
BSICW
6mA
13 (1)
BSDCW
6mA 50kΩ Pull-down
13 (1)
BSUCW
6mA 50kΩ Pull-up
13 (1)
BSWCW
6mA 5kΩ Pull-up
13 (1)
BSI3W
9mA
13 (1)
BSD3W
9mA 50kΩ Pull-down
13 (1)
BSU3W
9mA 50kΩ Pull-up
13 (1)
BSW3W
9mA 5kΩ Pull-up
13 (1)
BSI1W
12mA
23 (1)
BSD1W
12mA 50kΩ Pull-down
23 (1)
BSU1W
12mA 50kΩ Pull-up
23 (1)
BSW1W
12mA 5kΩ Pull-up
23 (1)
BSI5W
18mA
23 (1)
BSD5W
18mA 50kΩ Pull-down
23 (1)
BSU5W
18mA 50kΩ Pull-up
23 (1)
BSW5W
18mA 5kΩ Pull-up
23 (1)
BSIFW
24mA
23 (1)
BSDFW
24mA 50kΩ Pull-down
23 (1)
BSUFW
24mA 50kΩ Pull-up
23 (1)
BSWFW
24mA 5kΩ Pull-up
23 (1)
Block Library A13872EJ5V0BL
Function
Low-noise Schmitt I/O Buffer
I/O Buffer with EN(AND)
Block
Description
Cells (I/O)
Page
1-46
BFIUW
3mA
13 (1)
BFDUW
3mA 50kΩ Pull-down
13 (1)
BFUUW
3mA 50kΩ Pull-up
13 (1)
BFWUW
3mA 5kΩ Pull-up
13 (1)
BFICW
6mA
13 (1)
BFDCW
6mA 50kΩ Pull-down
13 (1)
BFUCW
6mA 50kΩ Pull-up
13 (1)
BFWCW
6mA 5kΩ Pull-up
13 (1)
BFI3W
9mA
13 (1)
BFD3W
9mA 50kΩ Pull-down
13 (1)
BFU3W
9mA 50kΩ Pull-up
13 (1)
BFW3W
9mA 5kΩ Pull-up
13 (1)
BFI1W
12mA
13 (1)
BFD1W
12mA 50kΩ Pull-down
13 (1)
BFU1W
12mA 50kΩ Pull-up
13 (1)
BFW1W
12mA 5kΩ Pull-up
13 (1)
BFI5W
18mA
13 (1)
BFD5W
18mA 50kΩ Pull-down
13 (1)
BFU5W
18mA 50kΩ Pull-up
13 (1)
BFW5W
18mA 5kΩ Pull-up
13 (1)
BFIFW
24mA
13 (1)
BFDFW
24mA 50kΩ Pull-down
13 (1)
BFUFW
24mA 50kΩ Pull-up
13 (1)
BFWFW
24mA 5kΩ Pull-up
13 (1)
BN2U
3mA
13 (1)
BN4U
3mA 50kΩ Pull-down
13 (1)
BN2C
6mA
13 (1)
BN4C
6mA 50kΩ Pull-down
13 (1)
BN23
9mA
13 (1)
BN43
9mA 50kΩ Pull-down
13 (1)
BN21
12mA
23 (1)
BN41
12mA 50kΩ Pull-down
23 (1)
BN25
18mA
23 (1)
BN45
18mA 50kΩ Pull-down
23 (1)
BN2F
24mA
23 (1)
BN4F
24mA 50kΩ Pull-down
23 (1)
Block Library A13872EJ5V0BL
1-52
Contents-7
Function
I/O Buffer with EN(OR)
Block
Description
Cells (I/O)
Page
1-56
BN3U
3mA
11 (1)
BN5U
3mA 50kΩ Pull-down
11 (1)
BN3C
6mA
11 (1)
BN5C
6mA 50kΩ Pull-down
11 (1)
BN33
9mA
11 (1)
BN53
9mA 50kΩ Pull-down
11 (1)
BN31
12mA
21 (1)
BN51
12mA 50kΩ Pull-down
21 (1)
BN35
18mA
21 (1)
BN55
18mA 50kΩ Pull-down
21 (1)
BN3F
24mA
21 (1)
BN5F
24mA 50kΩ Pull-down
21 (1)
1.2 TTL Level
Function
Input Buffer
Input Buffer with failsafe
Input Buffer with EN(AND)
Input Buffer with EN(OR)
Contents-8
Block
Description
Cells (I/O)
Page
1-64
FI02
-
3 (1)
FID2
50kΩ Pull-down
3 (1)
FIU2
50kΩ Pull-up
3 (1)
FIW2
5kΩ Pull-up
3 (1)
FIS2W
Schmitt
6 (1)
FDS2W
Schmitt 50kΩ Pull-down
6 (1)
FUS2W
Schmitt 50kΩ Pull-up
6 (1)
FWS2W
Schmitt 5kΩ Pull-up
6 (1)
FIA2
-
3 (1)
FDA2
50kΩ Pull-down
3 (1)
FIE2W
Schmitt
6 (1)
FDE2W
Schmitt 50kΩ Pull-down
6 (1)
FN12
-
7 (1)
FN22
50kΩ Pull-down
7 (1)
FN14
-
4 (1)
FN24
50kΩ Pull-down
4 (1)
Block Library A13872EJ5V0BL
1-66
1-68
1-70
Function
I/O Buffer
Block
Description
Cells (I/O)
Page
1-72
B00V
3mA
10 (1)
B0DV
3mA 50kΩ Pull-down
10 (1)
B0UV
3mA 50kΩ Pull-up
10 (1)
B0WV
3mA 5kΩ Pull-up
10 (1)
B00D
6mA
10 (1)
B0DD
6mA 50kΩ Pull-down
10 (1)
B0UD
6mA 50kΩ Pull-up
10 (1)
B0WD
6mA 5kΩ Pull-up
10 (1)
B004
9mA
10 (1)
B0D4
9mA 50kΩ Pull-down
10 (1)
B0U4
9mA 50kΩ Pull-up
10 (1)
B0W4
9mA 5kΩ Pull-up
10 (1)
B002
12mA
20 (1)
B0D2
12mA 50kΩ Pull-down
20 (1)
B0U2
12mA 50kΩ Pull-up
20 (1)
B0W2
12mA 5kΩ Pull-up
20 (1)
B006
18mA
20 (1)
B0D6
18mA 50kΩ Pull-down
20 (1)
B0U6
18mA 50kΩ Pull-up
20 (1)
B0W6
18mA 5kΩ Pull-up
20 (1)
B00G
24mA
20 (1)
B0DG
24mA 50kΩ Pull-down
20 (1)
B0UG
24mA 50kΩ Pull-up
20 (1)
B0WG
24mA 5kΩ Pull-up
20 (1)
Block Library A13872EJ5V0BL
Contents-9
Function
Low-noise I/O Buffer
Contents-10
Block
Description
Cells (I/O)
Page
1-78
BE0V
3mA
10 (1)
BEDV
3mA 50kΩ Pull-down
10 (1)
BEUV
3mA 50kΩ Pull-up
10 (1)
BEWV
3mA 5kΩ Pull-up
10 (1)
BE0D
6mA
10 (1)
BEDD
6mA 50kΩ Pull-down
10 (1)
BEUD
6mA 50kΩ Pull-up
10 (1)
BEWD
6mA 5kΩ Pull-up
10 (1)
BE04
9mA
10 (1)
BED4
9mA 50kΩ Pull-down
10 (1)
BEU4
9mA 50kΩ Pull-up
10 (1)
BEW4
9mA 5kΩ Pull-up
10 (1)
BE02
12mA
10 (1)
BED2
12mA 50kΩ Pull-down
10 (1)
BEU2
12mA 50kΩ Pull-up
10 (1)
BEW2
12mA 5kΩ Pull-up
10 (1)
BE06
18mA
10 (1)
BED6
18mA 50kΩ Pull-down
10 (1)
BEU6
18mA 50kΩ Pull-up
10 (1)
BEW6
18mA 5kΩ Pull-up
10 (1)
BE0G
24mA
10 (1)
BEDG
24mA 50kΩ Pull-down
10 (1)
BEUG
24mA 50kΩ Pull-up
10 (1)
BEWG
24mA 5kΩ Pull-up
10 (1)
Block Library A13872EJ5V0BL
Function
Schmitt I/O Buffer
Block
Description
Cells (I/O)
Page
1-84
BSIVW
3mA
13 (1)
BSDVW
3mA 50kΩ Pull-down
13 (1)
BSUVW
3mA 50kΩ Pull-up
13 (1)
BSWVW
3mA 5kΩ Pull-up
13 (1)
BSIDW
6mA
13 (1)
BSDDW
6mA 50kΩ Pull-down
13 (1)
BSUDW
6mA 50kΩ Pull-up
13 (1)
BSWDW
6mA 5kΩ Pull-up
13 (1)
BSI4W
9mA
13 (1)
BSD4W
9mA 50kΩ Pull-down
13 (1)
BSU4W
9mA 50kΩ Pull-up
13 (1)
BSW4W
9mA 5kΩ Pull-up
13 (1)
BSI2W
12mA
23 (1)
BSD2W
12mA 50kΩ Pull-down
23 (1)
BSU2W
12mA 50kΩ Pull-up
23 (1)
BSW2W
12mA 5kΩ Pull-up
23 (1)
BSI6W
18mA
23 (1)
BSD6W
18mA 50kΩ Pull-down
23 (1)
BSU6W
18mA 50kΩ Pull-up
23 (1)
BSW6W
18mA 5kΩ Pull-up
23 (1)
BSIGW
24mA
23 (1)
BSDGW
24mA 50kΩ Pull-down
23 (1)
BSUGW
24mA 50kΩ Pull-up
23 (1)
BSWGW
24mA 5kΩ Pull-up
23 (1)
Block Library A13872EJ5V0BL
Contents-11
Function
Low-noise Schmitt I/O Buffer
I/O Buffer with EN(AND)
Contents-12
Block
Description
Cells (I/O)
Page
1-90
BFIVW
3mA
13 (1)
BFDVW
3mA 50kΩ Pull-down
13 (1)
BFUVW
3mA 50kΩ Pull-up
13 (1)
BFWVW
3mA 5kΩ Pull-up
13 (1)
BFIDW
6mA
13 (1)
BFDDW
6mA 50kΩ Pull-down
13 (1)
BFUDW
6mA 50kΩ Pull-up
13 (1)
BFWDW
6mA 5kΩ Pull-up
13 (1)
BFI4W
9mA
13 (1)
BFD4W
9mA 50kΩ Pull-down
13 (1)
BFU4W
9mA 50kΩ Pull-up
13 (1)
BFW4W
9mA 5kΩ Pull-up
13 (1)
BFI2W
12mA
13 (1)
BFD2W
12mA 50kΩ Pull-down
13 (1)
BFU2W
12mA 50kΩ Pull-up
13 (1)
BFW2W
12mA 5kΩ Pull-up
13 (1)
BFI6W
18mA
13 (1)
BFD6W
18mA 50kΩ Pull-down
13 (1)
BFU6W
18mA 50kΩ Pull-up
13 (1)
BFW6W
18mA 5kΩ Pull-up
13 (1)
BFIGW
24mA
13 (1)
BFDGW
24mA 50kΩ Pull-down
13 (1)
BFUGW
24mA 50kΩ Pull-up
13 (1)
BFWGW
24mA 5kΩ Pull-up
13 (1)
BN2V
3mA
14 (1)
BN4V
3mA 50kΩ Pull-down
14 (1)
BN2D
6mA
14 (1)
BN4D
6mA 50kΩ Pull-down
14 (1)
BN24
9mA
14 (1)
BN44
9mA 50kΩ Pull-down
14 (1)
BN22
12mA
24 (1)
BN42
12mA 50kΩ Pull-down
24 (1)
BN26
18mA
24 (1)
BN46
18mA 50kΩ Pull-down
24 (1)
BN2G
24mA
24 (1)
BN4G
24mA 50kΩ Pull-down
24 (1)
Block Library A13872EJ5V0BL
1-96
Function
Block
I/O Buffer with EN(OR)
Description
Cells (I/O)
Page
1-100
BN3V
3mA
11 (1)
BN5V
3mA 50kΩ Pull-down
11 (1)
BN3D
6mA
11 (1)
BN5D
6mA 50kΩ Pull-down
11 (1)
BN34
9mA
11 (1)
BN54
9mA 50kΩ Pull-down
11 (1)
BN32
12mA
21 (1)
BN52
12mA 50kΩ Pull-down
21 (1)
BN36
18mA
21 (1)
BN56
18mA 50kΩ Pull-down
21 (1)
BN3G
24mA
21 (1)
BN5G
24mA 50kΩ Pull-down
21 (1)
1.3 Oscillator
Function
Block
Description
Cells (I/O)
Page
Oscillator Input Buffer
OSI1
-
0 (1)
1-108
Oscillator Input Buffer for Enable
OSI2
-
0 (1)
1-110
Oscillator Input Buffer for OSO9
OSI4
-
0 (1)
1-112
Oscillator Output Buffer (Internal Feedback Resistor)
OSO1
-
0 (1)
1-114
Oscillator Output Buffer (for Enable Type)
OSO7
-
0 (1)
1-116
Oscillator Output Buffer (External Feedback Resistor)
OSO9
-
0 (1)
1-118
Block Library A13872EJ5V0BL
Contents-13
Chapter 2 Function Block
2.1 Level Generator
Function
H, L Level Generator
Block
F091
Description
-
Cells (I/O)
Page
1 (-)
2-4
Cells (I/O)
Page
2-10
2.2 Inverter, Buffer, CTS Driver, Delay Gate
Function
Inverter
Buffer
CTS Driver (Inverter Type)
Delay Gate
Contents-14
Block
Description
L101
Single Out, Low Power
1 (-)
F101
Single Out
1 (-)
F102
Single Out, x2-drive
2 (-)
F143
Single Out, x3-drive
3 (-)
F144
Single Out, x4-drive
4 (-)
F145
Single Out, x5-drive
5 (-)
F146
Single Out, x6-drive
6 (-)
F148
Single Out, x8-drive
12 (-)
L111
Single Out, Low Power
1 (-)
F111
Single Out
2 (-)
F112
Single Out, x2-drive
3 (-)
F153
Single Out, x3-drive
4 (-)
F154
Single Out, x4-drive
5 (-)
F158
Single Out, x8-drive
11 (-)
FC42
Single type
132 (-)
FC82
Single type, x2-drive
396 (-)
FC44
Double type
340 (-)
FC84
Double type, x2-drive
1020 (-)
F131
-
6 (-)
F132
-
10 (-)
Block Library A13872EJ5V0BL
2-12
2-14
2-16
2.3 OR(NOR)
Function
2-Input NOR
3-Input NOR
4-Input NOR
5-Input NOR
6-Input NOR
8-Input NOR
2-Input OR
3-Input OR
4-Input OR
5-Input OR
6-Input OR
8-Input OR
Block
Description
Cells (I/O)
Page
2-22
L202
Low Power
1 (-)
F202
-
2 (-)
F222
x2-drive
4 (-)
F282
x4-drive
6 (-)
L203
Low Power
2 (-)
F203
-
3 (-)
F223
x2-drive
6 (-)
L204
Low Power
2 (-)
F204
-
4 (-)
L205
Low Power
4 (-)
F205
-
5 (-)
F225
x2-drive
6 (-)
F206
-
5 (-)
F226
x2-drive
6 (-)
L208
Low Power
7 (-)
F208
-
7 (-)
F228
x2-drive
8 (-)
L212
Low Power
2 (-)
F212
-
2 (-)
F232
x2-drive
3 (-)
F252
x4-drive
6 (-)
L213
Low Power
2 (-)
F213
-
3 (-)
F233
x2-drive
4 (-)
L214
Low Power
3 (-)
F214
-
3 (-)
F234
x2-drive
4 (-)
L215
Low Power
4 (-)
F215
-
5 (-)
F235
x2-drive
7 (-)
L216
Low Power
4 (-)
F216
-
5 (-)
F236
x2-drive
7 (-)
L218
Low Power
6 (-)
F218
-
8 (-)
F238
x2-drive
9 (-)
Block Library A13872EJ5V0BL
2-24
2-26
2-28
2-30
2-32
2-34
2-36
2-38
2-40
2-42
2-44
Contents-15
2.4 AND(NAND)
Function
2-Input NAND
3-Input NAND
4-Input NAND
5-Input NAND
6-Input NAND
8-Input NAND
2-Input AND
3-Input AND
4-Input AND
5-Input AND
6-Input AND
8-Input AND
Contents-16
Block
Description
Cells (I/O)
Page
2-50
L302
Low Power
1 (-)
F302
-
2 (-)
F322
x2-drive
4 (-)
F382
x4-drive
6 (-)
L303
Low Power
2 (-)
F303
-
3 (-)
F323
x2-drive
6 (-)
L304
Low Power
2 (-)
F304
-
4 (-)
F324
x2-drive
8 (-)
F305
-
5 (-)
F325
x2-drive
6 (-)
F306
-
5 (-)
F326
x2-drive
6 (-)
F308
-
6 (-)
F328
x2-drive
7 (-)
L312
Low Power
2 (-)
F312
-
2 (-)
F332
x2-drive
3 (-)
F352
x4-drive
6 (-)
L313
Low Power
2 (-)
F313
-
3 (-)
F333
x2-drive
4 (-)
L314
Low Power
3 (-)
F314
-
3 (-)
F334
x2-drive
4 (-)
L315
Low Power
4 (-)
F315
-
5 (-)
F335
x2-drive
7 (-)
L316
Low Power
4 (-)
F316
-
5 (-)
F336
x2-drive
7 (-)
L318
Low Power
5 (-)
F318
-
6 (-)
F338
x2-drive
8 (-)
Block Library A13872EJ5V0BL
2-52
2-54
2-56
2-58
2-60
2-62
2-64
2-66
2-68
2-70
2-72
2.5 AND-NOR
Function
1-2-Input AND-NOR
1-1-2-Input AND-NOR
1-3-Input AND-NOR
2-2-Input AND-NOR
2-2-2-Input AND-NOR
2-3-Input AND-NOR
1-2-2-Input AND-NOR
2-2-2-2-Input AND-NOR
Block
Description
Cells (I/O)
Page
2-78
L421
Low Power
2 (-)
F421
-
3 (-)
L422
Low Power
2 (-)
F422
-
4 (-)
L423
Low Power
2 (-)
F423
-
4 (-)
L424
Low Power
2 (-)
F424
-
4 (-)
L425
Low Power
3 (-)
F425
-
6 (-)
L427
Low Power
3 (-)
F427
-
5 (-)
L428
Low Power
3 (-)
F428
-
5 (-)
2-80
2-82
2-84
2-86
2-88
2-90
L429
Low Power
6 (-)
F429
-
6 (-)
L440
Low Power
3 (-)
F440
-
5 (-)
L441
Low Power
5 (-)
F441
-
7 (-)
L444
Low Power
8 (-)
F444
-
8 (-)
L446
Low Power
4 (-)
F446
-
5 (-)
L447
Low Power
5 (-)
F447
-
5 (-)
L448
Low Power
5 (-)
F448
-
5 (-)
3-3-3-3-Input AND-NOR
F449
-
8 (-)
2-106
3-3-3-Input AND-NOR
L460
Low Power
6 (-)
2-108
1-4-Input AND-NOR
1-5-Input AND-NOR
4-4-4-Input AND-NOR
1-1-1-2-Input AND-NOR
1-1-1-3-Input AND-NOR
1-1-2-2-Input AND-NOR
2-92
2-94
2-96
2-98
2-100
2-102
2-104
F460
-
7 (-)
1-2-3-Input AND-NOR
F462
-
6 (-)
2-110
1-1-3-Input AND-NOR
L463
Low Power
3 (-)
2-112
F463
-
5 (-)
L464
Low Power
5 (-)
F464
-
5 (-)
1-1-1-1-2-Input AND-NOR
F465
-
5 (-)
2-116
4-4-4-4-Input AND-NOR
F466
-
10 (-)
2-118
1-1-4-Input AND-NOR
Block Library A13872EJ5V0BL
2-114
Contents-17
2.6 OR-NAND
Function
1-4-Input OR-NAND
Block
Description
Cells (I/O)
Page
2-124
L430
Low Power
4 (-)
F430
-
5 (-)
L431
Low Power
2 (-)
F431
-
3 (-)
L432
Low Power
2 (-)
F432
-
4 (-)
L433
Low Power
2 (-)
F433
-
4 (-)
L434
Low Power
2 (-)
F434
-
4 (-)
2-3-Input OR-NAND
F435
-
5 (-)
2-134
3-3-Input OR-NAND
L436
Low Power
3 (-)
2-136
F436
-
6 (-)
1-2-2-Input OR-NAND
F437
-
5 (-)
2-138
2-2-2-Input OR-NAND
F438
-
6 (-)
2-140
1-5-Input OR-NAND
L439
Low Power
5 (-)
2-142
F439
-
6 (-)
L450
Low Power
5 (-)
F450
-
6 (-)
L451
Low Power
7 (-)
F451
-
8 (-)
L452
Low Power
4 (-)
F452
-
5 (-)
L453
Low Power
5 (-)
F453
-
6 (-)
4-4-4-Input OR-NAND
F457
-
10 (-)
2-152
1-1-1-2-Input OR-NAND
L458
Low Power
3 (-)
2-154
F458
-
5 (-)
L459
Low Power
5 (-)
F459
-
5 (-)
1-2-Input OR-NAND
1-1-2-Input OR-NAND
1-3-Input OR-NAND
2-2-Input OR-NAND
2-4-Input OR-NAND
4-4-Input OR-NAND
1-1-3-Input OR-NAND
1-1-4-Input OR-NAND
1-1-1-3-Input OR-NAND
2-126
2-128
2-130
2-132
2-144
2-146
2-148
2-150
2-156
1-1-1-1-2-Input OR-NAND
F490
-
5 (-)
2-158
1-2-3-Input OR-NAND
L491
Low Power
5 (-)
2-160
F491
-
5 (-)
L493
Low Power
6 (-)
F493
-
7 (-)
1-1-2-2-Input OR-NAND
F495
-
6 (-)
2-164
3-3-3-3-Input OR-NAND
F496
-
8 (-)
2-166
4-4-4-4-Input OR-NAND
F498
-
14 (-)
2-168
3-3-3-Input OR-NAND
Contents-18
Block Library A13872EJ5V0BL
2-162
2.7 Exclusive OR, Exclusive NOR
Function
2-Input Exclusive OR
3-Input Exclusive OR
2-Input Exclusive NOR
3-Input Exclusive NOR
Block
Description
Cells (I/O)
Page
2-174
L511
Low Power
3 (-)
F511
-
4 (-)
L516
Low Power
6 (-)
F516
-
7 (-)
L512
Low Power
3 (-)
F512
-
4 (-)
L517
Low Power
7 (-)
F517
-
7 (-)
Block Library A13872EJ5V0BL
2-176
2-178
2-180
Contents-19
2.8 Adder, 3-State Buffer, Decoder, Multiplexer, Generator
Function
Block
Description
Cells (I/O)
Page
1-Bit Full Adder
F521
-
9 (-)
2-186
4-Bit Full Adder
F523
-
32 (-)
2-188
4-Bit Look Ahead Carry Generator
F526
-
34 (-)
2-192
4-Bit Carry Look Ahead Adder
F527
-
69 (-)
2-194
3-State Buffer
L531
with EN, Low Power
4 (-)
2-198
F531
with EN
5 (-)
F533
with EN, x2-drive
7 (-)
F53F
with EN, x4-drive
11 (-)
L532
with ENB, Low Power
4 (-)
F532
with ENB
5 (-)
F534
with ENB, x2-drive
7 (-)
F53G
with ENB, x4-drive
11 (-)
F541
Inverter with EN
6 (-)
F543
Inverter with EN, x2-drive
8 (-)
F54F
Inverter with EN, x4-drive
12 (-)
F542
Inverter with ENB
6 (-)
F544
Inverter with ENB, x2-drive
8 (-)
F54G
Inverter with ENB, x4-drive
12 (-)
L560
Positive Out, Low Power
6 (-)
F560
Positive Out
10 (-)
L561
Negative Out, Low Power
6 (-)
F561
Negative Out
10 (-)
L565
Low Power
3 (-)
F565
-
4 (-)
L571
with ENB, Low Power
4 (-)
F571
with ENB
6 (-)
F564
-
8 (-)
F570
with ENB
10 (-)
F563
-
18 (-)
F569
with ENB
18 (-)
2 to 4 Decoder
2 to 1 Multiplexer (Positive Out)
4 to 1 Multiplexer (Positive Out)
8 to 1 Multiplexer (Positive Out)
Quad 2 to 1 Multiplexer (Negative Out)
2-202
2-206
2-208
2-210
L572
with ENB, Low Power
15 (-)
F572
with ENB
17 (-)
8-Bit Odd Parity Generator
F581
-
19 (-)
2-218
8-Bit Even Parity Generator
F582
-
19 (-)
2-220
Contents-20
Block Library A13872EJ5V0BL
2-214
2.9 RS-Latch, RS-F/F
Function
Block
Description
Cells (I/O)
Page
RS-Latch
F595
-
5 (-)
2-226
RS-F/F with R, S
F596
-
11 (-)
2-228
Cells (I/O)
Page
2-234
2.10 D-Latch
Function
D-Latch
Block
Description
F601
-
6 (-)
L601
Q Out, Low Power
4 (-)
F601NQ
Q Out
5 (-)
F601NB
QB Out
5 (-)
D-Latch, High Speed
F6R1
-
6 (-)
2-236
D-Latch with R
F602
-
6 (-)
2-238
L602
Q Out, Low Power
5 (-)
F602NQ
Q Out
6 (-)
F602NB
QB Out
5 (-)
D-Latch with R, High Speed
F6R2
-
7 (-)
2-240
D-Latch with RB
F603
-
7 (-)
2-242
L603
Q Out, Low Power
5 (-)
F603NQ
Q Out
5 (-)
F603NB
QB Out
6 (-)
D-Latch with RB, High Speed
F6R5
-
6 (-)
2-244
D-Latch with SB
F60K
-
7 (-)
2-246
F60KNQ
Q Out
6 (-)
F60KNB
QB Out
5 (-)
F60J
-
7 (-)
F60JNQ
Q Out
6 (-)
F60JNB
QB Out
6 (-)
F604
-
6 (-)
L604
Q Out, Low Power
4 (-)
F604NQ
Q Out
5 (-)
F604NB
QB Out
5 (-)
D-Latch (GB), High Speed
F6R8
-
6 (-)
2-254
D-Latch (GB) with RB
F605
-
7 (-)
2-256
D-Latch with RB, SB
D-Latch (GB)
D-Latch (GB) with RB, High Speed
L605
Q Out, Low Power
5 (-)
F605NQ
Q Out
5 (-)
F605NB
QB Out
6 (-)
F6R9
-
6 (-)
Block Library A13872EJ5V0BL
2-248
2-252
2-258
Contents-21
2.11 D-F/F
Function
D-F/F
D-F/F with R
D-F/F with S
D-F/F with R, S
D-F/F with RB
D-F/F with SB
D-F/F with RB, SB
D-F/F (CB)
D-F/F (CB) with RB
D-F/F (CB) with SB
D-F/F (CB) with RB, SB
D-F/F with 2 to 1 Selector
Contents-22
Block
Description
Cells (I/O)
Page
2-264
F641
-
8 (-)
L641
Q Out, Low Power
6 (-)
F641NQ
Q Out
7 (-)
F641NB
QB Out
7 (-)
F642
-
9 (-)
F642NQ
Q Out
8 (-)
F642NB
QB Out
8 (-)
F643
-
9 (-)
F643NQ
Q Out
8 (-)
F643NB
QB Out
8 (-)
F644
-
10 (-)
L644
Q Out, Low Power
8 (-)
F644NQ
Q Out
9 (-)
F644NB
QB Out
9 (-)
F615
-
9 (-)
L645
Q Out, Low Power
7 (-)
F615NQ
Q Out
8 (-)
F615NB
QB Out
8 (-)
F616
-
9 (-)
F616NQ
Q Out
8 (-)
F616NB
QB Out
8 (-)
F647
-
10 (-)
L647
Q Out, Low Power
8 (-)
F647NQ
Q Out
9 (-)
F647NB
QB Out
9 (-)
F661
-
8 (-)
L661
Q Out, Low Power
6 (-)
F661NQ
Q Out
7 (-)
F661NB
QB Out
7 (-)
F665
-
9 (-)
F665NQ
Q Out
8 (-)
F665NB
QB Out
8 (-)
F666
-
9 (-)
F666NQ
Q Out
8 (-)
F666NB
QB Out
8 (-)
F667
-
10 (-)
L667
Q Out, Low Power
8 (-)
F667NQ
Q Out
9 (-)
F667NB
QB Out
9 (-)
F641S
-
10 (-)
F641SQ
Q Out
9 (-)
F641SB
QB Out
9 (-)
Block Library A13872EJ5V0BL
2-266
2-268
2-270
2-272
2-274
2-276
2-278
2-280
2-282
2-284
2-286
Function
D-F/F with R, 2 to 1 Selector
D-F/F with S, 2 to 1 Selector
D-F/F with R, S, 2 to 1 Selector
D-F/F with RB, 2 to 1 Selector
D-F/F with SB, 2 to 1 Selector
D-F/F with RB, SB, 2 to 1 Selector
D-F/F (CB) with 2 to 1 Selector
D-F/F (CB) with RB, 2 to 1 Selector
D-F/F (CB) with SB, 2 to 1 Selector
D-F/F (CB) with RB, SB, 2 to 1 Selector
D-F/F with Hold
D-F/F with RB, Hold
Block
Description
Cells (I/O)
Page
2-288
F642S
-
11 (-)
F642SQ
Q Out
10 (-)
F642SB
QB Out
10 (-)
F643S
-
11 (-)
F643SQ
Q Out
10 (-)
F643SB
QB Out
10 (-)
F644S
-
12 (-)
F644SQ
Q Out
11 (-)
F644SB
QB Out
11 (-)
F615S
-
11 (-)
F615SQ
Q Out
10 (-)
F615SB
QB Out
10 (-)
F616S
-
11 (-)
F616SQ
Q Out
10 (-)
F616SB
QB Out
10 (-)
F647S
-
12 (-)
F647SQ
Q Out
11 (-)
F647SB
QB Out
11 (-)
F661S
-
10 (-)
F661SQ
Q Out
9 (-)
F661SB
QB Out
9 (-)
F665S
-
11 (-)
F665SQ
Q Out
10 (-)
F665SB
QB Out
10 (-)
F666S
-
11 (-)
F666SQ
Q Out
10 (-)
F666SB
QB Out
10 (-)
F667S
-
12 (-)
F667SQ
Q Out
11 (-)
F667SB
QB Out
11 (-)
F641H
-
10 (-)
F641HQ
Q Out
9 (-)
F641HB
QB Out
9 (-)
F615H
-
11 (-)
2-290
2-292
2-294
2-296
2-298
2-300
2-302
2-304
2-306
2-308
2-310
F615HQ
Q Out
10 (-)
F615HB
QB Out
10 (-)
F616H
-
11 (-)
F616HQ
Q Out
10 (-)
F616HB
QB Out
10 (-)
F647H
-
12 (-)
F647HQ
Q Out
11 (-)
F647HB
QB Out
11 (-)
D-F/F (CB) with 2 to 1 Selector(2 CTRL), RB
F673
-
11 (-)
2-316
D-F/F (CB) with Hold, 2 to 1 Selector(2 CTRL), RB
F674
-
12 (-)
2-318
D-F/F with SB, Hold
D-F/F with RB, SB, Hold
Block Library A13872EJ5V0BL
2-312
2-314
Contents-23
2.12 T-F/F, JK-F/F
Function
T-F/F with R, S
Block
Description
Cells (I/O)
Page
2-324
F744
-
9 (-)
L744
Q Out, Low Power
7 (-)
F744NQ
Q Out
8 (-)
F745
-
8 (-)
F745NQ
Q Out
7 (-)
F747
-
9 (-)
L747
Q Out, Low Power
7 (-)
F747NQ
Q Out
8 (-)
T-F/F with Data-Hold R, S
F791
-
12 (-)
2-330
T-F/F (TB) with RB
F765
-
8 (-)
2-332
F765NQ
Q Out
7 (-)
F767
-
9 (-)
L767
Q Out, Low Power
7 (-)
F767NQ
Q Out
8 (-)
T-F/F (TB) with Data-Hold RB, SB
F792
-
12 (-)
2-336
JK-F/F
F771
-
10 (-)
2-338
F771NQ
Q Out
9 (-)
F771NB
QB Out
9 (-)
JK-F/F, High Speed
F7D1
-
10 (-)
2-340
JK-F/F with R, S
F774
-
12 (-)
2-342
F774NQ
Q Out
11 (-)
F774NB
QB Out
11 (-)
F775
-
11 (-)
F775NQ
Q Out
10 (-)
F775NB
QB Out
10 (-)
F776
-
11 (-)
F776NQ
Q Out
10 (-)
F776NB
QB Out
10 (-)
F777
-
12 (-)
F777NQ
Q Out
11 (-)
F777NB
QB Out
11 (-)
F781
-
10 (-)
F781NQ
Q Out
9 (-)
F781NB
QB Out
9 (-)
JK-F/F (CB), High Speed
F7E1
-
10 (-)
2-352
JK-F/F (CB) with RB, SB
F787
-
12 (-)
2-354
F787NQ
Q Out
11 (-)
F787NB
QB Out
11 (-)
T-F/F with RB
T-F/F with RB, SB
T-F/F (TB) with RB, SB
JK-F/F with RB
JK-F/F with SB
JK-F/F with RB, SB
JK-F/F (CB)
Contents-24
Block Library A13872EJ5V0BL
2-326
2-328
2-334
2-344
2-346
2-348
2-350
Chapter 3 Scan Path Block
3.1 Standard Type
Function
Block
Description
Cells (I/O)
Page
Scan D-F/F with R, S, 2 to 1 Selector
S000
-
12 (-)
3-4
Scan D-F/F with 2 to 1 Selector
S002
-
10 (-)
3-6
Scan D-F/F with 2 to 1 Selector, High Speed
S003
-
11 (-)
3-8
Scan D-F/F with R, S, Hold, 2 to 1 Selector
S050
-
16 (-)
3-10
Scan D-F/F with Hold, 2 to 1 Selector
S052
-
14 (-)
3-12
Scan JK-F/F with R, S, D-F/F Function
S100
-
14 (-)
3-14
Scan JK-F/F with D-F/F Function
S102
-
12 (-)
3-16
Scan JK-F/F with R, S, Hold, D-F/F Function
S150
-
18 (-)
3-18
Scan JK-F/F with Hold, D-F/F Function
S152
-
16 (-)
3-20
Scan D-Latch with R, D-F/F Function
S201
-
13 (-)
3-22
Scan D-Latch with D-F/F Function
S202
-
12 (-)
3-24
Scan D-Latch with D-F/F Function, High Speed
S204
-
12 (-)
3-26
Scan D-Latch with R, Special Function, R
S301
-
8 (-)
3-28
Scan D-Latch with Special Function
S302
-
7 (-)
3-30
Scan D-Latch with Special Function, High Speed
S303
-
7 (-)
3-32
Cells (I/O)
Page
3.2 NEC Scan
Function
Block
Description
NEC Scan D-Latch
SE601
-
13 (-)
3-38
NEC Scan D-Latch with R
SE602
-
14 (-)
3-40
NEC Scan D-Latch with RB
SE603
-
14 (-)
3-42
NEC Scan D-Latch(GB)
SE604
-
13 (-)
3-44
NEC Scan D-Latch(GB) with RB
SE605
-
14 (-)
3-46
NEC Scan D-F/F
SE611
-
11 (-)
3-48
NEC Scan D-F/F with R, S
SE614
-
13 (-)
3-50
NEC Scan D-F/F with RB
SE615
-
12 (-)
3-52
NEC Scan D-F/F with SB
SE616
-
12 (-)
3-54
NEC Scan D-F/F with RB, SB
SE617
-
13 (-)
3-56
NEC Scan D-F/F (CB)
SE631
-
11 (-)
3-58
NEC Scan D-F/F (CB) with RB, SB
SE637
-
13 (-)
3-60
Block Library A13872EJ5V0BL
Contents-25
3.3 Scan Controller
Function
Block
Description
Cells (I/O)
Page
Clock Distributor
SCD1
-
8 (-)
3-66
Clock Distributor with Test (Positive Clock)
SCDC
-
2 (-)
3-68
Clock Distributor with Test (Negative Clock)
SCDD
-
2 (-)
3-70
I/F Control (AMC) with EN
SFEH
-
3 (-)
3-72
I/F Control (AMC) with ENB
SFEL
-
2 (-)
3-74
I/F Control (SMC) with EN
SOEH
-
3 (-)
3-76
I/F Control (SMC) with ENB
SOEL
-
2 (-)
3-78
Mega Macro Skip
SMS1
-
4 (-)
3-80
Set/Reset Control
SRH1
-
2 (-)
3-82
Set-B/Reset-B Control
SRL1
-
2 (-)
3-84
Loop Cut
SRPD
-
12 (-)
3-86
Clock Generator
SCKG
-
16 (-)
3-88
Common Input
SCI1
-
2 (-)
3-90
Common Output
SCO1
-
4 (-)
3-92
GND
SGND
-
2 (-)
3-94
Contents-26
Block Library A13872EJ5V0BL
Chapter 4 Boundary Scan Block
4.1 TAP Macro
Function
Block
Description
Cells (I/O)
Page
BScan TAP Macro
SBCJ
-
262 (-)
4-4
BScan TAP Macro with NEC Scan
SBCL
-
315 (-)
4-6
Cells (I/O)
Page
1 (-)
4-12
Cells (I/O)
Page
4.2 Level Generator
Function
BScan Level Generator (CLANP)
Block
SBZ1
Description
-
4.3 Data Register
Function
Block
Description
BScan Data Register for Input
SVRNI2
-
12 (-)
4-18
BScan Data Register for Output
SVRN22
-
24 (-)
4-20
BScan Data Register for 3-state
SVRN32
-
50 (-)
4-22
BScan Data Register for Bid
SVRNB2
-
57 (-)
4-24
Cells (I/O)
Page
4.4 D-latch, Selector, Shift Register
Function
Block
Description
BScan D-Latch with SB Q Out, Low Power
L606
-
5 (-)
4-30
BScan Selector
SBD1
-
4 (-)
4-32
BScan Shift Register
SBR1
-
8 (-)
4-34
BScan Data Selector for Output
SVSNA2
-
7 (-)
4-36
BScan Data Selector for Bid
SVSNB2
-
7 (-)
4-38
BScan Data Enable Selector for 3-state
SVSNC2
-
9 (-)
4-40
BScan Data Enable Selector for Bid
SVSNE2
-
9 (-)
4-42
Cells (I/O)
Page
4.5 Soft Macro
Function
Block
Description
BScan TAP Controller
SBCK
-
392 (-)
4-48
BScan Instruction Register (Internal Circuit)
SBM4
-
46 (-)
4-50
BScan Instruction Register
SBM5
-
140 (-)
4-52
BScan Instruction Decoder
SBM6
-
24 (-)
4-54
BScan Instruction Decoder with NEC Scan
SBMC
-
37 (-)
4-56
BScan Bypass Register
SBS3
-
26 (-)
4-58
Block Library A13872EJ5V0BL
Contents-27
Chapter 1
Interface Block
1-1
Block Library
A13872EJ5V0BL
Chapter 1 Interface Block
Chapter 1 Interface Block
[MEMO]
1.1
CMOS Level
Block Library
A13872EJ5V0BL
1-2
Block Library
A13872EJ5V0BL
1-3
Chapter 1 Interface Block
Function
Chapter 1 Interface Block
Block type
Block type
IN
Function
no resistor
with 50 KΩ P/D
with 50 KΩ P/U
with 5 KΩ P/U
Normal
FI01
FID1
FIU1
FIW1
1
3
Schmitt
FIS1W
FDS1W
FUS1W
FWS1W
1
6
I/O cells int. Cells
Truth Table
Logic Diagram for "Normal"
H01
N01
Y
A
Y
1
1
0
0
Logic Diagram for "Schmitt"
Block type
A
H01
N01
Y
Input
Path
→ OUT
FI01
A → Y
FID1
A → Y
FIU1
A → Y
FIW1
A → Y
FIS1W
A → Y
FDS1W
A → Y
FUS1W
A → Y
FWS1W
A → Y
Clock
A
Switching speed
t LD0 (ns)
5.0 V
Input Buffer
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
t1
T
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.160
0.103
0.160
0.103
0.160
0.103
0.160
0.103
0.673
0.901
0.673
0.901
0.673
0.901
0.673
0.901
0.236
0.168
0.236
0.168
0.236
0.168
0.236
0.168
0.949
1.332
0.949
1.332
0.949
1.332
0.949
1.332
0.452
0.328
0.452
0.328
0.452
0.328
0.452
0.328
1.621
2.207
1.621
2.207
1.621
2.207
1.621
2.207
0.007
0.010
0.007
0.010
0.007
0.010
0.007
0.010
0.008
0.009
0.008
0.009
0.008
0.009
0.008
0.009
0.010
0.012
0.010
0.012
0.010
0.012
0.010
0.012
0.011
0.012
0.011
0.012
0.011
0.012
0.011
0.012
0.014
0.017
0.014
0.017
0.014
0.017
0.014
0.017
0.017
0.016
0.017
0.016
0.017
0.016
0.017
0.016
MIN.
TYP.
Output
Symbol Fan-In Symbol Fan-Out
FI01 to FIW1
A
-
Y
52
FIS1W to FWS1W
A
-
Y
42
Logic Diagram for "Clock"
Block Library
A13872EJ5V0BL
1-4
Block Library
A13872EJ5V0BL
1-5
MAX.
Chapter 1 Interface Block
Function
Chapter 1 Interface Block
Block type
Block type
IN
Function
no resistor
with 50 KΩ P/D
Normal
FIA1
FDA1
1
3
Schmitt
FIE1W
FDE1W
1
6
with 50 KΩ P/U
with 5 KΩ P/U
I/O cells int. Cells
Truth Table
Logic Diagram for "Normal"
H01
N01
Y
A
Y
1
1
0
0
Logic Diagram for "Schmitt"
Block type
A
H01
N01
Y
Input
Path
→ OUT
FIA1
A → Y
FDA1
A → Y
FIE1W
A → Y
FDE1W
A → Y
Clock
A
Switching speed
t LD0 (ns)
5.0 V
Input Buffer with failsafe
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
t1
T
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.160
0.103
0.160
0.103
0.672
0.903
0.672
0.903
0.236
0.169
0.236
0.169
0.948
1.328
0.948
1.328
0.452
0.328
0.452
0.328
1.621
2.208
1.621
2.208
0.007
0.010
0.007
0.010
0.008
0.009
0.008
0.009
0.010
0.012
0.010
0.012
0.011
0.012
0.011
0.012
0.014
0.017
0.014
0.017
0.017
0.016
0.017
0.016
MIN.
TYP.
Output
Symbol Fan-In Symbol Fan-Out
FIA1 to FDA1
A
-
Y
52
FIE1W to FDE1W
A
-
Y
42
Logic Diagram for "Clock"
Block Library
A13872EJ5V0BL
1-6
Block Library
A13872EJ5V0BL
1-7
MAX.
Chapter 1 Interface Block
Function
Chapter 1 Interface Block
Switching speed
t LD0 (ns)
5.0 V
Input Buffer with EN(AND)
Block type
Block type
Function
no resistor
with 50 KΩ P/D
Normal
FN11
FN21
IN
with 50 KΩ P/U
with 5 KΩ P/U
I/O cells int. Cells
1
FN11
6
Path
→ OUT
A → Y
EN → Y
Schmitt
FN21
Clock
EN → Y
Truth Table
Logic Diagram for "Normal"
A H01
A → Y
A
EN
Y
0
0
0
0
1
0
1
0
0
1
1
1
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
t1
T
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.096
0.172
0.110
0.248
0.096
0.172
0.110
0.248
0.166
0.254
0.171
0.353
0.166
0.254
0.171
0.353
0.304
0.427
0.289
0.510
0.304
0.427
0.289
0.510
0.007
0.010
0.007
0.010
0.007
0.010
0.007
0.010
0.010
0.012
0.010
0.012
0.010
0.012
0.010
0.012
0.014
0.017
0.014
0.017
0.014
0.017
0.014
0.017
MIN.
TYP.
N01 Y
H02 EN
Logic Diagram for "Schmitt"
Block type
FN11 to FN21
Input
Output
Symbol Fan-In Symbol Fan-Out
A
-
EN
3.0
Y
53
Logic Diagram for "Clock"
Block Library
A13872EJ5V0BL
1-8
Block Library
A13872EJ5V0BL
1-9
MAX.
Chapter 1 Interface Block
Function
Chapter 1 Interface Block
Switching speed
t LD0 (ns)
5.0 V
Input Buffer with EN(OR)
Block type
Block type
Function
no resistor
with 50 KΩ P/D
Normal
FN13
FN23
IN
with 50 KΩ P/U
with 5 KΩ P/U
I/O cells int. Cells
1
FN13
4
Path
→ OUT
A → Y
EN → Y
Schmitt
FN23
Clock
EN → Y
Truth Table
Logic Diagram for "Normal"
A H01
N01 Y
H02 EN
A
EN
Y
0
0
0
0
1
1
1
0
1
1
1
1
Logic Diagram for "Schmitt"
Block type
FN13 to FN23
A → Y
Input
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
t1
T
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.117
0.242
0.093
0.240
0.117
0.242
0.093
0.240
0.183
0.346
0.160
0.365
0.183
0.346
0.160
0.365
0.298
0.553
0.270
0.675
0.298
0.553
0.270
0.675
0.007
0.010
0.007
0.010
0.007
0.010
0.007
0.010
0.010
0.013
0.010
0.013
0.010
0.013
0.010
0.013
0.014
0.018
0.014
0.018
0.014
0.018
0.014
0.018
MIN.
TYP.
MAX.
Output
Symbol Fan-In Symbol Fan-Out
A
-
EN
3.0
Y
52
Logic Diagram for "Clock"
Block Library
A13872EJ5V0BL
1 - 10
Block Library
A13872EJ5V0BL
1 - 11
Chapter 1 Interface Block
Chapter 1 Interface Block
Block type
Block type
Drivability
no resistor
with 50 KΩ P/D
IN
with 50 KΩ P/U
with 5 KΩ P/U
I/O cells int. Cells
1mA
Path
→ OUT
FO09
A → Y
FO04
A → Y
FO01
A → Y
FO02
A → Y
2mA
3mA
FO09
1
4
6mA
FO04
1
4
9mA
FO01
1
4
FO03
A → Y
12mA
FO02
1
12
FO06
A → Y
18mA
FO03
1
12
24mA
FO06
1
Logic Diagram
A
H01
Switching speed
t LD0 (ns)
CMOS 5.0 V
Output Buffer
Function
Block type
N01
Y
Input
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
MIN.
TYP.
MAX.
0.459
0.563
0.473
0.469
0.516
0.521
0.361
0.315
0.422
0.373
0.481
0.441
0.744
1.047
0.745
0.819
0.806
0.867
0.564
0.559
0.657
0.641
0.746
0.746
1.554
2.482
1.534
1.792
1.685
1.817
1.173
1.217
1.358
1.358
1.528
1.536
MIN.
t1
TYP.
T
MAX.
MIN.
TYP.
MAX.
0.042
0.077
0.028
0.038
0.017
0.026
0.014
0.019
0.010
0.013
0.008
0.010
0.056
0.103
0.037
0.052
0.023
0.035
0.019
0.026
0.014
0.018
0.012
0.014
0.079
0.151
0.053
0.075
0.034
0.051
0.028
0.038
0.022
0.026
0.020
0.021
12
Output
Symbol Fan-in Symbol Fan-out
FO09
A
6.2
Y
-
FO04
A
6.2
Y
-
FO01
A
6.2
Y
-
FO02
A
18.7
Y
-
FO03
A
18.7
Y
-
FO06
A
18.7
Y
-
Truth Table
A
Y
1
1
0
0
Block Library
A13872EJ5V0BL
1 - 12
Block Library
A13872EJ5V0BL
1 - 13
Chapter 1 Interface Block
Chapter 1 Interface Block
Block type
Block type
Drivability
no resistor
with 50 KΩ P/D
IN
with 50 KΩ P/U
with 5 KΩ P/U
I/O cells int. Cells
1mA
Path
→ OUT
FE09
A → Y
FE04
A → Y
FE01
A → Y
FE02
A → Y
2mA
3mA
FE09
1
5
6mA
FE04
1
5
9mA
FE01
1
5
FE03
A → Y
12mA
FE02
1
5
FE06
A → Y
18mA
FE03
1
5
24mA
FE06
1
Logic Diagram
A
H01
Switching speed
t LD0 (ns)
CMOS 5.0 V
Low-noise Output Buffer
Function
Block type
N01
Y
Input
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
MIN.
TYP.
MAX.
0.916
1.084
0.955
1.008
1.020
1.039
1.057
1.073
1.167
1.235
1.279
1.441
1.645
1.882
1.725
1.692
1.884
1.708
1.968
1.756
2.224
1.997
2.473
2.307
4.180
3.717
4.512
2.976
5.201
2.899
5.557
2.928
6.635
3.380
7.702
3.908
MIN.
t1
TYP.
T
MAX.
MIN.
TYP.
MAX.
0.044
0.078
0.031
0.042
0.022
0.030
0.020
0.025
0.018
0.020
0.017
0.017
0.059
0.105
0.042
0.056
0.031
0.041
0.029
0.034
0.026
0.027
0.026
0.022
0.086
0.152
0.065
0.080
0.053
0.056
0.050
0.044
0.049
0.032
0.049
0.027
5
Output
Symbol Fan-in Symbol Fan-out
FE09
A
9.6
Y
-
FE04
A
9.6
Y
-
FE01
A
9.5
Y
-
FE02
A
9.5
Y
-
FE03
A
9.6
Y
-
FE06
A
9.6
Y
-
Truth Table
A
Y
1
1
0
0
Block Library
A13872EJ5V0BL
1 - 14
Block Library
A13872EJ5V0BL
1 - 15
Chapter 1 Interface Block
Chapter 1 Interface Block
Block type
Block type
Drivability
no resistor
with 50 KΩ P/D
IN
with 50 KΩ P/U
with 5 KΩ P/U
I/O cells int. Cells
B00T
1mA
Path
→ OUT
A → Y
EN → Y
2mA
3mA
B00T
B0DT
B0UT
B0WT
1
7
6mA
B00E
B0DE
B0UE
B0WE
1
7
9mA
B008
B0D8
B0U8
B0W8
1
7
12mA
B007
B0D7
B0U7
B0W7
1
17
18mA
B009
B0D9
B0U9
B0W9
1
17
24mA
B00H
B0DH
B0UH
B0WH
1
17
Logic Diagram
Block type
B00T to B0WT
A
H01
N01
EN H02
B007 to B0W7
B009 to B0W9
Truth Table
Y
0
1
0
B00H to B0WH
1
1
1
X
0
Z
A → Y
EN → Y
B0UT
A → Y
EN → Y
Output
Symbol Fan-in Symbol Fan-out
A
6.3
EN
1.0
A
6.3
EN
1.0
A
6.3
EN
1.0
Y
-
B0WT
A → Y
EN → Y
B008 to B0W8
EN
Input
B0DT
Y
B00E to B0WE
A
Switching speed
t LD0 (ns)
CMOS 5.0 V
3-State Buffer
Function
A
16.9
EN
1.0
A
16.9
EN
1.0
A
16.9
EN
1.0
Y
Y
-
-
B00E
A → Y
EN → Y
Y
-
B0DE
Y
Y
EN → Y
-
-
A → Y
B0UE
A → Y
EN → Y
X:Irrelevant
B0WE
Z:High Impedance
A → Y
EN → Y
B008
A → Y
EN → Y
Block Library
A13872EJ5V0BL
1 - 16
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
MIN.
TYP.
MAX.
0.591
0.710
1.088
0.380
0.832
0.771
0.591
0.710
1.088
0.380
0.832
0.771
0.591
0.710
1.088
0.380
0.832
0.771
0.591
0.710
1.088
0.380
0.832
0.771
0.613
0.650
1.413
0.451
0.851
0.667
0.613
0.650
1.413
0.451
0.851
0.667
0.613
0.650
1.413
0.451
0.851
0.667
0.613
0.650
1.413
0.451
0.851
0.667
0.663
0.787
1.970
0.510
0.902
0.653
1.045
1.257
1.523
0.577
1.425
1.385
1.045
1.257
1.523
0.577
1.425
1.385
1.045
1.257
1.523
0.577
1.425
1.385
1.045
1.257
1.523
0.577
1.425
1.385
1.080
1.081
1.971
0.675
1.454
1.152
1.080
1.081
1.971
0.675
1.454
1.152
1.080
1.081
1.971
0.675
1.454
1.152
1.080
1.081
1.971
0.675
1.454
1.152
1.177
1.252
2.727
0.752
1.553
1.109
2.529
2.776
2.712
0.996
3.216
2.985
2.529
2.776
2.712
0.996
3.216
2.985
2.529
2.776
2.712
0.996
3.216
2.985
2.529
2.776
2.712
0.996
3.216
2.985
2.673
2.183
3.618
1.128
3.330
2.242
2.673
2.183
3.618
1.128
3.330
2.242
2.673
2.183
3.618
1.128
3.330
2.242
2.673
2.183
3.618
1.128
3.330
2.242
3.036
2.495
5.121
1.213
3.690
2.032
Block Library
MIN.
A13872EJ5V0BL
t1
TYP.
T
MAX.
MIN.
TYP.
MAX.
0.042
0.076
0.056
0.103
0.080
0.149
0.042
0.077
0.042
0.076
0.056
0.103
0.056
0.103
0.077
0.150
0.080
0.149
0.042
0.077
0.042
0.076
0.056
0.103
0.056
0.103
0.077
0.150
0.080
0.149
0.042
0.077
0.042
0.076
0.056
0.103
0.056
0.103
0.077
0.150
0.080
0.149
0.042
0.077
0.029
0.038
0.056
0.103
0.039
0.051
0.077
0.150
0.057
0.073
0.029
0.039
0.029
0.038
0.039
0.052
0.039
0.051
0.056
0.076
0.057
0.073
0.029
0.039
0.029
0.038
0.039
0.052
0.039
0.051
0.056
0.076
0.057
0.073
0.029
0.039
0.029
0.038
0.039
0.052
0.039
0.051
0.056
0.076
0.057
0.073
0.029
0.039
0.019
0.025
0.039
0.052
0.026
0.033
0.056
0.076
0.041
0.047
0.019
0.027
0.026
0.036
0.041
0.051
1 - 17
Chapter 1 Interface Block
Block type
IN
B0D8
EN → Y
B0U8
A → Y
EN → Y
B0W8
A → Y
EN → Y
B007
A → Y
EN → Y
B0D7
A → Y
EN → Y
B0U7
A → Y
EN → Y
B0W7
A → Y
EN → Y
B009
A → Y
EN → Y
B0D9
Switching speed
t LD0 (ns)
Path
→ OUT
A → Y
A → Y
EN → Y
Chapter 1 Interface Block
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
MIN.
TYP.
MAX.
0.663
0.787
1.970
0.510
0.902
0.653
0.663
0.787
1.970
0.510
0.902
0.653
0.663
0.787
1.970
0.510
0.902
0.653
0.491
0.508
1.692
0.628
0.952
0.646
0.491
0.508
1.692
0.628
0.952
0.646
0.491
0.508
1.692
0.628
0.952
0.646
0.491
0.508
1.692
0.628
0.952
0.646
0.540
0.619
2.230
0.713
0.997
0.647
0.540
0.619
2.230
0.713
0.997
0.647
1.177
1.252
2.727
0.752
1.553
1.109
1.177
1.252
2.727
0.752
1.553
1.109
1.177
1.252
2.727
0.752
1.553
1.109
0.857
0.827
2.427
0.961
1.561
1.051
0.857
0.827
2.427
0.961
1.561
1.051
0.857
0.827
2.427
0.961
1.561
1.051
0.857
0.827
2.427
0.961
1.561
1.051
0.952
0.988
3.165
1.069
1.655
1.048
0.952
0.988
3.165
1.069
1.655
1.048
3.036
2.495
5.121
1.213
3.690
2.032
3.036
2.495
5.121
1.213
3.690
2.032
3.036
2.495
5.121
1.213
3.690
2.032
2.145
1.674
4.634
1.612
3.392
1.954
2.145
1.674
4.634
1.612
3.392
1.954
2.145
1.674
4.634
1.612
3.392
1.954
2.145
1.674
4.634
1.612
3.392
1.954
2.455
1.917
6.099
1.724
3.703
1.880
2.455
1.917
6.099
1.724
3.703
1.880
Block Library
MIN.
A13872EJ5V0BL
t1
TYP.
Block type
T
MAX.
MIN.
TYP.
MAX.
0.019
0.025
0.026
0.033
0.041
0.047
IN
B0U9
A → Y
EN → Y
0.019
0.027
0.019
0.025
0.026
0.036
0.026
0.033
0.041
0.051
0.041
0.047
B0W9
A → Y
EN → Y
0.019
0.027
0.019
0.025
0.026
0.036
0.026
0.033
0.041
0.051
0.041
0.047
0.019
0.027
0.015
0.019
0.026
0.036
0.021
0.025
0.041
0.051
0.033
0.036
B00H
A → Y
EN → Y
B0DH
A → Y
EN → Y
0.015
0.020
0.015
0.019
0.021
0.027
0.021
0.025
0.032
0.038
0.033
0.036
B0UH
A → Y
EN → Y
0.015
0.020
0.015
0.019
0.021
0.027
0.021
0.025
0.032
0.038
0.033
0.036
B0WH
A → Y
EN → Y
0.015
0.020
0.015
0.019
0.021
0.027
0.021
0.025
0.032
0.038
0.033
0.036
0.015
0.020
0.012
0.013
0.021
0.027
0.017
0.017
0.032
0.038
0.029
0.026
0.012
0.014
0.012
0.013
0.017
0.019
0.017
0.017
0.028
0.027
0.029
0.026
0.012
0.014
0.017
0.019
0.028
0.027
1 - 18
Switching speed
t LD0 (ns)
Path
→ OUT
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
MIN.
TYP.
MAX.
0.540
0.619
2.230
0.713
0.997
0.647
0.540
0.619
2.230
0.713
0.997
0.647
0.588
0.729
2.768
0.796
1.036
0.650
0.588
0.729
2.768
0.796
1.036
0.650
0.588
0.729
2.768
0.796
1.036
0.650
0.588
0.729
2.768
0.796
1.036
0.650
0.952
0.988
3.165
1.069
1.655
1.048
0.952
0.988
3.165
1.069
1.655
1.048
1.038
1.148
3.922
1.176
1.734
1.054
1.038
1.148
3.922
1.176
1.734
1.054
1.038
1.148
3.922
1.176
1.734
1.054
1.038
1.148
3.922
1.176
1.734
1.054
2.455
1.917
6.099
1.724
3.703
1.880
2.455
1.917
6.099
1.724
3.703
1.880
2.740
2.184
7.625
1.839
3.989
1.852
2.740
2.184
7.625
1.839
3.989
1.852
2.740
2.184
7.625
1.839
3.989
1.852
2.740
2.184
7.625
1.839
3.989
1.852
Block Library
MIN.
t1
TYP.
A13872EJ5V0BL
T
MAX.
MIN.
TYP.
MAX.
0.012
0.013
0.017
0.017
0.029
0.026
0.012
0.014
0.012
0.013
0.017
0.019
0.017
0.017
0.028
0.027
0.029
0.026
0.012
0.014
0.011
0.010
0.017
0.019
0.015
0.014
0.028
0.027
0.028
0.021
0.011
0.011
0.011
0.010
0.015
0.016
0.015
0.014
0.027
0.022
0.028
0.021
0.011
0.011
0.011
0.010
0.015
0.016
0.015
0.014
0.027
0.022
0.028
0.021
0.011
0.011
0.011
0.010
0.015
0.016
0.015
0.014
0.027
0.022
0.028
0.021
0.011
0.011
0.015
0.016
0.027
0.022
1 - 19
Chapter 1 Interface Block
Chapter 1 Interface Block
Block type
Block type
Drivability
no resistor
with 50 KΩ P/D
IN
with 50 KΩ P/U
with 5 KΩ P/U
I/O cells int. Cells
BE0T
1mA
Path
→ OUT
A → Y
EN → Y
2mA
3mA
BE0T
BEDT
BEUT
BEWT
1
7
6mA
BE0E
BEDE
BEUE
BEWE
1
7
9mA
BE08
BED8
BEU8
BEW8
1
7
12mA
BE07
BED7
BEU7
BEW7
1
7
18mA
BE09
BED9
BEU9
BEW9
1
7
24mA
BE0H
BEDH
BEUH
BEWH
1
7
Logic Diagram
Block type
BE0T to BEWT
A
H01
N01
EN H02
BE07 to BEW7
BE09 to BEW9
Truth Table
Y
0
1
0
BE0H to BEWH
1
1
1
X
0
Z
A → Y
EN → Y
BEUT
A → Y
EN → Y
Output
Symbol Fan-in Symbol Fan-out
A
6.2
EN
4.0
A
6.1
EN
4.0
A
6.2
EN
4.0
Y
-
BEWT
A → Y
EN → Y
BE08 to BEW8
EN
Input
BEDT
Y
BE0E to BEWE
A
Switching speed
t LD0 (ns)
CMOS 5.0 V
Low-noise 3-State Buffer
Function
A
6.2
EN
4.0
A
6.2
EN
4.0
A
6.2
EN
4.0
Y
Y
-
-
BE0E
A → Y
EN → Y
Y
-
BEDE
Y
Y
EN → Y
-
-
A → Y
BEUE
A → Y
EN → Y
X:Irrelevant
BEWE
Z:High Impedance
A → Y
EN → Y
BE08
A → Y
EN → Y
Block Library
A13872EJ5V0BL
1 - 20
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
MIN.
TYP.
MAX.
0.906
0.903
0.697
0.638
0.907
0.940
0.906
0.903
0.697
0.638
0.907
0.940
0.906
0.903
0.697
0.638
0.907
0.940
0.906
0.903
0.697
0.638
0.907
0.940
0.951
0.874
0.948
0.817
0.943
0.868
0.951
0.874
0.948
0.817
0.943
0.868
0.951
0.874
0.948
0.817
0.943
0.868
0.951
0.874
0.948
0.817
0.943
0.868
1.027
1.034
1.369
0.981
1.005
0.864
1.649
1.561
0.916
0.928
1.682
1.673
1.649
1.561
0.916
0.928
1.682
1.673
1.649
1.561
0.916
0.928
1.682
1.673
1.649
1.561
0.916
0.928
1.682
1.673
1.724
1.428
1.269
1.158
1.755
1.494
1.724
1.428
1.269
1.158
1.755
1.494
1.724
1.428
1.269
1.158
1.755
1.494
1.724
1.428
1.269
1.158
1.755
1.494
1.876
1.615
1.836
1.364
1.906
1.475
4.217
3.193
1.493
1.536
4.261
3.375
4.217
3.193
1.493
1.536
4.261
3.375
4.217
3.193
1.493
1.536
4.261
3.375
4.217
3.193
1.493
1.536
4.261
3.375
4.530
2.630
2.217
1.799
4.570
2.680
4.530
2.630
2.217
1.799
4.570
2.680
4.530
2.630
2.217
1.799
4.570
2.680
4.530
2.630
2.217
1.799
4.570
2.680
5.188
2.959
3.377
2.013
5.246
2.488
Block Library
MIN.
A13872EJ5V0BL
t1
TYP.
T
MAX.
MIN.
TYP.
MAX.
0.044
0.077
0.059
0.103
0.086
0.150
0.044
0.077
0.044
0.077
0.059
0.104
0.059
0.103
0.086
0.151
0.086
0.150
0.044
0.077
0.044
0.077
0.059
0.104
0.059
0.103
0.086
0.151
0.086
0.150
0.044
0.077
0.044
0.077
0.059
0.104
0.059
0.103
0.086
0.151
0.086
0.150
0.044
0.077
0.031
0.039
0.059
0.104
0.042
0.053
0.086
0.151
0.066
0.075
0.031
0.040
0.031
0.039
0.042
0.054
0.042
0.053
0.066
0.077
0.066
0.075
0.031
0.040
0.031
0.039
0.042
0.054
0.042
0.053
0.066
0.077
0.066
0.075
0.031
0.040
0.031
0.039
0.042
0.054
0.042
0.053
0.066
0.077
0.066
0.075
0.031
0.040
0.022
0.026
0.042
0.054
0.031
0.035
0.066
0.077
0.053
0.049
0.022
0.029
0.031
0.038
0.053
0.054
1 - 21
Chapter 1 Interface Block
Block type
IN
BED8
EN → Y
BEU8
A → Y
EN → Y
BEW8
A → Y
EN → Y
BE07
A → Y
EN → Y
BED7
A → Y
EN → Y
BEU7
A → Y
EN → Y
BEW7
A → Y
EN → Y
BE09
A → Y
EN → Y
BED9
Switching speed
t LD0 (ns)
Path
→ OUT
A → Y
A → Y
EN → Y
Chapter 1 Interface Block
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
MIN.
TYP.
MAX.
1.027
1.034
1.369
0.981
1.005
0.864
1.027
1.034
1.369
0.981
1.005
0.864
1.027
1.034
1.369
0.981
1.005
0.864
1.086
1.107
1.585
1.138
1.039
0.873
1.086
1.107
1.585
1.138
1.039
0.873
1.086
1.107
1.585
1.138
1.039
0.873
1.086
1.107
1.585
1.138
1.039
0.873
1.249
1.391
2.247
1.467
1.139
0.902
1.249
1.391
2.247
1.467
1.139
0.902
1.876
1.615
1.836
1.364
1.906
1.475
1.876
1.615
1.836
1.364
1.906
1.475
1.876
1.615
1.836
1.364
1.906
1.475
1.963
1.718
2.130
1.564
1.989
1.486
1.963
1.718
2.130
1.564
1.989
1.486
1.963
1.718
2.130
1.564
1.989
1.486
1.963
1.718
2.130
1.564
1.989
1.486
2.239
2.128
3.020
1.974
2.241
1.547
2.239
2.128
3.020
1.974
2.241
1.547
5.188
2.959
3.377
2.013
5.246
2.488
5.188
2.959
3.377
2.013
5.246
2.488
5.188
2.959
3.377
2.013
5.246
2.488
5.554
3.065
3.959
2.214
5.597
2.412
5.554
3.065
3.959
2.214
5.597
2.412
5.554
3.065
3.959
2.214
5.597
2.412
5.554
3.065
3.959
2.214
5.597
2.412
6.618
3.712
5.777
2.649
6.670
2.379
6.618
3.712
5.777
2.649
6.670
2.379
Block Library
MIN.
A13872EJ5V0BL
t1
TYP.
Block type
T
MAX.
MIN.
TYP.
MAX.
0.022
0.026
0.031
0.035
0.053
0.049
IN
BEU9
A → Y
EN → Y
0.022
0.029
0.022
0.026
0.031
0.038
0.031
0.035
0.053
0.054
0.053
0.049
BEW9
A → Y
EN → Y
0.022
0.029
0.022
0.026
0.031
0.038
0.031
0.035
0.053
0.054
0.053
0.049
0.022
0.029
0.020
0.021
0.031
0.038
0.029
0.028
0.053
0.054
0.051
0.037
BE0H
A → Y
EN → Y
BEDH
A → Y
EN → Y
0.021
0.023
0.020
0.021
0.029
0.031
0.029
0.028
0.051
0.043
0.051
0.037
BEUH
A → Y
EN → Y
0.021
0.023
0.020
0.021
0.029
0.031
0.029
0.028
0.051
0.043
0.051
0.037
BEWH
A → Y
EN → Y
0.021
0.023
0.020
0.021
0.029
0.031
0.029
0.028
0.051
0.043
0.051
0.037
0.021
0.023
0.017
0.015
0.029
0.031
0.026
0.020
0.051
0.043
0.049
0.028
0.018
0.019
0.017
0.015
0.026
0.025
0.026
0.020
0.049
0.033
0.049
0.028
0.018
0.019
0.026
0.025
0.049
0.033
1 - 22
Switching speed
t LD0 (ns)
Path
→ OUT
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
MIN.
TYP.
MAX.
1.249
1.391
2.247
1.467
1.139
0.902
1.249
1.391
2.247
1.467
1.139
0.902
1.429
1.676
2.920
1.791
1.236
0.934
1.429
1.676
2.920
1.791
1.236
0.934
1.429
1.676
2.920
1.791
1.236
0.934
1.429
1.676
2.920
1.791
1.236
0.934
2.239
2.128
3.020
1.974
2.241
1.547
2.239
2.128
3.020
1.974
2.241
1.547
2.521
2.541
3.913
2.376
2.487
1.621
2.521
2.541
3.913
2.376
2.487
1.621
2.521
2.541
3.913
2.376
2.487
1.621
2.521
2.541
3.913
2.376
2.487
1.621
6.618
3.712
5.777
2.649
6.670
2.379
6.618
3.712
5.777
2.649
6.670
2.379
7.676
4.411
7.573
3.054
7.732
2.393
7.676
4.411
7.573
3.054
7.732
2.393
7.676
4.411
7.573
3.054
7.732
2.393
7.676
4.411
7.573
3.054
7.732
2.393
Block Library
MIN.
t1
TYP.
A13872EJ5V0BL
T
MAX.
MIN.
TYP.
MAX.
0.017
0.015
0.026
0.020
0.049
0.028
0.018
0.019
0.017
0.015
0.026
0.025
0.026
0.020
0.049
0.033
0.049
0.028
0.018
0.019
0.015
0.012
0.026
0.025
0.025
0.017
0.049
0.033
0.049
0.023
0.017
0.017
0.015
0.012
0.026
0.023
0.025
0.017
0.049
0.029
0.049
0.023
0.017
0.017
0.015
0.012
0.026
0.023
0.025
0.017
0.049
0.029
0.049
0.023
0.017
0.017
0.015
0.012
0.026
0.023
0.025
0.017
0.049
0.029
0.049
0.023
0.017
0.017
0.026
0.023
0.049
0.029
1 - 23
Chapter 1 Interface Block
Function
Chapter 1 Interface Block
Block type
Block type
Drivability
no resistor
Switching speed
t LD0 (ns)
CMOS 5.0 V
N-ch open drain Buffer
with 50 KΩ P/D
IN
with 50 KΩ P/U
with 5 KΩ P/U
I/O cells int. Cells
1mA
Path
→ OUT
EXT1
A → Y
EXT3
A → Y
EXW3
A → Y
EXT9
A → Y
2mA
3mA
6mA
9mA
EXT1
EXT3
EXW3
1
4
EXTB
A → Y
12mA
EXT9
EXTB
EXWB
1
4
EXWB
A → Y
18mA
EXT5
EXT7
EXW7
1
4
EXT5
A → Y
24mA
EXTD
EXTF
EXWF
1
EXT7
A → Y
Logic Diagram
Block type
N01 Y
EXT1 to EXW3
Input
4
Output
Symbol Fan-in Symbol Fan-out
A
6.2
Y
EXW7
A → Y
EXTD
A → Y
EXTF
A → Y
EXWF
A → Y
-
EXT9 to EXWB
A
6.2
Y
-
EXT5 to EXW7
A
6.2
Y
-
EXTD to EXWF
A
6.2
Y
-
A H01
(LZ)
(ZL)
(LZ)
(ZL)
(LZ)
(ZL)
(LZ)
(ZL)
(LZ)
(ZL)
(LZ)
(ZL)
(LZ)
(ZL)
(LZ)
(ZL)
(LZ)
(ZL)
(LZ)
(ZL)
(LZ)
(ZL)
(LZ)
(ZL)
MIN.
TYP.
MAX.
0.361
0.264
0.361
0.264
0.361
0.264
0.424
0.259
0.424
0.259
0.424
0.259
0.547
0.266
0.547
0.266
0.547
0.266
0.672
0.275
0.672
0.275
0.672
0.275
0.465
0.493
0.465
0.493
0.465
0.493
0.546
0.479
0.546
0.479
0.546
0.479
0.707
0.485
0.707
0.485
0.707
0.485
0.864
0.498
0.864
0.498
0.864
0.498
0.633
1.001
0.633
1.001
0.633
1.001
0.714
0.914
0.714
0.914
0.714
0.914
0.885
0.860
0.885
0.860
0.885
0.860
1.051
0.848
1.051
0.848
1.051
0.848
MIN.
t1
TYP.
T
MAX.
MIN.
TYP.
MAX.
0.026
0.035
0.050
0.026
0.035
0.050
0.026
0.035
0.050
0.020
0.026
0.038
0.020
0.026
0.038
0.020
0.026
0.038
0.014
0.019
0.026
0.014
0.019
0.026
0.014
0.019
0.026
0.011
0.015
0.021
0.011
0.015
0.021
0.011
0.015
0.021
Truth Table
A
Y
1
Z
0
0
Z:High Impedance
Connect a pull-up resistor to get a high level
Block Library
A13872EJ5V0BL
1 - 24
Block Library
A13872EJ5V0BL
1 - 25
Chapter 1 Interface Block
Function
Chapter 1 Interface Block
Block type
Block type
Drivability
no resistor
Switching speed
t LD0 (ns)
CMOS 5.0 V
N-ch open drain Buffer with failsafe
with 50 KΩ P/D
IN
with 50 KΩ P/U
with 5 KΩ P/U
I/O cells int. Cells
1mA
Path
→ OUT
EXO1
A → Y
EXO9
A → Y
EXO5
A → Y
EXOD
A → Y
2mA
3mA
6mA
9mA
EXO1
1
4
12mA
EXO9
1
4
18mA
EXO5
1
4
24mA
EXOD
1
Logic Diagram
Block type
N01 Y
Input
(LZ)
(ZL)
(LZ)
(ZL)
(LZ)
(ZL)
(LZ)
(ZL)
MIN.
TYP.
MAX.
0.361
0.264
0.424
0.259
0.547
0.266
0.672
0.275
0.465
0.493
0.546
0.479
0.707
0.485
0.864
0.498
0.633
1.001
0.714
0.914
0.885
0.860
1.051
0.848
MIN.
t1
TYP.
T
MAX.
MIN.
TYP.
MAX.
0.026
0.035
0.050
0.020
0.026
0.038
0.014
0.019
0.026
0.011
0.015
0.021
4
Output
Symbol Fan-in Symbol Fan-out
EXO1
A
6.2
Y
-
EXO9
A
6.2
Y
-
EXO5
A
6.2
Y
-
EXOD
A
6.2
Y
-
A H01
Truth Table
A
Y
1
Z
0
0
Z:High Impedance
Connect a pull-up resistor to get a high level
Block Library
A13872EJ5V0BL
1 - 26
Block Library
A13872EJ5V0BL
1 - 27
Chapter 1 Interface Block
Chapter 1 Interface Block
Block type
Block type
Drivability
no resistor
with 50 KΩ P/D
IN
with 50 KΩ P/U
with 5 KΩ P/U
I/O cells int. Cells
B00U
1mA
Path
→ OUT
A → Y0
EN → Y0
2mA
3mA
B00U
B0DU
B0UU
B0WU
1
10
6mA
B00C
B0DC
B0UC
B0WC
1
10
9mA
B003
B0D3
B0U3
B0W3
1
10
12mA
B001
B0D1
B0U1
B0W1
1
20
18mA
B005
B0D5
B0U5
B0W5
1
20
24mA
B00F
B0DF
B0UF
B0WF
1
20
Logic Diagram
Block type
B00U to B0WU
Input
Y0 → Y1
B0DU
EN → Y0
Y0 → Y1
Output
Symbol Fan-in Symbol Fan-out
A
6.3
EN
1.0
A
6.3
EN
1.0
A
6.3
EN
1.0
Y1
A → Y0
B0UU
A → Y0
52
EN → Y0
Y1 N02
B00C to B0WC
A H01
N01 Y0
EN H03
B003 to B0W3
B001 to B0W1
B005 to B0W5
Truth Table
A
EN
Y0
0
1
0
1
1
1
X
0
Z
B00F to B0WF
A
16.9
EN
1.0
A
16.9
EN
1.0
A
16.9
EN
1.0
Y1
52
Y0 → Y1
Y1
52
B0WU
Y1
52
Y0 → Y1
Y1
52
B00C
0
0
1
1
A → Y0
EN → Y0
Y1
52
Y0 → Y1
B0DC
A → Y0
EN → Y0
Z:High Impedance
Y1
A → Y0
EN → Y0
X:Irrelevant
Y0
Switching speed
t LD0 (ns)
CMOS 5.0 V
I/O Buffer
Function
Y0 → Y1
B0UC
A → Y0
EN → Y0
Y0 → Y1
Block Library
A13872EJ5V0BL
1 - 28
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
MIN.
TYP.
MAX.
0.591
0.710
1.088
0.380
0.832
0.771
0.160
0.103
0.591
0.710
1.088
0.380
0.832
0.771
0.160
0.103
0.591
0.710
1.088
0.380
0.832
0.771
0.160
0.103
0.591
0.710
1.088
0.380
0.832
0.771
0.160
0.103
0.613
0.650
1.413
0.451
0.851
0.667
0.160
0.103
0.613
0.650
1.413
0.451
0.851
0.667
0.160
0.103
0.613
0.650
1.413
0.451
0.851
0.667
0.160
0.103
1.045
1.257
1.523
0.577
1.425
1.385
0.236
0.168
1.045
1.257
1.523
0.577
1.425
1.385
0.236
0.168
1.045
1.257
1.523
0.577
1.425
1.385
0.236
0.168
1.045
1.257
1.523
0.577
1.425
1.385
0.236
0.168
1.080
1.081
1.971
0.675
1.454
1.152
0.236
0.168
1.080
1.081
1.971
0.675
1.454
1.152
0.236
0.168
1.080
1.081
1.971
0.675
1.454
1.152
0.236
0.168
2.529
2.776
2.712
0.996
3.216
2.985
0.452
0.328
2.529
2.776
2.712
0.996
3.216
2.985
0.452
0.328
2.529
2.776
2.712
0.996
3.216
2.985
0.452
0.328
2.529
2.776
2.712
0.996
3.216
2.985
0.452
0.328
2.673
2.183
3.618
1.128
3.330
2.242
0.452
0.328
2.673
2.183
3.618
1.128
3.330
2.242
0.452
0.328
2.673
2.183
3.618
1.128
3.330
2.242
0.452
0.328
Block Library
MIN.
0.007
0.010
0.007
0.010
0.007
0.010
0.007
0.010
0.007
0.010
0.007
0.010
0.007
0.010
A13872EJ5V0BL
t1
TYP.
0.010
0.012
0.010
0.012
0.010
0.012
0.010
0.012
0.010
0.012
0.010
0.012
0.010
0.012
T
MAX.
MIN.
TYP.
MAX.
0.042
0.076
0.056
0.103
0.080
0.149
0.042
0.077
0.056
0.103
0.077
0.150
0.042
0.076
0.056
0.103
0.080
0.149
0.042
0.077
0.056
0.103
0.077
0.150
0.042
0.076
0.056
0.103
0.080
0.149
0.042
0.077
0.056
0.103
0.077
0.150
0.042
0.076
0.056
0.103
0.080
0.149
0.042
0.077
0.056
0.103
0.077
0.150
0.029
0.038
0.039
0.051
0.057
0.073
0.029
0.039
0.039
0.052
0.056
0.076
0.029
0.038
0.039
0.051
0.057
0.073
0.029
0.039
0.039
0.052
0.056
0.076
0.029
0.038
0.039
0.051
0.057
0.073
0.029
0.039
0.039
0.052
0.056
0.076
0.014
0.017
0.014
0.017
0.014
0.017
0.014
0.017
0.014
0.017
0.014
0.017
0.014
0.017
1 - 29
Chapter 1 Interface Block
Block type
IN
B0WC
EN → Y0
Y0 → Y1
B003
A → Y0
EN → Y0
Y0 → Y1
B0D3
A → Y0
EN → Y0
Y0 → Y1
B0U3
A → Y0
EN → Y0
Y0 → Y1
B0W3
A → Y0
EN → Y0
Y0 → Y1
B001
A → Y0
EN → Y0
Y0 → Y1
B0D1
Switching speed
t LD0 (ns)
Path
→ OUT
A → Y0
A → Y0
EN → Y0
Y0 → Y1
Chapter 1 Interface Block
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
MIN.
TYP.
MAX.
0.613
0.650
1.413
0.451
0.851
0.667
0.160
0.103
0.663
0.787
1.970
0.510
0.902
0.653
0.160
0.103
0.663
0.787
1.970
0.510
0.902
0.653
0.160
0.103
0.663
0.787
1.970
0.510
0.902
0.653
0.160
0.103
0.663
0.787
1.970
0.510
0.902
0.653
0.160
0.103
0.491
0.508
1.692
0.628
0.952
0.646
0.160
0.103
0.491
0.508
1.692
0.628
0.952
0.646
0.160
0.103
1.080
1.081
1.971
0.675
1.454
1.152
0.236
0.168
1.177
1.252
2.727
0.752
1.553
1.109
0.236
0.168
1.177
1.252
2.727
0.752
1.553
1.109
0.236
0.168
1.177
1.252
2.727
0.752
1.553
1.109
0.236
0.168
1.177
1.252
2.727
0.752
1.553
1.109
0.236
0.168
0.857
0.827
2.427
0.961
1.561
1.051
0.236
0.168
0.857
0.827
2.427
0.961
1.561
1.051
0.236
0.168
2.673
2.183
3.618
1.128
3.330
2.242
0.452
0.328
3.036
2.495
5.121
1.213
3.690
2.032
0.452
0.328
3.036
2.495
5.121
1.213
3.690
2.032
0.452
0.328
3.036
2.495
5.121
1.213
3.690
2.032
0.452
0.328
3.036
2.495
5.121
1.213
3.690
2.032
0.452
0.328
2.145
1.674
4.634
1.612
3.392
1.954
0.452
0.328
2.145
1.674
4.634
1.612
3.392
1.954
0.452
0.328
Block Library
MIN.
t1
TYP.
Block type
T
MAX.
MIN.
TYP.
MAX.
0.029
0.038
0.039
0.051
0.057
0.073
IN
B0U1
A → Y0
EN → Y0
0.029
0.039
0.007
0.010
0.010
0.012
0.039
0.052
0.056
0.076
Y0 → Y1
0.014
0.017
0.019
0.025
0.026
0.033
0.041
0.047
B0W1
A → Y0
EN → Y0
0.007
0.010
0.010
0.012
0.019
0.027
0.026
0.036
0.041
0.051
0.019
0.025
0.026
0.033
0.041
0.047
Y0 → Y1
0.014
0.017
B005
A → Y0
EN → Y0
0.019
0.027
0.007
0.010
0.010
0.012
0.026
0.036
0.041
0.051
Y0 → Y1
0.014
0.017
0.019
0.025
0.026
0.033
0.041
0.047
B0D5
A → Y0
EN → Y0
0.019
0.027
0.007
0.010
0.010
0.012
0.026
0.036
0.041
0.051
Y0 → Y1
0.014
0.017
0.019
0.025
0.026
0.033
0.041
0.047
0.019
0.027
0.026
0.036
0.041
0.051
B0U5
A → Y0
EN → Y0
0.007
0.010
0.010
0.012
Y0 → Y1
0.014
0.017
0.015
0.019
0.021
0.025
0.033
0.036
B0W5
A → Y0
EN → Y0
0.015
0.020
0.007
0.010
0.010
0.012
0.021
0.027
0.032
0.038
Y0 → Y1
0.014
0.017
0.015
0.019
0.021
0.025
0.033
0.036
B00F
A → Y0
EN → Y0
0.015
0.020
0.007
0.010
A13872EJ5V0BL
0.010
0.012
0.021
0.027
0.032
0.038
Y0 → Y1
0.014
0.017
1 - 30
Switching speed
t LD0 (ns)
Path
→ OUT
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
MIN.
TYP.
MAX.
0.491
0.508
1.692
0.628
0.952
0.646
0.160
0.103
0.491
0.508
1.692
0.628
0.952
0.646
0.160
0.103
0.540
0.619
2.230
0.713
0.997
0.647
0.160
0.103
0.540
0.619
2.230
0.713
0.997
0.647
0.160
0.103
0.540
0.619
2.230
0.713
0.997
0.647
0.160
0.103
0.540
0.619
2.230
0.713
0.997
0.647
0.160
0.103
0.588
0.729
2.768
0.796
1.036
0.650
0.160
0.103
0.857
0.827
2.427
0.961
1.561
1.051
0.236
0.168
0.857
0.827
2.427
0.961
1.561
1.051
0.236
0.168
0.952
0.988
3.165
1.069
1.655
1.048
0.236
0.168
0.952
0.988
3.165
1.069
1.655
1.048
0.236
0.168
0.952
0.988
3.165
1.069
1.655
1.048
0.236
0.168
0.952
0.988
3.165
1.069
1.655
1.048
0.236
0.168
1.038
1.148
3.922
1.176
1.734
1.054
0.236
0.168
2.145
1.674
4.634
1.612
3.392
1.954
0.452
0.328
2.145
1.674
4.634
1.612
3.392
1.954
0.452
0.328
2.455
1.917
6.099
1.724
3.703
1.880
0.452
0.328
2.455
1.917
6.099
1.724
3.703
1.880
0.452
0.328
2.455
1.917
6.099
1.724
3.703
1.880
0.452
0.328
2.455
1.917
6.099
1.724
3.703
1.880
0.452
0.328
2.740
2.184
7.625
1.839
3.989
1.852
0.452
0.328
Block Library
MIN.
0.007
0.010
0.007
0.010
0.007
0.010
0.007
0.010
0.007
0.010
0.007
0.010
0.007
0.010
t1
TYP.
0.010
0.012
0.010
0.012
0.010
0.012
0.010
0.012
0.010
0.012
0.010
0.012
0.010
0.012
A13872EJ5V0BL
T
MAX.
MIN.
TYP.
MAX.
0.015
0.019
0.021
0.025
0.033
0.036
0.015
0.020
0.021
0.027
0.032
0.038
0.015
0.019
0.021
0.025
0.033
0.036
0.015
0.020
0.021
0.027
0.032
0.038
0.012
0.013
0.017
0.017
0.029
0.026
0.012
0.014
0.017
0.019
0.028
0.027
0.012
0.013
0.017
0.017
0.029
0.026
0.012
0.014
0.017
0.019
0.028
0.027
0.012
0.013
0.017
0.017
0.029
0.026
0.012
0.014
0.017
0.019
0.028
0.027
0.012
0.013
0.017
0.017
0.029
0.026
0.012
0.014
0.017
0.019
0.028
0.027
0.011
0.010
0.015
0.014
0.028
0.021
0.011
0.011
0.015
0.016
0.027
0.022
0.014
0.017
0.014
0.017
0.014
0.017
0.014
0.017
0.014
0.017
0.014
0.017
0.014
0.017
1 - 31
Chapter 1 Interface Block
Block type
IN
B0DF
EN → Y0
Y0 → Y1
B0UF
A → Y0
EN → Y0
Y0 → Y1
B0WF
Switching speed
t LD0 (ns)
Path
→ OUT
A → Y0
A → Y0
EN → Y0
Y0 → Y1
Chapter 1 Interface Block
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
MIN.
TYP.
MAX.
0.588
0.729
2.768
0.796
1.036
0.650
0.160
0.103
0.588
0.729
2.768
0.796
1.036
0.650
0.160
0.103
0.588
0.729
2.768
0.796
1.036
0.650
0.160
0.103
1.038
1.148
3.922
1.176
1.734
1.054
0.236
0.168
1.038
1.148
3.922
1.176
1.734
1.054
0.236
0.168
1.038
1.148
3.922
1.176
1.734
1.054
0.236
0.168
2.740
2.184
7.625
1.839
3.989
1.852
0.452
0.328
2.740
2.184
7.625
1.839
3.989
1.852
0.452
0.328
2.740
2.184
7.625
1.839
3.989
1.852
0.452
0.328
Block Library
MIN.
0.007
0.010
0.007
0.010
0.007
0.010
A13872EJ5V0BL
[MEMO]
t1
TYP.
0.010
0.012
0.010
0.012
0.010
0.012
T
MAX.
MIN.
TYP.
MAX.
0.011
0.010
0.015
0.014
0.028
0.021
0.011
0.011
0.015
0.016
0.027
0.022
0.011
0.010
0.015
0.014
0.028
0.021
0.011
0.011
0.015
0.016
0.027
0.022
0.011
0.010
0.015
0.014
0.028
0.021
0.011
0.011
0.015
0.016
0.027
0.022
0.014
0.017
0.014
0.017
0.014
0.017
1 - 32
Block Library
A13872EJ5V0BL
1 - 33
Chapter 1 Interface Block
Chapter 1 Interface Block
Block type
Block type
Drivability
no resistor
with 50 KΩ P/D
IN
with 50 KΩ P/U
with 5 KΩ P/U
I/O cells int. Cells
BE0U
1mA
Path
→ OUT
A → Y0
EN → Y0
2mA
3mA
BE0U
BEDU
BEUU
BEWU
1
10
6mA
BE0C
BEDC
BEUC
BEWC
1
10
9mA
BE03
BED3
BEU3
BEW3
1
10
12mA
BE01
BED1
BEU1
BEW1
1
10
18mA
BE05
BED5
BEU5
BEW5
1
10
24mA
BE0F
BEDF
BEUF
BEWF
1
10
Logic Diagram
Block type
BE0U to BEWU
Input
Y0 → Y1
BEDU
EN → Y0
Y0 → Y1
Output
Symbol Fan-in Symbol Fan-out
A
6.2
EN
4.0
A
6.1
EN
4.0
A
6.2
EN
4.0
Y1
A → Y0
BEUU
A → Y0
52
EN → Y0
Y1 N02
BE0C to BEWC
A H01
N01 Y0
EN H03
BE03 to BEW3
BE01 to BEW1
BE05 to BEW5
Truth Table
A
EN
Y0
0
1
0
1
1
1
X
0
Z
BE0F to BEWF
A
6.2
EN
4.0
A
6.2
EN
4.0
A
6.2
EN
4.0
Y1
52
Y0 → Y1
Y1
52
BEWU
Y1
52
Y0 → Y1
Y1
52
BE0C
0
0
1
1
A → Y0
EN → Y0
Y1
52
Y0 → Y1
BEDC
A → Y0
EN → Y0
Z:High Impedance
Y1
A → Y0
EN → Y0
X:Irrelevant
Y0
Switching speed
t LD0 (ns)
CMOS 5.0 V
Low-noise I/O Buffer
Function
Y0 → Y1
BEUC
A → Y0
EN → Y0
Y0 → Y1
Block Library
A13872EJ5V0BL
1 - 34
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
MIN.
TYP.
MAX.
0.906
0.903
0.697
0.638
0.907
0.940
0.160
0.103
0.906
0.903
0.697
0.638
0.907
0.940
0.160
0.103
0.906
0.903
0.697
0.638
0.907
0.940
0.160
0.103
0.906
0.903
0.697
0.638
0.907
0.940
0.160
0.103
0.951
0.874
0.948
0.817
0.943
0.868
0.160
0.103
0.951
0.874
0.948
0.817
0.943
0.868
0.160
0.103
0.951
0.874
0.948
0.817
0.943
0.868
0.160
0.103
1.649
1.561
0.916
0.928
1.682
1.673
0.236
0.168
1.649
1.561
0.916
0.928
1.682
1.673
0.236
0.168
1.649
1.561
0.916
0.928
1.682
1.673
0.236
0.168
1.649
1.561
0.916
0.928
1.682
1.673
0.236
0.168
1.724
1.428
1.269
1.158
1.755
1.494
0.236
0.168
1.724
1.428
1.269
1.158
1.755
1.494
0.236
0.168
1.724
1.428
1.269
1.158
1.755
1.494
0.236
0.168
4.217
3.193
1.493
1.536
4.261
3.375
0.452
0.328
4.217
3.193
1.493
1.536
4.261
3.375
0.452
0.328
4.217
3.193
1.493
1.536
4.261
3.375
0.452
0.328
4.217
3.193
1.493
1.536
4.261
3.375
0.452
0.328
4.530
2.630
2.217
1.799
4.570
2.680
0.452
0.328
4.530
2.630
2.217
1.799
4.570
2.680
0.452
0.328
4.530
2.630
2.217
1.799
4.570
2.680
0.452
0.328
Block Library
MIN.
0.007
0.010
0.007
0.010
0.007
0.010
0.007
0.010
0.007
0.010
0.007
0.010
0.007
0.010
A13872EJ5V0BL
t1
TYP.
0.010
0.012
0.010
0.012
0.010
0.012
0.010
0.012
0.010
0.012
0.010
0.012
0.010
0.012
T
MAX.
MIN.
TYP.
MAX.
0.044
0.077
0.059
0.103
0.086
0.150
0.044
0.077
0.059
0.104
0.086
0.151
0.044
0.077
0.059
0.103
0.086
0.150
0.044
0.077
0.059
0.104
0.086
0.151
0.044
0.077
0.059
0.103
0.086
0.150
0.044
0.077
0.059
0.104
0.086
0.151
0.044
0.077
0.059
0.103
0.086
0.150
0.044
0.077
0.059
0.104
0.086
0.151
0.031
0.039
0.042
0.053
0.066
0.075
0.031
0.040
0.042
0.054
0.066
0.077
0.031
0.039
0.042
0.053
0.066
0.075
0.031
0.040
0.042
0.054
0.066
0.077
0.031
0.039
0.042
0.053
0.066
0.075
0.031
0.040
0.042
0.054
0.066
0.077
0.014
0.017
0.014
0.017
0.014
0.017
0.014
0.017
0.014
0.017
0.014
0.017
0.014
0.017
1 - 35
Chapter 1 Interface Block
Block type
IN
BEWC
EN → Y0
Y0 → Y1
BE03
A → Y0
EN → Y0
Y0 → Y1
BED3
A → Y0
EN → Y0
Y0 → Y1
BEU3
A → Y0
EN → Y0
Y0 → Y1
BEW3
A → Y0
EN → Y0
Y0 → Y1
BE01
A → Y0
EN → Y0
Y0 → Y1
BED1
Switching speed
t LD0 (ns)
Path
→ OUT
A → Y0
A → Y0
EN → Y0
Y0 → Y1
Chapter 1 Interface Block
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
MIN.
TYP.
MAX.
0.951
0.874
0.948
0.817
0.943
0.868
0.160
0.103
1.027
1.034
1.369
0.981
1.005
0.864
0.160
0.103
1.027
1.034
1.369
0.981
1.005
0.864
0.160
0.103
1.027
1.034
1.369
0.981
1.005
0.864
0.160
0.103
1.027
1.034
1.369
0.981
1.005
0.864
0.160
0.103
1.086
1.107
1.585
1.138
1.039
0.873
0.160
0.103
1.086
1.107
1.585
1.138
1.039
0.873
0.160
0.103
1.724
1.428
1.269
1.158
1.755
1.494
0.236
0.168
1.876
1.615
1.836
1.364
1.906
1.475
0.236
0.168
1.876
1.615
1.836
1.364
1.906
1.475
0.236
0.168
1.876
1.615
1.836
1.364
1.906
1.475
0.236
0.168
1.876
1.615
1.836
1.364
1.906
1.475
0.236
0.168
1.963
1.718
2.130
1.564
1.989
1.486
0.236
0.168
1.963
1.718
2.130
1.564
1.989
1.486
0.236
0.168
4.530
2.630
2.217
1.799
4.570
2.680
0.452
0.328
5.188
2.959
3.377
2.013
5.246
2.488
0.452
0.328
5.188
2.959
3.377
2.013
5.246
2.488
0.452
0.328
5.188
2.959
3.377
2.013
5.246
2.488
0.452
0.328
5.188
2.959
3.377
2.013
5.246
2.488
0.452
0.328
5.554
3.065
3.959
2.214
5.597
2.412
0.452
0.328
5.554
3.065
3.959
2.214
5.597
2.412
0.452
0.328
Block Library
MIN.
t1
TYP.
Block type
T
MAX.
MIN.
TYP.
MAX.
0.031
0.039
0.042
0.053
0.066
0.075
IN
BEU1
A → Y0
EN → Y0
0.031
0.040
0.007
0.010
0.010
0.012
0.042
0.054
0.066
0.077
Y0 → Y1
0.014
0.017
0.022
0.026
0.031
0.035
0.053
0.049
BEW1
A → Y0
EN → Y0
0.007
0.010
0.010
0.012
0.022
0.029
0.031
0.038
0.053
0.054
0.022
0.026
0.031
0.035
0.053
0.049
Y0 → Y1
0.014
0.017
BE05
A → Y0
EN → Y0
0.022
0.029
0.007
0.010
0.010
0.012
0.031
0.038
0.053
0.054
Y0 → Y1
0.014
0.017
0.022
0.026
0.031
0.035
0.053
0.049
BED5
A → Y0
EN → Y0
0.022
0.029
0.007
0.010
0.010
0.012
0.031
0.038
0.053
0.054
Y0 → Y1
0.014
0.017
0.022
0.026
0.031
0.035
0.053
0.049
0.022
0.029
0.031
0.038
0.053
0.054
BEU5
A → Y0
EN → Y0
0.007
0.010
0.010
0.012
Y0 → Y1
0.014
0.017
0.020
0.021
0.029
0.028
0.051
0.037
BEW5
A → Y0
EN → Y0
0.021
0.023
0.007
0.010
0.010
0.012
0.029
0.031
0.051
0.043
Y0 → Y1
0.014
0.017
0.020
0.021
0.029
0.028
0.051
0.037
BE0F
A → Y0
EN → Y0
0.021
0.023
0.007
0.010
A13872EJ5V0BL
0.010
0.012
0.029
0.031
0.051
0.043
Y0 → Y1
0.014
0.017
1 - 36
Switching speed
t LD0 (ns)
Path
→ OUT
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
MIN.
TYP.
MAX.
1.086
1.107
1.585
1.138
1.039
0.873
0.160
0.103
1.086
1.107
1.585
1.138
1.039
0.873
0.160
0.103
1.249
1.391
2.247
1.467
1.139
0.902
0.160
0.103
1.249
1.391
2.247
1.467
1.139
0.902
0.160
0.103
1.249
1.391
2.247
1.467
1.139
0.902
0.160
0.103
1.249
1.391
2.247
1.467
1.139
0.902
0.160
0.103
1.429
1.676
2.920
1.791
1.236
0.934
0.160
0.103
1.963
1.718
2.130
1.564
1.989
1.486
0.236
0.168
1.963
1.718
2.130
1.564
1.989
1.486
0.236
0.168
2.239
2.128
3.020
1.974
2.241
1.547
0.236
0.168
2.239
2.128
3.020
1.974
2.241
1.547
0.236
0.168
2.239
2.128
3.020
1.974
2.241
1.547
0.236
0.168
2.239
2.128
3.020
1.974
2.241
1.547
0.236
0.168
2.521
2.541
3.913
2.376
2.487
1.621
0.236
0.168
5.554
3.065
3.959
2.214
5.597
2.412
0.452
0.328
5.554
3.065
3.959
2.214
5.597
2.412
0.452
0.328
6.618
3.712
5.777
2.649
6.670
2.379
0.452
0.328
6.618
3.712
5.777
2.649
6.670
2.379
0.452
0.328
6.618
3.712
5.777
2.649
6.670
2.379
0.452
0.328
6.618
3.712
5.777
2.649
6.670
2.379
0.452
0.328
7.676
4.411
7.573
3.054
7.732
2.393
0.452
0.328
Block Library
MIN.
0.007
0.010
0.007
0.010
0.007
0.010
0.007
0.010
0.007
0.010
0.007
0.010
0.007
0.010
t1
TYP.
0.010
0.012
0.010
0.012
0.010
0.012
0.010
0.012
0.010
0.012
0.010
0.012
0.010
0.012
A13872EJ5V0BL
T
MAX.
MIN.
TYP.
MAX.
0.020
0.021
0.029
0.028
0.051
0.037
0.021
0.023
0.029
0.031
0.051
0.043
0.020
0.021
0.029
0.028
0.051
0.037
0.021
0.023
0.029
0.031
0.051
0.043
0.017
0.015
0.026
0.020
0.049
0.028
0.018
0.019
0.026
0.025
0.049
0.033
0.017
0.015
0.026
0.020
0.049
0.028
0.018
0.019
0.026
0.025
0.049
0.033
0.017
0.015
0.026
0.020
0.049
0.028
0.018
0.019
0.026
0.025
0.049
0.033
0.017
0.015
0.026
0.020
0.049
0.028
0.018
0.019
0.026
0.025
0.049
0.033
0.015
0.012
0.025
0.017
0.049
0.023
0.017
0.017
0.026
0.023
0.049
0.029
0.014
0.017
0.014
0.017
0.014
0.017
0.014
0.017
0.014
0.017
0.014
0.017
0.014
0.017
1 - 37
Chapter 1 Interface Block
Block type
IN
BEDF
EN → Y0
Y0 → Y1
BEUF
A → Y0
EN → Y0
Y0 → Y1
BEWF
Switching speed
t LD0 (ns)
Path
→ OUT
A → Y0
A → Y0
EN → Y0
Y0 → Y1
Chapter 1 Interface Block
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
MIN.
TYP.
MAX.
1.429
1.676
2.920
1.791
1.236
0.934
0.160
0.103
1.429
1.676
2.920
1.791
1.236
0.934
0.160
0.103
1.429
1.676
2.920
1.791
1.236
0.934
0.160
0.103
2.521
2.541
3.913
2.376
2.487
1.621
0.236
0.168
2.521
2.541
3.913
2.376
2.487
1.621
0.236
0.168
2.521
2.541
3.913
2.376
2.487
1.621
0.236
0.168
7.676
4.411
7.573
3.054
7.732
2.393
0.452
0.328
7.676
4.411
7.573
3.054
7.732
2.393
0.452
0.328
7.676
4.411
7.573
3.054
7.732
2.393
0.452
0.328
Block Library
MIN.
0.007
0.010
0.007
0.010
0.007
0.010
A13872EJ5V0BL
[MEMO]
t1
TYP.
0.010
0.012
0.010
0.012
0.010
0.012
T
MAX.
MIN.
TYP.
MAX.
0.015
0.012
0.025
0.017
0.049
0.023
0.017
0.017
0.026
0.023
0.049
0.029
0.015
0.012
0.025
0.017
0.049
0.023
0.017
0.017
0.026
0.023
0.049
0.029
0.015
0.012
0.025
0.017
0.049
0.023
0.017
0.017
0.026
0.023
0.049
0.029
0.014
0.017
0.014
0.017
0.014
0.017
1 - 38
Block Library
A13872EJ5V0BL
1 - 39
Chapter 1 Interface Block
Chapter 1 Interface Block
Block type
Block type
Drivability
no resistor
with 50 KΩ P/D
IN
with 50 KΩ P/U
with 5 KΩ P/U
I/O cells int. Cells
BSIUW
1mA
Path
→ OUT
A → Y0
EN → Y0
2mA
3mA
BSIUW
BSDUW
BSUUW
BSWUW
1
13
6mA
BSICW
BSDCW
BSUCW
BSWCW
1
13
9mA
BSI3W
BSD3W
BSU3W
BSW3W
1
13
12mA
BSI1W
BSD1W
BSU1W
BSW1W
1
23
18mA
BSI5W
BSD5W
BSU5W
BSW5W
1
23
24mA
BSIFW
BSDFW
BSUFW
BSWFW
1
23
Logic Diagram
Block type
BSIUW to BSWUW
Input
Y0 → Y1
BSDUW
EN → Y0
Y0 → Y1
Output
Symbol Fan-in Symbol Fan-out
A
6.3
EN
1.0
A
6.3
EN
1.0
A
6.3
EN
1.0
Y1
A → Y0
BSUUW
A → Y0
42
EN → Y0
Y1 N02
BSICW to BSWCW
A H02
N01 Y0
EN H03
BSI3W to BSW3W
BSI1W to BSW1W
BSI5W to BSW5W
Truth Table
A
EN
Y0
0
1
0
1
1
1
X
0
Z
BSIFW to BSWFW
A
16.9
EN
1.0
A
16.9
EN
1.0
A
16.9
EN
1.0
Y1
42
Y0 → Y1
Y1
42
BSWUW
Y1
42
Y0 → Y1
Y1
42
BSICW
0
0
1
1
A → Y0
EN → Y0
Y1
42
Y0 → Y1
BSDCW
A → Y0
EN → Y0
Z:High Impedance
Y1
A → Y0
EN → Y0
X:Irrelevant
Y0
Switching speed
t LD0 (ns)
CMOS 5.0 V
Schmitt I/O Buffer
Function
Y0 → Y1
BSUCW
A → Y0
EN → Y0
Y0 → Y1
Block Library
A13872EJ5V0BL
1 - 40
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
MIN.
TYP.
MAX.
0.591
0.710
1.088
0.380
0.832
0.771
0.673
0.901
0.591
0.710
1.088
0.380
0.832
0.771
0.673
0.901
0.591
0.710
1.088
0.380
0.832
0.771
0.673
0.901
0.591
0.710
1.088
0.380
0.832
0.771
0.673
0.901
0.613
0.650
1.413
0.451
0.851
0.667
0.673
0.901
0.613
0.650
1.413
0.451
0.851
0.667
0.673
0.901
0.613
0.650
1.413
0.451
0.851
0.667
0.673
0.901
1.045
1.257
1.523
0.577
1.425
1.385
0.949
1.332
1.045
1.257
1.523
0.577
1.425
1.385
0.949
1.332
1.045
1.257
1.523
0.577
1.425
1.385
0.949
1.332
1.045
1.257
1.523
0.577
1.425
1.385
0.949
1.332
1.080
1.081
1.971
0.675
1.454
1.152
0.949
1.332
1.080
1.081
1.971
0.675
1.454
1.152
0.949
1.332
1.080
1.081
1.971
0.675
1.454
1.152
0.949
1.332
2.529
2.776
2.712
0.996
3.216
2.985
1.621
2.207
2.529
2.776
2.712
0.996
3.216
2.985
1.621
2.207
2.529
2.776
2.712
0.996
3.216
2.985
1.621
2.207
2.529
2.776
2.712
0.996
3.216
2.985
1.621
2.207
2.673
2.183
3.618
1.128
3.330
2.242
1.621
2.207
2.673
2.183
3.618
1.128
3.330
2.242
1.621
2.207
2.673
2.183
3.618
1.128
3.330
2.242
1.621
2.207
Block Library
MIN.
0.008
0.009
0.008
0.009
0.008
0.009
0.008
0.009
0.008
0.009
0.008
0.009
0.008
0.009
A13872EJ5V0BL
t1
TYP.
0.011
0.012
0.011
0.012
0.011
0.012
0.011
0.012
0.011
0.012
0.011
0.012
0.011
0.012
T
MAX.
MIN.
TYP.
MAX.
0.042
0.076
0.056
0.103
0.080
0.149
0.042
0.077
0.056
0.103
0.077
0.150
0.042
0.076
0.056
0.103
0.080
0.149
0.042
0.077
0.056
0.103
0.077
0.150
0.042
0.076
0.056
0.103
0.080
0.149
0.042
0.077
0.056
0.103
0.077
0.150
0.042
0.076
0.056
0.103
0.080
0.149
0.042
0.077
0.056
0.103
0.077
0.150
0.029
0.038
0.039
0.051
0.057
0.073
0.029
0.039
0.039
0.052
0.056
0.076
0.029
0.038
0.039
0.051
0.057
0.073
0.029
0.039
0.039
0.052
0.056
0.076
0.029
0.038
0.039
0.051
0.057
0.073
0.029
0.039
0.039
0.052
0.056
0.076
0.017
0.016
0.017
0.016
0.017
0.016
0.017
0.016
0.017
0.016
0.017
0.016
0.017
0.016
1 - 41
Chapter 1 Interface Block
Block type
IN
BSWCW
EN → Y0
Y0 → Y1
BSI3W
A → Y0
EN → Y0
Y0 → Y1
BSD3W
A → Y0
EN → Y0
Y0 → Y1
BSU3W
A → Y0
EN → Y0
Y0 → Y1
BSW3W
A → Y0
EN → Y0
Y0 → Y1
BSI1W
A → Y0
EN → Y0
Y0 → Y1
BSD1W
Switching speed
t LD0 (ns)
Path
→ OUT
A → Y0
A → Y0
EN → Y0
Y0 → Y1
Chapter 1 Interface Block
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
MIN.
TYP.
MAX.
0.613
0.650
1.413
0.451
0.851
0.667
0.673
0.901
0.663
0.787
1.970
0.510
0.902
0.653
0.673
0.901
0.663
0.787
1.970
0.510
0.902
0.653
0.673
0.901
0.663
0.787
1.970
0.510
0.902
0.653
0.673
0.901
0.663
0.787
1.970
0.510
0.902
0.653
0.673
0.901
0.491
0.508
1.692
0.628
0.952
0.646
0.673
0.901
0.491
0.508
1.692
0.628
0.952
0.646
0.673
0.901
1.080
1.081
1.971
0.675
1.454
1.152
0.949
1.332
1.177
1.252
2.727
0.752
1.553
1.109
0.949
1.332
1.177
1.252
2.727
0.752
1.553
1.109
0.949
1.332
1.177
1.252
2.727
0.752
1.553
1.109
0.949
1.332
1.177
1.252
2.727
0.752
1.553
1.109
0.949
1.332
0.857
0.827
2.427
0.961
1.561
1.051
0.949
1.332
0.857
0.827
2.427
0.961
1.561
1.051
0.949
1.332
2.673
2.183
3.618
1.128
3.330
2.242
1.621
2.207
3.036
2.495
5.121
1.213
3.690
2.032
1.621
2.207
3.036
2.495
5.121
1.213
3.690
2.032
1.621
2.207
3.036
2.495
5.121
1.213
3.690
2.032
1.621
2.207
3.036
2.495
5.121
1.213
3.690
2.032
1.621
2.207
2.145
1.674
4.634
1.612
3.392
1.954
1.621
2.207
2.145
1.674
4.634
1.612
3.392
1.954
1.621
2.207
Block Library
MIN.
t1
TYP.
Block type
T
MAX.
MIN.
TYP.
MAX.
0.029
0.038
0.039
0.051
0.057
0.073
IN
BSU1W
A → Y0
EN → Y0
0.029
0.039
0.008
0.009
0.011
0.012
0.039
0.052
0.056
0.076
Y0 → Y1
0.017
0.016
0.019
0.025
0.026
0.033
0.041
0.047
BSW1W
A → Y0
EN → Y0
0.008
0.009
0.011
0.012
0.019
0.027
0.026
0.036
0.041
0.051
0.019
0.025
0.026
0.033
0.041
0.047
Y0 → Y1
0.017
0.016
BSI5W
A → Y0
EN → Y0
0.019
0.027
0.008
0.009
0.011
0.012
0.026
0.036
0.041
0.051
Y0 → Y1
0.017
0.016
0.019
0.025
0.026
0.033
0.041
0.047
BSD5W
A → Y0
EN → Y0
0.019
0.027
0.008
0.009
0.011
0.012
0.026
0.036
0.041
0.051
Y0 → Y1
0.017
0.016
0.019
0.025
0.026
0.033
0.041
0.047
0.019
0.027
0.026
0.036
0.041
0.051
BSU5W
A → Y0
EN → Y0
0.008
0.009
0.011
0.012
Y0 → Y1
0.017
0.016
0.015
0.019
0.021
0.025
0.033
0.036
BSW5W
A → Y0
EN → Y0
0.015
0.020
0.008
0.009
0.011
0.012
0.021
0.027
0.032
0.038
Y0 → Y1
0.017
0.016
0.015
0.019
0.021
0.025
0.033
0.036
BSIFW
A → Y0
EN → Y0
0.015
0.020
0.008
0.009
A13872EJ5V0BL
0.011
0.012
0.021
0.027
0.032
0.038
Y0 → Y1
0.017
0.016
1 - 42
Switching speed
t LD0 (ns)
Path
→ OUT
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
MIN.
TYP.
MAX.
0.491
0.508
1.692
0.628
0.952
0.646
0.673
0.901
0.491
0.508
1.692
0.628
0.952
0.646
0.673
0.901
0.540
0.619
2.230
0.713
0.997
0.647
0.673
0.901
0.540
0.619
2.230
0.713
0.997
0.647
0.673
0.901
0.540
0.619
2.230
0.713
0.997
0.647
0.673
0.901
0.540
0.619
2.230
0.713
0.997
0.647
0.673
0.901
0.588
0.729
2.768
0.796
1.036
0.650
0.673
0.901
0.857
0.827
2.427
0.961
1.561
1.051
0.949
1.332
0.857
0.827
2.427
0.961
1.561
1.051
0.949
1.332
0.952
0.988
3.165
1.069
1.655
1.048
0.949
1.332
0.952
0.988
3.165
1.069
1.655
1.048
0.949
1.332
0.952
0.988
3.165
1.069
1.655
1.048
0.949
1.332
0.952
0.988
3.165
1.069
1.655
1.048
0.949
1.332
1.038
1.148
3.922
1.176
1.734
1.054
0.949
1.332
2.145
1.674
4.634
1.612
3.392
1.954
1.621
2.207
2.145
1.674
4.634
1.612
3.392
1.954
1.621
2.207
2.455
1.917
6.099
1.724
3.703
1.880
1.621
2.207
2.455
1.917
6.099
1.724
3.703
1.880
1.621
2.207
2.455
1.917
6.099
1.724
3.703
1.880
1.621
2.207
2.455
1.917
6.099
1.724
3.703
1.880
1.621
2.207
2.740
2.184
7.625
1.839
3.989
1.852
1.621
2.207
Block Library
MIN.
0.008
0.009
0.008
0.009
0.008
0.009
0.008
0.009
0.008
0.009
0.008
0.009
0.008
0.009
t1
TYP.
0.011
0.012
0.011
0.012
0.011
0.012
0.011
0.012
0.011
0.012
0.011
0.012
0.011
0.012
A13872EJ5V0BL
T
MAX.
MIN.
TYP.
MAX.
0.015
0.019
0.021
0.025
0.033
0.036
0.015
0.020
0.021
0.027
0.032
0.038
0.015
0.019
0.021
0.025
0.033
0.036
0.015
0.020
0.021
0.027
0.032
0.038
0.012
0.013
0.017
0.017
0.029
0.026
0.012
0.014
0.017
0.019
0.028
0.027
0.012
0.013
0.017
0.017
0.029
0.026
0.012
0.014
0.017
0.019
0.028
0.027
0.012
0.013
0.017
0.017
0.029
0.026
0.012
0.014
0.017
0.019
0.028
0.027
0.012
0.013
0.017
0.017
0.029
0.026
0.012
0.014
0.017
0.019
0.028
0.027
0.011
0.010
0.015
0.014
0.028
0.021
0.011
0.011
0.015
0.016
0.027
0.022
0.017
0.016
0.017
0.016
0.017
0.016
0.017
0.016
0.017
0.016
0.017
0.016
0.017
0.016
1 - 43
Chapter 1 Interface Block
Block type
IN
BSDFW
EN → Y0
Y0 → Y1
BSUFW
A → Y0
EN → Y0
Y0 → Y1
BSWFW
Switching speed
t LD0 (ns)
Path
→ OUT
A → Y0
A → Y0
EN → Y0
Y0 → Y1
Chapter 1 Interface Block
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
MIN.
TYP.
MAX.
0.588
0.729
2.768
0.796
1.036
0.650
0.673
0.901
0.588
0.729
2.768
0.796
1.036
0.650
0.673
0.901
0.588
0.729
2.768
0.796
1.036
0.650
0.673
0.901
1.038
1.148
3.922
1.176
1.734
1.054
0.949
1.332
1.038
1.148
3.922
1.176
1.734
1.054
0.949
1.332
1.038
1.148
3.922
1.176
1.734
1.054
0.949
1.332
2.740
2.184
7.625
1.839
3.989
1.852
1.621
2.207
2.740
2.184
7.625
1.839
3.989
1.852
1.621
2.207
2.740
2.184
7.625
1.839
3.989
1.852
1.621
2.207
Block Library
MIN.
0.008
0.009
0.008
0.009
0.008
0.009
A13872EJ5V0BL
[MEMO]
t1
TYP.
0.011
0.012
0.011
0.012
0.011
0.012
T
MAX.
MIN.
TYP.
MAX.
0.011
0.010
0.015
0.014
0.028
0.021
0.011
0.011
0.015
0.016
0.027
0.022
0.011
0.010
0.015
0.014
0.028
0.021
0.011
0.011
0.015
0.016
0.027
0.022
0.011
0.010
0.015
0.014
0.028
0.021
0.011
0.011
0.015
0.016
0.027
0.022
0.017
0.016
0.017
0.016
0.017
0.016
1 - 44
Block Library
A13872EJ5V0BL
1 - 45
Chapter 1 Interface Block
Chapter 1 Interface Block
Block type
Block type
Drivability
no resistor
with 50 KΩ P/D
IN
with 50 KΩ P/U
with 5 KΩ P/U
I/O cells int. Cells
BFIUW
1mA
Path
→ OUT
A → Y0
EN → Y0
2mA
3mA
BFIUW
BFDUW
BFUUW
BFWUW
1
13
6mA
BFICW
BFDCW
BFUCW
BFWCW
1
13
9mA
BFI3W
BFD3W
BFU3W
BFW3W
1
13
12mA
BFI1W
BFD1W
BFU1W
BFW1W
1
13
18mA
BFI5W
BFD5W
BFU5W
BFW5W
1
13
24mA
BFIFW
BFDFW
BFUFW
BFWFW
1
13
Logic Diagram
Block type
BFIUW to BFWUW
Input
Y0 → Y1
BFDUW
EN → Y0
Y0 → Y1
Output
Symbol Fan-in Symbol Fan-out
A
6.2
EN
4.0
A
6.1
EN
4.0
A
6.2
EN
4.0
Y1
A → Y0
BFUUW
A → Y0
42
EN → Y0
Y1 N02
BFICW to BFWCW
A H02
N01 Y0
EN H03
BFI3W to BFW3W
BFI1W to BFW1W
BFI5W to BFW5W
Truth Table
A
EN
Y0
0
1
0
1
1
1
X
0
Z
BFIFW to BFWFW
A
6.2
EN
4.0
A
6.2
EN
4.0
A
6.2
EN
4.0
Y1
42
Y0 → Y1
Y1
42
BFWUW
Y1
42
Y0 → Y1
Y1
42
BFICW
0
0
1
1
A → Y0
EN → Y0
Y1
42
Y0 → Y1
BFDCW
A → Y0
EN → Y0
Z:High Impedance
Y1
A → Y0
EN → Y0
X:Irrelevant
Y0
Switching speed
t LD0 (ns)
CMOS 5.0 V
Low-noise Schmitt I/O Buffer
Function
Y0 → Y1
BFUCW
A → Y0
EN → Y0
Y0 → Y1
Block Library
A13872EJ5V0BL
1 - 46
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
MIN.
TYP.
MAX.
0.906
0.903
0.697
0.638
0.907
0.940
0.673
0.901
0.906
0.903
0.697
0.638
0.907
0.940
0.673
0.901
0.906
0.903
0.697
0.638
0.907
0.940
0.673
0.901
0.906
0.903
0.697
0.638
0.907
0.940
0.673
0.901
0.951
0.874
0.948
0.817
0.943
0.868
0.673
0.901
0.951
0.874
0.948
0.817
0.943
0.868
0.673
0.901
0.951
0.874
0.948
0.817
0.943
0.868
0.673
0.901
1.649
1.561
0.916
0.928
1.682
1.673
0.949
1.332
1.649
1.561
0.916
0.928
1.682
1.673
0.949
1.332
1.649
1.561
0.916
0.928
1.682
1.673
0.949
1.332
1.649
1.561
0.916
0.928
1.682
1.673
0.949
1.332
1.724
1.428
1.269
1.158
1.755
1.494
0.949
1.332
1.724
1.428
1.269
1.158
1.755
1.494
0.949
1.332
1.724
1.428
1.269
1.158
1.755
1.494
0.949
1.332
4.217
3.193
1.493
1.536
4.261
3.375
1.621
2.207
4.217
3.193
1.493
1.536
4.261
3.375
1.621
2.207
4.217
3.193
1.493
1.536
4.261
3.375
1.621
2.207
4.217
3.193
1.493
1.536
4.261
3.375
1.621
2.207
4.530
2.630
2.217
1.799
4.570
2.680
1.621
2.207
4.530
2.630
2.217
1.799
4.570
2.680
1.621
2.207
4.530
2.630
2.217
1.799
4.570
2.680
1.621
2.207
Block Library
MIN.
0.008
0.009
0.008
0.009
0.008
0.009
0.008
0.009
0.008
0.009
0.008
0.009
0.008
0.009
A13872EJ5V0BL
t1
TYP.
0.011
0.012
0.011
0.012
0.011
0.012
0.011
0.012
0.011
0.012
0.011
0.012
0.011
0.012
T
MAX.
MIN.
TYP.
MAX.
0.044
0.077
0.059
0.103
0.086
0.150
0.044
0.077
0.059
0.104
0.086
0.151
0.044
0.077
0.059
0.103
0.086
0.150
0.044
0.077
0.059
0.104
0.086
0.151
0.044
0.077
0.059
0.103
0.086
0.150
0.044
0.077
0.059
0.104
0.086
0.151
0.044
0.077
0.059
0.103
0.086
0.150
0.044
0.077
0.059
0.104
0.086
0.151
0.031
0.039
0.042
0.053
0.066
0.075
0.031
0.040
0.042
0.054
0.066
0.077
0.031
0.039
0.042
0.053
0.066
0.075
0.031
0.040
0.042
0.054
0.066
0.077
0.031
0.039
0.042
0.053
0.066
0.075
0.031
0.040
0.042
0.054
0.066
0.077
0.017
0.016
0.017
0.016
0.017
0.016
0.017
0.016
0.017
0.016
0.017
0.016
0.017
0.016
1 - 47
Chapter 1 Interface Block
Block type
IN
BFWCW
EN → Y0
Y0 → Y1
BFI3W
A → Y0
EN → Y0
Y0 → Y1
BFD3W
A → Y0
EN → Y0
Y0 → Y1
BFU3W
A → Y0
EN → Y0
Y0 → Y1
BFW3W
A → Y0
EN → Y0
Y0 → Y1
BFI1W
A → Y0
EN → Y0
Y0 → Y1
BFD1W
Switching speed
t LD0 (ns)
Path
→ OUT
A → Y0
A → Y0
EN → Y0
Y0 → Y1
Chapter 1 Interface Block
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
MIN.
TYP.
MAX.
0.951
0.874
0.948
0.817
0.943
0.868
0.673
0.901
1.027
1.034
1.369
0.981
1.005
0.864
0.673
0.901
1.027
1.034
1.369
0.981
1.005
0.864
0.673
0.901
1.027
1.034
1.369
0.981
1.005
0.864
0.673
0.901
1.027
1.034
1.369
0.981
1.005
0.864
0.673
0.901
1.086
1.107
1.585
1.138
1.039
0.873
0.673
0.901
1.086
1.107
1.585
1.138
1.039
0.873
0.673
0.901
1.724
1.428
1.269
1.158
1.755
1.494
0.949
1.332
1.876
1.615
1.836
1.364
1.906
1.475
0.949
1.332
1.876
1.615
1.836
1.364
1.906
1.475
0.949
1.332
1.876
1.615
1.836
1.364
1.906
1.475
0.949
1.332
1.876
1.615
1.836
1.364
1.906
1.475
0.949
1.332
1.963
1.718
2.130
1.564
1.989
1.486
0.949
1.332
1.963
1.718
2.130
1.564
1.989
1.486
0.949
1.332
4.530
2.630
2.217
1.799
4.570
2.680
1.621
2.207
5.188
2.959
3.377
2.013
5.246
2.488
1.621
2.207
5.188
2.959
3.377
2.013
5.246
2.488
1.621
2.207
5.188
2.959
3.377
2.013
5.246
2.488
1.621
2.207
5.188
2.959
3.377
2.013
5.246
2.488
1.621
2.207
5.554
3.065
3.959
2.214
5.597
2.412
1.621
2.207
5.554
3.065
3.959
2.214
5.597
2.412
1.621
2.207
Block Library
MIN.
t1
TYP.
Block type
T
MAX.
MIN.
TYP.
MAX.
0.031
0.039
0.042
0.053
0.066
0.075
IN
BFU1W
A → Y0
EN → Y0
0.031
0.040
0.008
0.009
0.011
0.012
0.042
0.054
0.066
0.077
Y0 → Y1
0.017
0.016
0.022
0.026
0.031
0.035
0.053
0.049
BFW1W
A → Y0
EN → Y0
0.008
0.009
0.011
0.012
0.022
0.029
0.031
0.038
0.053
0.054
0.022
0.026
0.031
0.035
0.053
0.049
Y0 → Y1
0.017
0.016
BFI5W
A → Y0
EN → Y0
0.022
0.029
0.008
0.009
0.011
0.012
0.031
0.038
0.053
0.054
Y0 → Y1
0.017
0.016
0.022
0.026
0.031
0.035
0.053
0.049
BFD5W
A → Y0
EN → Y0
0.022
0.029
0.008
0.009
0.011
0.012
0.031
0.038
0.053
0.054
Y0 → Y1
0.017
0.016
0.022
0.026
0.031
0.035
0.053
0.049
0.022
0.029
0.031
0.038
0.053
0.054
BFU5W
A → Y0
EN → Y0
0.008
0.009
0.011
0.012
Y0 → Y1
0.017
0.016
0.020
0.021
0.029
0.028
0.051
0.037
BFW5W
A → Y0
EN → Y0
0.021
0.023
0.008
0.009
0.011
0.012
0.029
0.031
0.051
0.043
Y0 → Y1
0.017
0.016
0.020
0.021
0.029
0.028
0.051
0.037
BFIFW
A → Y0
EN → Y0
0.021
0.023
0.008
0.009
A13872EJ5V0BL
0.011
0.012
0.029
0.031
0.051
0.043
Y0 → Y1
0.017
0.016
1 - 48
Switching speed
t LD0 (ns)
Path
→ OUT
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
MIN.
TYP.
MAX.
1.086
1.107
1.585
1.138
1.039
0.873
0.673
0.901
1.086
1.107
1.585
1.138
1.039
0.873
0.673
0.901
1.249
1.391
2.247
1.467
1.139
0.902
0.673
0.901
1.249
1.391
2.247
1.467
1.139
0.902
0.673
0.901
1.249
1.391
2.247
1.467
1.139
0.902
0.673
0.901
1.249
1.391
2.247
1.467
1.139
0.902
0.673
0.901
1.429
1.676
2.920
1.791
1.236
0.934
0.673
0.901
1.963
1.718
2.130
1.564
1.989
1.486
0.949
1.332
1.963
1.718
2.130
1.564
1.989
1.486
0.949
1.332
2.239
2.128
3.020
1.974
2.241
1.547
0.949
1.332
2.239
2.128
3.020
1.974
2.241
1.547
0.949
1.332
2.239
2.128
3.020
1.974
2.241
1.547
0.949
1.332
2.239
2.128
3.020
1.974
2.241
1.547
0.949
1.332
2.521
2.541
3.913
2.376
2.487
1.621
0.949
1.332
5.554
3.065
3.959
2.214
5.597
2.412
1.621
2.207
5.554
3.065
3.959
2.214
5.597
2.412
1.621
2.207
6.618
3.712
5.777
2.649
6.670
2.379
1.621
2.207
6.618
3.712
5.777
2.649
6.670
2.379
1.621
2.207
6.618
3.712
5.777
2.649
6.670
2.379
1.621
2.207
6.618
3.712
5.777
2.649
6.670
2.379
1.621
2.207
7.676
4.411
7.573
3.054
7.732
2.393
1.621
2.207
Block Library
MIN.
0.008
0.009
0.008
0.009
0.008
0.009
0.008
0.009
0.008
0.009
0.008
0.009
0.008
0.009
t1
TYP.
0.011
0.012
0.011
0.012
0.011
0.012
0.011
0.012
0.011
0.012
0.011
0.012
0.011
0.012
A13872EJ5V0BL
T
MAX.
MIN.
TYP.
MAX.
0.020
0.021
0.029
0.028
0.051
0.037
0.021
0.023
0.029
0.031
0.051
0.043
0.020
0.021
0.029
0.028
0.051
0.037
0.021
0.023
0.029
0.031
0.051
0.043
0.017
0.015
0.026
0.020
0.049
0.028
0.018
0.019
0.026
0.025
0.049
0.033
0.017
0.015
0.026
0.020
0.049
0.028
0.018
0.019
0.026
0.025
0.049
0.033
0.017
0.015
0.026
0.020
0.049
0.028
0.018
0.019
0.026
0.025
0.049
0.033
0.017
0.015
0.026
0.020
0.049
0.028
0.018
0.019
0.026
0.025
0.049
0.033
0.015
0.012
0.025
0.017
0.049
0.023
0.017
0.017
0.026
0.023
0.049
0.029
0.017
0.016
0.017
0.016
0.017
0.016
0.017
0.016
0.017
0.016
0.017
0.016
0.017
0.016
1 - 49
Chapter 1 Interface Block
Block type
IN
BFDFW
EN → Y0
Y0 → Y1
BFUFW
A → Y0
EN → Y0
Y0 → Y1
BFWFW
Switching speed
t LD0 (ns)
Path
→ OUT
A → Y0
A → Y0
EN → Y0
Y0 → Y1
Chapter 1 Interface Block
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
MIN.
TYP.
MAX.
1.429
1.676
2.920
1.791
1.236
0.934
0.673
0.901
1.429
1.676
2.920
1.791
1.236
0.934
0.673
0.901
1.429
1.676
2.920
1.791
1.236
0.934
0.673
0.901
2.521
2.541
3.913
2.376
2.487
1.621
0.949
1.332
2.521
2.541
3.913
2.376
2.487
1.621
0.949
1.332
2.521
2.541
3.913
2.376
2.487
1.621
0.949
1.332
7.676
4.411
7.573
3.054
7.732
2.393
1.621
2.207
7.676
4.411
7.573
3.054
7.732
2.393
1.621
2.207
7.676
4.411
7.573
3.054
7.732
2.393
1.621
2.207
Block Library
MIN.
0.008
0.009
0.008
0.009
0.008
0.009
A13872EJ5V0BL
[MEMO]
t1
TYP.
0.011
0.012
0.011
0.012
0.011
0.012
T
MAX.
MIN.
TYP.
MAX.
0.015
0.012
0.025
0.017
0.049
0.023
0.017
0.017
0.026
0.023
0.049
0.029
0.015
0.012
0.025
0.017
0.049
0.023
0.017
0.017
0.026
0.023
0.049
0.029
0.015
0.012
0.025
0.017
0.049
0.023
0.017
0.017
0.026
0.023
0.049
0.029
0.017
0.016
0.017
0.016
0.017
0.016
1 - 50
Block Library
A13872EJ5V0BL
1 - 51
Chapter 1 Interface Block
Chapter 1 Interface Block
Block type
Block type
Drivability
no resistor
with 50 KΩ P/D
IN
with 50 KΩ P/U
with 5 KΩ P/U
I/O cells int. Cells
BN2U
1mA
Path
→ OUT
A → Y0
EN → Y0
2mA
3mA
BN2U
BN4U
1
13
6mA
BN2C
BN4C
1
13
9mA
BN23
BN43
1
13
12mA
BN21
BN41
1
23
18mA
BN25
BN45
1
23
24mA
BN2F
BN4F
1
23
Logic Diagram
Block type
BN2U to BN4U
ENI H04
Input
ENI → Y1
Y0 → Y1
BN4U
BN2C to BN4C
Output
Symbol Fan-in Symbol Fan-out
A
6.3
EN
1.0
ENI
3.0
Y1
ENI → Y1
53
Y0 → Y1
BN2C
A
6.3
EN
1.0
ENI
3.0
A
6.3
Y1
ENI → Y1
BN23 to BN43
EN H03
BN21 to BN41
Truth Table
EN
Y0
0
1
0
1
1
1
X
0
Z
A → Y0
EN → Y0
53
N01 Y0
A
A → Y0
EN → Y0
Y1 N02
A H01
EN
1.0
ENI
3.0
A
16.9
EN
1.0
ENI
3.0
Y1
53
Y0 → Y1
BN4C
Y1
A → Y0
EN → Y0
53
ENI → Y1
BN25 to BN45
A
16.9
EN
1.0
ENI
3.0
A
16.9
Y1
53
Y0 → Y1
BN23
X:Irrelevant
BN2F to BN4F
Z:High Impedance
Y0
ENI
Y1
0
0
0
0
1
0
1
0
0
1
1
1
Switching speed
t LD0 (ns)
CMOS 5.0 V
I/O Buffer with EN(AND)
Function
EN
1.0
ENI
3.0
Y1
A → Y0
EN → Y0
53
ENI → Y1
Y0 → Y1
BN43
A → Y0
EN → Y0
Block Library
A13872EJ5V0BL
1 - 52
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
MIN.
TYP.
MAX.
0.591
0.710
1.088
0.380
0.832
0.771
0.110
0.248
0.096
0.172
0.591
0.710
1.088
0.380
0.832
0.771
0.110
0.248
0.096
0.172
0.613
0.650
1.413
0.451
0.851
0.667
0.110
0.248
0.096
0.172
0.613
0.650
1.413
0.451
0.851
0.667
0.110
0.248
0.096
0.172
0.663
0.787
1.970
0.510
0.902
0.653
0.110
0.248
0.096
0.172
0.663
0.787
1.970
0.510
0.902
0.653
1.045
1.257
1.523
0.577
1.425
1.385
0.171
0.353
0.166
0.254
1.045
1.257
1.523
0.577
1.425
1.385
0.171
0.353
0.166
0.254
1.080
1.081
1.971
0.675
1.454
1.152
0.171
0.353
0.166
0.254
1.080
1.081
1.971
0.675
1.454
1.152
0.171
0.353
0.166
0.254
1.177
1.252
2.727
0.752
1.553
1.109
0.171
0.353
0.166
0.254
1.177
1.252
2.727
0.752
1.553
1.109
2.529
2.776
2.712
0.996
3.216
2.985
0.289
0.510
0.304
0.427
2.529
2.776
2.712
0.996
3.216
2.985
0.289
0.510
0.304
0.427
2.673
2.183
3.618
1.128
3.330
2.242
0.289
0.510
0.304
0.427
2.673
2.183
3.618
1.128
3.330
2.242
0.289
0.510
0.304
0.427
3.036
2.495
5.121
1.213
3.690
2.032
0.289
0.510
0.304
0.427
3.036
2.495
5.121
1.213
3.690
2.032
Block Library
MIN.
0.007
0.010
0.007
0.010
0.007
0.010
0.007
0.010
0.007
0.010
0.007
0.010
0.007
0.010
0.007
0.010
0.007
0.010
0.007
0.010
A13872EJ5V0BL
t1
TYP.
0.010
0.012
0.010
0.012
0.010
0.012
0.010
0.012
0.010
0.012
0.010
0.012
0.010
0.012
0.010
0.012
0.010
0.012
0.010
0.012
T
MAX.
MIN.
TYP.
MAX.
0.042
0.076
0.056
0.103
0.080
0.149
0.042
0.077
0.056
0.103
0.077
0.150
0.042
0.076
0.056
0.103
0.080
0.149
0.042
0.077
0.056
0.103
0.077
0.150
0.029
0.038
0.039
0.051
0.057
0.073
0.029
0.039
0.039
0.052
0.056
0.076
0.029
0.038
0.039
0.051
0.057
0.073
0.029
0.039
0.039
0.052
0.056
0.076
0.019
0.025
0.026
0.033
0.041
0.047
0.019
0.027
0.026
0.036
0.041
0.051
0.019
0.025
0.026
0.033
0.041
0.047
0.019
0.027
0.026
0.036
0.041
0.051
0.014
0.017
0.014
0.017
0.014
0.017
0.014
0.017
0.014
0.017
0.014
0.017
0.014
0.017
0.014
0.017
0.014
0.017
0.014
0.017
1 - 53
Chapter 1 Interface Block
Block type
IN
Y0 → Y1
BN21
A → Y0
EN → Y0
ENI → Y1
Y0 → Y1
BN41
A → Y0
EN → Y0
ENI → Y1
Y0 → Y1
BN25
A → Y0
EN → Y0
ENI → Y1
Y0 → Y1
BN45
A → Y0
EN → Y0
ENI → Y1
Y0 → Y1
BN2F
Switching speed
t LD0 (ns)
Path
→ OUT
ENI → Y1
A → Y0
EN → Y0
ENI → Y1
Y0 → Y1
Chapter 1 Interface Block
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.110
0.248
0.096
0.172
0.491
0.508
1.692
0.628
0.952
0.646
0.110
0.248
0.096
0.172
0.491
0.508
1.692
0.628
0.952
0.646
0.110
0.248
0.096
0.172
0.540
0.619
2.230
0.713
0.997
0.647
0.110
0.248
0.096
0.172
0.540
0.619
2.230
0.713
0.997
0.647
0.110
0.248
0.096
0.172
0.588
0.729
2.768
0.796
1.036
0.650
0.110
0.248
0.096
0.172
0.171
0.353
0.166
0.254
0.857
0.827
2.427
0.961
1.561
1.051
0.171
0.353
0.166
0.254
0.857
0.827
2.427
0.961
1.561
1.051
0.171
0.353
0.166
0.254
0.952
0.988
3.165
1.069
1.655
1.048
0.171
0.353
0.166
0.254
0.952
0.988
3.165
1.069
1.655
1.048
0.171
0.353
0.166
0.254
1.038
1.148
3.922
1.176
1.734
1.054
0.171
0.353
0.166
0.254
0.289
0.510
0.304
0.427
2.145
1.674
4.634
1.612
3.392
1.954
0.289
0.510
0.304
0.427
2.145
1.674
4.634
1.612
3.392
1.954
0.289
0.510
0.304
0.427
2.455
1.917
6.099
1.724
3.703
1.880
0.289
0.510
0.304
0.427
2.455
1.917
6.099
1.724
3.703
1.880
0.289
0.510
0.304
0.427
2.740
2.184
7.625
1.839
3.989
1.852
0.289
0.510
0.304
0.427
0.007
0.010
0.007
0.010
0.010
0.012
0.010
0.012
0.014
0.017
0.014
0.017
Block Library
Block type
T
MIN.
TYP.
IN
MAX.
BN4F
A → Y0
EN → Y0
0.015
0.019
0.021
0.025
0.033
0.036
ENI → Y1
0.007
0.010
0.007
0.010
0.007
0.010
0.007
0.010
0.007
0.010
0.007
0.010
0.007
0.010
0.007
0.010
0.007
0.010
0.007
0.010
A13872EJ5V0BL
0.010
0.012
0.010
0.012
0.010
0.012
0.010
0.012
0.010
0.012
0.010
0.012
0.010
0.012
0.010
0.012
0.010
0.012
0.010
0.012
0.015
0.020
0.021
0.027
0.032
0.038
0.015
0.019
0.021
0.025
0.033
0.036
0.015
0.020
0.021
0.027
0.032
0.038
0.012
0.013
0.017
0.017
0.029
0.026
0.012
0.014
0.017
0.019
0.028
0.027
0.012
0.013
0.017
0.017
0.029
0.026
0.012
0.014
0.017
0.019
0.028
0.027
0.011
0.010
0.015
0.014
0.028
0.021
0.011
0.011
0.015
0.016
0.027
0.022
Switching speed
t LD0 (ns)
Path
→ OUT
Y0 → Y1
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
MIN.
TYP.
MAX.
0.588
0.729
2.768
0.796
1.036
0.650
0.110
0.248
0.096
0.172
1.038
1.148
3.922
1.176
1.734
1.054
0.171
0.353
0.166
0.254
2.740
2.184
7.625
1.839
3.989
1.852
0.289
0.510
0.304
0.427
MIN.
0.007
0.010
0.007
0.010
t1
TYP.
0.010
0.012
0.010
0.012
T
MAX.
MIN.
TYP.
MAX.
0.011
0.010
0.015
0.014
0.028
0.021
0.011
0.011
0.015
0.016
0.027
0.022
0.014
0.017
0.014
0.017
0.014
0.017
0.014
0.017
0.014
0.017
0.014
0.017
0.014
0.017
0.014
0.017
0.014
0.017
0.014
0.017
0.014
0.017
0.014
0.017
1 - 54
Block Library
A13872EJ5V0BL
1 - 55
Chapter 1 Interface Block
Chapter 1 Interface Block
Block type
Block type
Drivability
no resistor
with 50 KΩ P/D
IN
with 50 KΩ P/U
with 5 KΩ P/U
I/O cells int. Cells
BN3U
1mA
Path
→ OUT
A → Y0
EN → Y0
2mA
3mA
BN3U
BN5U
1
11
6mA
BN3C
BN5C
1
11
9mA
BN33
BN53
1
11
12mA
BN31
BN51
1
21
18mA
BN35
BN55
1
21
24mA
BN3F
BN5F
1
21
Logic Diagram
Block type
BN3U to BN5U
ENI H04
Input
ENI → Y1
Y0 → Y1
BN5U
BN3C to BN5C
Output
Symbol Fan-in Symbol Fan-out
A
6.3
EN
1.0
ENI
3.0
Y1
ENI → Y1
52
Y0 → Y1
BN3C
A
6.3
EN
1.0
ENI
3.0
A
6.3
Y1
ENI → Y1
BN33 to BN53
EN H03
BN31 to BN51
Truth Table
EN
Y0
0
1
0
1
1
1
X
0
Z
A → Y0
EN → Y0
52
N01 Y0
A
A → Y0
EN → Y0
Y1 N02
A H01
EN
1.0
ENI
3.0
A
16.9
EN
1.0
ENI
3.0
Y1
52
Y0 → Y1
BN5C
Y1
A → Y0
EN → Y0
52
ENI → Y1
BN35 to BN55
A
16.9
EN
1.0
ENI
3.0
A
16.9
Y1
52
Y0 → Y1
BN33
X:Irrelevant
BN3F to BN5F
Z:High Impedance
Y0
ENI
Y1
0
0
0
0
1
1
1
0
1
1
1
1
Switching speed
t LD0 (ns)
CMOS 5.0 V
I/O Buffer with EN(OR)
Function
EN
1.0
ENI
3.0
Y1
A → Y0
EN → Y0
52
ENI → Y1
Y0 → Y1
BN53
A → Y0
EN → Y0
Block Library
A13872EJ5V0BL
1 - 56
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
MIN.
TYP.
MAX.
0.591
0.710
1.088
0.380
0.832
0.771
0.093
0.240
0.117
0.242
0.591
0.710
1.088
0.380
0.832
0.771
0.093
0.240
0.117
0.242
0.613
0.650
1.413
0.451
0.851
0.667
0.093
0.240
0.117
0.242
0.613
0.650
1.413
0.451
0.851
0.667
0.093
0.240
0.117
0.242
0.663
0.787
1.970
0.510
0.902
0.653
0.093
0.240
0.117
0.242
0.663
0.787
1.970
0.510
0.902
0.653
1.045
1.257
1.523
0.577
1.425
1.385
0.160
0.365
0.183
0.346
1.045
1.257
1.523
0.577
1.425
1.385
0.160
0.365
0.183
0.346
1.080
1.081
1.971
0.675
1.454
1.152
0.160
0.365
0.183
0.346
1.080
1.081
1.971
0.675
1.454
1.152
0.160
0.365
0.183
0.346
1.177
1.252
2.727
0.752
1.553
1.109
0.160
0.365
0.183
0.346
1.177
1.252
2.727
0.752
1.553
1.109
2.529
2.776
2.712
0.996
3.216
2.985
0.270
0.675
0.298
0.553
2.529
2.776
2.712
0.996
3.216
2.985
0.270
0.675
0.298
0.553
2.673
2.183
3.618
1.128
3.330
2.242
0.270
0.675
0.298
0.553
2.673
2.183
3.618
1.128
3.330
2.242
0.270
0.675
0.298
0.553
3.036
2.495
5.121
1.213
3.690
2.032
0.270
0.675
0.298
0.553
3.036
2.495
5.121
1.213
3.690
2.032
Block Library
MIN.
0.007
0.010
0.007
0.010
0.007
0.010
0.007
0.010
0.007
0.010
0.007
0.010
0.007
0.010
0.007
0.010
0.007
0.010
0.007
0.010
A13872EJ5V0BL
t1
TYP.
0.010
0.013
0.010
0.013
0.010
0.013
0.010
0.013
0.010
0.013
0.010
0.013
0.010
0.013
0.010
0.013
0.010
0.013
0.010
0.013
T
MAX.
MIN.
TYP.
MAX.
0.042
0.076
0.056
0.103
0.080
0.149
0.042
0.077
0.056
0.103
0.077
0.150
0.042
0.076
0.056
0.103
0.080
0.149
0.042
0.077
0.056
0.103
0.077
0.150
0.029
0.038
0.039
0.051
0.057
0.073
0.029
0.039
0.039
0.052
0.056
0.076
0.029
0.038
0.039
0.051
0.057
0.073
0.029
0.039
0.039
0.052
0.056
0.076
0.019
0.025
0.026
0.033
0.041
0.047
0.019
0.027
0.026
0.036
0.041
0.051
0.019
0.025
0.026
0.033
0.041
0.047
0.019
0.027
0.026
0.036
0.041
0.051
0.014
0.018
0.014
0.018
0.014
0.018
0.014
0.018
0.014
0.018
0.014
0.018
0.014
0.018
0.014
0.018
0.014
0.018
0.014
0.018
1 - 57
Chapter 1 Interface Block
Block type
IN
Y0 → Y1
BN31
A → Y0
EN → Y0
ENI → Y1
Y0 → Y1
BN51
A → Y0
EN → Y0
ENI → Y1
Y0 → Y1
BN35
A → Y0
EN → Y0
ENI → Y1
Y0 → Y1
BN55
A → Y0
EN → Y0
ENI → Y1
Y0 → Y1
BN3F
Switching speed
t LD0 (ns)
Path
→ OUT
ENI → Y1
A → Y0
EN → Y0
ENI → Y1
Y0 → Y1
Chapter 1 Interface Block
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.093
0.240
0.117
0.242
0.491
0.508
1.692
0.628
0.952
0.646
0.093
0.240
0.117
0.242
0.491
0.508
1.692
0.628
0.952
0.646
0.093
0.240
0.117
0.242
0.540
0.619
2.230
0.713
0.997
0.647
0.093
0.240
0.117
0.242
0.540
0.619
2.230
0.713
0.997
0.647
0.093
0.240
0.117
0.242
0.588
0.729
2.768
0.796
1.036
0.650
0.093
0.240
0.117
0.242
0.160
0.365
0.183
0.346
0.857
0.827
2.427
0.961
1.561
1.051
0.160
0.365
0.183
0.346
0.857
0.827
2.427
0.961
1.561
1.051
0.160
0.365
0.183
0.346
0.952
0.988
3.165
1.069
1.655
1.048
0.160
0.365
0.183
0.346
0.952
0.988
3.165
1.069
1.655
1.048
0.160
0.365
0.183
0.346
1.038
1.148
3.922
1.176
1.734
1.054
0.160
0.365
0.183
0.346
0.270
0.675
0.298
0.553
2.145
1.674
4.634
1.612
3.392
1.954
0.270
0.675
0.298
0.553
2.145
1.674
4.634
1.612
3.392
1.954
0.270
0.675
0.298
0.553
2.455
1.917
6.099
1.724
3.703
1.880
0.270
0.675
0.298
0.553
2.455
1.917
6.099
1.724
3.703
1.880
0.270
0.675
0.298
0.553
2.740
2.184
7.625
1.839
3.989
1.852
0.270
0.675
0.298
0.553
0.007
0.010
0.007
0.010
0.010
0.013
0.010
0.013
0.014
0.018
0.014
0.018
Block Library
Block type
T
MIN.
TYP.
IN
MAX.
BN5F
A → Y0
EN → Y0
0.015
0.019
0.021
0.025
0.033
0.036
ENI → Y1
0.007
0.010
0.007
0.010
0.007
0.010
0.007
0.010
0.007
0.010
0.007
0.010
0.007
0.010
0.007
0.010
0.007
0.010
0.007
0.010
A13872EJ5V0BL
0.010
0.013
0.010
0.013
0.010
0.013
0.010
0.013
0.010
0.013
0.010
0.013
0.010
0.013
0.010
0.013
0.010
0.013
0.010
0.013
0.015
0.020
0.021
0.027
0.032
0.038
0.015
0.019
0.021
0.025
0.033
0.036
0.015
0.020
0.021
0.027
0.032
0.038
0.012
0.013
0.017
0.017
0.029
0.026
0.012
0.014
0.017
0.019
0.028
0.027
0.012
0.013
0.017
0.017
0.029
0.026
0.012
0.014
0.017
0.019
0.028
0.027
0.011
0.010
0.015
0.014
0.028
0.021
0.011
0.011
0.015
0.016
0.027
0.022
Switching speed
t LD0 (ns)
Path
→ OUT
Y0 → Y1
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
MIN.
TYP.
MAX.
0.588
0.729
2.768
0.796
1.036
0.650
0.093
0.240
0.117
0.242
1.038
1.148
3.922
1.176
1.734
1.054
0.160
0.365
0.183
0.346
2.740
2.184
7.625
1.839
3.989
1.852
0.270
0.675
0.298
0.553
MIN.
0.007
0.010
0.007
0.010
t1
TYP.
0.010
0.013
0.010
0.013
T
MAX.
MIN.
TYP.
MAX.
0.011
0.010
0.015
0.014
0.028
0.021
0.011
0.011
0.015
0.016
0.027
0.022
0.014
0.018
0.014
0.018
0.014
0.018
0.014
0.018
0.014
0.018
0.014
0.018
0.014
0.018
0.014
0.018
0.014
0.018
0.014
0.018
0.014
0.018
0.014
0.018
1 - 58
Block Library
A13872EJ5V0BL
1 - 59
Chapter 1 Interface Block
Chapter 1 Interface Block
[MEMO]
[MEMO]
Block Library
A13872EJ5V0BL
1 - 60
Block Library
A13872EJ5V0BL
1 - 61
Chapter 1 Interface Block
Chapter 1 Interface Block
[MEMO]
1.2
TTL Level
Block Library
A13872EJ5V0BL
1 - 62
Block Library
A13872EJ5V0BL
1 - 63
Chapter 1 Interface Block
Function
Chapter 1 Interface Block
Block type
Block type
IN
Function
no resistor
with 50 KΩ P/D
with 50 KΩ P/U
with 5 KΩ P/U
Normal
FI02
FID2
FIU2
FIW2
1
3
Schmitt
FIS2W
FDS2W
FUS2W
FWS2W
1
6
I/O cells int. Cells
Truth Table
Logic Diagram for "Normal"
H01
N01
Y
A
Y
1
1
0
0
Logic Diagram for "Schmitt"
Block type
A
H01
N01
Y
Input
Path
→ OUT
FI02
A → Y
FID2
A → Y
FIU2
A → Y
FIW2
A → Y
FIS2W
A → Y
FDS2W
A → Y
FUS2W
A → Y
FWS2W
A → Y
Clock
A
Switching speed
t LD0 (ns)
5.0 V
Input Buffer
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
t1
T
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.176
0.138
0.176
0.138
0.176
0.138
0.176
0.138
1.184
2.208
1.184
2.208
1.184
2.208
1.184
2.208
0.266
0.197
0.266
0.197
0.266
0.197
0.266
0.197
1.976
3.267
1.976
3.267
1.976
3.267
1.976
3.267
0.417
0.328
0.417
0.328
0.417
0.328
0.417
0.328
4.048
5.483
4.048
5.483
4.048
5.483
4.048
5.483
0.011
0.007
0.011
0.007
0.011
0.007
0.011
0.007
0.008
0.012
0.008
0.012
0.008
0.012
0.008
0.012
0.016
0.009
0.016
0.009
0.016
0.009
0.016
0.009
0.011
0.015
0.011
0.015
0.011
0.015
0.011
0.015
0.022
0.012
0.022
0.012
0.022
0.012
0.022
0.012
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
MIN.
TYP.
MAX.
Output
Symbol Fan-In Symbol Fan-Out
FI02 to FIW2
A
-
Y
34
FIS2W to FWS2W
A
-
Y
37
Logic Diagram for "Clock"
Block Library
A13872EJ5V0BL
1 - 64
Block Library
A13872EJ5V0BL
1 - 65
Chapter 1 Interface Block
Function
Chapter 1 Interface Block
Block type
Block type
IN
Function
no resistor
with 50 KΩ P/D
Normal
FIA2
FDA2
1
3
Schmitt
FIE2W
FDE2W
1
6
with 50 KΩ P/U
with 5 KΩ P/U
I/O cells int. Cells
Truth Table
Logic Diagram for "Normal"
H01
N01
Y
A
Y
1
1
0
0
Logic Diagram for "Schmitt"
Block type
A
H01
N01
Y
Input
Path
→ OUT
FIA2
A → Y
FDA2
A → Y
FIE2W
A → Y
FDE2W
A → Y
Clock
A
Switching speed
t LD0 (ns)
5.0 V
Input Buffer with failsafe
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
t1
T
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.176
0.138
0.176
0.138
1.184
2.208
1.184
2.208
0.266
0.198
0.266
0.198
1.976
3.267
1.976
3.267
0.417
0.328
0.417
0.328
4.048
5.483
4.048
5.483
0.011
0.007
0.011
0.007
0.008
0.012
0.008
0.012
0.016
0.009
0.016
0.009
0.011
0.015
0.011
0.015
0.022
0.012
0.022
0.012
0.017
0.022
0.017
0.022
MIN.
TYP.
MAX.
Output
Symbol Fan-In Symbol Fan-Out
FIA2 to FDA2
A
-
Y
34
FIE2W to FDE2W
A
-
Y
37
Logic Diagram for "Clock"
Block Library
A13872EJ5V0BL
1 - 66
Block Library
A13872EJ5V0BL
1 - 67
Chapter 1 Interface Block
Function
Chapter 1 Interface Block
Switching speed
t LD0 (ns)
5.0 V
Input Buffer with EN(AND)
Block type
Block type
Function
no resistor
with 50 KΩ P/D
Normal
FN12
FN22
IN
with 50 KΩ P/U
with 5 KΩ P/U
I/O cells int. Cells
1
FN12
7
Path
→ OUT
A → Y
EN → Y
Schmitt
FN22
Clock
EN → Y
Truth Table
Logic Diagram for "Normal"
A H01
A → Y
A
EN
Y
0
0
0
0
1
0
1
0
0
1
1
1
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
t1
T
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.112
0.160
0.122
0.173
0.112
0.160
0.122
0.173
0.187
0.234
0.185
0.245
0.187
0.234
0.185
0.245
0.315
0.371
0.297
0.345
0.315
0.371
0.297
0.345
0.011
0.007
0.011
0.007
0.011
0.007
0.011
0.007
0.015
0.008
0.015
0.008
0.015
0.008
0.015
0.008
0.021
0.012
0.021
0.011
0.021
0.012
0.021
0.011
MIN.
TYP.
MAX.
N01 Y
H02 EN
Logic Diagram for "Schmitt"
Block type
FN12 to FN22
Input
Output
Symbol Fan-In Symbol Fan-Out
A
-
EN
4.1
Y
35
Logic Diagram for "Clock"
Block Library
A13872EJ5V0BL
1 - 68
Block Library
A13872EJ5V0BL
1 - 69
Chapter 1 Interface Block
Function
Chapter 1 Interface Block
Switching speed
t LD0 (ns)
5.0 V
Input Buffer with EN(OR)
Block type
Block type
Function
no resistor
with 50 KΩ P/D
Normal
FN14
FN24
IN
with 50 KΩ P/U
with 5 KΩ P/U
I/O cells int. Cells
1
FN14
4
Path
→ OUT
A → Y
EN → Y
Schmitt
FN24
Clock
EN → Y
Truth Table
Logic Diagram for "Normal"
A H01
N01 Y
H02 EN
A
EN
Y
0
0
0
0
1
1
1
0
1
1
1
1
Logic Diagram for "Schmitt"
Block type
FN14 to FN24
A → Y
Input
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
t1
T
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.103
0.223
0.164
0.203
0.103
0.223
0.164
0.203
0.166
0.311
0.241
0.331
0.166
0.311
0.241
0.331
0.247
0.432
0.365
0.596
0.247
0.432
0.365
0.596
0.011
0.007
0.011
0.007
0.011
0.007
0.011
0.007
0.015
0.009
0.015
0.009
0.015
0.009
0.015
0.009
0.021
0.013
0.022
0.013
0.021
0.013
0.022
0.013
MIN.
TYP.
MAX.
Output
Symbol Fan-In Symbol Fan-Out
A
-
EN
2.0
Y
34
Logic Diagram for "Clock"
Block Library
A13872EJ5V0BL
1 - 70
Block Library
A13872EJ5V0BL
1 - 71
Chapter 1 Interface Block
Chapter 1 Interface Block
Block type
Block type
Drivability
no resistor
with 50 KΩ P/D
IN
with 50 KΩ P/U
with 5 KΩ P/U
I/O cells int. Cells
B00V
1mA
Path
→ OUT
A → Y0
EN → Y0
2mA
3mA
B00V
B0DV
B0UV
B0WV
1
10
6mA
B00D
B0DD
B0UD
B0WD
1
10
9mA
B004
B0D4
B0U4
B0W4
1
10
12mA
B002
B0D2
B0U2
B0W2
1
20
18mA
B006
B0D6
B0U6
B0W6
1
20
24mA
B00G
B0DG
B0UG
B0WG
1
20
Logic Diagram
Block type
B00V to B0WV
Input
Y0 → Y1
B0DV
EN → Y0
Y0 → Y1
Output
Symbol Fan-in Symbol Fan-out
A
6.3
EN
1.0
A
6.3
EN
1.0
A
6.3
EN
1.0
Y1
A → Y0
B0UV
A → Y0
34
EN → Y0
Y1 N02
B00D to B0WD
A H01
N01 Y0
EN H03
B004 to B0W4
B002 to B0W2
B006 to B0W6
Truth Table
A
EN
Y0
0
1
0
1
1
1
X
0
Z
B00G to B0WG
A
16.9
EN
1.0
A
16.9
EN
1.0
A
16.9
EN
1.0
Y1
34
Y0 → Y1
Y1
34
B0WV
Y1
34
Y0 → Y1
Y1
34
B00D
0
0
1
1
A → Y0
EN → Y0
Y1
34
Y0 → Y1
B0DD
A → Y0
EN → Y0
Z:High Impedance
Y1
A → Y0
EN → Y0
X:Irrelevant
Y0
Switching speed
t LD0 (ns)
TTL 5.0 V
I/O Buffer
Function
Y0 → Y1
B0UD
A → Y0
EN → Y0
Y0 → Y1
Block Library
A13872EJ5V0BL
1 - 72
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
MIN.
TYP.
MAX.
0.591
0.710
1.088
0.380
0.832
0.771
0.176
0.138
0.591
0.710
1.088
0.380
0.832
0.771
0.176
0.138
0.591
0.710
1.088
0.380
0.832
0.771
0.176
0.138
0.591
0.710
1.088
0.380
0.832
0.771
0.176
0.138
0.613
0.650
1.413
0.451
0.851
0.667
0.176
0.138
0.613
0.650
1.413
0.451
0.851
0.667
0.176
0.138
0.613
0.650
1.413
0.451
0.851
0.667
0.176
0.138
1.045
1.257
1.523
0.577
1.425
1.385
0.266
0.197
1.045
1.257
1.523
0.577
1.425
1.385
0.266
0.197
1.045
1.257
1.523
0.577
1.425
1.385
0.266
0.197
1.045
1.257
1.523
0.577
1.425
1.385
0.266
0.197
1.080
1.081
1.971
0.675
1.454
1.152
0.266
0.197
1.080
1.081
1.971
0.675
1.454
1.152
0.266
0.197
1.080
1.081
1.971
0.675
1.454
1.152
0.266
0.197
2.529
2.776
2.712
0.996
3.216
2.985
0.417
0.328
2.529
2.776
2.712
0.996
3.216
2.985
0.417
0.328
2.529
2.776
2.712
0.996
3.216
2.985
0.417
0.328
2.529
2.776
2.712
0.996
3.216
2.985
0.417
0.328
2.673
2.183
3.618
1.128
3.330
2.242
0.417
0.328
2.673
2.183
3.618
1.128
3.330
2.242
0.417
0.328
2.673
2.183
3.618
1.128
3.330
2.242
0.417
0.328
Block Library
MIN.
0.011
0.007
0.011
0.007
0.011
0.007
0.011
0.007
0.011
0.007
0.011
0.007
0.011
0.007
A13872EJ5V0BL
t1
TYP.
0.016
0.009
0.016
0.009
0.016
0.009
0.016
0.009
0.016
0.009
0.016
0.009
0.016
0.009
T
MAX.
MIN.
TYP.
MAX.
0.042
0.076
0.056
0.103
0.080
0.149
0.042
0.077
0.056
0.103
0.077
0.150
0.042
0.076
0.056
0.103
0.080
0.149
0.042
0.077
0.056
0.103
0.077
0.150
0.042
0.076
0.056
0.103
0.080
0.149
0.042
0.077
0.056
0.103
0.077
0.150
0.042
0.076
0.056
0.103
0.080
0.149
0.042
0.077
0.056
0.103
0.077
0.150
0.029
0.038
0.039
0.051
0.057
0.073
0.029
0.039
0.039
0.052
0.056
0.076
0.029
0.038
0.039
0.051
0.057
0.073
0.029
0.039
0.039
0.052
0.056
0.076
0.029
0.038
0.039
0.051
0.057
0.073
0.029
0.039
0.039
0.052
0.056
0.076
0.022
0.012
0.022
0.012
0.022
0.012
0.022
0.012
0.022
0.012
0.022
0.012
0.022
0.012
1 - 73
Chapter 1 Interface Block
Block type
IN
B0WD
EN → Y0
Y0 → Y1
B004
A → Y0
EN → Y0
Y0 → Y1
B0D4
A → Y0
EN → Y0
Y0 → Y1
B0U4
A → Y0
EN → Y0
Y0 → Y1
B0W4
A → Y0
EN → Y0
Y0 → Y1
B002
A → Y0
EN → Y0
Y0 → Y1
B0D2
Switching speed
t LD0 (ns)
Path
→ OUT
A → Y0
A → Y0
EN → Y0
Y0 → Y1
Chapter 1 Interface Block
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
MIN.
TYP.
MAX.
0.613
0.650
1.413
0.451
0.851
0.667
0.176
0.138
0.663
0.787
1.970
0.510
0.902
0.653
0.176
0.138
0.663
0.787
1.970
0.510
0.902
0.653
0.176
0.138
0.663
0.787
1.970
0.510
0.902
0.653
0.176
0.138
0.663
0.787
1.970
0.510
0.902
0.653
0.176
0.138
0.491
0.508
1.692
0.628
0.952
0.646
0.176
0.138
0.491
0.508
1.692
0.628
0.952
0.646
0.176
0.138
1.080
1.081
1.971
0.675
1.454
1.152
0.266
0.197
1.177
1.252
2.727
0.752
1.553
1.109
0.266
0.197
1.177
1.252
2.727
0.752
1.553
1.109
0.266
0.197
1.177
1.252
2.727
0.752
1.553
1.109
0.266
0.197
1.177
1.252
2.727
0.752
1.553
1.109
0.266
0.197
0.857
0.827
2.427
0.961
1.561
1.051
0.266
0.197
0.857
0.827
2.427
0.961
1.561
1.051
0.266
0.197
2.673
2.183
3.618
1.128
3.330
2.242
0.417
0.328
3.036
2.495
5.121
1.213
3.690
2.032
0.417
0.328
3.036
2.495
5.121
1.213
3.690
2.032
0.417
0.328
3.036
2.495
5.121
1.213
3.690
2.032
0.417
0.328
3.036
2.495
5.121
1.213
3.690
2.032
0.417
0.328
2.145
1.674
4.634
1.612
3.392
1.954
0.417
0.328
2.145
1.674
4.634
1.612
3.392
1.954
0.417
0.328
Block Library
MIN.
t1
TYP.
Block type
T
MAX.
MIN.
TYP.
MAX.
0.029
0.038
0.039
0.051
0.057
0.073
IN
B0U2
A → Y0
EN → Y0
0.029
0.039
0.011
0.007
0.016
0.009
0.039
0.052
0.056
0.076
Y0 → Y1
0.022
0.012
0.019
0.025
0.026
0.033
0.041
0.047
B0W2
A → Y0
EN → Y0
0.011
0.007
0.016
0.009
0.019
0.027
0.026
0.036
0.041
0.051
0.019
0.025
0.026
0.033
0.041
0.047
Y0 → Y1
0.022
0.012
B006
A → Y0
EN → Y0
0.019
0.027
0.011
0.007
0.016
0.009
0.026
0.036
0.041
0.051
Y0 → Y1
0.022
0.012
0.019
0.025
0.026
0.033
0.041
0.047
B0D6
A → Y0
EN → Y0
0.019
0.027
0.011
0.007
0.016
0.009
0.026
0.036
0.041
0.051
Y0 → Y1
0.022
0.012
0.019
0.025
0.026
0.033
0.041
0.047
0.019
0.027
0.026
0.036
0.041
0.051
B0U6
A → Y0
EN → Y0
0.011
0.007
0.016
0.009
Y0 → Y1
0.022
0.012
0.015
0.019
0.021
0.025
0.033
0.036
B0W6
A → Y0
EN → Y0
0.015
0.020
0.011
0.007
0.016
0.009
0.021
0.027
0.032
0.038
Y0 → Y1
0.022
0.012
0.015
0.019
0.021
0.025
0.033
0.036
B00G
A → Y0
EN → Y0
0.015
0.020
0.011
0.007
A13872EJ5V0BL
0.016
0.009
0.021
0.027
0.032
0.038
Y0 → Y1
0.022
0.012
1 - 74
Switching speed
t LD0 (ns)
Path
→ OUT
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
MIN.
TYP.
MAX.
0.491
0.508
1.692
0.628
0.952
0.646
0.176
0.138
0.491
0.508
1.692
0.628
0.952
0.646
0.176
0.138
0.540
0.619
2.230
0.713
0.997
0.647
0.176
0.138
0.540
0.619
2.230
0.713
0.997
0.647
0.176
0.138
0.540
0.619
2.230
0.713
0.997
0.647
0.176
0.138
0.540
0.619
2.230
0.713
0.997
0.647
0.176
0.138
0.588
0.729
2.768
0.796
1.036
0.650
0.176
0.138
0.857
0.827
2.427
0.961
1.561
1.051
0.266
0.197
0.857
0.827
2.427
0.961
1.561
1.051
0.266
0.197
0.952
0.988
3.165
1.069
1.655
1.048
0.266
0.197
0.952
0.988
3.165
1.069
1.655
1.048
0.266
0.197
0.952
0.988
3.165
1.069
1.655
1.048
0.266
0.197
0.952
0.988
3.165
1.069
1.655
1.048
0.266
0.197
1.038
1.148
3.922
1.176
1.734
1.054
0.266
0.197
2.145
1.674
4.634
1.612
3.392
1.954
0.417
0.328
2.145
1.674
4.634
1.612
3.392
1.954
0.417
0.328
2.455
1.917
6.099
1.724
3.703
1.880
0.417
0.328
2.455
1.917
6.099
1.724
3.703
1.880
0.417
0.328
2.455
1.917
6.099
1.724
3.703
1.880
0.417
0.328
2.455
1.917
6.099
1.724
3.703
1.880
0.417
0.328
2.740
2.184
7.625
1.839
3.989
1.852
0.417
0.328
Block Library
MIN.
0.011
0.007
0.011
0.007
0.011
0.007
0.011
0.007
0.011
0.007
0.011
0.007
0.011
0.007
t1
TYP.
0.016
0.009
0.016
0.009
0.016
0.009
0.016
0.009
0.016
0.009
0.016
0.009
0.016
0.009
A13872EJ5V0BL
T
MAX.
MIN.
TYP.
MAX.
0.015
0.019
0.021
0.025
0.033
0.036
0.015
0.020
0.021
0.027
0.032
0.038
0.015
0.019
0.021
0.025
0.033
0.036
0.015
0.020
0.021
0.027
0.032
0.038
0.012
0.013
0.017
0.017
0.029
0.026
0.012
0.014
0.017
0.019
0.028
0.027
0.012
0.013
0.017
0.017
0.029
0.026
0.012
0.014
0.017
0.019
0.028
0.027
0.012
0.013
0.017
0.017
0.029
0.026
0.012
0.014
0.017
0.019
0.028
0.027
0.012
0.013
0.017
0.017
0.029
0.026
0.012
0.014
0.017
0.019
0.028
0.027
0.011
0.010
0.015
0.014
0.028
0.021
0.011
0.011
0.015
0.016
0.027
0.022
0.022
0.012
0.022
0.012
0.022
0.012
0.022
0.012
0.022
0.012
0.022
0.012
0.022
0.012
1 - 75
Chapter 1 Interface Block
Block type
IN
B0DG
EN → Y0
Y0 → Y1
B0UG
A → Y0
EN → Y0
Y0 → Y1
B0WG
Switching speed
t LD0 (ns)
Path
→ OUT
A → Y0
A → Y0
EN → Y0
Y0 → Y1
Chapter 1 Interface Block
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
MIN.
TYP.
MAX.
0.588
0.729
2.768
0.796
1.036
0.650
0.176
0.138
0.588
0.729
2.768
0.796
1.036
0.650
0.176
0.138
0.588
0.729
2.768
0.796
1.036
0.650
0.176
0.138
1.038
1.148
3.922
1.176
1.734
1.054
0.266
0.197
1.038
1.148
3.922
1.176
1.734
1.054
0.266
0.197
1.038
1.148
3.922
1.176
1.734
1.054
0.266
0.197
2.740
2.184
7.625
1.839
3.989
1.852
0.417
0.328
2.740
2.184
7.625
1.839
3.989
1.852
0.417
0.328
2.740
2.184
7.625
1.839
3.989
1.852
0.417
0.328
Block Library
MIN.
0.011
0.007
0.011
0.007
0.011
0.007
A13872EJ5V0BL
[MEMO]
t1
TYP.
0.016
0.009
0.016
0.009
0.016
0.009
T
MAX.
MIN.
TYP.
MAX.
0.011
0.010
0.015
0.014
0.028
0.021
0.011
0.011
0.015
0.016
0.027
0.022
0.011
0.010
0.015
0.014
0.028
0.021
0.011
0.011
0.015
0.016
0.027
0.022
0.011
0.010
0.015
0.014
0.028
0.021
0.011
0.011
0.015
0.016
0.027
0.022
0.022
0.012
0.022
0.012
0.022
0.012
1 - 76
Block Library
A13872EJ5V0BL
1 - 77
Chapter 1 Interface Block
Chapter 1 Interface Block
Block type
Block type
Drivability
no resistor
with 50 KΩ P/D
IN
with 50 KΩ P/U
with 5 KΩ P/U
I/O cells int. Cells
BE0V
1mA
Path
→ OUT
A → Y0
EN → Y0
2mA
3mA
BE0V
BEDV
BEUV
BEWV
1
10
6mA
BE0D
BEDD
BEUD
BEWD
1
10
9mA
BE04
BED4
BEU4
BEW4
1
10
12mA
BE02
BED2
BEU2
BEW2
1
10
18mA
BE06
BED6
BEU6
BEW6
1
10
24mA
BE0G
BEDG
BEUG
BEWG
1
10
Logic Diagram
Block type
BE0V to BEWV
Input
Y0 → Y1
BEDV
EN → Y0
Y0 → Y1
Output
Symbol Fan-in Symbol Fan-out
A
6.2
EN
4.0
A
6.1
EN
4.0
A
6.2
EN
4.0
Y1
A → Y0
BEUV
A → Y0
34
EN → Y0
Y1 N02
BE0D to BEWD
A H01
N01 Y0
EN H03
BE04 to BEW4
BE02 to BEW2
BE06 to BEW6
Truth Table
A
EN
Y0
0
1
0
1
1
1
X
0
Z
BE0G to BEWG
A
6.2
EN
4.0
A
6.2
EN
4.0
A
6.2
EN
4.0
Y1
34
Y0 → Y1
Y1
34
BEWV
Y1
34
Y0 → Y1
Y1
34
BE0D
0
0
1
1
A → Y0
EN → Y0
Y1
34
Y0 → Y1
BEDD
A → Y0
EN → Y0
Z:High Impedance
Y1
A → Y0
EN → Y0
X:Irrelevant
Y0
Switching speed
t LD0 (ns)
TTL 5.0 V
Low-noise I/O Buffer
Function
Y0 → Y1
BEUD
A → Y0
EN → Y0
Y0 → Y1
Block Library
A13872EJ5V0BL
1 - 78
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
MIN.
TYP.
MAX.
0.906
0.903
0.697
0.638
0.907
0.940
0.176
0.138
0.906
0.903
0.697
0.638
0.907
0.940
0.176
0.138
0.906
0.903
0.697
0.638
0.907
0.940
0.176
0.138
0.906
0.903
0.697
0.638
0.907
0.940
0.176
0.138
0.951
0.874
0.948
0.817
0.943
0.868
0.176
0.138
0.951
0.874
0.948
0.817
0.943
0.868
0.176
0.138
0.951
0.874
0.948
0.817
0.943
0.868
0.176
0.138
1.649
1.561
0.916
0.928
1.682
1.673
0.266
0.197
1.649
1.561
0.916
0.928
1.682
1.673
0.266
0.197
1.649
1.561
0.916
0.928
1.682
1.673
0.266
0.197
1.649
1.561
0.916
0.928
1.682
1.673
0.266
0.197
1.724
1.428
1.269
1.158
1.755
1.494
0.266
0.197
1.724
1.428
1.269
1.158
1.755
1.494
0.266
0.197
1.724
1.428
1.269
1.158
1.755
1.494
0.266
0.197
4.217
3.193
1.493
1.536
4.261
3.375
0.417
0.328
4.217
3.193
1.493
1.536
4.261
3.375
0.417
0.328
4.217
3.193
1.493
1.536
4.261
3.375
0.417
0.328
4.217
3.193
1.493
1.536
4.261
3.375
0.417
0.328
4.530
2.630
2.217
1.799
4.570
2.680
0.417
0.328
4.530
2.630
2.217
1.799
4.570
2.680
0.417
0.328
4.530
2.630
2.217
1.799
4.570
2.680
0.417
0.328
Block Library
MIN.
0.011
0.007
0.011
0.007
0.011
0.007
0.011
0.007
0.011
0.007
0.011
0.007
0.011
0.007
A13872EJ5V0BL
t1
TYP.
0.016
0.009
0.016
0.009
0.016
0.009
0.016
0.009
0.016
0.009
0.016
0.009
0.016
0.009
T
MAX.
MIN.
TYP.
MAX.
0.044
0.077
0.059
0.103
0.086
0.150
0.044
0.077
0.059
0.104
0.086
0.151
0.044
0.077
0.059
0.103
0.086
0.150
0.044
0.077
0.059
0.104
0.086
0.151
0.044
0.077
0.059
0.103
0.086
0.150
0.044
0.077
0.059
0.104
0.086
0.151
0.044
0.077
0.059
0.103
0.086
0.150
0.044
0.077
0.059
0.104
0.086
0.151
0.031
0.039
0.042
0.053
0.066
0.075
0.031
0.040
0.042
0.054
0.066
0.077
0.031
0.039
0.042
0.053
0.066
0.075
0.031
0.040
0.042
0.054
0.066
0.077
0.031
0.039
0.042
0.053
0.066
0.075
0.031
0.040
0.042
0.054
0.066
0.077
0.022
0.012
0.022
0.012
0.022
0.012
0.022
0.012
0.022
0.012
0.022
0.012
0.022
0.012
1 - 79
Chapter 1 Interface Block
Block type
IN
BEWD
EN → Y0
Y0 → Y1
BE04
A → Y0
EN → Y0
Y0 → Y1
BED4
A → Y0
EN → Y0
Y0 → Y1
BEU4
A → Y0
EN → Y0
Y0 → Y1
BEW4
A → Y0
EN → Y0
Y0 → Y1
BE02
A → Y0
EN → Y0
Y0 → Y1
BED2
Switching speed
t LD0 (ns)
Path
→ OUT
A → Y0
A → Y0
EN → Y0
Y0 → Y1
Chapter 1 Interface Block
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
MIN.
TYP.
MAX.
0.951
0.874
0.948
0.817
0.943
0.868
0.176
0.138
1.027
1.034
1.369
0.981
1.005
0.864
0.176
0.138
1.027
1.034
1.369
0.981
1.005
0.864
0.176
0.138
1.027
1.034
1.369
0.981
1.005
0.864
0.176
0.138
1.027
1.034
1.369
0.981
1.005
0.864
0.176
0.138
1.086
1.107
1.585
1.138
1.039
0.873
0.176
0.138
1.086
1.107
1.585
1.138
1.039
0.873
0.176
0.138
1.724
1.428
1.269
1.158
1.755
1.494
0.266
0.197
1.876
1.615
1.836
1.364
1.906
1.475
0.266
0.197
1.876
1.615
1.836
1.364
1.906
1.475
0.266
0.197
1.876
1.615
1.836
1.364
1.906
1.475
0.266
0.197
1.876
1.615
1.836
1.364
1.906
1.475
0.266
0.197
1.963
1.718
2.130
1.564
1.989
1.486
0.266
0.197
1.963
1.718
2.130
1.564
1.989
1.486
0.266
0.197
4.530
2.630
2.217
1.799
4.570
2.680
0.417
0.328
5.188
2.959
3.377
2.013
5.246
2.488
0.417
0.328
5.188
2.959
3.377
2.013
5.246
2.488
0.417
0.328
5.188
2.959
3.377
2.013
5.246
2.488
0.417
0.328
5.188
2.959
3.377
2.013
5.246
2.488
0.417
0.328
5.554
3.065
3.959
2.214
5.597
2.412
0.417
0.328
5.554
3.065
3.959
2.214
5.597
2.412
0.417
0.328
Block Library
MIN.
t1
TYP.
Block type
T
MAX.
MIN.
TYP.
MAX.
0.031
0.039
0.042
0.053
0.066
0.075
IN
BEU2
A → Y0
EN → Y0
0.031
0.040
0.011
0.007
0.016
0.009
0.042
0.054
0.066
0.077
Y0 → Y1
0.022
0.012
0.022
0.026
0.031
0.035
0.053
0.049
BEW2
A → Y0
EN → Y0
0.011
0.007
0.016
0.009
0.022
0.029
0.031
0.038
0.053
0.054
0.022
0.026
0.031
0.035
0.053
0.049
Y0 → Y1
0.022
0.012
BE06
A → Y0
EN → Y0
0.022
0.029
0.011
0.007
0.016
0.009
0.031
0.038
0.053
0.054
Y0 → Y1
0.022
0.012
0.022
0.026
0.031
0.035
0.053
0.049
BED6
A → Y0
EN → Y0
0.022
0.029
0.011
0.007
0.016
0.009
0.031
0.038
0.053
0.054
Y0 → Y1
0.022
0.012
0.022
0.026
0.031
0.035
0.053
0.049
0.022
0.029
0.031
0.038
0.053
0.054
BEU6
A → Y0
EN → Y0
0.011
0.007
0.016
0.009
Y0 → Y1
0.022
0.012
0.020
0.021
0.029
0.028
0.051
0.037
BEW6
A → Y0
EN → Y0
0.021
0.023
0.011
0.007
0.016
0.009
0.029
0.031
0.051
0.043
Y0 → Y1
0.022
0.012
0.020
0.021
0.029
0.028
0.051
0.037
BE0G
A → Y0
EN → Y0
0.021
0.023
0.011
0.007
A13872EJ5V0BL
0.016
0.009
0.029
0.031
0.051
0.043
Y0 → Y1
0.022
0.012
1 - 80
Switching speed
t LD0 (ns)
Path
→ OUT
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
MIN.
TYP.
MAX.
1.086
1.107
1.585
1.138
1.039
0.873
0.176
0.138
1.086
1.107
1.585
1.138
1.039
0.873
0.176
0.138
1.249
1.391
2.247
1.467
1.139
0.902
0.176
0.138
1.249
1.391
2.247
1.467
1.139
0.902
0.176
0.138
1.249
1.391
2.247
1.467
1.139
0.902
0.176
0.138
1.249
1.391
2.247
1.467
1.139
0.902
0.176
0.138
1.429
1.676
2.920
1.791
1.236
0.934
0.176
0.138
1.963
1.718
2.130
1.564
1.989
1.486
0.266
0.197
1.963
1.718
2.130
1.564
1.989
1.486
0.266
0.197
2.239
2.128
3.020
1.974
2.241
1.547
0.266
0.197
2.239
2.128
3.020
1.974
2.241
1.547
0.266
0.197
2.239
2.128
3.020
1.974
2.241
1.547
0.266
0.197
2.239
2.128
3.020
1.974
2.241
1.547
0.266
0.197
2.521
2.541
3.913
2.376
2.487
1.621
0.266
0.197
5.554
3.065
3.959
2.214
5.597
2.412
0.417
0.328
5.554
3.065
3.959
2.214
5.597
2.412
0.417
0.328
6.618
3.712
5.777
2.649
6.670
2.379
0.417
0.328
6.618
3.712
5.777
2.649
6.670
2.379
0.417
0.328
6.618
3.712
5.777
2.649
6.670
2.379
0.417
0.328
6.618
3.712
5.777
2.649
6.670
2.379
0.417
0.328
7.676
4.411
7.573
3.054
7.732
2.393
0.417
0.328
Block Library
MIN.
0.011
0.007
0.011
0.007
0.011
0.007
0.011
0.007
0.011
0.007
0.011
0.007
0.011
0.007
t1
TYP.
0.016
0.009
0.016
0.009
0.016
0.009
0.016
0.009
0.016
0.009
0.016
0.009
0.016
0.009
A13872EJ5V0BL
T
MAX.
MIN.
TYP.
MAX.
0.020
0.021
0.029
0.028
0.051
0.037
0.021
0.023
0.029
0.031
0.051
0.043
0.020
0.021
0.029
0.028
0.051
0.037
0.021
0.023
0.029
0.031
0.051
0.043
0.017
0.015
0.026
0.020
0.049
0.028
0.018
0.019
0.026
0.025
0.049
0.033
0.017
0.015
0.026
0.020
0.049
0.028
0.018
0.019
0.026
0.025
0.049
0.033
0.017
0.015
0.026
0.020
0.049
0.028
0.018
0.019
0.026
0.025
0.049
0.033
0.017
0.015
0.026
0.020
0.049
0.028
0.018
0.019
0.026
0.025
0.049
0.033
0.015
0.012
0.025
0.017
0.049
0.023
0.017
0.017
0.026
0.023
0.049
0.029
0.022
0.012
0.022
0.012
0.022
0.012
0.022
0.012
0.022
0.012
0.022
0.012
0.022
0.012
1 - 81
Chapter 1 Interface Block
Block type
IN
BEDG
EN → Y0
Y0 → Y1
BEUG
A → Y0
EN → Y0
Y0 → Y1
BEWG
Switching speed
t LD0 (ns)
Path
→ OUT
A → Y0
A → Y0
EN → Y0
Y0 → Y1
Chapter 1 Interface Block
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
MIN.
TYP.
MAX.
1.429
1.676
2.920
1.791
1.236
0.934
0.176
0.138
1.429
1.676
2.920
1.791
1.236
0.934
0.176
0.138
1.429
1.676
2.920
1.791
1.236
0.934
0.176
0.138
2.521
2.541
3.913
2.376
2.487
1.621
0.266
0.197
2.521
2.541
3.913
2.376
2.487
1.621
0.266
0.197
2.521
2.541
3.913
2.376
2.487
1.621
0.266
0.197
7.676
4.411
7.573
3.054
7.732
2.393
0.417
0.328
7.676
4.411
7.573
3.054
7.732
2.393
0.417
0.328
7.676
4.411
7.573
3.054
7.732
2.393
0.417
0.328
Block Library
MIN.
0.011
0.007
0.011
0.007
0.011
0.007
A13872EJ5V0BL
[MEMO]
t1
TYP.
0.016
0.009
0.016
0.009
0.016
0.009
T
MAX.
MIN.
TYP.
MAX.
0.015
0.012
0.025
0.017
0.049
0.023
0.017
0.017
0.026
0.023
0.049
0.029
0.015
0.012
0.025
0.017
0.049
0.023
0.017
0.017
0.026
0.023
0.049
0.029
0.015
0.012
0.025
0.017
0.049
0.023
0.017
0.017
0.026
0.023
0.049
0.029
0.022
0.012
0.022
0.012
0.022
0.012
1 - 82
Block Library
A13872EJ5V0BL
1 - 83
Chapter 1 Interface Block
Chapter 1 Interface Block
Block type
Block type
Drivability
no resistor
with 50 KΩ P/D
IN
with 50 KΩ P/U
with 5 KΩ P/U
I/O cells int. Cells
BSIVW
1mA
Path
→ OUT
A → Y0
EN → Y0
2mA
3mA
BSIVW
BSDVW
BSUVW
BSWVW
1
13
6mA
BSIDW
BSDDW
BSUDW
BSWDW
1
13
9mA
BSI4W
BSD4W
BSU4W
BSW4W
1
13
12mA
BSI2W
BSD2W
BSU2W
BSW2W
1
23
18mA
BSI6W
BSD6W
BSU6W
BSW6W
1
23
24mA
BSIGW
BSDGW
BSUGW
BSWGW
1
23
Logic Diagram
Block type
BSIVW to BSWVW
Input
Y0 → Y1
BSDVW
EN → Y0
Y0 → Y1
Output
Symbol Fan-in Symbol Fan-out
A
6.3
EN
1.0
A
6.3
EN
1.0
A
6.3
EN
1.0
Y1
A → Y0
BSUVW
A → Y0
37
EN → Y0
Y1 N02
BSIDW to BSWDW
A H02
N01 Y0
EN H03
BSI4W to BSW4W
BSI2W to BSW2W
BSI6W to BSW6W
Truth Table
A
EN
Y0
0
1
0
1
1
1
X
0
Z
BSIGW to BSWGW
A
16.9
EN
1.0
A
16.9
EN
1.0
A
16.9
EN
1.0
Y1
37
Y0 → Y1
Y1
37
BSWVW
Y1
37
Y0 → Y1
Y1
37
BSIDW
0
0
1
1
A → Y0
EN → Y0
Y1
37
Y0 → Y1
BSDDW
A → Y0
EN → Y0
Z:High Impedance
Y1
A → Y0
EN → Y0
X:Irrelevant
Y0
Switching speed
t LD0 (ns)
TTL 5.0 V
Schmitt I/O Buffer
Function
Y0 → Y1
BSUDW
A → Y0
EN → Y0
Y0 → Y1
Block Library
A13872EJ5V0BL
1 - 84
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
MIN.
TYP.
MAX.
0.591
0.710
1.088
0.380
0.832
0.771
1.184
2.208
0.591
0.710
1.088
0.380
0.832
0.771
1.184
2.208
0.591
0.710
1.088
0.380
0.832
0.771
1.184
2.208
0.591
0.710
1.088
0.380
0.832
0.771
1.184
2.208
0.613
0.650
1.413
0.451
0.851
0.667
1.184
2.208
0.613
0.650
1.413
0.451
0.851
0.667
1.184
2.208
0.613
0.650
1.413
0.451
0.851
0.667
1.184
2.208
1.045
1.257
1.523
0.577
1.425
1.385
1.976
3.267
1.045
1.257
1.523
0.577
1.425
1.385
1.976
3.267
1.045
1.257
1.523
0.577
1.425
1.385
1.976
3.267
1.045
1.257
1.523
0.577
1.425
1.385
1.976
3.267
1.080
1.081
1.971
0.675
1.454
1.152
1.976
3.267
1.080
1.081
1.971
0.675
1.454
1.152
1.976
3.267
1.080
1.081
1.971
0.675
1.454
1.152
1.976
3.267
2.529
2.776
2.712
0.996
3.216
2.985
4.048
5.483
2.529
2.776
2.712
0.996
3.216
2.985
4.048
5.483
2.529
2.776
2.712
0.996
3.216
2.985
4.048
5.483
2.529
2.776
2.712
0.996
3.216
2.985
4.048
5.483
2.673
2.183
3.618
1.128
3.330
2.242
4.048
5.483
2.673
2.183
3.618
1.128
3.330
2.242
4.048
5.483
2.673
2.183
3.618
1.128
3.330
2.242
4.048
5.483
Block Library
MIN.
0.008
0.012
0.008
0.012
0.008
0.012
0.008
0.012
0.008
0.012
0.008
0.012
0.008
0.012
A13872EJ5V0BL
t1
TYP.
0.011
0.015
0.011
0.015
0.011
0.015
0.011
0.015
0.011
0.015
0.011
0.015
0.011
0.015
T
MAX.
MIN.
TYP.
MAX.
0.042
0.076
0.056
0.103
0.080
0.149
0.042
0.077
0.056
0.103
0.077
0.150
0.042
0.076
0.056
0.103
0.080
0.149
0.042
0.077
0.056
0.103
0.077
0.150
0.042
0.076
0.056
0.103
0.080
0.149
0.042
0.077
0.056
0.103
0.077
0.150
0.042
0.076
0.056
0.103
0.080
0.149
0.042
0.077
0.056
0.103
0.077
0.150
0.029
0.038
0.039
0.051
0.057
0.073
0.029
0.039
0.039
0.052
0.056
0.076
0.029
0.038
0.039
0.051
0.057
0.073
0.029
0.039
0.039
0.052
0.056
0.076
0.029
0.038
0.039
0.051
0.057
0.073
0.029
0.039
0.039
0.052
0.056
0.076
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
1 - 85
Chapter 1 Interface Block
Block type
IN
BSWDW
EN → Y0
Y0 → Y1
BSI4W
A → Y0
EN → Y0
Y0 → Y1
BSD4W
A → Y0
EN → Y0
Y0 → Y1
BSU4W
A → Y0
EN → Y0
Y0 → Y1
BSW4W
A → Y0
EN → Y0
Y0 → Y1
BSI2W
A → Y0
EN → Y0
Y0 → Y1
BSD2W
Switching speed
t LD0 (ns)
Path
→ OUT
A → Y0
A → Y0
EN → Y0
Y0 → Y1
Chapter 1 Interface Block
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
MIN.
TYP.
MAX.
0.613
0.650
1.413
0.451
0.851
0.667
1.184
2.208
0.663
0.787
1.970
0.510
0.902
0.653
1.184
2.208
0.663
0.787
1.970
0.510
0.902
0.653
1.184
2.208
0.663
0.787
1.970
0.510
0.902
0.653
1.184
2.208
0.663
0.787
1.970
0.510
0.902
0.653
1.184
2.208
0.491
0.508
1.692
0.628
0.952
0.646
1.184
2.208
0.491
0.508
1.692
0.628
0.952
0.646
1.184
2.208
1.080
1.081
1.971
0.675
1.454
1.152
1.976
3.267
1.177
1.252
2.727
0.752
1.553
1.109
1.976
3.267
1.177
1.252
2.727
0.752
1.553
1.109
1.976
3.267
1.177
1.252
2.727
0.752
1.553
1.109
1.976
3.267
1.177
1.252
2.727
0.752
1.553
1.109
1.976
3.267
0.857
0.827
2.427
0.961
1.561
1.051
1.976
3.267
0.857
0.827
2.427
0.961
1.561
1.051
1.976
3.267
2.673
2.183
3.618
1.128
3.330
2.242
4.048
5.483
3.036
2.495
5.121
1.213
3.690
2.032
4.048
5.483
3.036
2.495
5.121
1.213
3.690
2.032
4.048
5.483
3.036
2.495
5.121
1.213
3.690
2.032
4.048
5.483
3.036
2.495
5.121
1.213
3.690
2.032
4.048
5.483
2.145
1.674
4.634
1.612
3.392
1.954
4.048
5.483
2.145
1.674
4.634
1.612
3.392
1.954
4.048
5.483
Block Library
MIN.
t1
TYP.
Block type
T
MAX.
MIN.
TYP.
MAX.
0.029
0.038
0.039
0.051
0.057
0.073
IN
BSU2W
A → Y0
EN → Y0
0.029
0.039
0.008
0.012
0.011
0.015
0.039
0.052
0.056
0.076
Y0 → Y1
0.017
0.022
0.019
0.025
0.026
0.033
0.041
0.047
BSW2W
A → Y0
EN → Y0
0.008
0.012
0.011
0.015
0.019
0.027
0.026
0.036
0.041
0.051
0.019
0.025
0.026
0.033
0.041
0.047
Y0 → Y1
0.017
0.022
BSI6W
A → Y0
EN → Y0
0.019
0.027
0.008
0.012
0.011
0.015
0.026
0.036
0.041
0.051
Y0 → Y1
0.017
0.022
0.019
0.025
0.026
0.033
0.041
0.047
BSD6W
A → Y0
EN → Y0
0.019
0.027
0.008
0.012
0.011
0.015
0.026
0.036
0.041
0.051
Y0 → Y1
0.017
0.022
0.019
0.025
0.026
0.033
0.041
0.047
0.019
0.027
0.026
0.036
0.041
0.051
BSU6W
A → Y0
EN → Y0
0.008
0.012
0.011
0.015
Y0 → Y1
0.017
0.022
0.015
0.019
0.021
0.025
0.033
0.036
BSW6W
A → Y0
EN → Y0
0.015
0.020
0.008
0.012
0.011
0.015
0.021
0.027
0.032
0.038
Y0 → Y1
0.017
0.022
0.015
0.019
0.021
0.025
0.033
0.036
BSIGW
A → Y0
EN → Y0
0.015
0.020
0.008
0.012
A13872EJ5V0BL
0.011
0.015
0.021
0.027
0.032
0.038
Y0 → Y1
0.017
0.022
1 - 86
Switching speed
t LD0 (ns)
Path
→ OUT
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
MIN.
TYP.
MAX.
0.491
0.508
1.692
0.628
0.952
0.646
1.184
2.208
0.491
0.508
1.692
0.628
0.952
0.646
1.184
2.208
0.540
0.619
2.230
0.713
0.997
0.647
1.184
2.208
0.540
0.619
2.230
0.713
0.997
0.647
1.184
2.208
0.540
0.619
2.230
0.713
0.997
0.647
1.184
2.208
0.540
0.619
2.230
0.713
0.997
0.647
1.184
2.208
0.588
0.729
2.768
0.796
1.036
0.650
1.184
2.208
0.857
0.827
2.427
0.961
1.561
1.051
1.976
3.267
0.857
0.827
2.427
0.961
1.561
1.051
1.976
3.267
0.952
0.988
3.165
1.069
1.655
1.048
1.976
3.267
0.952
0.988
3.165
1.069
1.655
1.048
1.976
3.267
0.952
0.988
3.165
1.069
1.655
1.048
1.976
3.267
0.952
0.988
3.165
1.069
1.655
1.048
1.976
3.267
1.038
1.148
3.922
1.176
1.734
1.054
1.976
3.267
2.145
1.674
4.634
1.612
3.392
1.954
4.048
5.483
2.145
1.674
4.634
1.612
3.392
1.954
4.048
5.483
2.455
1.917
6.099
1.724
3.703
1.880
4.048
5.483
2.455
1.917
6.099
1.724
3.703
1.880
4.048
5.483
2.455
1.917
6.099
1.724
3.703
1.880
4.048
5.483
2.455
1.917
6.099
1.724
3.703
1.880
4.048
5.483
2.740
2.184
7.625
1.839
3.989
1.852
4.048
5.483
Block Library
MIN.
0.008
0.012
0.008
0.012
0.008
0.012
0.008
0.012
0.008
0.012
0.008
0.012
0.008
0.012
t1
TYP.
0.011
0.015
0.011
0.015
0.011
0.015
0.011
0.015
0.011
0.015
0.011
0.015
0.011
0.015
A13872EJ5V0BL
T
MAX.
MIN.
TYP.
MAX.
0.015
0.019
0.021
0.025
0.033
0.036
0.015
0.020
0.021
0.027
0.032
0.038
0.015
0.019
0.021
0.025
0.033
0.036
0.015
0.020
0.021
0.027
0.032
0.038
0.012
0.013
0.017
0.017
0.029
0.026
0.012
0.014
0.017
0.019
0.028
0.027
0.012
0.013
0.017
0.017
0.029
0.026
0.012
0.014
0.017
0.019
0.028
0.027
0.012
0.013
0.017
0.017
0.029
0.026
0.012
0.014
0.017
0.019
0.028
0.027
0.012
0.013
0.017
0.017
0.029
0.026
0.012
0.014
0.017
0.019
0.028
0.027
0.011
0.010
0.015
0.014
0.028
0.021
0.011
0.011
0.015
0.016
0.027
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
1 - 87
Chapter 1 Interface Block
Block type
IN
BSDGW
EN → Y0
Y0 → Y1
BSUGW
A → Y0
EN → Y0
Y0 → Y1
BSWGW
Switching speed
t LD0 (ns)
Path
→ OUT
A → Y0
A → Y0
EN → Y0
Y0 → Y1
Chapter 1 Interface Block
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
MIN.
TYP.
MAX.
0.588
0.729
2.768
0.796
1.036
0.650
1.184
2.208
0.588
0.729
2.768
0.796
1.036
0.650
1.184
2.208
0.588
0.729
2.768
0.796
1.036
0.650
1.184
2.208
1.038
1.148
3.922
1.176
1.734
1.054
1.976
3.267
1.038
1.148
3.922
1.176
1.734
1.054
1.976
3.267
1.038
1.148
3.922
1.176
1.734
1.054
1.976
3.267
2.740
2.184
7.625
1.839
3.989
1.852
4.048
5.483
2.740
2.184
7.625
1.839
3.989
1.852
4.048
5.483
2.740
2.184
7.625
1.839
3.989
1.852
4.048
5.483
Block Library
MIN.
0.008
0.012
0.008
0.012
0.008
0.012
A13872EJ5V0BL
[MEMO]
t1
TYP.
0.011
0.015
0.011
0.015
0.011
0.015
T
MAX.
MIN.
TYP.
MAX.
0.011
0.010
0.015
0.014
0.028
0.021
0.011
0.011
0.015
0.016
0.027
0.022
0.011
0.010
0.015
0.014
0.028
0.021
0.011
0.011
0.015
0.016
0.027
0.022
0.011
0.010
0.015
0.014
0.028
0.021
0.011
0.011
0.015
0.016
0.027
0.022
0.017
0.022
0.017
0.022
0.017
0.022
1 - 88
Block Library
A13872EJ5V0BL
1 - 89
Chapter 1 Interface Block
Chapter 1 Interface Block
Block type
Block type
Drivability
no resistor
with 50 KΩ P/D
IN
with 50 KΩ P/U
with 5 KΩ P/U
I/O cells int. Cells
BFIVW
1mA
Path
→ OUT
A → Y0
EN → Y0
2mA
3mA
BFIVW
BFDVW
BFUVW
BFWVW
1
13
6mA
BFIDW
BFDDW
BFUDW
BFWDW
1
13
9mA
BFI4W
BFD4W
BFU4W
BFW4W
1
13
12mA
BFI2W
BFD2W
BFU2W
BFW2W
1
13
18mA
BFI6W
BFD6W
BFU6W
BFW6W
1
13
24mA
BFIGW
BFDGW
BFUGW
BFWGW
1
13
Logic Diagram
Block type
BFIVW to BFWVW
Input
Y0 → Y1
BFDVW
EN → Y0
Y0 → Y1
Output
Symbol Fan-in Symbol Fan-out
A
6.2
EN
4.0
A
6.1
EN
4.0
A
6.2
EN
4.0
Y1
A → Y0
BFUVW
A → Y0
37
EN → Y0
Y1 N02
BFIDW to BFWDW
A H02
N01 Y0
EN H03
BFI4W to BFW4W
BFI2W to BFW2W
BFI6W to BFW6W
Truth Table
A
EN
Y0
0
1
0
1
1
1
X
0
Z
BFIGW to BFWGW
A
6.2
EN
4.0
A
6.2
EN
4.0
A
6.2
EN
4.0
Y1
37
Y0 → Y1
Y1
37
BFWVW
Y1
37
Y0 → Y1
Y1
37
BFIDW
0
0
1
1
A → Y0
EN → Y0
Y1
37
Y0 → Y1
BFDDW
A → Y0
EN → Y0
Z:High Impedance
Y1
A → Y0
EN → Y0
X:Irrelevant
Y0
Switching speed
t LD0 (ns)
TTL 5.0 V
Low-noise Schmitt I/O Buffer
Function
Y0 → Y1
BFUDW
A → Y0
EN → Y0
Y0 → Y1
Block Library
A13872EJ5V0BL
1 - 90
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
MIN.
TYP.
MAX.
0.906
0.903
0.697
0.638
0.907
0.940
1.184
2.208
0.906
0.903
0.697
0.638
0.907
0.940
1.184
2.208
0.906
0.903
0.697
0.638
0.907
0.940
1.184
2.208
0.906
0.903
0.697
0.638
0.907
0.940
1.184
2.208
0.951
0.874
0.948
0.817
0.943
0.868
1.184
2.208
0.951
0.874
0.948
0.817
0.943
0.868
1.184
2.208
0.951
0.874
0.948
0.817
0.943
0.868
1.184
2.208
1.649
1.561
0.916
0.928
1.682
1.673
1.976
3.267
1.649
1.561
0.916
0.928
1.682
1.673
1.976
3.267
1.649
1.561
0.916
0.928
1.682
1.673
1.976
3.267
1.649
1.561
0.916
0.928
1.682
1.673
1.976
3.267
1.724
1.428
1.269
1.158
1.755
1.494
1.976
3.267
1.724
1.428
1.269
1.158
1.755
1.494
1.976
3.267
1.724
1.428
1.269
1.158
1.755
1.494
1.976
3.267
4.217
3.193
1.493
1.536
4.261
3.375
4.048
5.483
4.217
3.193
1.493
1.536
4.261
3.375
4.048
5.483
4.217
3.193
1.493
1.536
4.261
3.375
4.048
5.483
4.217
3.193
1.493
1.536
4.261
3.375
4.048
5.483
4.530
2.630
2.217
1.799
4.570
2.680
4.048
5.483
4.530
2.630
2.217
1.799
4.570
2.680
4.048
5.483
4.530
2.630
2.217
1.799
4.570
2.680
4.048
5.483
Block Library
MIN.
0.008
0.012
0.008
0.012
0.008
0.012
0.008
0.012
0.008
0.012
0.008
0.012
0.008
0.012
A13872EJ5V0BL
t1
TYP.
0.011
0.015
0.011
0.015
0.011
0.015
0.011
0.015
0.011
0.015
0.011
0.015
0.011
0.015
T
MAX.
MIN.
TYP.
MAX.
0.044
0.077
0.059
0.103
0.086
0.150
0.044
0.077
0.059
0.104
0.086
0.151
0.044
0.077
0.059
0.103
0.086
0.150
0.044
0.077
0.059
0.104
0.086
0.151
0.044
0.077
0.059
0.103
0.086
0.150
0.044
0.077
0.059
0.104
0.086
0.151
0.044
0.077
0.059
0.103
0.086
0.150
0.044
0.077
0.059
0.104
0.086
0.151
0.031
0.039
0.042
0.053
0.066
0.075
0.031
0.040
0.042
0.054
0.066
0.077
0.031
0.039
0.042
0.053
0.066
0.075
0.031
0.040
0.042
0.054
0.066
0.077
0.031
0.039
0.042
0.053
0.066
0.075
0.031
0.040
0.042
0.054
0.066
0.077
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
1 - 91
Chapter 1 Interface Block
Block type
IN
BFWDW
EN → Y0
Y0 → Y1
BFI4W
A → Y0
EN → Y0
Y0 → Y1
BFD4W
A → Y0
EN → Y0
Y0 → Y1
BFU4W
A → Y0
EN → Y0
Y0 → Y1
BFW4W
A → Y0
EN → Y0
Y0 → Y1
BFI2W
A → Y0
EN → Y0
Y0 → Y1
BFD2W
Switching speed
t LD0 (ns)
Path
→ OUT
A → Y0
A → Y0
EN → Y0
Y0 → Y1
Chapter 1 Interface Block
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
MIN.
TYP.
MAX.
0.951
0.874
0.948
0.817
0.943
0.868
1.184
2.208
1.027
1.034
1.369
0.981
1.005
0.864
1.184
2.208
1.027
1.034
1.369
0.981
1.005
0.864
1.184
2.208
1.027
1.034
1.369
0.981
1.005
0.864
1.184
2.208
1.027
1.034
1.369
0.981
1.005
0.864
1.184
2.208
1.086
1.107
1.585
1.138
1.039
0.873
1.184
2.208
1.086
1.107
1.585
1.138
1.039
0.873
1.184
2.208
1.724
1.428
1.269
1.158
1.755
1.494
1.976
3.267
1.876
1.615
1.836
1.364
1.906
1.475
1.976
3.267
1.876
1.615
1.836
1.364
1.906
1.475
1.976
3.267
1.876
1.615
1.836
1.364
1.906
1.475
1.976
3.267
1.876
1.615
1.836
1.364
1.906
1.475
1.976
3.267
1.963
1.718
2.130
1.564
1.989
1.486
1.976
3.267
1.963
1.718
2.130
1.564
1.989
1.486
1.976
3.267
4.530
2.630
2.217
1.799
4.570
2.680
4.048
5.483
5.188
2.959
3.377
2.013
5.246
2.488
4.048
5.483
5.188
2.959
3.377
2.013
5.246
2.488
4.048
5.483
5.188
2.959
3.377
2.013
5.246
2.488
4.048
5.483
5.188
2.959
3.377
2.013
5.246
2.488
4.048
5.483
5.554
3.065
3.959
2.214
5.597
2.412
4.048
5.483
5.554
3.065
3.959
2.214
5.597
2.412
4.048
5.483
Block Library
MIN.
t1
TYP.
Block type
T
MAX.
MIN.
TYP.
MAX.
0.031
0.039
0.042
0.053
0.066
0.075
IN
BFU2W
A → Y0
EN → Y0
0.031
0.040
0.008
0.012
0.011
0.015
0.042
0.054
0.066
0.077
Y0 → Y1
0.017
0.022
0.022
0.026
0.031
0.035
0.053
0.049
BFW2W
A → Y0
EN → Y0
0.008
0.012
0.011
0.015
0.022
0.029
0.031
0.038
0.053
0.054
0.022
0.026
0.031
0.035
0.053
0.049
Y0 → Y1
0.017
0.022
BFI6W
A → Y0
EN → Y0
0.022
0.029
0.008
0.012
0.011
0.015
0.031
0.038
0.053
0.054
Y0 → Y1
0.017
0.022
0.022
0.026
0.031
0.035
0.053
0.049
BFD6W
A → Y0
EN → Y0
0.022
0.029
0.008
0.012
0.011
0.015
0.031
0.038
0.053
0.054
Y0 → Y1
0.017
0.022
0.022
0.026
0.031
0.035
0.053
0.049
0.022
0.029
0.031
0.038
0.053
0.054
BFU6W
A → Y0
EN → Y0
0.008
0.012
0.011
0.015
Y0 → Y1
0.017
0.022
0.020
0.021
0.029
0.028
0.051
0.037
BFW6W
A → Y0
EN → Y0
0.021
0.023
0.008
0.012
0.011
0.015
0.029
0.031
0.051
0.043
Y0 → Y1
0.017
0.022
0.020
0.021
0.029
0.028
0.051
0.037
BFIGW
A → Y0
EN → Y0
0.021
0.023
0.008
0.012
A13872EJ5V0BL
0.011
0.015
0.029
0.031
0.051
0.043
Y0 → Y1
0.017
0.022
1 - 92
Switching speed
t LD0 (ns)
Path
→ OUT
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
MIN.
TYP.
MAX.
1.086
1.107
1.585
1.138
1.039
0.873
1.184
2.208
1.086
1.107
1.585
1.138
1.039
0.873
1.184
2.208
1.249
1.391
2.247
1.467
1.139
0.902
1.184
2.208
1.249
1.391
2.247
1.467
1.139
0.902
1.184
2.208
1.249
1.391
2.247
1.467
1.139
0.902
1.184
2.208
1.249
1.391
2.247
1.467
1.139
0.902
1.184
2.208
1.429
1.676
2.920
1.791
1.236
0.934
1.184
2.208
1.963
1.718
2.130
1.564
1.989
1.486
1.976
3.267
1.963
1.718
2.130
1.564
1.989
1.486
1.976
3.267
2.239
2.128
3.020
1.974
2.241
1.547
1.976
3.267
2.239
2.128
3.020
1.974
2.241
1.547
1.976
3.267
2.239
2.128
3.020
1.974
2.241
1.547
1.976
3.267
2.239
2.128
3.020
1.974
2.241
1.547
1.976
3.267
2.521
2.541
3.913
2.376
2.487
1.621
1.976
3.267
5.554
3.065
3.959
2.214
5.597
2.412
4.048
5.483
5.554
3.065
3.959
2.214
5.597
2.412
4.048
5.483
6.618
3.712
5.777
2.649
6.670
2.379
4.048
5.483
6.618
3.712
5.777
2.649
6.670
2.379
4.048
5.483
6.618
3.712
5.777
2.649
6.670
2.379
4.048
5.483
6.618
3.712
5.777
2.649
6.670
2.379
4.048
5.483
7.676
4.411
7.573
3.054
7.732
2.393
4.048
5.483
Block Library
MIN.
0.008
0.012
0.008
0.012
0.008
0.012
0.008
0.012
0.008
0.012
0.008
0.012
0.008
0.012
t1
TYP.
0.011
0.015
0.011
0.015
0.011
0.015
0.011
0.015
0.011
0.015
0.011
0.015
0.011
0.015
A13872EJ5V0BL
T
MAX.
MIN.
TYP.
MAX.
0.020
0.021
0.029
0.028
0.051
0.037
0.021
0.023
0.029
0.031
0.051
0.043
0.020
0.021
0.029
0.028
0.051
0.037
0.021
0.023
0.029
0.031
0.051
0.043
0.017
0.015
0.026
0.020
0.049
0.028
0.018
0.019
0.026
0.025
0.049
0.033
0.017
0.015
0.026
0.020
0.049
0.028
0.018
0.019
0.026
0.025
0.049
0.033
0.017
0.015
0.026
0.020
0.049
0.028
0.018
0.019
0.026
0.025
0.049
0.033
0.017
0.015
0.026
0.020
0.049
0.028
0.018
0.019
0.026
0.025
0.049
0.033
0.015
0.012
0.025
0.017
0.049
0.023
0.017
0.017
0.026
0.023
0.049
0.029
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
1 - 93
Chapter 1 Interface Block
Block type
IN
BFDGW
EN → Y0
Y0 → Y1
BFUGW
A → Y0
EN → Y0
Y0 → Y1
BFWGW
Switching speed
t LD0 (ns)
Path
→ OUT
A → Y0
A → Y0
EN → Y0
Y0 → Y1
Chapter 1 Interface Block
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
MIN.
TYP.
MAX.
1.429
1.676
2.920
1.791
1.236
0.934
1.184
2.208
1.429
1.676
2.920
1.791
1.236
0.934
1.184
2.208
1.429
1.676
2.920
1.791
1.236
0.934
1.184
2.208
2.521
2.541
3.913
2.376
2.487
1.621
1.976
3.267
2.521
2.541
3.913
2.376
2.487
1.621
1.976
3.267
2.521
2.541
3.913
2.376
2.487
1.621
1.976
3.267
7.676
4.411
7.573
3.054
7.732
2.393
4.048
5.483
7.676
4.411
7.573
3.054
7.732
2.393
4.048
5.483
7.676
4.411
7.573
3.054
7.732
2.393
4.048
5.483
Block Library
MIN.
0.008
0.012
0.008
0.012
0.008
0.012
A13872EJ5V0BL
[MEMO]
t1
TYP.
0.011
0.015
0.011
0.015
0.011
0.015
T
MAX.
MIN.
TYP.
MAX.
0.015
0.012
0.025
0.017
0.049
0.023
0.017
0.017
0.026
0.023
0.049
0.029
0.015
0.012
0.025
0.017
0.049
0.023
0.017
0.017
0.026
0.023
0.049
0.029
0.015
0.012
0.025
0.017
0.049
0.023
0.017
0.017
0.026
0.023
0.049
0.029
0.017
0.022
0.017
0.022
0.017
0.022
1 - 94
Block Library
A13872EJ5V0BL
1 - 95
Chapter 1 Interface Block
Chapter 1 Interface Block
Block type
Block type
Drivability
no resistor
with 50 KΩ P/D
IN
with 50 KΩ P/U
with 5 KΩ P/U
I/O cells int. Cells
BN2V
1mA
Path
→ OUT
A → Y0
EN → Y0
2mA
3mA
BN2V
BN4V
1
14
6mA
BN2D
BN4D
1
14
9mA
BN24
BN44
1
14
12mA
BN22
BN42
1
24
18mA
BN26
BN46
1
24
24mA
BN2G
BN4G
1
24
Logic Diagram
Block type
BN2V to BN4V
ENI H04
Input
ENI → Y1
Y0 → Y1
BN4V
BN2D to BN4D
Output
Symbol Fan-in Symbol Fan-out
A
6.3
EN
1.0
ENI
4.1
Y1
ENI → Y1
35
Y0 → Y1
BN2D
A
6.3
EN
1.0
ENI
4.1
A
6.3
Y1
ENI → Y1
BN24 to BN44
EN H03
BN22 to BN42
Truth Table
EN
Y0
0
1
0
1
1
1
X
0
Z
A → Y0
EN → Y0
35
N01 Y0
A
A → Y0
EN → Y0
Y1 N02
A H01
EN
1.0
ENI
4.1
A
16.9
EN
1.0
ENI
4.1
Y1
35
Y0 → Y1
BN4D
Y1
A → Y0
EN → Y0
35
ENI → Y1
BN26 to BN46
A
16.9
EN
1.0
ENI
4.1
A
16.9
EN
1.0
ENI
4.1
Y1
35
Y0 → Y1
BN24
X:Irrelevant
BN2G to BN4G
Z:High Impedance
Y0
ENI
Y1
0
0
0
0
1
0
1
0
0
1
1
1
Switching speed
t LD0 (ns)
TTL 5.0 V
I/O Buffer with EN(AND)
Function
Y1
A → Y0
EN → Y0
35
ENI → Y1
Y0 → Y1
BN44
A → Y0
EN → Y0
Block Library
A13872EJ5V0BL
1 - 96
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
MIN.
TYP.
MAX.
0.591
0.710
1.088
0.380
0.832
0.771
0.122
0.173
0.112
0.160
0.591
0.710
1.088
0.380
0.832
0.771
0.122
0.173
0.112
0.160
0.613
0.650
1.413
0.451
0.851
0.667
0.122
0.173
0.112
0.160
0.613
0.650
1.413
0.451
0.851
0.667
0.122
0.173
0.112
0.160
0.663
0.787
1.970
0.510
0.902
0.653
0.122
0.173
0.112
0.160
0.663
0.787
1.970
0.510
0.902
0.653
1.045
1.257
1.523
0.577
1.425
1.385
0.185
0.245
0.187
0.234
1.045
1.257
1.523
0.577
1.425
1.385
0.185
0.245
0.187
0.234
1.080
1.081
1.971
0.675
1.454
1.152
0.185
0.245
0.187
0.234
1.080
1.081
1.971
0.675
1.454
1.152
0.185
0.245
0.187
0.234
1.177
1.252
2.727
0.752
1.553
1.109
0.185
0.245
0.187
0.234
1.177
1.252
2.727
0.752
1.553
1.109
2.529
2.776
2.712
0.996
3.216
2.985
0.297
0.345
0.315
0.371
2.529
2.776
2.712
0.996
3.216
2.985
0.297
0.345
0.315
0.371
2.673
2.183
3.618
1.128
3.330
2.242
0.297
0.345
0.315
0.371
2.673
2.183
3.618
1.128
3.330
2.242
0.297
0.345
0.315
0.371
3.036
2.495
5.121
1.213
3.690
2.032
0.297
0.345
0.315
0.371
3.036
2.495
5.121
1.213
3.690
2.032
Block Library
MIN.
0.011
0.007
0.011
0.007
0.011
0.007
0.011
0.007
0.011
0.007
0.011
0.007
0.011
0.007
0.011
0.007
0.011
0.007
0.011
0.007
A13872EJ5V0BL
t1
TYP.
0.015
0.008
0.015
0.008
0.015
0.008
0.015
0.008
0.015
0.008
0.015
0.008
0.015
0.008
0.015
0.008
0.015
0.008
0.015
0.008
T
MAX.
MIN.
TYP.
MAX.
0.042
0.076
0.056
0.103
0.080
0.149
0.042
0.077
0.056
0.103
0.077
0.150
0.042
0.076
0.056
0.103
0.080
0.149
0.042
0.077
0.056
0.103
0.077
0.150
0.029
0.038
0.039
0.051
0.057
0.073
0.029
0.039
0.039
0.052
0.056
0.076
0.029
0.038
0.039
0.051
0.057
0.073
0.029
0.039
0.039
0.052
0.056
0.076
0.019
0.025
0.026
0.033
0.041
0.047
0.019
0.027
0.026
0.036
0.041
0.051
0.019
0.025
0.026
0.033
0.041
0.047
0.019
0.027
0.026
0.036
0.041
0.051
0.021
0.011
0.021
0.012
0.021
0.011
0.021
0.012
0.021
0.011
0.021
0.012
0.021
0.011
0.021
0.012
0.021
0.011
0.021
0.012
1 - 97
Chapter 1 Interface Block
Block type
IN
Y0 → Y1
BN22
A → Y0
EN → Y0
ENI → Y1
Y0 → Y1
BN42
A → Y0
EN → Y0
ENI → Y1
Y0 → Y1
BN26
A → Y0
EN → Y0
ENI → Y1
Y0 → Y1
BN46
A → Y0
EN → Y0
ENI → Y1
Y0 → Y1
BN2G
Switching speed
t LD0 (ns)
Path
→ OUT
ENI → Y1
A → Y0
EN → Y0
ENI → Y1
Y0 → Y1
Chapter 1 Interface Block
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.122
0.173
0.112
0.160
0.491
0.508
1.692
0.628
0.952
0.646
0.122
0.173
0.112
0.160
0.491
0.508
1.692
0.628
0.952
0.646
0.122
0.173
0.112
0.160
0.540
0.619
2.230
0.713
0.997
0.647
0.122
0.173
0.112
0.160
0.540
0.619
2.230
0.713
0.997
0.647
0.122
0.173
0.112
0.160
0.588
0.729
2.768
0.796
1.036
0.650
0.122
0.173
0.112
0.160
0.185
0.245
0.187
0.234
0.857
0.827
2.427
0.961
1.561
1.051
0.185
0.245
0.187
0.234
0.857
0.827
2.427
0.961
1.561
1.051
0.185
0.245
0.187
0.234
0.952
0.988
3.165
1.069
1.655
1.048
0.185
0.245
0.187
0.234
0.952
0.988
3.165
1.069
1.655
1.048
0.185
0.245
0.187
0.234
1.038
1.148
3.922
1.176
1.734
1.054
0.185
0.245
0.187
0.234
0.297
0.345
0.315
0.371
2.145
1.674
4.634
1.612
3.392
1.954
0.297
0.345
0.315
0.371
2.145
1.674
4.634
1.612
3.392
1.954
0.297
0.345
0.315
0.371
2.455
1.917
6.099
1.724
3.703
1.880
0.297
0.345
0.315
0.371
2.455
1.917
6.099
1.724
3.703
1.880
0.297
0.345
0.315
0.371
2.740
2.184
7.625
1.839
3.989
1.852
0.297
0.345
0.315
0.371
0.011
0.007
0.011
0.007
0.015
0.008
0.015
0.008
0.021
0.011
0.021
0.012
Block Library
Block type
T
MIN.
TYP.
IN
MAX.
BN4G
A → Y0
EN → Y0
0.015
0.019
0.021
0.025
0.033
0.036
ENI → Y1
0.011
0.007
0.011
0.007
0.011
0.007
0.011
0.007
0.011
0.007
0.011
0.007
0.011
0.007
0.011
0.007
0.011
0.007
0.011
0.007
A13872EJ5V0BL
0.015
0.008
0.015
0.008
0.015
0.008
0.015
0.008
0.015
0.008
0.015
0.008
0.015
0.008
0.015
0.008
0.015
0.008
0.015
0.008
0.015
0.020
0.021
0.027
0.032
0.038
0.015
0.019
0.021
0.025
0.033
0.036
0.015
0.020
0.021
0.027
0.032
0.038
0.012
0.013
0.017
0.017
0.029
0.026
0.012
0.014
0.017
0.019
0.028
0.027
0.012
0.013
0.017
0.017
0.029
0.026
0.012
0.014
0.017
0.019
0.028
0.027
0.011
0.010
0.015
0.014
0.028
0.021
0.011
0.011
0.015
0.016
0.027
0.022
Switching speed
t LD0 (ns)
Path
→ OUT
Y0 → Y1
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
MIN.
TYP.
MAX.
0.588
0.729
2.768
0.796
1.036
0.650
0.122
0.173
0.112
0.160
1.038
1.148
3.922
1.176
1.734
1.054
0.185
0.245
0.187
0.234
2.740
2.184
7.625
1.839
3.989
1.852
0.297
0.345
0.315
0.371
MIN.
0.011
0.007
0.011
0.007
t1
TYP.
0.015
0.008
0.015
0.008
T
MAX.
MIN.
TYP.
MAX.
0.011
0.010
0.015
0.014
0.028
0.021
0.011
0.011
0.015
0.016
0.027
0.022
0.021
0.011
0.021
0.012
0.021
0.011
0.021
0.012
0.021
0.011
0.021
0.012
0.021
0.011
0.021
0.012
0.021
0.011
0.021
0.012
0.021
0.011
0.021
0.012
1 - 98
Block Library
A13872EJ5V0BL
1 - 99
Chapter 1 Interface Block
Chapter 1 Interface Block
Block type
Block type
Drivability
no resistor
with 50 KΩ P/D
IN
with 50 KΩ P/U
with 5 KΩ P/U
I/O cells int. Cells
BN3V
1mA
Path
→ OUT
A → Y0
EN → Y0
2mA
3mA
BN3V
BN5V
1
11
6mA
BN3D
BN5D
1
11
9mA
BN34
BN54
1
11
12mA
BN32
BN52
1
21
18mA
BN36
BN56
1
21
24mA
BN3G
BN5G
1
21
Logic Diagram
Block type
BN3V to BN5V
ENI H04
Input
ENI → Y1
Y0 → Y1
BN5V
BN3D to BN5D
Output
Symbol Fan-in Symbol Fan-out
A
6.3
EN
1.0
ENI
2.0
Y1
ENI → Y1
34
Y0 → Y1
BN3D
A
6.3
EN
1.0
ENI
2.0
A
6.3
Y1
ENI → Y1
BN34 to BN54
EN H03
BN32 to BN52
Truth Table
EN
Y0
0
1
0
1
1
1
X
0
Z
A → Y0
EN → Y0
34
N01 Y0
A
A → Y0
EN → Y0
Y1 N02
A H01
EN
1.0
ENI
2.0
A
16.9
EN
1.0
ENI
2.0
Y1
34
Y0 → Y1
BN5D
Y1
A → Y0
EN → Y0
34
ENI → Y1
BN36 to BN56
A
16.9
EN
1.0
ENI
2.0
A
16.9
EN
1.0
ENI
2.0
Y1
34
Y0 → Y1
BN34
X:Irrelevant
BN3G to BN5G
Z:High Impedance
Y0
ENI
Y1
0
0
0
0
1
1
1
0
1
1
1
1
Switching speed
t LD0 (ns)
TTL 5.0 V
I/O Buffer with EN(OR)
Function
Y1
A → Y0
EN → Y0
34
ENI → Y1
Y0 → Y1
BN54
A → Y0
EN → Y0
Block Library
A13872EJ5V0BL
1 - 100
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
MIN.
TYP.
MAX.
0.591
0.710
1.088
0.380
0.832
0.771
0.164
0.203
0.103
0.223
0.591
0.710
1.088
0.380
0.832
0.771
0.164
0.203
0.103
0.223
0.613
0.650
1.413
0.451
0.851
0.667
0.164
0.203
0.103
0.223
0.613
0.650
1.413
0.451
0.851
0.667
0.164
0.203
0.103
0.223
0.663
0.787
1.970
0.510
0.902
0.653
0.164
0.203
0.103
0.223
0.663
0.787
1.970
0.510
0.902
0.653
1.045
1.257
1.523
0.577
1.425
1.385
0.241
0.331
0.166
0.311
1.045
1.257
1.523
0.577
1.425
1.385
0.241
0.331
0.166
0.311
1.080
1.081
1.971
0.675
1.454
1.152
0.241
0.331
0.166
0.311
1.080
1.081
1.971
0.675
1.454
1.152
0.241
0.331
0.166
0.311
1.177
1.252
2.727
0.752
1.553
1.109
0.241
0.331
0.166
0.311
1.177
1.252
2.727
0.752
1.553
1.109
2.529
2.776
2.712
0.996
3.216
2.985
0.365
0.596
0.247
0.432
2.529
2.776
2.712
0.996
3.216
2.985
0.365
0.596
0.247
0.432
2.673
2.183
3.618
1.128
3.330
2.242
0.365
0.596
0.247
0.432
2.673
2.183
3.618
1.128
3.330
2.242
0.365
0.596
0.247
0.432
3.036
2.495
5.121
1.213
3.690
2.032
0.365
0.596
0.247
0.432
3.036
2.495
5.121
1.213
3.690
2.032
Block Library
MIN.
0.011
0.007
0.011
0.007
0.011
0.007
0.011
0.007
0.011
0.007
0.011
0.007
0.011
0.007
0.011
0.007
0.011
0.007
0.011
0.007
A13872EJ5V0BL
t1
TYP.
0.015
0.009
0.015
0.009
0.015
0.009
0.015
0.009
0.015
0.009
0.015
0.009
0.015
0.009
0.015
0.009
0.015
0.009
0.015
0.009
T
MAX.
MIN.
TYP.
MAX.
0.042
0.076
0.056
0.103
0.080
0.149
0.042
0.077
0.056
0.103
0.077
0.150
0.042
0.076
0.056
0.103
0.080
0.149
0.042
0.077
0.056
0.103
0.077
0.150
0.029
0.038
0.039
0.051
0.057
0.073
0.029
0.039
0.039
0.052
0.056
0.076
0.029
0.038
0.039
0.051
0.057
0.073
0.029
0.039
0.039
0.052
0.056
0.076
0.019
0.025
0.026
0.033
0.041
0.047
0.019
0.027
0.026
0.036
0.041
0.051
0.019
0.025
0.026
0.033
0.041
0.047
0.019
0.027
0.026
0.036
0.041
0.051
0.022
0.013
0.021
0.013
0.022
0.013
0.021
0.013
0.022
0.013
0.021
0.013
0.022
0.013
0.021
0.013
0.022
0.013
0.021
0.013
1 - 101
Chapter 1 Interface Block
Block type
IN
Y0 → Y1
BN32
A → Y0
EN → Y0
ENI → Y1
Y0 → Y1
BN52
A → Y0
EN → Y0
ENI → Y1
Y0 → Y1
BN36
A → Y0
EN → Y0
ENI → Y1
Y0 → Y1
BN56
A → Y0
EN → Y0
ENI → Y1
Y0 → Y1
BN3G
Switching speed
t LD0 (ns)
Path
→ OUT
ENI → Y1
A → Y0
EN → Y0
ENI → Y1
Y0 → Y1
Chapter 1 Interface Block
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.164
0.203
0.103
0.223
0.491
0.508
1.692
0.628
0.952
0.646
0.164
0.203
0.103
0.223
0.491
0.508
1.692
0.628
0.952
0.646
0.164
0.203
0.103
0.223
0.540
0.619
2.230
0.713
0.997
0.647
0.164
0.203
0.103
0.223
0.540
0.619
2.230
0.713
0.997
0.647
0.164
0.203
0.103
0.223
0.588
0.729
2.768
0.796
1.036
0.650
0.164
0.203
0.103
0.223
0.241
0.331
0.166
0.311
0.857
0.827
2.427
0.961
1.561
1.051
0.241
0.331
0.166
0.311
0.857
0.827
2.427
0.961
1.561
1.051
0.241
0.331
0.166
0.311
0.952
0.988
3.165
1.069
1.655
1.048
0.241
0.331
0.166
0.311
0.952
0.988
3.165
1.069
1.655
1.048
0.241
0.331
0.166
0.311
1.038
1.148
3.922
1.176
1.734
1.054
0.241
0.331
0.166
0.311
0.365
0.596
0.247
0.432
2.145
1.674
4.634
1.612
3.392
1.954
0.365
0.596
0.247
0.432
2.145
1.674
4.634
1.612
3.392
1.954
0.365
0.596
0.247
0.432
2.455
1.917
6.099
1.724
3.703
1.880
0.365
0.596
0.247
0.432
2.455
1.917
6.099
1.724
3.703
1.880
0.365
0.596
0.247
0.432
2.740
2.184
7.625
1.839
3.989
1.852
0.365
0.596
0.247
0.432
0.011
0.007
0.011
0.007
0.015
0.009
0.015
0.009
0.022
0.013
0.021
0.013
Block Library
Block type
T
MIN.
TYP.
IN
MAX.
BN5G
A → Y0
EN → Y0
0.015
0.019
0.021
0.025
0.033
0.036
ENI → Y1
0.011
0.007
0.011
0.007
0.011
0.007
0.011
0.007
0.011
0.007
0.011
0.007
0.011
0.007
0.011
0.007
0.011
0.007
0.011
0.007
A13872EJ5V0BL
0.015
0.009
0.015
0.009
0.015
0.009
0.015
0.009
0.015
0.009
0.015
0.009
0.015
0.009
0.015
0.009
0.015
0.009
0.015
0.009
0.015
0.020
0.021
0.027
0.032
0.038
0.015
0.019
0.021
0.025
0.033
0.036
0.015
0.020
0.021
0.027
0.032
0.038
0.012
0.013
0.017
0.017
0.029
0.026
0.012
0.014
0.017
0.019
0.028
0.027
0.012
0.013
0.017
0.017
0.029
0.026
0.012
0.014
0.017
0.019
0.028
0.027
0.011
0.010
0.015
0.014
0.028
0.021
0.011
0.011
0.015
0.016
0.027
0.022
Switching speed
t LD0 (ns)
Path
→ OUT
Y0 → Y1
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
MIN.
TYP.
MAX.
0.588
0.729
2.768
0.796
1.036
0.650
0.164
0.203
0.103
0.223
1.038
1.148
3.922
1.176
1.734
1.054
0.241
0.331
0.166
0.311
2.740
2.184
7.625
1.839
3.989
1.852
0.365
0.596
0.247
0.432
MIN.
0.011
0.007
0.011
0.007
t1
TYP.
0.015
0.009
0.015
0.009
T
MAX.
MIN.
TYP.
MAX.
0.011
0.010
0.015
0.014
0.028
0.021
0.011
0.011
0.015
0.016
0.027
0.022
0.022
0.013
0.021
0.013
0.022
0.013
0.021
0.013
0.022
0.013
0.021
0.013
0.022
0.013
0.021
0.013
0.022
0.013
0.021
0.013
0.022
0.013
0.021
0.013
1 - 102
Block Library
A13872EJ5V0BL
1 - 103
Chapter 1 Interface Block
Chapter 1 Interface Block
[MEMO]
[MEMO]
Block Library
A13872EJ5V0BL
1 - 104
Block Library
A13872EJ5V0BL
1 - 105
Chapter 1 Interface Block
Chapter 1 Interface Block
[MEMO]
1.3
Oscillator
Block Library
A13872EJ5V0BL
1 - 106
Block Library
A13872EJ5V0BL
1 - 107
Chapter 1 Interface Block
Chapter 1 Interface Block
Switching speed
t LD0 (ns)
Oscillator Input Buffer
Function
Block type
Block type
IN
Function
Normal
I/O cells
OSI1
1
int. cells
OSI1
Path
→ OUT
XT1 → O
(HH)
(LL)
t1
T
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.010
0.010
0.010
0.010
0.010
0.010
0.001
0.001
0.001
0.001
0.001
0.001
MIN.
TYP.
MAX.
0
Oscillation stop function
_
Block type
Logic Diagram
OSI1
XT1 H01
N01
Input
Output
Symbol Fan-in Symbol Fan-out
XT1
-
O
10
O
Truth Table
XT1
O
0
0
1
1
Block Library
A13872EJ5V0BL
1 - 108
Block Library
A13872EJ5V0BL
1 - 109
Chapter 1 Interface Block
Chapter 1 Interface Block
Switching speed
t LD0 (ns)
Oscillator Input Buffer for Enable
Function
Block type
Block type
IN
Function
I/O cells
int. cells
Normal
Oscillation stop function
OSI2
1
OSI2
Path
→ OUT
XT1 → O
(HH)
(LL)
t1
T
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.010
0.010
0.010
0.010
0.010
0.010
0.001
0.001
0.001
0.001
0.001
0.001
MIN.
TYP.
MAX.
0
_
Block type
Logic Diagram
OSI2
XT1 H01
N01
Input
Output
Symbol Fan-in Symbol Fan-out
XT1
-
EN
3.0
O
10
O
EN H02
Truth Table
XT1
EN
O
0
0
0
1
0
1
1
1
1
0
1
X
← Prohibition
X:Irrelevant
Block Library
A13872EJ5V0BL
1 - 110
Block Library
A13872EJ5V0BL
1 - 111
Chapter 1 Interface Block
Chapter 1 Interface Block
Switching speed
t LD0 (ns)
Oscillator Input Buffer for OSO9
Function
Block type
Block type
IN
Function
Normal
I/O cells
OSI4
1
int. cells
OSI4
Path
→ OUT
XT1 → O
(HH)
(LL)
t1
T
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.010
0.010
0.010
0.010
0.010
0.010
0.001
0.001
0.001
0.001
0.001
0.001
MIN.
TYP.
MAX.
0
Oscillation stop function
_
Block type
Logic Diagram
OSI4
XT1 H01
N01
Input
Output
Symbol Fan-in Symbol Fan-out
XT1
-
O
10
O
Truth Table
XT1
O
0
0
1
1
Block Library
A13872EJ5V0BL
1 - 112
Block Library
A13872EJ5V0BL
1 - 113
Chapter 1 Interface Block
Chapter 1 Interface Block
Switching speed
t LD0 (ns)
Oscillator Output Buffer (Internal Feedback Resistor)
Function
Block type
Block type
Function
MHz range
IN
kHz range
I/O cells
int. cells
External feedback Resistor
Internal feedback Resistor
OSO1
Path
→ OUT
I1 → XT2
I1 → O2
OSO1
1
(HL)
(LH)
(HL)
(LH)
MIN.
TYP.
MAX.
0.010
0.010
8.240
4.649
0.010
0.010
17.530
9.408
0.010
0.010
17.530
9.408
MIN.
0.009
0.008
t1
TYP.
0.017
0.014
T
MAX.
MIN.
TYP.
MAX.
0.001
0.001
0.001
0.001
0.001
0.001
0.017
0.014
0
Internal feedback Resistor
Oscillation stop function
Block type
Logic Diagram
OSO1
I1 H01
N01
Input
Output
Symbol Fan-in Symbol Fan-out
I1
1.0
XT2
-
O2
52
XT2
O2 N02
Truth Table
I1
XT2
O2
0
1
1
1
0
0
Block Library
A13872EJ5V0BL
1 - 114
Block Library
A13872EJ5V0BL
1 - 115
Chapter 1 Interface Block
Chapter 1 Interface Block
Switching speed
t LD0 (ns)
Oscillator Output Buffer (for Enable Type)
Function
Block type
Block type
Function
MHz range
IN
kHz range
I/O cells
int. cells
External feedback Resistor
OSO7
1
Block type
Logic Diagram
OSO7
I1 H01
I1 → XT2
I1 → O2
Internal feedback Resistor
Internal feedback Resistor
Oscillation stop function
OSO7
Path
→ OUT
N01
Input
(HL)
(LH)
(HL)
(LH)
MIN.
TYP.
MAX.
0.010
0.010
8.240
4.649
0.010
0.010
17.530
9.408
0.010
0.010
17.530
9.408
MIN.
0.009
0.008
t1
TYP.
0.017
0.014
T
MAX.
MIN.
TYP.
MAX.
0.001
0.001
0.001
0.001
0.001
0.001
0.017
0.014
0
Output
Symbol Fan-in Symbol Fan-out
I1
1.0
XT2
-
EN
3.0
O2
52
XT2
EN H02
O2 N02
Truth Table
I1
EN
XT2
O2
0
0
1
1
1
0
0
0
1
1
0
0
0
1
X
X
← Prohibition
X:Irrelevant
Block Library
A13872EJ5V0BL
1 - 116
Block Library
A13872EJ5V0BL
1 - 117
Chapter 1 Interface Block
Chapter 1 Interface Block
Switching speed
t LD0 (ns)
Oscillator Output Buffer (External Feedback Resistor)
Function
Block type
Block type
Function
MHz range
External feedback Resistor
IN
kHz range
I/O cells
OSO9
int. cells
1
0
OSO9
Path
→ OUT
I1 → XT2
I1 → O2
Internal feedback Resistor
(HL)
(LH)
(HL)
(LH)
MIN.
TYP.
MAX.
0.010
0.010
8.240
4.649
0.010
0.010
17.530
9.408
0.010
0.010
17.530
9.408
MIN.
0.009
0.008
t1
TYP.
0.017
0.014
T
MAX.
MIN.
TYP.
MAX.
0.001
0.001
0.001
0.001
0.001
0.001
0.017
0.014
Internal feedback Resistor
Oscillation stop function
Block type
Logic Diagram
OSO9
I1 H01
N01
Input
Output
Symbol Fan-in Symbol Fan-out
I1
1.0
XT2
-
O2
52
XT2
O2 N02
Truth Table
I1
XT2
O2
0
1
1
1
0
0
Block Library
A13872EJ5V0BL
1 - 118
Block Library
A13872EJ5V0BL
1 - 119
Chapter 2
Function Block
2-1
Block Library
A13872EJ5V0BL
Chapter 2 Function Block
Chapter 2 Function Block
[MEMO]
2.1
Level Generator
Block Library
A13872EJ5V0BL
2-2
Block Library
A13872EJ5V0BL
2-3
Chapter 2 Function Block
Chapter 2 Function Block
H, L Level Generator
Function
Block
type
Standard type
Block type
Normal
High speed
Drivability
Name
cells
-
F091
1
Name
IN
Path
→ OUT
Switching speed
t LD0 (ns)
MIN.
TYP.
MAX.
Input
t1
MIN.
TYP.
MAX.
Symbol
Output
Fanin Symbol Fanout
H
L
F091
cells
152
152
Logic Diagram
N01
H
N02
L
Truth Table
H
L
1
0
Block Library
A13872EJ5V0BL
2-4
Block Library
A13872EJ5V0BL
2-5
Chapter 2 Function Block
Chapter 2 Function Block
[MEMO]
[MEMO]
Block Library
A13872EJ5V0BL
2-6
Block Library
A13872EJ5V0BL
2-7
Chapter 2 Function Block
Chapter 2 Function Block
[MEMO]
2.2
Inverter, Buffer, CTS Driver, Delay Gate
Block Library
A13872EJ5V0BL
2-8
Block Library
A13872EJ5V0BL
2-9
Chapter 2 Function Block
Chapter 2 Function Block
Inverter
Function
Block type
Single output type
Drivability
Name
cells
Low Power
L101
1
x1
F101
1
x2
F102
2
x3
F143
3
x4
F144
4
x5
F145
5
x6
F146
6
x8
F148
12
Block
type
Multi output type
Name
cells
x12
Logic Diagram for "Single output type"
A
H01
N01
IN
Path
→ OUT
L101
A → Y
F101
A → Y
F102
A → Y
F143
A → Y
F144
A → Y
F145
A → Y
F146
A → Y
F148
A → Y
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.089
0.058
0.069
0.044
0.065
0.043
0.070
0.044
0.067
0.044
0.070
0.044
0.069
0.044
0.224
0.191
0.115
0.087
0.088
0.063
0.085
0.062
0.090
0.065
0.088
0.065
0.090
0.066
0.088
0.065
0.351
0.297
0.166
0.143
0.122
0.103
0.119
0.101
0.123
0.105
0.121
0.103
0.123
0.105
0.122
0.104
0.623
0.537
0.020
0.021
0.010
0.011
0.005
0.006
0.003
0.004
0.003
0.003
0.002
0.002
0.002
0.002
0.001
0.001
0.024
0.029
0.012
0.015
0.006
0.008
0.004
0.005
0.003
0.004
0.002
0.003
0.002
0.003
0.002
0.002
0.032
0.042
0.016
0.021
0.008
0.011
0.005
0.007
0.004
0.005
0.003
0.004
0.003
0.004
0.002
0.003
Symbol
A
Output
Fanin Symbol Fanout
1.0
Y
17
A
2.0
Y
34
A
4.1
Y
69
A
6.2
Y
103
A
8.3
Y
139
A
10.4
Y
172
A
12.4
Y
207
A
4.1
Y
280
Y
Logic Diagram for "Multi output type 1"
Logic Diagram for "Multi output type 2"
Block Library
A13872EJ5V0BL
2 - 10
Block Library
A13872EJ5V0BL
2 - 11
Chapter 2 Function Block
Chapter 2 Function Block
Buffer
Function
Block type
Single output type
Drivability
Name
cells
Low Power
L111
1
x1
F111
2
x2
F112
3
x3
F153
4
x4
F154
5
Block
type
Multi output type
Name
cells
x5
IN
Path
→ OUT
L111
A → Y
F111
A → Y
F112
A → Y
F153
A → Y
F154
A → Y
F158
A → Y
x6
x8
F158
11
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.128
0.126
0.095
0.099
0.126
0.129
0.151
0.159
0.175
0.183
0.148
0.151
0.196
0.198
0.144
0.149
0.182
0.194
0.216
0.237
0.245
0.276
0.210
0.226
0.334
0.356
0.243
0.259
0.296
0.333
0.350
0.413
0.396
0.482
0.336
0.389
0.022
0.020
0.011
0.010
0.006
0.005
0.004
0.003
0.003
0.003
0.001
0.001
0.030
0.024
0.015
0.012
0.008
0.006
0.005
0.004
0.004
0.003
0.002
0.002
0.042
0.033
0.021
0.016
0.011
0.008
0.007
0.006
0.005
0.004
0.003
0.002
Symbol
A
Output
Fanin Symbol Fanout
1.0
Y
17
A
2.1
Y
35
A
2.1
Y
70
A
2.1
Y
104
A
2.1
Y
139
A
6.2
Y
278
x12
Logic Diagram for "Single output type"
A
H01
N01
Y
Logic Diagram for "Multi output type 1"
Logic Diagram for "Multi output type 2"
Block Library
A13872EJ5V0BL
2 - 12
Block Library
A13872EJ5V0BL
2 - 13
Chapter 2 Function Block
Chapter 2 Function Block
CTS Driver (Inverter Type)
Function
Single type
Block type
Standard type
(Small scale circuit)
Drivability
Name
cells
x1
FC42
x2
FC82
Double type
(Middle scale circuit)
Name
cells
Block
type
(Large scale circuit)
IN
Path
→ OUT
FC42
A → Y
340
FC82
A → Y
1020
FC44
A → Y
FC84
A → Y
Name
cells
132
FC44
396
FC84
x3
x4
x5
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.628
0.720
0.480
0.480
0.294
0.313
0.702
0.681
1.048
1.370
0.807
0.834
0.507
0.564
1.178
1.124
1.081
1.419
1.285
1.277
0.572
0.663
2.133
2.008
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
Symbol
A
Output
Fanin Symbol Fanout
7.7
Y
4449
A
3.8
Y
8963
A
7.7
Y
8899
A
3.8
Y
17926
Logic Diagram
A
H01
N01
Block Library
Y
A13872EJ5V0BL
2 - 14
Block Library
A13872EJ5V0BL
2 - 15
Chapter 2 Function Block
Chapter 2 Function Block
Delay Gate
Function
Block
type
Standard type
Block type
Normal
High speed
Drivability
Name
cells
-
F131
6
F132
10
Name
IN
Path
→ OUT
F131
A → Y
F132
A → Y
cells
(HH)
(LL)
(HH)
(LL)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.968
0.901
1.899
1.829
1.620
1.492
3.212
3.085
3.278
2.893
6.581
6.198
0.011
0.011
0.011
0.011
0.016
0.015
0.016
0.015
0.022
0.022
0.022
0.022
Symbol
A
A
Output
Fanin Symbol Fanout
1.0
Y
32
1.0
Y
32
Logic Diagram
A
H01
N01
Y
Truth Table
A
Y
0
0
1
1
Block Library
A13872EJ5V0BL
2 - 16
Block Library
A13872EJ5V0BL
2 - 17
Chapter 2 Function Block
Chapter 2 Function Block
[MEMO]
[MEMO]
Block Library
A13872EJ5V0BL
2 - 18
Block Library
A13872EJ5V0BL
2 - 19
Chapter 2 Function Block
Chapter 2 Function Block
[MEMO]
2.3
OR(NOR)
Block Library
A13872EJ5V0BL
2 - 20
Block Library
A13872EJ5V0BL
2 - 21
Chapter 2 Function Block
Function
Block type
Chapter 2 Function Block
2-Input NOR
Normal
with 1 inverter with 2 inverter with 3 inverter with 4 inverter
Drivability
Name
cells
Low Power
L202
1
x1
F202
2
x2
F222
4
x4
F282
6
Name
cells
Name
cells
Name
cells
Name
Block
type
-
cells
L202
Drivability
A → Y
B → Y
F202
A → Y
B → Y
x8
Block type
IN
Path
→ OUT
Normal
Name
with 1 inverter with 2 inverter with 3 inverter with 4 inverter
cells
Name
cells
Name
cells
Name
cells
Name
-
F222
A → Y
cells
B → Y
Low Power
x1
F282
A → Y
x2
B → Y
x4
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.079
0.078
0.093
0.064
0.086
0.074
0.086
0.074
0.084
0.081
0.084
0.081
0.263
0.308
0.278
0.293
0.113
0.115
0.128
0.111
0.121
0.116
0.121
0.116
0.121
0.122
0.121
0.122
0.414
0.484
0.434
0.479
0.167
0.196
0.196
0.253
0.182
0.227
0.182
0.227
0.183
0.235
0.183
0.235
0.734
0.897
0.774
0.956
0.020
0.037
0.020
0.037
0.010
0.019
0.010
0.019
0.005
0.009
0.005
0.009
0.003
0.003
0.003
0.003
0.024
0.053
0.024
0.053
0.012
0.026
0.012
0.026
0.006
0.013
0.006
0.013
0.003
0.004
0.003
0.004
0.033
0.077
0.033
0.077
0.016
0.039
0.016
0.039
0.008
0.019
0.008
0.019
0.004
0.005
0.004
0.005
Symbol
A
B
Output
Fanin Symbol Fanout
1.0
1.0
Y
8
A
B
2.1
2.1
Y
17
A
B
4.1
4.1
Y
34
A
B
1.0
1.0
Y
139
x8
Logic Diagram for "Normal"
A
H01
B
H02
Logic Diagram for "with 1 inverter"
N01
Logic Diagram for "with 3 inverter"
Logic Diagram for "with 2 inverter"
Y
Logic Diagram for "with 4 inverter"
Block Library
A13872EJ5V0BL
2 - 22
Block Library
A13872EJ5V0BL
2 - 23
Chapter 2 Function Block
Function
Block type
Chapter 2 Function Block
3-Input NOR
Normal
with 1 inverter with 2 inverter with 3 inverter with 4 inverter
Drivability
Name
cells
Low Power
L203
2
x1
F203
3
x2
F223
6
Name
cells
Name
cells
Name
cells
Name
Block
type
-
cells
L203
IN
Path
→ OUT
A → Y
B → Y
C → Y
x4
F203
x8
Block type
Drivability
Normal
Name
with 1 inverter with 2 inverter with 3 inverter with 4 inverter
cells
Name
cells
Name
cells
Name
cells
Name
-
A → Y
B → Y
cells
C → Y
Low Power
x1
F223
A → Y
x2
B → Y
x4
x8
C → Y
Logic Diagram for "Normal"
A H01
B H02
C H03
Logic Diagram for "with 1 inverter"
N01
Logic Diagram for "with 3 inverter"
Logic Diagram for "with 2 inverter"
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.089
0.117
0.102
0.121
0.110
0.126
0.083
0.106
0.093
0.116
0.084
0.106
0.096
0.138
0.100
0.137
0.096
0.139
0.126
0.165
0.143
0.199
0.155
0.256
0.118
0.162
0.134
0.199
0.118
0.164
0.139
0.228
0.145
0.215
0.139
0.228
0.175
0.215
0.207
0.374
0.213
0.548
0.151
0.256
0.178
0.406
0.150
0.258
0.189
0.396
0.207
0.391
0.189
0.397
0.020
0.058
0.020
0.058
0.020
0.059
0.011
0.029
0.010
0.029
0.010
0.029
0.005
0.015
0.005
0.015
0.005
0.015
0.024
0.081
0.024
0.082
0.025
0.082
0.013
0.041
0.013
0.041
0.013
0.041
0.006
0.021
0.006
0.021
0.006
0.021
0.032
0.118
0.033
0.118
0.035
0.119
0.017
0.059
0.018
0.060
0.017
0.059
0.009
0.030
0.008
0.030
0.009
0.030
Symbol
A
B
C
Output
Fanin Symbol Fanout
1.0
1.0
1.0
Y
4
A
B
C
2.1
2.1
2.1
Y
10
A
B
C
4.4
4.2
4.3
Y
17
Y
Logic Diagram for "with 4 inverter"
Block Library
A13872EJ5V0BL
2 - 24
Block Library
A13872EJ5V0BL
2 - 25
Chapter 2 Function Block
Function
Block type
Chapter 2 Function Block
4-Input NOR
Normal
with 1 inverter with 2 inverter with 3 inverter with 4 inverter
Drivability
Name
cells
Low Power
L204
2
x1
F204
4
Name
cells
Name
cells
Name
cells
Name
Block
type
-
cells
L204
IN
Path
→ OUT
A → Y
B → Y
x2
C → Y
x4
D → Y
x8
Block type
Drivability
Normal
Name
with 1 inverter with 2 inverter with 3 inverter with 4 inverter
cells
Name
cells
Name
cells
Name
cells
Name
-
F204
A → Y
cells
Low Power
B → Y
x1
C → Y
x2
D → Y
x4
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.087
0.114
0.099
0.132
0.106
0.161
0.108
0.158
0.197
0.272
0.214
0.257
0.215
0.262
0.232
0.248
0.125
0.153
0.142
0.211
0.154
0.333
0.151
0.342
0.325
0.446
0.345
0.440
0.351
0.421
0.372
0.416
0.173
0.157
0.205
0.377
0.213
0.732
0.205
0.797
0.585
0.878
0.622
0.936
0.609
0.798
0.646
0.854
0.020
0.074
0.020
0.074
0.020
0.075
0.020
0.075
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.024
0.104
0.024
0.105
0.025
0.105
0.025
0.105
0.012
0.015
0.012
0.015
0.013
0.015
0.013
0.015
0.032
0.152
0.033
0.153
0.035
0.153
0.035
0.153
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
Symbol
A
B
C
D
A
B
C
D
Output
Fanin Symbol Fanout
1.0
1.0
1.0
1.0
Y
2
1.0
1.0
1.0
1.0
Y
34
x8
Logic Diagram for "Normal"
A
B
C
D
H01
H02
H03
H04
Logic Diagram for "with 1 inverter"
N01
Logic Diagram for "with 3 inverter"
Logic Diagram for "with 2 inverter"
Y
Logic Diagram for "with 4 inverter"
Block Library
A13872EJ5V0BL
2 - 26
Block Library
A13872EJ5V0BL
2 - 27
Chapter 2 Function Block
Function
Block type
Chapter 2 Function Block
5-Input NOR
Normal
with 1 inverter with 2 inverter with 3 inverter with 4 inverter
Drivability
Name
cells
Low Power
L205
4
x1
F205
5
x2
F225
6
Name
cells
Name
cells
Name
cells
Name
Block
type
-
cells
L205
IN
Path
→ OUT
A → Y
B → Y
C → Y
x4
D → Y
x8
Block type
Drivability
Normal
Name
with 1 inverter with 2 inverter with 3 inverter with 4 inverter
cells
Name
cells
Name
cells
Name
cells
Name
-
E → Y
cells
F205
Low Power
x1
A → Y
B → Y
x2
C → Y
x4
x8
D → Y
Logic Diagram for "Normal"
A
B
C
D
E
H01
H02
H03
H04
H05
Logic Diagram for "with 1 inverter"
Logic Diagram for "with 2 inverter"
E → Y
F225
N01
Y
A → Y
B → Y
C → Y
D → Y
E → Y
Logic Diagram for "with 3 inverter"
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.182
0.248
0.199
0.236
0.214
0.337
0.230
0.340
0.241
0.343
0.198
0.270
0.215
0.258
0.228
0.354
0.244
0.357
0.254
0.359
0.243
0.325
0.259
0.311
0.271
0.408
0.286
0.410
0.297
0.413
0.303
0.410
0.324
0.405
0.350
0.521
0.370
0.551
0.386
0.606
0.327
0.445
0.348
0.440
0.371
0.549
0.391
0.578
0.406
0.632
0.399
0.534
0.419
0.531
0.440
0.637
0.461
0.666
0.477
0.720
0.554
0.807
0.589
0.865
0.589
0.883
0.629
1.043
0.651
1.217
0.589
0.878
0.626
0.937
0.622
0.940
0.662
1.101
0.688
1.284
0.719
1.064
0.756
1.123
0.750
1.120
0.792
1.279
0.826
1.462
0.020
0.022
0.020
0.022
0.020
0.022
0.020
0.022
0.020
0.022
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.005
0.006
0.005
0.006
0.005
0.006
0.005
0.006
0.005
0.006
0.024
0.030
0.024
0.030
0.024
0.030
0.024
0.030
0.025
0.030
0.012
0.015
0.012
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.006
0.008
0.006
0.008
0.006
0.008
0.006
0.008
0.006
0.008
0.033
0.042
0.033
0.042
0.033
0.042
0.033
0.042
0.033
0.042
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.009
0.011
0.009
0.011
0.009
0.011
0.009
0.011
0.009
0.011
Symbol
A
B
C
D
E
Output
Fanin Symbol Fanout
1.0
1.0
1.0
1.0
1.0
Y
16
A
B
C
D
E
1.0
1.0
1.0
1.0
1.0
Y
34
A
B
C
D
E
1.0
1.0
1.0
1.0
1.0
Y
66
Logic Diagram for "with 4 inverter"
Block Library
A13872EJ5V0BL
2 - 28
Block Library
A13872EJ5V0BL
2 - 29
Chapter 2 Function Block
Function
Block type
Drivability
Chapter 2 Function Block
6-Input NOR
Normal
with 1 inverter with 2 inverter with 3 inverter with 4 inverter
Name
cells
x1
F206
5
x2
F226
6
Name
cells
Name
cells
Name
cells
Name
Block
type
-
cells
F206
IN
Path
→ OUT
A → Y
Low Power
B → Y
C → Y
x4
D → Y
x8
Block type
Drivability
Normal
Name
with 1 inverter with 2 inverter with 3 inverter with 4 inverter
cells
Name
cells
Name
cells
Name
cells
Name
-
E → Y
cells
F → Y
Low Power
x1
F226
A → Y
x2
B → Y
x4
x8
C → Y
Logic Diagram for "Normal"
A
B
C
D
E
F
H01
H02
H03
H04
H05
H06
Logic Diagram for "with 1 inverter"
Logic Diagram for "with 2 inverter"
D → Y
E → Y
N01
Logic Diagram for "with 3 inverter"
F → Y
Y
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.210
0.369
0.226
0.374
0.235
0.377
0.231
0.358
0.245
0.361
0.255
0.365
0.264
0.435
0.279
0.440
0.289
0.443
0.277
0.409
0.292
0.412
0.304
0.416
0.344
0.591
0.364
0.622
0.378
0.677
0.370
0.555
0.390
0.585
0.406
0.639
0.429
0.701
0.448
0.732
0.466
0.786
0.448
0.640
0.469
0.670
0.486
0.725
0.596
1.061
0.636
1.225
0.659
1.409
0.618
0.949
0.659
1.110
0.683
1.296
0.746
1.280
0.785
1.444
0.821
1.628
0.761
1.125
0.803
1.285
0.838
1.472
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.005
0.006
0.005
0.006
0.005
0.006
0.005
0.006
0.005
0.006
0.005
0.006
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.006
0.008
0.006
0.008
0.006
0.008
0.006
0.008
0.006
0.008
0.006
0.008
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.009
0.011
0.009
0.011
0.009
0.011
0.009
0.011
0.009
0.011
0.009
0.011
Symbol
A
B
C
D
E
F
A
B
C
D
E
F
Output
Fanin Symbol Fanout
1.0
1.0
1.0
1.0
1.0
1.0
Y
34
1.0
1.0
1.0
1.0
1.0
1.0
Y
66
Logic Diagram for "with 4 inverter"
Block Library
A13872EJ5V0BL
2 - 30
Block Library
A13872EJ5V0BL
2 - 31
Chapter 2 Function Block
Function
Block type
Chapter 2 Function Block
8-Input NOR
Normal
with 1 inverter with 2 inverter with 3 inverter with 4 inverter
Drivability
Name
cells
Low Power
L208
7
x1
F208
7
x2
F228
8
Name
cells
Name
cells
Name
cells
Name
Block
type
-
cells
L208
IN
Path
→ OUT
A → Y
B → Y
C → Y
x4
D → Y
x8
Block type
Drivability
Normal
Name
with 1 inverter with 2 inverter with 3 inverter with 4 inverter
cells
Name
cells
Name
cells
Name
cells
Name
-
E → Y
cells
Low Power
F → Y
x1
G → Y
x2
H → Y
x4
x8
F208
Logic Diagram for "Normal"
A
B
C
D
E
F
G
H
H01
H02
H03
H04
H05
H06
H07
H08
Logic Diagram for "with 1 inverter"
Logic Diagram for "with 2 inverter"
A → Y
B → Y
C → Y
N01
D → Y
Y
E → Y
F → Y
G → Y
Logic Diagram for "with 3 inverter"
H → Y
Logic Diagram for "with 4 inverter"
F228
A → Y
B → Y
C → Y
D → Y
E → Y
F → Y
G → Y
H → Y
Block Library
A13872EJ5V0BL
2 - 32
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.202
0.333
0.217
0.318
0.220
0.343
0.234
0.329
0.249
0.368
0.265
0.354
0.262
0.375
0.275
0.360
0.208
0.355
0.224
0.340
0.226
0.367
0.242
0.351
0.253
0.393
0.269
0.379
0.264
0.399
0.279
0.383
0.259
0.452
0.273
0.437
0.271
0.456
0.286
0.439
0.302
0.487
0.316
0.469
0.313
0.491
0.327
0.474
0.344
0.582
0.364
0.578
0.369
0.593
0.389
0.587
0.409
0.626
0.429
0.620
0.425
0.632
0.445
0.625
0.352
0.623
0.373
0.618
0.377
0.634
0.398
0.628
0.418
0.671
0.437
0.664
0.431
0.673
0.452
0.667
0.429
0.790
0.450
0.785
0.449
0.790
0.470
0.784
0.491
0.831
0.513
0.825
0.507
0.832
0.527
0.825
0.659
1.326
0.696
1.384
0.680
1.299
0.718
1.357
0.712
1.299
0.749
1.358
0.730
1.289
0.767
1.345
0.667
1.424
0.705
1.482
0.688
1.401
0.727
1.457
0.723
1.406
0.761
1.464
0.738
1.392
0.776
1.447
0.801
1.782
0.840
1.840
0.817
1.738
0.856
1.795
0.852
1.750
0.892
1.805
0.868
1.730
0.907
1.790
0.020
0.022
0.020
0.022
0.020
0.022
0.020
0.022
0.020
0.022
0.020
0.022
0.020
0.022
0.020
0.022
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.005
0.006
0.005
0.006
0.005
0.006
0.005
0.006
0.005
0.006
0.005
0.006
0.005
0.006
0.005
0.006
0.025
0.030
0.025
0.030
0.025
0.030
0.025
0.030
0.025
0.030
0.025
0.030
0.025
0.030
0.025
0.030
0.013
0.016
0.013
0.016
0.013
0.016
0.013
0.016
0.013
0.016
0.013
0.016
0.013
0.016
0.013
0.016
0.007
0.008
0.007
0.008
0.007
0.008
0.007
0.008
0.007
0.008
0.007
0.008
0.007
0.008
0.007
0.008
0.033
0.044
0.033
0.044
0.033
0.044
0.033
0.044
0.034
0.044
0.034
0.044
0.034
0.044
0.034
0.044
0.017
0.023
0.017
0.023
0.017
0.023
0.017
0.023
0.017
0.023
0.017
0.023
0.017
0.023
0.017
0.023
0.009
0.012
0.009
0.012
0.009
0.012
0.009
0.012
0.009
0.012
0.009
0.012
0.009
0.012
0.009
0.012
Block Library
A13872EJ5V0BL
Symbol
A
B
C
D
E
F
G
H
Output
Fanin Symbol Fanout
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Y
15
A
B
C
D
E
F
G
H
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Y
31
A
B
C
D
E
F
G
H
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Y
57
2 - 33
Chapter 2 Function Block
Function
Block type
Chapter 2 Function Block
2-Input OR
Normal
with 1 inverter with 2 inverter with 3 inverter with 4 inverter
Drivability
Name
cells
Low Power
L212
2
x1
F212
2
x2
F232
3
x4
F252
6
Name
cells
Name
cells
Name
cells
Name
Block
type
-
cells
L212
Drivability
A → Y
B → Y
F212
A → Y
B → Y
x8
Block type
IN
Path
→ OUT
Normal
Name
with 1 inverter with 2 inverter with 3 inverter with 4 inverter
cells
Name
cells
Name
cells
Name
cells
Name
-
F232
A → Y
cells
B → Y
Low Power
x1
F252
A → Y
x2
B → Y
x4
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.117
0.182
0.134
0.169
0.133
0.207
0.148
0.194
0.182
0.280
0.194
0.265
0.190
0.278
0.190
0.278
0.193
0.283
0.214
0.279
0.205
0.320
0.224
0.317
0.264
0.445
0.282
0.442
0.276
0.449
0.276
0.449
0.337
0.515
0.373
0.573
0.345
0.579
0.382
0.639
0.440
0.815
0.480
0.875
0.465
0.852
0.465
0.853
0.021
0.020
0.021
0.020
0.011
0.010
0.011
0.010
0.006
0.005
0.006
0.005
0.003
0.003
0.003
0.003
0.029
0.025
0.029
0.025
0.015
0.013
0.015
0.013
0.008
0.007
0.008
0.007
0.004
0.003
0.004
0.003
0.042
0.034
0.042
0.034
0.021
0.018
0.021
0.018
0.011
0.010
0.011
0.010
0.005
0.005
0.005
0.005
Symbol
A
B
Output
Fanin Symbol Fanout
1.0
1.0
Y
17
A
B
1.0
1.0
Y
34
A
B
1.0
1.0
Y
68
A
B
2.0
2.1
Y
139
x8
Logic Diagram for "Normal"
A
Logic Diagram for "with 1 inverter"
Logic Diagram for "with 2 inverter"
H01
N01
Y
B H02
Logic Diagram for "with 3 inverter"
Logic Diagram for "with 4 inverter"
Block Library
A13872EJ5V0BL
2 - 34
Block Library
A13872EJ5V0BL
2 - 35
Chapter 2 Function Block
Function
Block type
Chapter 2 Function Block
3-Input OR
Normal
with 1 inverter with 2 inverter with 3 inverter with 4 inverter
Drivability
Name
cells
Low Power
L213
2
x1
F213
3
x2
F233
4
Name
cells
Name
cells
Name
cells
Name
Block
type
-
cells
L213
IN
Path
→ OUT
A → Y
B → Y
C → Y
x4
F213
x8
Block type
Drivability
Normal
Name
with 1 inverter with 2 inverter with 3 inverter with 4 inverter
cells
Name
cells
Name
cells
Name
cells
Name
-
A → Y
B → Y
cells
C → Y
Low Power
x1
F233
A → Y
x2
B → Y
x4
x8
C → Y
Logic Diagram for "Normal"
A H01
B H02
C H03
Logic Diagram for "with 1 inverter"
N01
Logic Diagram for "with 3 inverter"
Logic Diagram for "with 2 inverter"
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.130
0.267
0.145
0.270
0.153
0.272
0.145
0.307
0.159
0.312
0.170
0.317
0.191
0.412
0.203
0.416
0.215
0.420
0.212
0.404
0.232
0.433
0.244
0.485
0.223
0.468
0.241
0.500
0.258
0.557
0.278
0.642
0.296
0.679
0.315
0.736
0.347
0.645
0.384
0.803
0.404
0.985
0.355
0.759
0.397
0.927
0.419
1.113
0.449
1.101
0.493
1.274
0.525
1.457
0.022
0.021
0.022
0.021
0.022
0.021
0.011
0.011
0.011
0.011
0.011
0.011
0.006
0.006
0.006
0.006
0.006
0.006
0.030
0.027
0.030
0.027
0.030
0.027
0.015
0.014
0.015
0.014
0.015
0.014
0.008
0.008
0.008
0.008
0.008
0.008
0.042
0.038
0.042
0.038
0.043
0.037
0.021
0.020
0.021
0.020
0.022
0.020
0.011
0.011
0.011
0.011
0.011
0.011
Symbol
A
B
C
Output
Fanin Symbol Fanout
1.0
1.0
1.0
Y
16
A
B
C
1.0
1.0
1.0
Y
34
A
B
C
1.0
1.0
1.0
Y
68
Y
Logic Diagram for "with 4 inverter"
Block Library
A13872EJ5V0BL
2 - 36
Block Library
A13872EJ5V0BL
2 - 37
Chapter 2 Function Block
Function
Block type
Chapter 2 Function Block
4-Input OR
Normal
with 1 inverter with 2 inverter with 3 inverter with 4 inverter
Drivability
Name
cells
Low Power
L214
3
x1
F214
3
x2
F234
4
Name
cells
Name
cells
Name
cells
Name
Block
type
-
cells
L214
IN
Path
→ OUT
A → Y
B → Y
C → Y
x4
D → Y
x8
Block type
Drivability
Normal
Name
with 1 inverter with 2 inverter with 3 inverter with 4 inverter
cells
Name
cells
Name
cells
Name
cells
Name
-
F214
A → Y
cells
Low Power
B → Y
x1
C → Y
x2
D → Y
x4
x8
F234
Logic Diagram for "Normal"
A
B
C
D
H01
H02
H03
H04
Logic Diagram for "with 1 inverter"
Logic Diagram for "with 2 inverter"
A → Y
B → Y
C → Y
N01
Logic Diagram for "with 3 inverter"
Y
D → Y
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.127
0.298
0.142
0.315
0.153
0.339
0.153
0.336
0.142
0.343
0.155
0.359
0.167
0.389
0.167
0.383
0.188
0.471
0.200
0.490
0.213
0.522
0.213
0.517
0.211
0.446
0.232
0.500
0.247
0.611
0.247
0.626
0.220
0.517
0.239
0.574
0.255
0.698
0.256
0.708
0.276
0.736
0.295
0.802
0.314
0.928
0.314
0.937
0.346
0.678
0.386
0.901
0.409
1.262
0.404
1.331
0.353
0.804
0.393
1.049
0.419
1.418
0.413
1.487
0.446
1.233
0.491
1.496
0.525
1.871
0.520
1.936
0.021
0.022
0.021
0.022
0.021
0.022
0.021
0.022
0.011
0.011
0.011
0.011
0.011
0.011
0.011
0.011
0.006
0.006
0.006
0.006
0.006
0.006
0.006
0.006
0.030
0.028
0.029
0.028
0.030
0.028
0.030
0.028
0.015
0.015
0.015
0.015
0.015
0.015
0.015
0.015
0.008
0.008
0.008
0.008
0.008
0.008
0.008
0.008
0.042
0.040
0.042
0.041
0.043
0.040
0.044
0.041
0.021
0.021
0.021
0.022
0.022
0.022
0.022
0.022
0.011
0.012
0.011
0.012
0.011
0.012
0.011
0.012
Symbol
A
B
C
D
Output
Fanin Symbol Fanout
1.0
1.0
1.0
1.0
Y
16
A
B
C
D
1.0
1.0
1.0
1.0
Y
34
A
B
C
D
1.0
1.0
1.0
1.0
Y
67
Logic Diagram for "with 4 inverter"
Block Library
A13872EJ5V0BL
2 - 38
Block Library
A13872EJ5V0BL
2 - 39
Chapter 2 Function Block
Function
Block type
Chapter 2 Function Block
5-Input OR
Normal
with 1 inverter with 2 inverter with 3 inverter with 4 inverter
Drivability
Name
cells
Low Power
L215
4
x1
F215
5
x2
F235
7
Name
cells
Name
cells
Name
cells
Name
Block
type
-
cells
L215
IN
Path
→ OUT
A → Y
B → Y
C → Y
x4
D → Y
x8
Block type
Drivability
Normal
Name
with 1 inverter with 2 inverter with 3 inverter with 4 inverter
cells
Name
cells
Name
cells
Name
cells
Name
-
E → Y
cells
F215
Low Power
x1
A → Y
B → Y
x2
C → Y
x4
x8
D → Y
Logic Diagram for "Normal"
A
B
C
D
E
H01
H02
H03
H04
H05
Logic Diagram for "with 1 inverter"
Logic Diagram for "with 2 inverter"
E → Y
F235
N01
Y
A → Y
B → Y
C → Y
D → Y
E → Y
Logic Diagram for "with 3 inverter"
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.115
0.187
0.132
0.176
0.139
0.264
0.154
0.266
0.164
0.268
0.150
0.228
0.164
0.212
0.161
0.333
0.174
0.339
0.185
0.341
0.252
0.352
0.268
0.337
0.279
0.429
0.295
0.432
0.305
0.437
0.192
0.304
0.212
0.299
0.226
0.397
0.246
0.426
0.262
0.479
0.234
0.359
0.253
0.355
0.250
0.519
0.269
0.550
0.285
0.606
0.415
0.573
0.435
0.569
0.456
0.671
0.476
0.702
0.491
0.755
0.335
0.587
0.370
0.645
0.361
0.635
0.400
0.792
0.421
0.976
0.393
0.676
0.430
0.735
0.402
0.878
0.443
1.046
0.467
1.230
0.761
1.121
0.798
1.180
0.789
1.176
0.830
1.336
0.856
1.521
0.022
0.030
0.022
0.030
0.022
0.030
0.022
0.030
0.022
0.030
0.011
0.015
0.011
0.015
0.011
0.015
0.011
0.015
0.011
0.015
0.006
0.005
0.006
0.005
0.006
0.005
0.006
0.005
0.006
0.005
0.030
0.041
0.030
0.041
0.030
0.041
0.030
0.041
0.030
0.041
0.015
0.021
0.015
0.020
0.015
0.021
0.015
0.021
0.015
0.021
0.008
0.006
0.008
0.006
0.008
0.006
0.008
0.006
0.008
0.006
0.042
0.063
0.042
0.063
0.042
0.063
0.042
0.062
0.043
0.062
0.021
0.031
0.021
0.031
0.021
0.032
0.021
0.032
0.022
0.032
0.011
0.008
0.011
0.008
0.011
0.008
0.011
0.008
0.011
0.008
Symbol
A
B
C
D
E
Output
Fanin Symbol Fanout
1.0
1.0
1.0
1.0
1.0
Y
12
A
B
C
D
E
1.0
1.0
1.0
1.0
1.0
Y
24
A
B
C
D
E
1.0
1.0
1.0
1.0
1.0
Y
70
Logic Diagram for "with 4 inverter"
Block Library
A13872EJ5V0BL
2 - 40
Block Library
A13872EJ5V0BL
2 - 41
Chapter 2 Function Block
Function
Block type
Chapter 2 Function Block
6-Input OR
Normal
with 1 inverter with 2 inverter with 3 inverter with 4 inverter
Drivability
Name
cells
Low Power
L216
4
x1
F216
5
x2
F236
7
Name
cells
Name
cells
Name
cells
Name
Block
type
-
cells
L216
IN
Path
→ OUT
A → Y
B → Y
C → Y
x4
D → Y
x8
Block type
Drivability
Normal
Name
with 1 inverter with 2 inverter with 3 inverter with 4 inverter
cells
Name
cells
Name
cells
Name
cells
Name
-
E → Y
cells
F → Y
Low Power
x1
F216
A → Y
x2
B → Y
x4
x8
C → Y
Logic Diagram for "Normal"
A
B
C
D
E
F
H01
H02
H03
H04
H05
H06
Logic Diagram for "with 1 inverter"
Logic Diagram for "with 2 inverter"
D → Y
E → Y
N01
F → Y
Y
F236
A → Y
B → Y
C → Y
Logic Diagram for "with 3 inverter"
D → Y
Logic Diagram for "with 4 inverter"
E → Y
F → Y
Block Library
A13872EJ5V0BL
2 - 42
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.136
0.299
0.150
0.305
0.160
0.308
0.144
0.271
0.158
0.274
0.169
0.278
0.168
0.345
0.181
0.349
0.191
0.352
0.171
0.353
0.184
0.358
0.194
0.362
0.268
0.447
0.283
0.451
0.293
0.454
0.285
0.432
0.301
0.436
0.311
0.439
0.219
0.467
0.239
0.498
0.253
0.550
0.232
0.406
0.252
0.437
0.268
0.491
0.265
0.542
0.283
0.576
0.299
0.629
0.267
0.556
0.285
0.587
0.301
0.646
0.439
0.717
0.459
0.747
0.473
0.802
0.464
0.677
0.484
0.706
0.500
0.761
0.357
0.790
0.395
0.954
0.416
1.139
0.368
0.647
0.408
0.808
0.430
0.994
0.441
0.960
0.483
1.126
0.508
1.304
0.443
0.976
0.484
1.143
0.511
1.329
0.780
1.301
0.820
1.466
0.843
1.652
0.801
1.182
0.842
1.343
0.868
1.528
0.023
0.031
0.023
0.031
0.023
0.031
0.022
0.030
0.022
0.030
0.022
0.030
0.011
0.016
0.011
0.016
0.011
0.016
0.011
0.016
0.011
0.016
0.011
0.016
0.006
0.005
0.006
0.005
0.006
0.005
0.006
0.005
0.006
0.005
0.006
0.005
0.031
0.042
0.031
0.042
0.031
0.042
0.031
0.041
0.031
0.041
0.031
0.041
0.015
0.022
0.015
0.022
0.015
0.021
0.015
0.022
0.015
0.022
0.015
0.022
0.008
0.006
0.008
0.006
0.008
0.006
0.008
0.006
0.008
0.006
0.008
0.006
0.043
0.066
0.043
0.066
0.044
0.066
0.043
0.063
0.043
0.063
0.044
0.063
0.021
0.033
0.021
0.033
0.022
0.033
0.021
0.033
0.021
0.033
0.022
0.033
0.011
0.008
0.011
0.008
0.011
0.008
0.011
0.008
0.011
0.008
0.011
0.008
Block Library
A13872EJ5V0BL
Symbol
A
B
C
D
E
F
Output
Fanin Symbol Fanout
1.0
1.0
1.0
1.0
1.0
1.0
Y
12
A
B
C
D
E
F
1.0
1.0
1.0
1.0
1.0
1.0
Y
22
A
B
C
D
E
F
1.0
1.0
1.0
1.0
1.0
1.0
Y
71
2 - 43
Chapter 2 Function Block
Function
Block type
Chapter 2 Function Block
8-Input OR
Normal
with 1 inverter with 2 inverter with 3 inverter with 4 inverter
Drivability
Name
cells
Low Power
L218
6
x1
F218
8
x2
F238
9
Name
cells
Name
cells
Name
cells
Name
Block
type
-
cells
L218
IN
Path
→ OUT
A → Y
B → Y
C → Y
x4
D → Y
x8
Block type
Drivability
Normal
Name
with 1 inverter with 2 inverter with 3 inverter with 4 inverter
cells
Name
cells
Name
cells
Name
cells
Name
-
E → Y
cells
Low Power
F → Y
x1
G → Y
x2
H → Y
x4
x8
F218
Logic Diagram for "Normal"
A
B
C
D
E
F
G
H
H01
H02
H03
H04
H05
H06
H07
H08
Logic Diagram for "with 1 inverter"
Logic Diagram for "with 2 inverter"
A → Y
B → Y
C → Y
N01
D → Y
Y
E → Y
F → Y
G → Y
Logic Diagram for "with 3 inverter"
H → Y
Logic Diagram for "with 4 inverter"
F238
A → Y
B → Y
C → Y
D → Y
E → Y
F → Y
G → Y
H → Y
Block Library
A13872EJ5V0BL
2 - 44
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.128
0.224
0.143
0.209
0.139
0.231
0.154
0.217
0.158
0.257
0.173
0.243
0.163
0.262
0.178
0.246
0.241
0.409
0.255
0.394
0.255
0.416
0.271
0.401
0.287
0.455
0.302
0.439
0.291
0.454
0.307
0.439
0.266
0.445
0.282
0.430
0.281
0.453
0.297
0.438
0.322
0.490
0.337
0.476
0.324
0.495
0.340
0.479
0.216
0.389
0.236
0.386
0.233
0.397
0.253
0.392
0.261
0.433
0.281
0.427
0.267
0.430
0.287
0.426
0.408
0.711
0.429
0.707
0.430
0.717
0.450
0.711
0.476
0.767
0.496
0.762
0.484
0.762
0.504
0.757
0.447
0.768
0.467
0.763
0.471
0.774
0.491
0.768
0.528
0.825
0.547
0.819
0.531
0.825
0.552
0.819
0.401
0.923
0.437
0.982
0.415
0.891
0.453
0.948
0.440
0.893
0.477
0.951
0.448
0.874
0.485
0.930
0.781
1.606
0.819
1.665
0.799
1.571
0.838
1.628
0.843
1.598
0.881
1.655
0.853
1.573
0.892
1.628
0.852
1.713
0.890
1.771
0.871
1.678
0.910
1.734
0.930
1.705
0.966
1.762
0.931
1.688
0.970
1.742
0.022
0.051
0.022
0.051
0.022
0.051
0.022
0.051
0.022
0.051
0.022
0.051
0.022
0.051
0.022
0.051
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.006
0.005
0.006
0.005
0.006
0.005
0.006
0.005
0.006
0.005
0.006
0.005
0.006
0.005
0.006
0.005
0.030
0.075
0.030
0.075
0.030
0.075
0.030
0.075
0.030
0.075
0.030
0.075
0.030
0.075
0.030
0.075
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.008
0.006
0.008
0.006
0.008
0.006
0.008
0.006
0.008
0.006
0.008
0.006
0.008
0.006
0.008
0.006
0.042
0.123
0.042
0.123
0.042
0.123
0.042
0.123
0.042
0.123
0.042
0.123
0.042
0.123
0.042
0.123
0.021
0.017
0.021
0.017
0.021
0.017
0.021
0.017
0.021
0.017
0.021
0.017
0.021
0.017
0.021
0.017
0.011
0.008
0.011
0.008
0.011
0.008
0.011
0.008
0.011
0.008
0.011
0.008
0.011
0.008
0.011
0.008
Block Library
A13872EJ5V0BL
Symbol
A
B
C
D
E
F
G
H
Output
Fanin Symbol Fanout
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Y
4
A
B
C
D
E
F
G
H
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Y
35
A
B
C
D
E
F
G
H
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Y
70
2 - 45
Chapter 2 Function Block
Chapter 2 Function Block
[MEMO]
[MEMO]
Block Library
A13872EJ5V0BL
2 - 46
Block Library
A13872EJ5V0BL
2 - 47
Chapter 2 Function Block
Chapter 2 Function Block
[MEMO]
2.4
AND(NAND)
Block Library
A13872EJ5V0BL
2 - 48
Block Library
A13872EJ5V0BL
2 - 49
Chapter 2 Function Block
Function
Block type
Chapter 2 Function Block
2-Input NAND
Normal
with 1 inverter with 2 inverter with 3 inverter with 4 inverter
Drivability
Name
cells
Low Power
L302
1
x1
F302
2
x2
F322
4
x4
F382
6
Name
cells
Name
cells
Name
cells
Name
Block
type
-
cells
L302
Drivability
A → Y
B → Y
F302
A → Y
B → Y
x8
Block type
IN
Path
→ OUT
Normal
Name
with 1 inverter with 2 inverter with 3 inverter with 4 inverter
cells
Name
cells
Name
cells
Name
cells
Name
-
F322
A → Y
cells
B → Y
Low Power
x1
F382
A → Y
x2
B → Y
x4
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.104
0.047
0.083
0.064
0.093
0.057
0.092
0.057
0.095
0.060
0.094
0.060
0.318
0.227
0.298
0.252
0.137
0.080
0.114
0.099
0.128
0.091
0.126
0.091
0.133
0.094
0.131
0.094
0.489
0.366
0.464
0.390
0.225
0.139
0.192
0.154
0.211
0.147
0.211
0.147
0.216
0.151
0.217
0.152
0.901
0.672
0.869
0.693
0.030
0.022
0.029
0.021
0.015
0.011
0.015
0.011
0.007
0.005
0.007
0.005
0.003
0.003
0.003
0.003
0.040
0.030
0.040
0.029
0.020
0.015
0.020
0.015
0.010
0.007
0.010
0.007
0.003
0.004
0.003
0.004
0.061
0.042
0.062
0.042
0.031
0.021
0.031
0.021
0.015
0.010
0.015
0.010
0.004
0.005
0.004
0.005
Symbol
A
B
Output
Fanin Symbol Fanout
1.0
1.0
Y
13
A
B
2.1
2.1
Y
26
A
B
4.2
4.2
Y
53
A
B
1.0
1.0
Y
140
x8
Logic Diagram for "Normal"
A
Logic Diagram for "with 1 inverter"
Logic Diagram for "with 2 inverter"
H01
N01
Y
B H02
Logic Diagram for "with 3 inverter"
Logic Diagram for "with 4 inverter"
Block Library
A13872EJ5V0BL
2 - 50
Block Library
A13872EJ5V0BL
2 - 51
Chapter 2 Function Block
Function
Block type
Chapter 2 Function Block
3-Input NAND
Normal
with 1 inverter with 2 inverter with 3 inverter with 4 inverter
Drivability
Name
cells
Low Power
L303
2
x1
F303
3
x2
F323
6
Name
cells
Name
cells
Name
cells
Name
Block
type
-
cells
L303
IN
Path
→ OUT
A → Y
B → Y
C → Y
x4
F303
x8
Block type
Drivability
Normal
Name
with 1 inverter with 2 inverter with 3 inverter with 4 inverter
cells
Name
cells
Name
cells
Name
cells
Name
-
A → Y
B → Y
cells
C → Y
Low Power
x1
F323
A → Y
x2
B → Y
x4
x8
C → Y
Logic Diagram for "Normal"
A H01
B H02
C H03
Logic Diagram for "with 1 inverter"
N01
Logic Diagram for "with 3 inverter"
Logic Diagram for "with 2 inverter"
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.138
0.055
0.132
0.071
0.128
0.091
0.115
0.062
0.124
0.073
0.115
0.063
0.141
0.076
0.140
0.073
0.142
0.076
0.210
0.103
0.208
0.121
0.211
0.149
0.168
0.106
0.183
0.120
0.169
0.107
0.220
0.129
0.215
0.126
0.220
0.129
0.460
0.201
0.457
0.217
0.456
0.241
0.349
0.187
0.363
0.196
0.350
0.188
0.472
0.224
0.469
0.221
0.471
0.224
0.041
0.022
0.041
0.021
0.041
0.021
0.020
0.011
0.020
0.011
0.020
0.011
0.010
0.005
0.010
0.005
0.010
0.005
0.058
0.030
0.058
0.029
0.058
0.029
0.029
0.015
0.029
0.015
0.029
0.015
0.015
0.007
0.015
0.007
0.015
0.007
0.093
0.042
0.093
0.042
0.093
0.042
0.047
0.021
0.047
0.021
0.047
0.021
0.023
0.010
0.023
0.010
0.023
0.010
Symbol
A
B
C
Output
Fanin Symbol Fanout
1.0
1.0
1.0
Y
6
A
B
C
2.1
2.1
2.1
Y
15
A
B
C
4.3
4.2
4.3
Y
26
Y
Logic Diagram for "with 4 inverter"
Block Library
A13872EJ5V0BL
2 - 52
Block Library
A13872EJ5V0BL
2 - 53
Chapter 2 Function Block
Function
Block type
Chapter 2 Function Block
4-Input NAND
Normal
with 1 inverter with 2 inverter with 3 inverter with 4 inverter
Drivability
Name
cells
Low Power
L304
2
x1
F304
4
x2
F324
8
Name
cells
Name
cells
Name
cells
Name
Block
type
-
cells
L304
IN
Path
→ OUT
A → Y
B → Y
C → Y
x4
D → Y
x8
Block type
Drivability
Normal
Name
with 1 inverter with 2 inverter with 3 inverter with 4 inverter
cells
Name
cells
Name
cells
Name
cells
Name
-
F304
A → Y
cells
Low Power
B → Y
x1
C → Y
x2
D → Y
x4
x8
F324
Logic Diagram for "Normal"
A
B
C
D
H01
H02
H03
H04
Logic Diagram for "with 1 inverter"
N01
Logic Diagram for "with 3 inverter"
Logic Diagram for "with 2 inverter"
A → Y
B → Y
C → Y
Y
D → Y
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.142
0.052
0.145
0.067
0.158
0.088
0.149
0.094
0.156
0.075
0.163
0.081
0.163
0.081
0.156
0.074
0.157
0.074
0.164
0.081
0.164
0.081
0.157
0.074
0.215
0.100
0.229
0.119
0.258
0.147
0.251
0.154
0.249
0.129
0.259
0.137
0.259
0.138
0.249
0.129
0.251
0.130
0.259
0.138
0.260
0.138
0.250
0.130
0.535
0.200
0.549
0.216
0.576
0.239
0.567
0.249
0.572
0.228
0.584
0.233
0.583
0.234
0.572
0.228
0.572
0.229
0.586
0.234
0.585
0.234
0.571
0.228
0.051
0.022
0.051
0.022
0.051
0.022
0.051
0.022
0.025
0.011
0.025
0.011
0.025
0.011
0.025
0.011
0.013
0.005
0.013
0.005
0.013
0.005
0.013
0.006
0.074
0.030
0.074
0.029
0.075
0.030
0.075
0.030
0.037
0.015
0.037
0.015
0.037
0.015
0.037
0.015
0.019
0.008
0.019
0.007
0.019
0.007
0.019
0.008
0.123
0.042
0.123
0.042
0.123
0.042
0.123
0.042
0.062
0.021
0.062
0.021
0.062
0.021
0.062
0.021
0.031
0.011
0.031
0.010
0.031
0.010
0.031
0.011
Symbol
A
B
C
D
Output
Fanin Symbol Fanout
1.0
1.0
1.0
1.0
Y
4
A
B
C
D
2.1
2.1
2.1
2.2
Y
8
A
B
C
D
4.4
4.4
4.4
4.4
Y
17
Logic Diagram for "with 4 inverter"
Block Library
A13872EJ5V0BL
2 - 54
Block Library
A13872EJ5V0BL
2 - 55
Chapter 2 Function Block
Function
Block type
Drivability
Chapter 2 Function Block
5-Input NAND
Normal
with 1 inverter with 2 inverter with 3 inverter with 4 inverter
Name
cells
x1
F305
5
x2
F325
6
Name
cells
Name
cells
Name
cells
Name
Block
type
-
cells
F305
IN
Path
→ OUT
A → Y
Low Power
B → Y
C → Y
x4
D → Y
x8
Block type
Drivability
Normal
Name
with 1 inverter with 2 inverter with 3 inverter with 4 inverter
cells
Name
cells
Name
cells
Name
cells
Name
-
E → Y
cells
F325
Low Power
x1
A → Y
B → Y
x2
C → Y
x4
x8
D → Y
Logic Diagram for "Normal"
A
B
C
D
E
H01
H02
H03
H04
H05
Logic Diagram for "with 1 inverter"
N01
Logic Diagram for "with 3 inverter"
Logic Diagram for "with 2 inverter"
E → Y
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.306
0.172
0.288
0.194
0.366
0.191
0.359
0.215
0.356
0.245
0.378
0.207
0.361
0.234
0.440
0.231
0.432
0.255
0.429
0.286
0.488
0.289
0.465
0.318
0.601
0.339
0.596
0.365
0.600
0.401
0.608
0.341
0.585
0.370
0.725
0.399
0.718
0.426
0.722
0.463
0.904
0.544
0.872
0.563
1.266
0.683
1.260
0.702
1.262
0.733
1.132
0.640
1.100
0.661
1.500
0.795
1.492
0.814
1.493
0.845
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.005
0.006
0.005
0.006
0.005
0.006
0.005
0.006
0.005
0.006
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.007
0.008
0.007
0.008
0.007
0.008
0.007
0.008
0.007
0.008
0.018
0.021
0.018
0.021
0.018
0.021
0.018
0.021
0.018
0.021
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
Symbol
A
B
C
D
E
A
B
C
D
E
Output
Fanin Symbol Fanout
1.0
1.0
1.0
1.0
1.0
Y
35
1.0
1.0
1.0
1.0
1.0
Y
69
Y
Logic Diagram for "with 4 inverter"
Block Library
A13872EJ5V0BL
2 - 56
Block Library
A13872EJ5V0BL
2 - 57
Chapter 2 Function Block
Function
Block type
Drivability
Chapter 2 Function Block
6-Input NAND
Normal
with 1 inverter with 2 inverter with 3 inverter with 4 inverter
Name
cells
x1
F306
5
x2
F326
6
Name
cells
Name
cells
Name
cells
Name
Block
type
-
cells
F306
IN
Path
→ OUT
A → Y
Low Power
B → Y
C → Y
x4
D → Y
x8
Block type
Drivability
Normal
Name
with 1 inverter with 2 inverter with 3 inverter with 4 inverter
cells
Name
cells
Name
cells
Name
cells
Name
-
E → Y
cells
F → Y
Low Power
x1
F326
A → Y
x2
B → Y
x4
x8
C → Y
Logic Diagram for "Normal"
A
B
C
D
E
F
H01
H02
H03
H04
H05
H06
Logic Diagram for "with 1 inverter"
Logic Diagram for "with 2 inverter"
D → Y
E → Y
N01
Logic Diagram for "with 3 inverter"
Y
F → Y
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.372
0.180
0.366
0.204
0.362
0.233
0.371
0.195
0.365
0.218
0.361
0.249
0.448
0.219
0.440
0.242
0.439
0.275
0.446
0.235
0.439
0.259
0.435
0.290
0.607
0.321
0.603
0.346
0.606
0.383
0.609
0.344
0.604
0.370
0.607
0.407
0.730
0.378
0.727
0.405
0.731
0.444
0.734
0.404
0.728
0.431
0.731
0.469
1.254
0.639
1.247
0.657
1.248
0.688
1.276
0.686
1.272
0.708
1.273
0.740
1.488
0.746
1.482
0.765
1.483
0.797
1.514
0.800
1.509
0.822
1.508
0.852
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.005
0.006
0.005
0.006
0.005
0.006
0.005
0.006
0.005
0.006
0.005
0.006
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.007
0.008
0.007
0.008
0.007
0.008
0.007
0.008
0.007
0.008
0.007
0.008
0.018
0.021
0.018
0.021
0.018
0.021
0.018
0.021
0.018
0.021
0.018
0.021
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
Symbol
A
B
C
D
E
F
A
B
C
D
E
F
Output
Fanin Symbol Fanout
1.0
1.0
1.0
1.0
1.0
1.0
Y
35
1.0
1.0
1.0
1.0
1.0
1.0
Y
69
Logic Diagram for "with 4 inverter"
Block Library
A13872EJ5V0BL
2 - 58
Block Library
A13872EJ5V0BL
2 - 59
Chapter 2 Function Block
Function
Block type
Drivability
Chapter 2 Function Block
8-Input NAND
Normal
with 1 inverter with 2 inverter with 3 inverter with 4 inverter
Name
cells
x1
F308
6
x2
F328
7
Name
cells
Name
cells
Name
cells
Name
Block
type
-
cells
F308
IN
Path
→ OUT
A → Y
Low Power
B → Y
C → Y
x4
D → Y
x8
Block type
Drivability
Normal
Name
with 1 inverter with 2 inverter with 3 inverter with 4 inverter
cells
Name
cells
Name
cells
Name
cells
Name
-
E → Y
cells
Low Power
F → Y
x1
G → Y
x2
H → Y
x4
x8
F328
Logic Diagram for "Normal"
A
B
C
D
E
F
G
H
H01
H02
H03
H04
H05
H06
H07
H08
Logic Diagram for "with 1 inverter"
Logic Diagram for "with 2 inverter"
A → Y
B → Y
C → Y
N01
D → Y
Y
E → Y
F → Y
G → Y
Logic Diagram for "with 3 inverter"
H → Y
Logic Diagram for "with 4 inverter"
Block Library
A13872EJ5V0BL
2 - 60
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.397
0.174
0.402
0.196
0.411
0.225
0.402
0.234
0.390
0.186
0.392
0.208
0.402
0.238
0.395
0.248
0.475
0.213
0.479
0.236
0.490
0.268
0.481
0.278
0.467
0.227
0.469
0.250
0.481
0.283
0.473
0.294
0.648
0.314
0.661
0.340
0.688
0.376
0.682
0.388
0.639
0.333
0.648
0.360
0.676
0.398
0.671
0.410
0.778
0.372
0.790
0.399
0.819
0.439
0.814
0.453
0.768
0.396
0.777
0.422
0.806
0.463
0.801
0.476
1.401
0.631
1.413
0.651
1.443
0.682
1.432
0.694
1.403
0.676
1.418
0.696
1.444
0.729
1.435
0.742
1.646
0.739
1.659
0.759
1.687
0.794
1.680
0.806
1.646
0.792
1.660
0.811
1.689
0.847
1.682
0.859
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.005
0.006
0.005
0.006
0.005
0.006
0.005
0.006
0.005
0.006
0.005
0.006
0.005
0.006
0.005
0.006
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.007
0.008
0.007
0.008
0.007
0.008
0.007
0.008
0.007
0.008
0.007
0.008
0.007
0.008
0.007
0.008
0.018
0.021
0.018
0.021
0.018
0.021
0.018
0.021
0.018
0.021
0.018
0.021
0.018
0.021
0.018
0.021
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
Block Library
A13872EJ5V0BL
Symbol
A
B
C
D
E
F
G
H
A
B
C
D
E
F
G
H
Output
Fanin Symbol Fanout
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Y
35
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Y
69
2 - 61
Chapter 2 Function Block
Function
Block type
Chapter 2 Function Block
2-Input AND
Normal
with 1 inverter with 2 inverter with 3 inverter with 4 inverter
Drivability
Name
cells
Low Power
L312
2
x1
F312
2
x2
F332
3
x4
F352
6
Name
cells
Name
cells
Name
cells
Name
Block
type
-
cells
L312
Drivability
A → Y
B → Y
F312
A → Y
B → Y
x8
Block type
IN
Path
→ OUT
Normal
Name
with 1 inverter with 2 inverter with 3 inverter with 4 inverter
cells
Name
cells
Name
cells
Name
cells
Name
-
F332
A → Y
cells
B → Y
Low Power
x1
F352
A → Y
x2
B → Y
x4
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.165
0.116
0.149
0.143
0.184
0.132
0.164
0.155
0.242
0.183
0.217
0.200
0.231
0.194
0.231
0.194
0.251
0.193
0.227
0.221
0.274
0.213
0.248
0.236
0.361
0.288
0.334
0.309
0.351
0.303
0.350
0.303
0.452
0.355
0.421
0.375
0.499
0.380
0.467
0.400
0.673
0.515
0.640
0.534
0.663
0.531
0.662
0.530
0.021
0.020
0.021
0.020
0.011
0.010
0.011
0.010
0.006
0.005
0.006
0.005
0.003
0.003
0.003
0.003
0.030
0.024
0.030
0.024
0.015
0.012
0.015
0.012
0.008
0.006
0.008
0.006
0.004
0.003
0.004
0.003
0.042
0.033
0.042
0.033
0.022
0.017
0.022
0.017
0.011
0.009
0.011
0.009
0.006
0.004
0.006
0.004
Symbol
A
B
Output
Fanin Symbol Fanout
1.0
1.0
Y
17
A
B
1.0
1.0
Y
34
A
B
1.0
1.0
Y
67
A
B
2.1
2.1
Y
134
x8
Logic Diagram for "Normal"
A
Logic Diagram for "with 1 inverter"
Logic Diagram for "with 2 inverter"
H01
N01
Y
B H02
Logic Diagram for "with 3 inverter"
Logic Diagram for "with 4 inverter"
Block Library
A13872EJ5V0BL
2 - 62
Block Library
A13872EJ5V0BL
2 - 63
Chapter 2 Function Block
Function
Block type
Chapter 2 Function Block
3-Input AND
Normal
with 1 inverter with 2 inverter with 3 inverter with 4 inverter
Drivability
Name
cells
Low Power
L313
2
x1
F313
3
x2
F333
4
Name
cells
Name
cells
Name
cells
Name
Block
type
-
cells
L313
IN
Path
→ OUT
A → Y
B → Y
C → Y
x4
F313
x8
Block type
Drivability
Normal
Name
with 1 inverter with 2 inverter with 3 inverter with 4 inverter
cells
Name
cells
Name
cells
Name
cells
Name
-
A → Y
B → Y
cells
C → Y
Low Power
x1
F333
A → Y
x2
B → Y
x4
x8
C → Y
Logic Diagram for "Normal"
A H01
B H02
C H03
Logic Diagram for "with 1 inverter"
N01
Logic Diagram for "with 3 inverter"
Logic Diagram for "with 2 inverter"
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.225
0.127
0.219
0.150
0.213
0.174
0.252
0.142
0.243
0.162
0.239
0.190
0.322
0.190
0.312
0.207
0.306
0.232
0.360
0.226
0.355
0.253
0.358
0.281
0.400
0.243
0.394
0.268
0.400
0.304
0.515
0.313
0.512
0.338
0.516
0.373
0.776
0.452
0.770
0.471
0.770
0.491
0.863
0.470
0.854
0.488
0.859
0.518
1.112
0.593
1.106
0.613
1.106
0.642
0.022
0.020
0.022
0.020
0.022
0.020
0.011
0.010
0.011
0.010
0.011
0.010
0.006
0.005
0.006
0.005
0.006
0.005
0.030
0.025
0.030
0.025
0.030
0.025
0.015
0.013
0.015
0.013
0.015
0.013
0.008
0.007
0.008
0.007
0.008
0.007
0.043
0.034
0.043
0.034
0.043
0.033
0.022
0.017
0.022
0.017
0.022
0.017
0.012
0.009
0.012
0.009
0.012
0.009
Symbol
A
B
C
Output
Fanin Symbol Fanout
1.0
1.0
1.0
Y
16
A
B
C
1.0
1.0
1.0
Y
33
A
B
C
1.0
1.0
1.0
Y
62
Y
Logic Diagram for "with 4 inverter"
Block Library
A13872EJ5V0BL
2 - 64
Block Library
A13872EJ5V0BL
2 - 65
Chapter 2 Function Block
Function
Block type
Chapter 2 Function Block
4-Input AND
Normal
with 1 inverter with 2 inverter with 3 inverter with 4 inverter
Drivability
Name
cells
Low Power
L314
3
x1
F314
3
x2
F334
4
Name
cells
Name
cells
Name
cells
Name
Block
type
-
cells
L314
IN
Path
→ OUT
A → Y
B → Y
C → Y
x4
D → Y
x8
Block type
Drivability
Normal
Name
with 1 inverter with 2 inverter with 3 inverter with 4 inverter
cells
Name
cells
Name
cells
Name
cells
Name
-
F314
A → Y
cells
Low Power
B → Y
x1
C → Y
x2
D → Y
x4
x8
F334
Logic Diagram for "Normal"
A
B
C
D
H01
H02
H03
H04
Logic Diagram for "with 1 inverter"
N01
Logic Diagram for "with 3 inverter"
Logic Diagram for "with 2 inverter"
A → Y
B → Y
C → Y
Y
D → Y
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.254
0.124
0.257
0.146
0.267
0.177
0.258
0.187
0.280
0.136
0.281
0.155
0.293
0.186
0.282
0.194
0.365
0.186
0.366
0.202
0.377
0.229
0.368
0.237
0.408
0.224
0.418
0.251
0.446
0.290
0.440
0.303
0.450
0.237
0.461
0.262
0.492
0.300
0.486
0.312
0.599
0.309
0.612
0.334
0.643
0.371
0.634
0.384
0.928
0.452
0.941
0.472
0.967
0.502
0.959
0.518
1.033
0.463
1.045
0.483
1.077
0.516
1.065
0.528
1.364
0.588
1.377
0.610
1.406
0.639
1.398
0.655
0.022
0.020
0.022
0.020
0.022
0.020
0.022
0.020
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.006
0.005
0.006
0.005
0.006
0.005
0.006
0.005
0.030
0.025
0.030
0.025
0.030
0.025
0.030
0.025
0.016
0.013
0.016
0.013
0.016
0.013
0.016
0.013
0.008
0.006
0.008
0.007
0.008
0.007
0.008
0.007
0.044
0.033
0.044
0.033
0.044
0.034
0.044
0.034
0.023
0.017
0.023
0.017
0.023
0.017
0.023
0.017
0.012
0.009
0.012
0.009
0.012
0.009
0.012
0.009
Symbol
A
B
C
D
Output
Fanin Symbol Fanout
1.0
1.0
1.0
1.0
Y
16
A
B
C
D
1.0
1.0
1.0
1.0
Y
31
A
B
C
D
1.0
1.0
1.0
1.0
Y
58
Logic Diagram for "with 4 inverter"
Block Library
A13872EJ5V0BL
2 - 66
Block Library
A13872EJ5V0BL
2 - 67
Chapter 2 Function Block
Function
Block type
Chapter 2 Function Block
5-Input AND
Normal
with 1 inverter with 2 inverter with 3 inverter with 4 inverter
Drivability
Name
cells
Low Power
L315
4
x1
F315
5
x2
F335
7
Name
cells
Name
cells
Name
cells
Name
Block
type
-
cells
L315
IN
Path
→ OUT
A → Y
B → Y
C → Y
x4
D → Y
x8
Block type
Drivability
Normal
Name
with 1 inverter with 2 inverter with 3 inverter with 4 inverter
cells
Name
cells
Name
cells
Name
cells
Name
-
E → Y
cells
F315
Low Power
x1
A → Y
B → Y
x2
C → Y
x4
x8
D → Y
Logic Diagram for "Normal"
A
B
C
D
E
H01
H02
H03
H04
H05
Logic Diagram for "with 1 inverter"
Logic Diagram for "with 2 inverter"
E → Y
F335
N01
Y
A → Y
B → Y
C → Y
D → Y
E → Y
Logic Diagram for "with 3 inverter"
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.178
0.116
0.163
0.141
0.238
0.136
0.233
0.160
0.228
0.188
0.218
0.152
0.197
0.172
0.286
0.159
0.277
0.179
0.272
0.205
0.358
0.249
0.341
0.271
0.420
0.269
0.412
0.292
0.409
0.322
0.278
0.195
0.255
0.223
0.391
0.245
0.387
0.271
0.390
0.307
0.336
0.248
0.310
0.273
0.459
0.275
0.454
0.299
0.458
0.334
0.578
0.414
0.554
0.442
0.691
0.465
0.685
0.491
0.689
0.528
0.508
0.360
0.475
0.381
0.867
0.492
0.862
0.514
0.862
0.542
0.631
0.450
0.598
0.469
0.993
0.534
0.986
0.552
0.989
0.582
1.087
0.779
1.055
0.800
1.451
0.921
1.443
0.940
1.446
0.971
0.038
0.020
0.038
0.020
0.038
0.020
0.038
0.020
0.038
0.020
0.019
0.010
0.019
0.010
0.019
0.010
0.019
0.010
0.019
0.010
0.006
0.005
0.006
0.005
0.006
0.005
0.006
0.005
0.006
0.005
0.053
0.025
0.053
0.025
0.053
0.025
0.053
0.025
0.053
0.025
0.027
0.013
0.027
0.013
0.027
0.013
0.027
0.013
0.027
0.013
0.008
0.006
0.008
0.006
0.008
0.006
0.008
0.006
0.008
0.006
0.077
0.033
0.077
0.033
0.077
0.034
0.077
0.034
0.077
0.034
0.039
0.017
0.039
0.017
0.039
0.018
0.039
0.018
0.039
0.018
0.011
0.008
0.011
0.008
0.011
0.008
0.011
0.008
0.011
0.008
Symbol
A
B
C
D
E
Output
Fanin Symbol Fanout
1.0
1.0
1.0
1.0
1.0
Y
8
A
B
C
D
E
1.0
1.0
1.0
1.0
1.0
Y
16
A
B
C
D
E
1.0
1.0
1.0
1.0
1.0
Y
70
Logic Diagram for "with 4 inverter"
Block Library
A13872EJ5V0BL
2 - 68
Block Library
A13872EJ5V0BL
2 - 69
Chapter 2 Function Block
Function
Block type
Chapter 2 Function Block
6-Input AND
Normal
with 1 inverter with 2 inverter with 3 inverter with 4 inverter
Drivability
Name
cells
Low Power
L316
4
x1
F316
5
x2
F336
7
Name
cells
Name
cells
Name
cells
Name
Block
type
-
cells
L316
IN
Path
→ OUT
A → Y
B → Y
C → Y
x4
D → Y
x8
Block type
Drivability
Normal
Name
with 1 inverter with 2 inverter with 3 inverter with 4 inverter
cells
Name
cells
Name
cells
Name
cells
Name
-
E → Y
cells
F → Y
Low Power
x1
F316
A → Y
x2
B → Y
x4
x8
C → Y
Logic Diagram for "Normal"
A
B
C
D
E
F
H01
H02
H03
H04
H05
H06
Logic Diagram for "with 1 inverter"
Logic Diagram for "with 2 inverter"
D → Y
E → Y
N01
F → Y
Y
F336
A → Y
B → Y
C → Y
Logic Diagram for "with 3 inverter"
D → Y
Logic Diagram for "with 4 inverter"
E → Y
F → Y
Block Library
A13872EJ5V0BL
2 - 70
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.246
0.128
0.241
0.151
0.237
0.180
0.242
0.138
0.236
0.161
0.232
0.191
0.288
0.164
0.278
0.183
0.274
0.211
0.290
0.165
0.281
0.185
0.277
0.213
0.426
0.258
0.419
0.280
0.415
0.309
0.425
0.273
0.418
0.295
0.414
0.327
0.398
0.230
0.394
0.255
0.399
0.293
0.397
0.247
0.392
0.273
0.395
0.311
0.465
0.282
0.459
0.307
0.463
0.344
0.466
0.284
0.462
0.308
0.467
0.346
0.697
0.446
0.694
0.472
0.696
0.508
0.698
0.470
0.693
0.495
0.697
0.533
0.856
0.460
0.850
0.480
0.851
0.511
0.876
0.497
0.870
0.515
0.870
0.546
1.005
0.550
0.999
0.568
0.999
0.599
1.010
0.552
1.003
0.572
1.005
0.603
1.438
0.875
1.432
0.894
1.431
0.925
1.462
0.922
1.456
0.945
1.457
0.978
0.038
0.020
0.038
0.020
0.038
0.020
0.038
0.020
0.038
0.020
0.038
0.020
0.019
0.010
0.019
0.010
0.019
0.010
0.019
0.010
0.019
0.010
0.019
0.010
0.006
0.005
0.006
0.005
0.006
0.005
0.006
0.005
0.006
0.005
0.006
0.005
0.053
0.025
0.053
0.025
0.053
0.025
0.053
0.025
0.053
0.025
0.053
0.025
0.027
0.012
0.027
0.012
0.027
0.013
0.027
0.012
0.027
0.013
0.027
0.013
0.008
0.006
0.008
0.006
0.008
0.006
0.008
0.006
0.008
0.006
0.008
0.006
0.077
0.034
0.077
0.034
0.077
0.034
0.077
0.034
0.077
0.034
0.077
0.034
0.039
0.017
0.039
0.017
0.039
0.017
0.039
0.017
0.039
0.017
0.039
0.017
0.011
0.008
0.011
0.008
0.011
0.008
0.011
0.008
0.011
0.008
0.011
0.008
Block Library
A13872EJ5V0BL
Symbol
A
B
C
D
E
F
Output
Fanin Symbol Fanout
1.0
1.0
1.0
1.0
1.0
1.0
Y
8
A
B
C
D
E
F
1.0
1.0
1.0
1.0
1.0
1.0
Y
16
A
B
C
D
E
F
1.0
1.0
1.0
1.0
1.0
1.0
Y
70
2 - 71
Chapter 2 Function Block
Function
Block type
Chapter 2 Function Block
8-Input AND
Normal
with 1 inverter with 2 inverter with 3 inverter with 4 inverter
Drivability
Name
cells
Low Power
L318
5
x1
F318
6
x2
F338
8
Name
cells
Name
cells
Name
cells
Name
Block
type
-
cells
L318
IN
Path
→ OUT
A → Y
B → Y
C → Y
x4
D → Y
x8
Block type
Drivability
Normal
Name
with 1 inverter with 2 inverter with 3 inverter with 4 inverter
cells
Name
cells
Name
cells
Name
cells
Name
-
E → Y
cells
Low Power
F → Y
x1
G → Y
x2
H → Y
x4
x8
F318
Logic Diagram for "Normal"
A
B
C
D
E
F
G
H
H01
H02
H03
H04
H05
H06
H07
H08
Logic Diagram for "with 1 inverter"
Logic Diagram for "with 2 inverter"
A → Y
B → Y
C → Y
N01
D → Y
Y
E → Y
F → Y
G → Y
Logic Diagram for "with 3 inverter"
H → Y
Logic Diagram for "with 4 inverter"
F338
A → Y
B → Y
C → Y
D → Y
E → Y
F → Y
G → Y
H → Y
Block Library
A13872EJ5V0BL
2 - 72
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.273
0.122
0.276
0.142
0.288
0.173
0.278
0.181
0.265
0.133
0.269
0.155
0.279
0.186
0.270
0.197
0.323
0.159
0.324
0.178
0.335
0.206
0.326
0.216
0.324
0.159
0.325
0.179
0.336
0.207
0.327
0.217
0.454
0.252
0.458
0.274
0.467
0.303
0.459
0.313
0.455
0.269
0.456
0.291
0.467
0.321
0.459
0.331
0.442
0.224
0.453
0.250
0.483
0.289
0.477
0.300
0.435
0.242
0.444
0.268
0.473
0.308
0.468
0.319
0.524
0.277
0.536
0.302
0.564
0.340
0.559
0.353
0.525
0.278
0.537
0.303
0.566
0.341
0.561
0.353
0.741
0.441
0.754
0.467
0.781
0.503
0.777
0.515
0.743
0.467
0.752
0.493
0.779
0.531
0.774
0.543
1.006
0.454
1.018
0.473
1.049
0.507
1.040
0.518
1.012
0.492
1.025
0.511
1.055
0.545
1.046
0.557
1.194
0.544
1.207
0.563
1.237
0.596
1.224
0.609
1.197
0.545
1.209
0.565
1.239
0.598
1.227
0.610
1.591
0.869
1.605
0.889
1.634
0.920
1.624
0.933
1.611
0.925
1.624
0.944
1.652
0.977
1.643
0.990
0.038
0.020
0.038
0.020
0.038
0.020
0.038
0.020
0.038
0.020
0.038
0.020
0.038
0.020
0.038
0.020
0.019
0.010
0.019
0.010
0.019
0.010
0.019
0.010
0.019
0.010
0.019
0.010
0.019
0.010
0.019
0.010
0.006
0.005
0.006
0.005
0.006
0.005
0.006
0.005
0.006
0.005
0.006
0.005
0.006
0.005
0.006
0.005
0.053
0.025
0.053
0.025
0.053
0.025
0.053
0.025
0.053
0.025
0.053
0.025
0.053
0.025
0.053
0.025
0.027
0.012
0.027
0.013
0.027
0.013
0.027
0.013
0.027
0.012
0.027
0.012
0.027
0.013
0.027
0.013
0.008
0.006
0.008
0.006
0.008
0.006
0.008
0.006
0.008
0.006
0.008
0.006
0.008
0.006
0.008
0.006
0.078
0.033
0.078
0.033
0.078
0.034
0.078
0.034
0.077
0.034
0.077
0.034
0.077
0.034
0.077
0.034
0.039
0.017
0.039
0.017
0.039
0.017
0.039
0.017
0.039
0.017
0.039
0.017
0.039
0.017
0.039
0.017
0.011
0.008
0.011
0.008
0.011
0.008
0.011
0.008
0.011
0.008
0.011
0.008
0.011
0.008
0.011
0.008
Block Library
A13872EJ5V0BL
Symbol
A
B
C
D
E
F
G
H
Output
Fanin Symbol Fanout
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Y
8
A
B
C
D
E
F
G
H
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Y
16
A
B
C
D
E
F
G
H
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Y
70
2 - 73
Chapter 2 Function Block
Chapter 2 Function Block
[MEMO]
[MEMO]
Block Library
A13872EJ5V0BL
2 - 74
Block Library
A13872EJ5V0BL
2 - 75
Chapter 2 Function Block
Chapter 2 Function Block
[MEMO]
2.5
AND-NOR
Block Library
A13872EJ5V0BL
2 - 76
Block Library
A13872EJ5V0BL
2 - 77
Chapter 2 Function Block
Function
Block type
Chapter 2 Function Block
1-2-Input AND-NOR
Normal
with inv. A
Drivability
Name
cells
Low Power
L421
2
x1
F421
3
Name
cells
with inv. B
Name
cells
with inv. C
Name
cells
with inv. D
Name
cells
with inv. E
Name
cells
Block
type
L421
IN
Path
→ OUT
A → Y
B → Y
x2
C → Y
x4
F421
x8
Block type
with inv. F
with inv. G
with inv. H
Drivability
Name
Name
Name
cells
cells
-
-
-
A → Y
B → Y
cells
C → Y
Low Power
x1
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.081
0.070
0.132
0.067
0.115
0.116
0.070
0.079
0.109
0.087
0.109
0.087
0.124
0.194
0.196
0.141
0.182
0.215
0.104
0.132
0.165
0.158
0.166
0.158
0.172
0.247
0.385
0.328
0.362
0.401
0.134
0.148
0.282
0.305
0.282
0.305
0.020
0.029
0.031
0.038
0.031
0.042
0.010
0.017
0.015
0.021
0.015
0.021
0.024
0.058
0.042
0.053
0.042
0.058
0.013
0.029
0.021
0.029
0.020
0.029
0.033
0.082
0.064
0.077
0.064
0.082
0.016
0.041
0.033
0.042
0.033
0.042
Symbol
A
B
C
A
B
C
Output
Fanin Symbol Fanout
1.0
1.0
1.0
Y
7
2.1
2.1
2.1
Y
15
x2
x4
x8
Logic Diagram for "Normal"
Logic Diagram for "with inv. A type"
Logic Diagram for "with inv. B type"
Logic Diagram for "with inv. C type"
Logic Diagram for "with inv. D type"
Logic Diagram for "with inv. E type"
Logic Diagram for "with inv. F type"
Logic Diagram for "with inv. G type"
Logic Diagram for "with inv. H type"
C H03
B H02
N01 Y
A H01
Block Library
A13872EJ5V0BL
2 - 78
Block Library
A13872EJ5V0BL
2 - 79
Chapter 2 Function Block
Function
Block type
Chapter 2 Function Block
1-1-2-Input AND-NOR
Normal
with inv. A
Drivability
Name
cells
Low Power
L422
2
x1
F422
4
Name
cells
with inv. B
Name
cells
with inv. C
Name
cells
with inv. D
Name
cells
with inv. E
Name
cells
Block
type
L422
IN
Path
→ OUT
A → Y
B → Y
x2
C → Y
x4
D → Y
x8
Block type
with inv. F
with inv. G
with inv. H
Drivability
Name
Name
Name
cells
cells
-
-
-
F422
A → Y
cells
Low Power
B → Y
x1
C → Y
x2
D → Y
x4
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.091
0.113
0.103
0.110
0.147
0.125
0.120
0.159
0.074
0.107
0.096
0.121
0.118
0.151
0.121
0.150
0.134
0.233
0.152
0.267
0.223
0.264
0.195
0.313
0.111
0.153
0.143
0.265
0.187
0.291
0.188
0.293
0.180
0.279
0.213
0.444
0.401
0.562
0.367
0.606
0.137
0.114
0.181
0.464
0.307
0.573
0.306
0.577
0.020
0.049
0.020
0.049
0.030
0.059
0.030
0.059
0.011
0.028
0.010
0.028
0.016
0.033
0.015
0.033
0.024
0.082
0.024
0.082
0.041
0.082
0.041
0.082
0.012
0.044
0.013
0.045
0.021
0.045
0.021
0.045
0.032
0.118
0.033
0.118
0.065
0.119
0.065
0.118
0.016
0.062
0.018
0.064
0.035
0.064
0.035
0.064
Symbol
A
B
C
D
A
B
C
D
Output
Fanin Symbol Fanout
1.0
1.0
1.0
1.0
Y
4
2.1
2.1
2.0
2.0
Y
8
x8
Logic Diagram for "Normal"
Logic Diagram for "with inv. A type"
Logic Diagram for "with inv. B type"
Logic Diagram for "with inv. C type"
Logic Diagram for "with inv. D type"
Logic Diagram for "with inv. E type"
Logic Diagram for "with inv. F type"
Logic Diagram for "with inv. G type"
Logic Diagram for "with inv. H type"
D H04
C H03
B H02
A H01
N01 Y
Block Library
A13872EJ5V0BL
2 - 80
Block Library
A13872EJ5V0BL
2 - 81
Chapter 2 Function Block
Function
Block type
Chapter 2 Function Block
1-3-Input AND-NOR
Normal
with inv. A
Drivability
Name
cells
Low Power
L423
2
x1
F423
4
Name
cells
with inv. B
Name
cells
with inv. C
Name
cells
with inv. D
Name
cells
with inv. E
Name
cells
Block
type
L423
IN
Path
→ OUT
A → Y
B → Y
x2
C → Y
x4
D → Y
x8
Block type
with inv. F
with inv. G
with inv. H
Drivability
Name
Name
Name
cells
cells
-
-
-
F423
A → Y
cells
Low Power
B → Y
x1
C → Y
x2
D → Y
x4
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.082
0.068
0.148
0.062
0.151
0.111
0.134
0.132
0.065
0.065
0.137
0.097
0.149
0.112
0.135
0.097
0.124
0.234
0.232
0.139
0.247
0.215
0.236
0.245
0.102
0.172
0.219
0.185
0.237
0.208
0.219
0.185
0.173
0.287
0.531
0.326
0.544
0.396
0.530
0.431
0.130
0.175
0.467
0.351
0.483
0.370
0.468
0.352
0.020
0.027
0.041
0.038
0.041
0.042
0.041
0.042
0.010
0.015
0.021
0.021
0.020
0.021
0.021
0.021
0.025
0.058
0.058
0.053
0.058
0.058
0.058
0.058
0.013
0.029
0.029
0.030
0.029
0.030
0.030
0.030
0.032
0.082
0.094
0.077
0.094
0.083
0.094
0.083
0.017
0.041
0.049
0.042
0.049
0.042
0.049
0.042
Symbol
A
B
C
D
A
B
C
D
Output
Fanin Symbol Fanout
1.0
1.0
1.0
1.0
Y
5
2.1
2.0
2.1
2.1
Y
11
x8
Logic Diagram for "Normal"
Logic Diagram for "with inv. A type"
Logic Diagram for "with inv. B type"
Logic Diagram for "with inv. C type"
Logic Diagram for "with inv. D type"
Logic Diagram for "with inv. E type"
Logic Diagram for "with inv. F type"
Logic Diagram for "with inv. G type"
Logic Diagram for "with inv. H type"
D H04
C H03
B H02
N01 Y
A H01
Block Library
A13872EJ5V0BL
2 - 82
Block Library
A13872EJ5V0BL
2 - 83
Chapter 2 Function Block
Function
Block type
Chapter 2 Function Block
2-2-Input AND-NOR
Normal
with inv. A
Drivability
Name
cells
Low Power
L424
2
x1
F424
4
Name
cells
with inv. B
Name
cells
with inv. C
Name
cells
with inv. D
Name
cells
with inv. E
Name
cells
Block
type
L424
IN
Path
→ OUT
A → Y
B → Y
x2
C → Y
x4
D → Y
x8
Block type
with inv. F
with inv. G
with inv. H
Drivability
Name
Name
Name
cells
cells
-
-
-
F424
A → Y
cells
Low Power
B → Y
x1
C → Y
x2
D → Y
x4
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.113
0.084
0.091
0.103
0.162
0.085
0.137
0.104
0.122
0.116
0.123
0.116
0.152
0.106
0.152
0.106
0.170
0.172
0.144
0.204
0.257
0.244
0.232
0.279
0.197
0.228
0.196
0.229
0.255
0.259
0.255
0.260
0.249
0.202
0.218
0.230
0.526
0.459
0.494
0.495
0.362
0.359
0.362
0.360
0.542
0.517
0.540
0.513
0.030
0.033
0.030
0.033
0.030
0.032
0.029
0.032
0.015
0.016
0.015
0.016
0.015
0.016
0.015
0.016
0.040
0.058
0.040
0.058
0.041
0.058
0.041
0.058
0.020
0.029
0.020
0.029
0.020
0.029
0.020
0.029
0.062
0.082
0.061
0.082
0.064
0.083
0.064
0.082
0.031
0.041
0.031
0.041
0.032
0.041
0.032
0.042
Symbol
A
B
C
D
A
B
C
D
Output
Fanin Symbol Fanout
1.0
1.0
1.0
1.0
Y
6
2.1
2.1
2.0
2.0
Y
11
x8
Logic Diagram for "Normal"
Logic Diagram for "with inv. A type"
Logic Diagram for "with inv. B type"
Logic Diagram for "with inv. C type"
Logic Diagram for "with inv. D type"
Logic Diagram for "with inv. E type"
Logic Diagram for "with inv. F type"
Logic Diagram for "with inv. G type"
Logic Diagram for "with inv. H type"
D H04
C H03
N01 Y
B H02
A H01
Block Library
A13872EJ5V0BL
2 - 84
Block Library
A13872EJ5V0BL
2 - 85
Chapter 2 Function Block
Function
Block type
Chapter 2 Function Block
2-2-2-Input AND-NOR
Normal
with inv. A
Drivability
Name
cells
Low Power
L425
3
x1
F425
6
Name
cells
with inv. B
Name
cells
with inv. C
Name
cells
with inv. D
Name
cells
with inv. E
Name
cells
Block
type
L425
IN
Path
→ OUT
A → Y
B → Y
x2
C → Y
x4
D → Y
x8
Block type
with inv. F
with inv. G
with inv. H
Drivability
Name
Name
Name
cells
cells
-
-
-
E → Y
cells
F → Y
Low Power
x1
F425
A → Y
x2
B → Y
x4
x8
C → Y
Logic Diagram for "Normal"
Logic Diagram for "with inv. A type"
Logic Diagram for "with inv. B type"
F H06
D → Y
E → Y
E H05
F → Y
D H04
N01 Y
C H03
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.129
0.109
0.105
0.131
0.181
0.139
0.155
0.163
0.208
0.159
0.179
0.186
0.140
0.154
0.141
0.154
0.189
0.183
0.190
0.184
0.195
0.190
0.196
0.191
0.201
0.271
0.174
0.317
0.281
0.467
0.254
0.519
0.348
0.560
0.319
0.610
0.228
0.326
0.227
0.327
0.318
0.519
0.320
0.519
0.358
0.567
0.359
0.568
0.271
0.200
0.240
0.235
0.547
0.735
0.515
0.783
0.731
1.004
0.695
1.060
0.388
0.372
0.387
0.373
0.674
0.938
0.673
0.934
0.781
1.097
0.782
1.092
0.030
0.044
0.030
0.044
0.029
0.044
0.029
0.044
0.030
0.043
0.030
0.043
0.015
0.022
0.015
0.022
0.015
0.022
0.015
0.022
0.015
0.022
0.015
0.022
0.040
0.086
0.040
0.086
0.041
0.087
0.041
0.086
0.042
0.087
0.042
0.086
0.020
0.043
0.020
0.043
0.021
0.043
0.021
0.044
0.021
0.043
0.021
0.043
0.061
0.121
0.061
0.121
0.064
0.124
0.064
0.123
0.068
0.124
0.068
0.123
0.031
0.061
0.031
0.061
0.033
0.062
0.033
0.062
0.035
0.062
0.035
0.062
Symbol
A
B
C
D
E
F
A
B
C
D
E
F
Output
Fanin Symbol Fanout
1.0
1.0
1.0
1.0
1.0
1.0
Y
2
2.1
2.1
2.1
2.0
2.0
2.1
Y
2
B H02
A H01
Logic Diagram for "with inv. C type"
Logic Diagram for "with inv. D type"
Logic Diagram for "with inv. E type"
Logic Diagram for "with inv. F type"
Logic Diagram for "with inv. G type"
Logic Diagram for "with inv. H type"
Block Library
A13872EJ5V0BL
2 - 86
Block Library
A13872EJ5V0BL
2 - 87
Chapter 2 Function Block
Function
Block type
Chapter 2 Function Block
2-3-Input AND-NOR
Normal
with inv. A
Drivability
Name
cells
Low Power
L427
3
x1
F427
5
Name
cells
with inv. B
Name
cells
with inv. C
Name
cells
with inv. D
Name
cells
with inv. E
Name
cells
Block
type
L427
IN
Path
→ OUT
A → Y
B → Y
x2
C → Y
x4
D → Y
x8
Block type
with inv. F
with inv. G
with inv. H
Drivability
Name
Name
Name
cells
cells
-
-
-
E → Y
cells
F427
Low Power
x1
A → Y
B → Y
x2
C → Y
x4
x8
D → Y
Logic Diagram for "Normal"
Logic Diagram for "with inv. A type"
Logic Diagram for "with inv. B type"
Logic Diagram for "with inv. C type"
Logic Diagram for "with inv. D type"
Logic Diagram for "with inv. E type"
Logic Diagram for "with inv. F type"
Logic Diagram for "with inv. G type"
Logic Diagram for "with inv. H type"
E H05
D H04
C H03
E → Y
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.173
0.088
0.157
0.123
0.158
0.084
0.161
0.126
0.147
0.140
0.157
0.096
0.158
0.096
0.124
0.103
0.135
0.115
0.124
0.102
0.338
0.328
0.327
0.397
0.291
0.264
0.308
0.333
0.295
0.362
0.304
0.328
0.305
0.328
0.200
0.187
0.213
0.207
0.199
0.185
0.803
0.705
0.784
0.762
0.670
0.453
0.682
0.509
0.666
0.536
0.682
0.618
0.682
0.616
0.373
0.244
0.388
0.258
0.373
0.242
0.031
0.028
0.030
0.029
0.041
0.029
0.041
0.032
0.041
0.032
0.015
0.014
0.015
0.014
0.020
0.016
0.020
0.016
0.020
0.016
0.042
0.058
0.042
0.058
0.058
0.058
0.058
0.058
0.058
0.058
0.021
0.029
0.021
0.029
0.029
0.029
0.029
0.029
0.029
0.029
0.065
0.082
0.065
0.082
0.093
0.082
0.093
0.082
0.093
0.082
0.034
0.042
0.034
0.042
0.047
0.041
0.046
0.041
0.046
0.041
Symbol
A
B
C
D
E
A
B
C
D
E
Output
Fanin Symbol Fanout
1.0
1.0
1.0
1.0
1.0
Y
3
2.0
2.0
2.1
2.1
2.1
Y
8
N01 Y
B H02
A H01
Block Library
A13872EJ5V0BL
2 - 88
Block Library
A13872EJ5V0BL
2 - 89
Chapter 2 Function Block
Function
Block type
Chapter 2 Function Block
1-2-2-Input AND-NOR
Normal
with inv. A
Drivability
Name
cells
Low Power
L428
3
x1
F428
5
Name
cells
with inv. B
Name
cells
with inv. C
Name
cells
with inv. D
Name
cells
with inv. E
Name
cells
Block
type
L428
IN
Path
→ OUT
A → Y
B → Y
x2
C → Y
x4
D → Y
x8
Block type
with inv. F
with inv. G
with inv. H
Drivability
Name
Name
Name
cells
cells
-
-
-
E → Y
cells
F428
Low Power
x1
A → Y
B → Y
x2
C → Y
x4
x8
D → Y
Logic Diagram for "Normal"
Logic Diagram for "with inv. A type"
Logic Diagram for "with inv. B type"
Logic Diagram for "with inv. C type"
Logic Diagram for "with inv. D type"
Logic Diagram for "with inv. E type"
Logic Diagram for "with inv. F type"
Logic Diagram for "with inv. G type"
Logic Diagram for "with inv. H type"
E H05
E → Y
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.094
0.093
0.146
0.113
0.133
0.171
0.167
0.145
0.150
0.207
0.084
0.107
0.123
0.142
0.123
0.141
0.137
0.175
0.137
0.175
0.146
0.343
0.241
0.375
0.233
0.457
0.291
0.455
0.279
0.554
0.124
0.197
0.196
0.299
0.197
0.300
0.219
0.405
0.216
0.404
0.184
0.293
0.426
0.596
0.408
0.656
0.512
0.851
0.491
0.929
0.145
0.147
0.314
0.457
0.314
0.455
0.348
0.730
0.347
0.730
0.020
0.038
0.031
0.050
0.031
0.048
0.031
0.048
0.031
0.050
0.010
0.022
0.015
0.027
0.015
0.027
0.016
0.027
0.016
0.027
0.024
0.082
0.042
0.087
0.042
0.082
0.043
0.082
0.043
0.082
0.012
0.043
0.021
0.044
0.021
0.044
0.022
0.044
0.022
0.044
0.032
0.118
0.064
0.123
0.064
0.118
0.069
0.119
0.069
0.118
0.016
0.060
0.033
0.063
0.033
0.063
0.037
0.063
0.037
0.063
Symbol
A
B
C
D
E
A
B
C
D
E
Output
Fanin Symbol Fanout
1.0
1.0
1.0
1.0
1.0
Y
2
2.1
2.0
2.0
2.0
2.0
Y
7
D H04
C H03
N01 Y
B H02
A H01
Block Library
A13872EJ5V0BL
2 - 90
Block Library
A13872EJ5V0BL
2 - 91
Chapter 2 Function Block
Function
Block type
Chapter 2 Function Block
2-2-2-2-Input AND-NOR
Normal
with inv. A
Drivability
Name
cells
Low Power
L429
6
x1
F429
6
Name
cells
with inv. B
Name
cells
with inv. C
Name
cells
with inv. D
Name
cells
with inv. E
Name
cells
Block
type
L429
IN
Path
→ OUT
A → Y
B → Y
x2
C → Y
x4
D → Y
x8
Block type
with inv. F
with inv. G
with inv. H
Drivability
Name
Name
Name
cells
cells
-
-
-
E → Y
cells
Low Power
F → Y
x1
G → Y
x2
H → Y
x4
x8
F429
Logic Diagram for "Normal"
Logic Diagram for "with inv. A type"
Logic Diagram for "with inv. B type"
A → Y
B → Y
H H08
C → Y
G H07
F H06
D → Y
E H05
N01Y
D H04
E → Y
C H03
B H02
F → Y
A H01
G → Y
Logic Diagram for "with inv. C type"
Logic Diagram for "with inv. D type"
Logic Diagram for "with inv. E type"
Logic Diagram for "with inv. F type"
Logic Diagram for "with inv. G type"
Logic Diagram for "with inv. H type"
Block Library
A13872EJ5V0BL
2 - 92
H → Y
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.243
0.256
0.225
0.286
0.301
0.254
0.275
0.284
0.261
0.248
0.242
0.276
0.321
0.244
0.296
0.271
0.256
0.272
0.237
0.304
0.316
0.273
0.290
0.304
0.272
0.261
0.253
0.290
0.332
0.259
0.308
0.288
0.405
0.517
0.380
0.567
0.493
0.592
0.465
0.644
0.432
0.482
0.406
0.524
0.520
0.556
0.494
0.602
0.427
0.547
0.401
0.598
0.515
0.622
0.487
0.674
0.450
0.506
0.424
0.549
0.538
0.579
0.512
0.627
0.712
0.868
0.680
0.908
0.994
1.138
0.961
1.180
0.732
0.782
0.700
0.817
1.023
1.045
0.990
1.080
0.744
0.934
0.712
0.974
1.031
1.203
0.998
1.245
0.760
0.833
0.730
0.869
1.055
1.096
1.022
1.132
0.020
0.021
0.020
0.021
0.020
0.021
0.020
0.021
0.020
0.021
0.020
0.021
0.020
0.021
0.020
0.021
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.024
0.029
0.024
0.029
0.024
0.029
0.024
0.029
0.024
0.029
0.024
0.029
0.025
0.029
0.025
0.029
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.013
0.015
0.012
0.015
0.033
0.042
0.033
0.042
0.033
0.042
0.033
0.042
0.033
0.042
0.033
0.042
0.033
0.042
0.033
0.042
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
Block Library
A13872EJ5V0BL
Symbol
A
B
C
D
E
F
G
H
A
B
C
D
E
F
G
H
Output
Fanin Symbol Fanout
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Y
17
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Y
34
2 - 93
Chapter 2 Function Block
Function
Block type
Chapter 2 Function Block
1-4-Input AND-NOR
Normal
with inv. A
Drivability
Name
cells
Low Power
L440
3
x1
F440
5
Name
cells
with inv. B
Name
cells
with inv. C
Name
cells
with inv. D
Name
cells
with inv. E
Name
cells
Block
type
L440
IN
Path
→ OUT
A → Y
B → Y
x2
C → Y
x4
D → Y
x8
Block type
with inv. F
with inv. G
with inv. H
Drivability
Name
Name
Name
cells
cells
-
-
-
E → Y
cells
F440
Low Power
x1
A → Y
B → Y
x2
C → Y
x4
x8
D → Y
Logic Diagram for "Normal"
Logic Diagram for "with inv. A type"
Logic Diagram for "with inv. B type"
Logic Diagram for "with inv. C type"
Logic Diagram for "with inv. D type"
Logic Diagram for "with inv. E type"
Logic Diagram for "with inv. F type"
Logic Diagram for "with inv. G type"
Logic Diagram for "with inv. H type"
E
D
C
B
A
H05
H04
H03
H02
H01
E → Y
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.081
0.064
0.183
0.073
0.207
0.124
0.206
0.146
0.213
0.181
0.076
0.072
0.185
0.120
0.193
0.127
0.193
0.127
0.185
0.120
0.124
0.279
0.314
0.165
0.360
0.249
0.371
0.279
0.383
0.330
0.110
0.187
0.317
0.228
0.326
0.239
0.327
0.239
0.317
0.228
0.171
0.300
0.854
0.380
0.898
0.470
0.906
0.502
0.919
0.546
0.136
0.181
0.732
0.408
0.743
0.421
0.743
0.421
0.732
0.411
0.020
0.026
0.053
0.038
0.052
0.042
0.053
0.042
0.052
0.043
0.010
0.014
0.026
0.022
0.026
0.021
0.026
0.021
0.026
0.022
0.025
0.058
0.076
0.053
0.076
0.058
0.076
0.058
0.076
0.059
0.013
0.029
0.038
0.030
0.038
0.030
0.038
0.030
0.038
0.030
0.033
0.083
0.127
0.077
0.127
0.083
0.127
0.082
0.127
0.083
0.016
0.041
0.065
0.042
0.065
0.042
0.065
0.042
0.065
0.042
Symbol
A
B
C
D
E
A
B
C
D
E
Output
Fanin Symbol Fanout
1.0
1.0
1.0
1.0
1.0
Y
1
2.1
2.1
2.1
2.1
2.1
Y
4
N01 Y
Block Library
A13872EJ5V0BL
2 - 94
Block Library
A13872EJ5V0BL
2 - 95
Chapter 2 Function Block
Function
Block type
Chapter 2 Function Block
1-5-Input AND-NOR
Normal
with inv. A
Drivability
Name
cells
Low Power
L441
5
x1
F441
7
Name
cells
with inv. B
Name
cells
with inv. C
Name
cells
with inv. D
Name
cells
with inv. E
Name
cells
Block
type
L441
IN
Path
→ OUT
A → Y
B → Y
x2
C → Y
x4
D → Y
x8
Block type
with inv. F
with inv. G
with inv. H
Drivability
Name
Name
Name
cells
cells
-
-
-
E → Y
cells
F → Y
Low Power
x1
F441
A → Y
x2
B → Y
x4
x8
C → Y
Logic Diagram for "Normal"
F
E
D
C
B
A
H06
H05
H04
H03
H02
H01
Logic Diagram for "with inv. A type"
Logic Diagram for "with inv. B type"
D → Y
E → Y
F → Y
N01 Y
Logic Diagram for "with inv. C type"
Logic Diagram for "with inv. D type"
Logic Diagram for "with inv. E type"
Logic Diagram for "with inv. F type"
Logic Diagram for "with inv. G type"
Logic Diagram for "with inv. H type"
Block Library
A13872EJ5V0BL
2 - 96
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.080
0.069
0.270
0.201
0.253
0.225
0.339
0.261
0.332
0.283
0.326
0.304
0.072
0.081
0.289
0.240
0.272
0.264
0.356
0.251
0.350
0.275
0.343
0.298
0.121
0.191
0.445
0.356
0.422
0.383
0.557
0.464
0.551
0.491
0.554
0.517
0.105
0.133
0.464
0.404
0.439
0.433
0.582
0.440
0.579
0.468
0.581
0.497
0.171
0.241
0.905
0.718
0.873
0.738
1.182
0.881
1.176
0.900
1.176
0.921
0.135
0.152
0.873
0.749
0.842
0.769
1.214
0.851
1.208
0.871
1.210
0.891
0.020
0.029
0.031
0.038
0.031
0.038
0.031
0.043
0.031
0.043
0.031
0.043
0.010
0.016
0.015
0.022
0.015
0.022
0.015
0.022
0.015
0.022
0.015
0.022
0.025
0.058
0.042
0.053
0.042
0.053
0.042
0.058
0.042
0.058
0.042
0.058
0.013
0.029
0.021
0.030
0.021
0.030
0.021
0.030
0.021
0.030
0.021
0.030
0.032
0.082
0.065
0.077
0.065
0.077
0.064
0.082
0.064
0.082
0.064
0.082
0.016
0.041
0.033
0.042
0.033
0.042
0.033
0.042
0.033
0.042
0.033
0.042
Block Library
A13872EJ5V0BL
Symbol
A
B
C
D
E
F
A
B
C
D
E
F
Output
Fanin Symbol Fanout
1.0
1.0
1.0
1.0
1.0
1.0
Y
7
2.1
1.0
1.0
1.0
1.0
1.0
Y
16
2 - 97
Chapter 2 Function Block
Function
Block type
Chapter 2 Function Block
4-4-4-Input AND-NOR
Normal
with inv. A
Drivability
Name
cells
Low Power
L444
8
x1
F444
8
Name
cells
with inv. B
Name
cells
with inv. C
Name
cells
with inv. D
Name
cells
with inv. E
Name
cells
Block
type
L444
IN
Path
→ OUT
A → Y
B → Y
x2
C → Y
x4
D → Y
x8
Block type
with inv. F
with inv. G
with inv. H
Drivability
Name
Name
Name
cells
cells
-
-
-
E → Y
cells
Low Power
F → Y
x1
G → Y
x2
H → Y
x4
x8
I → Y
Logic Diagram for "Normal"
L
K
J
I
H12
H11
H10
H09
H
G
F
E
H08
H07
H06
H05
D
C
B
A
H04
H03
H02
H01
Logic Diagram for "with inv. A type"
Logic Diagram for "with inv. B type"
J → Y
K → Y
L → Y
N01 Y
F444
A → Y
B → Y
C → Y
Logic Diagram for "with inv. C type"
Logic Diagram for "with inv. D type"
Logic Diagram for "with inv. E type"
D → Y
E → Y
F → Y
G → Y
H → Y
I → Y
J → Y
Logic Diagram for "with inv. F type"
Logic Diagram for "with inv. G type"
Logic Diagram for "with inv. H type"
K → Y
L → Y
Block Library
A13872EJ5V0BL
2 - 98
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.316
0.197
0.318
0.220
0.327
0.255
0.320
0.265
0.364
0.242
0.366
0.266
0.379
0.301
0.371
0.313
0.576
0.278
0.579
0.300
0.593
0.331
0.584
0.346
0.326
0.207
0.331
0.232
0.340
0.265
0.332
0.277
0.377
0.251
0.380
0.275
0.390
0.312
0.383
0.324
0.588
0.289
0.589
0.313
0.603
0.343
0.593
0.357
0.512
0.361
0.522
0.389
0.549
0.428
0.544
0.442
0.689
0.630
0.701
0.678
0.729
0.759
0.725
0.794
1.051
0.818
1.066
0.866
1.100
0.956
1.091
0.992
0.532
0.377
0.543
0.405
0.571
0.445
0.566
0.460
0.712
0.655
0.725
0.703
0.752
0.785
0.748
0.821
1.071
0.839
1.083
0.889
1.118
0.980
1.109
1.017
1.131
0.755
1.143
0.776
1.171
0.808
1.163
0.821
1.296
0.967
1.310
1.003
1.335
1.063
1.325
1.090
2.671
1.508
2.684
1.567
2.720
1.625
2.710
1.670
1.170
0.798
1.183
0.819
1.210
0.850
1.201
0.866
1.338
1.011
1.352
1.050
1.373
1.109
1.366
1.141
2.709
1.568
2.728
1.601
2.756
1.681
2.748
1.704
0.020
0.022
0.020
0.022
0.020
0.021
0.020
0.021
0.020
0.021
0.020
0.021
0.020
0.021
0.020
0.021
0.020
0.021
0.020
0.021
0.020
0.021
0.020
0.021
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.025
0.030
0.025
0.030
0.025
0.030
0.025
0.029
0.025
0.030
0.025
0.030
0.025
0.030
0.025
0.030
0.025
0.030
0.025
0.030
0.025
0.030
0.025
0.030
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.033
0.042
0.033
0.042
0.033
0.042
0.033
0.042
0.033
0.042
0.033
0.042
0.033
0.042
0.033
0.042
0.033
0.042
0.033
0.042
0.034
0.042
0.034
0.042
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
Block Library
A13872EJ5V0BL
Symbol
A
B
C
D
E
F
G
H
I
J
K
L
A
B
C
D
E
F
G
H
I
J
K
L
Output
Fanin Symbol Fanout
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Y
16
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Y
34
2 - 99
Chapter 2 Function Block
Function
Block type
Chapter 2 Function Block
1-1-1-2-Input AND-NOR
Normal
with inv. A
Drivability
Name
cells
Low Power
L446
4
x1
F446
5
Name
cells
with inv. B
Name
cells
with inv. C
Name
cells
with inv. D
Name
cells
with inv. E
Name
cells
Block
type
L446
IN
Path
→ OUT
A → Y
B → Y
x2
C → Y
x4
D → Y
x8
Block type
with inv. F
with inv. G
with inv. H
Drivability
Name
Name
Name
cells
cells
-
-
-
E → Y
cells
F446
Low Power
x1
A → Y
B → Y
x2
C → Y
x4
x8
D → Y
Logic Diagram for "Normal"
Logic Diagram for "with inv. A type"
Logic Diagram for "with inv. B type"
Logic Diagram for "with inv. C type"
Logic Diagram for "with inv. D type"
Logic Diagram for "with inv. E type"
Logic Diagram for "with inv. F type"
Logic Diagram for "with inv. G type"
Logic Diagram for "with inv. H type"
E H05
D
C
B
A
H04
H03
H02
H01
E → Y
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.184
0.251
0.202
0.239
0.207
0.230
0.289
0.238
0.277
0.314
0.197
0.272
0.214
0.257
0.217
0.242
0.300
0.253
0.287
0.327
0.307
0.415
0.328
0.410
0.356
0.516
0.465
0.424
0.451
0.532
0.324
0.445
0.345
0.440
0.373
0.536
0.481
0.449
0.467
0.552
0.560
0.814
0.595
0.873
0.598
0.842
0.894
0.891
0.872
0.989
0.584
0.877
0.621
0.935
0.622
0.889
0.925
0.940
0.904
1.039
0.020
0.022
0.020
0.022
0.020
0.022
0.020
0.022
0.020
0.022
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.024
0.030
0.024
0.030
0.024
0.030
0.024
0.030
0.024
0.030
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.033
0.042
0.033
0.042
0.033
0.042
0.033
0.042
0.033
0.042
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
Symbol
A
B
C
D
E
A
B
C
D
E
Output
Fanin Symbol Fanout
1.0
1.0
1.0
1.0
1.0
Y
16
1.0
1.0
1.0
1.0
1.0
Y
34
N01 Y
Block Library
A13872EJ5V0BL
2 - 100
Block Library
A13872EJ5V0BL
2 - 101
Chapter 2 Function Block
Function
Block type
Chapter 2 Function Block
1-1-1-3-Input AND-NOR
Normal
with inv. A
Drivability
Name
cells
Low Power
L447
5
x1
F447
5
Name
cells
with inv. B
Name
cells
with inv. C
Name
cells
with inv. D
Name
cells
with inv. E
Name
cells
Block
type
L447
IN
Path
→ OUT
A → Y
B → Y
x2
C → Y
x4
D → Y
x8
Block type
with inv. F
with inv. G
with inv. H
Drivability
Name
Name
Name
cells
cells
-
-
-
E → Y
cells
F → Y
Low Power
x1
F447
A → Y
x2
B → Y
x4
x8
C → Y
Logic Diagram for "Normal"
F
E
D
C
B
A
H06
H05
H04
H03
H02
H01
Logic Diagram for "with inv. A type"
Logic Diagram for "with inv. B type"
D → Y
E → Y
N01 Y
F → Y
Logic Diagram for "with inv. C type"
Logic Diagram for "with inv. D type"
Logic Diagram for "with inv. E type"
Logic Diagram for "with inv. F type"
Logic Diagram for "with inv. G type"
Logic Diagram for "with inv. H type"
Block Library
A13872EJ5V0BL
2 - 102
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.190
0.257
0.207
0.244
0.208
0.225
0.328
0.235
0.332
0.307
0.316
0.335
0.196
0.268
0.212
0.255
0.221
0.241
0.347
0.254
0.351
0.330
0.335
0.359
0.314
0.422
0.335
0.417
0.365
0.564
0.534
0.426
0.548
0.528
0.538
0.568
0.324
0.441
0.344
0.436
0.386
0.596
0.564
0.457
0.579
0.564
0.569
0.604
0.570
0.824
0.605
0.883
0.608
0.890
1.112
0.896
1.125
0.984
1.109
1.028
0.584
0.873
0.621
0.930
0.637
0.954
1.165
0.957
1.181
1.049
1.165
1.093
0.020
0.022
0.020
0.022
0.020
0.022
0.020
0.022
0.020
0.022
0.020
0.022
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.024
0.030
0.024
0.030
0.024
0.030
0.024
0.030
0.024
0.030
0.024
0.030
0.012
0.015
0.012
0.015
0.013
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.033
0.043
0.033
0.043
0.033
0.043
0.033
0.043
0.033
0.043
0.033
0.043
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
Block Library
A13872EJ5V0BL
Symbol
A
B
C
D
E
F
A
B
C
D
E
F
Output
Fanin Symbol Fanout
1.0
1.0
1.0
1.0
1.0
1.0
Y
16
1.0
1.0
1.0
1.0
1.0
1.0
Y
34
2 - 103
Chapter 2 Function Block
Function
Block type
Chapter 2 Function Block
1-1-2-2-Input AND-NOR
Normal
with inv. A
Drivability
Name
cells
Low Power
L448
5
x1
F448
5
Name
cells
with inv. B
Name
cells
with inv. C
Name
cells
with inv. D
Name
cells
with inv. E
Name
cells
Block
type
L448
IN
Path
→ OUT
A → Y
B → Y
x2
C → Y
x4
D → Y
x8
Block type
with inv. F
with inv. G
with inv. H
Drivability
Name
Name
Name
cells
cells
-
-
-
E → Y
cells
F → Y
Low Power
x1
F448
A → Y
x2
B → Y
x4
x8
C → Y
Logic Diagram for "Normal"
Logic Diagram for "with inv. A type"
Logic Diagram for "with inv. B type"
F H06
D → Y
E → Y
E H05
F → Y
D H04
N01 Y
C H03
B H02
A H01
Logic Diagram for "with inv. C type"
Logic Diagram for "with inv. D type"
Logic Diagram for "with inv. E type"
Logic Diagram for "with inv. F type"
Logic Diagram for "with inv. G type"
Logic Diagram for "with inv. H type"
Block Library
A13872EJ5V0BL
2 - 104
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.184
0.253
0.201
0.239
0.262
0.250
0.244
0.279
0.306
0.246
0.282
0.274
0.195
0.267
0.212
0.255
0.283
0.275
0.263
0.303
0.326
0.272
0.301
0.300
0.306
0.416
0.326
0.410
0.435
0.488
0.409
0.532
0.525
0.560
0.498
0.607
0.324
0.440
0.344
0.436
0.465
0.527
0.438
0.573
0.553
0.602
0.527
0.649
0.557
0.815
0.592
0.872
0.738
0.791
0.707
0.825
1.029
1.052
0.996
1.092
0.583
0.872
0.620
0.930
0.785
0.864
0.755
0.899
1.080
1.128
1.046
1.167
0.020
0.022
0.020
0.021
0.020
0.021
0.020
0.021
0.020
0.021
0.020
0.021
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.024
0.029
0.024
0.029
0.025
0.029
0.024
0.029
0.024
0.030
0.024
0.029
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.013
0.015
0.033
0.042
0.033
0.042
0.033
0.042
0.033
0.042
0.033
0.042
0.033
0.042
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
Block Library
A13872EJ5V0BL
Symbol
A
B
C
D
E
F
A
B
C
D
E
F
Output
Fanin Symbol Fanout
1.0
1.0
1.0
1.0
1.0
1.0
Y
17
1.0
1.0
1.0
1.0
1.0
1.0
Y
34
2 - 105
Chapter 2 Function Block
Function
Block type
Drivability
Chapter 2 Function Block
3-3-3-3-Input AND-NOR
Normal
with inv. A
Name
cells
F449
8
Name
cells
with inv. B
Name
cells
with inv. C
Name
cells
with inv. D
Name
cells
with inv. E
Name
cells
Low Power
x1
Block
type
F449
IN
Path
→ OUT
A → Y
B → Y
x2
C → Y
x4
D → Y
x8
Block type
with inv. F
with inv. G
with inv. H
Drivability
Name
Name
Name
cells
cells
-
-
-
E → Y
cells
Low Power
F → Y
x1
G → Y
x2
H → Y
x4
x8
I → Y
Logic Diagram for "Normal"
Logic Diagram for "with inv. A type"
Logic Diagram for "with inv. B type"
L H12
K H11
J H10
J → Y
K → Y
I H09
H H08
G H07
L → Y
N01 Y
F H06
E H05
D H04
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.300
0.243
0.309
0.302
0.293
0.321
0.369
0.266
0.371
0.317
0.353
0.338
0.320
0.234
0.326
0.290
0.312
0.308
0.393
0.250
0.394
0.299
0.379
0.317
0.553
0.662
0.570
0.763
0.559
0.808
0.716
0.775
0.734
0.876
0.722
0.923
0.590
0.608
0.606
0.694
0.594
0.734
0.757
0.717
0.775
0.809
0.762
0.849
1.088
1.155
1.100
1.226
1.087
1.265
1.719
1.521
1.733
1.599
1.716
1.628
1.119
1.018
1.132
1.082
1.117
1.115
1.771
1.380
1.784
1.443
1.767
1.487
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.012
0.015
0.012
0.015
0.012
0.015
0.013
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
Symbol
A
B
C
D
E
F
G
H
I
J
K
L
Output
Fanin Symbol Fanout
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Y
C H03
B H02
A H01
Logic Diagram for "with inv. C type"
Logic Diagram for "with inv. D type"
Logic Diagram for "with inv. E type"
Logic Diagram for "with inv. F type"
Logic Diagram for "with inv. G type"
Logic Diagram for "with inv. H type"
Block Library
A13872EJ5V0BL
2 - 106
Block Library
A13872EJ5V0BL
2 - 107
34
Chapter 2 Function Block
Function
Block type
Chapter 2 Function Block
3-3-3-Input AND-NOR
Normal
with inv. A
Drivability
Name
cells
Low Power
L460
6
x1
F460
7
Name
cells
with inv. B
Name
cells
with inv. C
Name
cells
with inv. D
Name
cells
with inv. E
Name
cells
Block
type
L460
IN
Path
→ OUT
A → Y
B → Y
x2
C → Y
x4
D → Y
x8
Block type
with inv. F
with inv. G
with inv. H
Drivability
Name
Name
Name
cells
cells
-
-
-
E → Y
cells
Low Power
F → Y
x1
G → Y
x2
H → Y
x4
x8
I → Y
Logic Diagram for "Normal"
Logic Diagram for "with inv. A type"
Logic Diagram for "with inv. B type"
I H09
H H08
G H07
F H06
E H05
D H04
F460
A → Y
B → Y
C → Y
N01 Y
D → Y
C H03
B H02
A H01
E → Y
F → Y
Logic Diagram for "with inv. C type"
Logic Diagram for "with inv. D type"
Logic Diagram for "with inv. E type"
G → Y
H → Y
I → Y
Logic Diagram for "with inv. F type"
Logic Diagram for "with inv. G type"
Block Library
A13872EJ5V0BL
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.292
0.201
0.286
0.225
0.281
0.262
0.339
0.241
0.345
0.295
0.329
0.310
0.431
0.245
0.433
0.291
0.417
0.309
0.312
0.219
0.304
0.243
0.302
0.276
0.352
0.253
0.353
0.306
0.338
0.323
0.440
0.258
0.442
0.305
0.427
0.323
0.472
0.362
0.468
0.390
0.470
0.431
0.634
0.650
0.651
0.739
0.639
0.777
0.755
0.721
0.772
0.807
0.760
0.847
0.502
0.390
0.497
0.417
0.501
0.457
0.656
0.678
0.672
0.766
0.659
0.806
0.770
0.742
0.790
0.832
0.778
0.873
0.992
0.754
0.985
0.775
0.986
0.810
1.300
1.157
1.314
1.227
1.299
1.261
1.774
1.409
1.786
1.471
1.771
1.514
1.042
0.813
1.036
0.833
1.038
0.865
1.338
1.214
1.352
1.280
1.336
1.315
1.806
1.453
1.822
1.530
1.805
1.562
0.020
0.022
0.020
0.022
0.020
0.022
0.020
0.022
0.020
0.022
0.020
0.022
0.020
0.022
0.020
0.022
0.020
0.022
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.024
0.030
0.024
0.030
0.024
0.030
0.024
0.030
0.024
0.030
0.024
0.030
0.024
0.030
0.024
0.030
0.024
0.030
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.033
0.042
0.033
0.042
0.033
0.042
0.033
0.042
0.033
0.042
0.033
0.042
0.033
0.042
0.033
0.042
0.033
0.042
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
Symbol
A
B
C
D
E
F
G
H
I
A
B
C
D
E
F
G
H
I
Output
Fanin Symbol Fanout
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Y
16
1.0
1.0
1.0
1.1
1.0
1.0
1.0
1.0
1.0
Y
34
Logic Diagram for "with inv. H type"
2 - 108
Block Library
A13872EJ5V0BL
2 - 109
Chapter 2 Function Block
Function
Block type
Drivability
Chapter 2 Function Block
1-2-3-Input AND-NOR
Normal
with inv. A
Name
cells
F462
6
Name
cells
with inv. B
Name
cells
with inv. C
Name
cells
with inv. D
Name
cells
with inv. E
Name
cells
Low Power
x1
Block
type
F462
IN
Path
→ OUT
A → Y
B → Y
x2
C → Y
x4
D → Y
x8
Block type
with inv. F
with inv. G
with inv. H
Drivability
Name
Name
Name
cells
cells
-
-
-
E → Y
cells
F → Y
Low Power
x1
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.196
0.210
0.208
0.227
0.196
0.209
0.122
0.127
0.123
0.127
0.089
0.112
0.337
0.473
0.354
0.505
0.336
0.471
0.210
0.382
0.211
0.382
0.140
0.320
0.756
0.867
0.772
0.897
0.755
0.864
0.359
0.561
0.359
0.559
0.184
0.324
0.021
0.028
0.021
0.028
0.021
0.028
0.015
0.026
0.015
0.026
0.010
0.021
0.031
0.045
0.031
0.045
0.031
0.045
0.021
0.045
0.020
0.045
0.012
0.044
0.053
0.063
0.053
0.063
0.053
0.063
0.032
0.063
0.032
0.063
0.016
0.062
Symbol
A
B
C
D
E
F
Output
Fanin Symbol Fanout
2.1
2.0
2.1
2.1
2.0
2.1
Y
x2
x4
x8
Logic Diagram for "Normal"
Logic Diagram for "with inv. A type"
Logic Diagram for "with inv. B type"
Logic Diagram for "with inv. C type"
Logic Diagram for "with inv. D type"
Logic Diagram for "with inv. E type"
Logic Diagram for "with inv. F type"
Logic Diagram for "with inv. G type"
Logic Diagram for "with inv. H type"
F H06
E H05
N01 Y
D H04
C H03
B H02
A H01
Block Library
A13872EJ5V0BL
2 - 110
Block Library
A13872EJ5V0BL
2 - 111
1
Chapter 2 Function Block
Function
Block type
Chapter 2 Function Block
1-1-3-Input AND-NOR
Normal
with inv. A
Drivability
Name
cells
Low Power
L463
3
x1
F463
5
Name
cells
with inv. B
Name
cells
with inv. C
Name
cells
with inv. D
Name
cells
with inv. E
Name
cells
Block
type
L463
IN
Path
→ OUT
A → Y
B → Y
x2
C → Y
x4
D → Y
x8
Block type
with inv. F
with inv. G
with inv. H
Drivability
Name
Name
Name
cells
cells
-
-
-
E → Y
cells
F463
Low Power
x1
A → Y
B → Y
x2
C → Y
x4
x8
D → Y
Logic Diagram for "Normal"
Logic Diagram for "with inv. A type"
Logic Diagram for "with inv. B type"
Logic Diagram for "with inv. C type"
Logic Diagram for "with inv. D type"
Logic Diagram for "with inv. E type"
Logic Diagram for "with inv. F type"
Logic Diagram for "with inv. G type"
Logic Diagram for "with inv. H type"
E
D
C
B
A
H05
H04
H03
H02
H01
E → Y
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.091
0.109
0.102
0.101
0.189
0.141
0.183
0.176
0.180
0.239
0.077
0.114
0.090
0.101
0.157
0.189
0.174
0.212
0.158
0.191
0.136
0.327
0.154
0.362
0.311
0.302
0.310
0.354
0.315
0.449
0.127
0.289
0.145
0.319
0.270
0.365
0.289
0.398
0.271
0.368
0.180
0.345
0.213
0.504
0.693
0.641
0.687
0.702
0.687
0.774
0.177
0.330
0.204
0.489
0.586
0.691
0.600
0.722
0.587
0.693
0.020
0.045
0.020
0.045
0.041
0.059
0.041
0.059
0.041
0.059
0.011
0.027
0.010
0.027
0.021
0.034
0.021
0.034
0.021
0.034
0.025
0.082
0.025
0.082
0.060
0.082
0.060
0.082
0.060
0.082
0.012
0.045
0.012
0.046
0.030
0.046
0.030
0.046
0.030
0.046
0.033
0.118
0.033
0.118
0.099
0.119
0.099
0.119
0.099
0.118
0.016
0.064
0.017
0.065
0.051
0.065
0.051
0.064
0.051
0.064
Symbol
A
B
C
D
E
A
B
C
D
E
Output
Fanin Symbol Fanout
1.0
1.0
1.0
1.0
1.0
Y
2
2.1
2.0
2.1
2.1
2.1
Y
6
N01 Y
Block Library
A13872EJ5V0BL
2 - 112
Block Library
A13872EJ5V0BL
2 - 113
Chapter 2 Function Block
Function
Block type
Chapter 2 Function Block
1-1-4-Input AND-NOR
Normal
with inv. A
Drivability
Name
cells
Low Power
L464
5
x1
F464
5
Name
cells
with inv. B
Name
cells
with inv. C
Name
cells
with inv. D
Name
cells
with inv. E
Name
cells
Block
type
L464
IN
Path
→ OUT
A → Y
B → Y
x2
C → Y
x4
D → Y
x8
Block type
with inv. F
with inv. G
with inv. H
Drivability
Name
Name
Name
cells
cells
-
-
-
E → Y
cells
F → Y
Low Power
x1
F464
A → Y
x2
B → Y
x4
x8
C → Y
Logic Diagram for "Normal"
F
E
D
C
B
A
H06
H05
H04
H03
H02
H01
Logic Diagram for "with inv. A type"
Logic Diagram for "with inv. B type"
D → Y
E → Y
F → Y
N01 Y
Logic Diagram for "with inv. C type"
Logic Diagram for "with inv. D type"
Logic Diagram for "with inv. E type"
Logic Diagram for "with inv. F type"
Logic Diagram for "with inv. G type"
Logic Diagram for "with inv. H type"
Block Library
A13872EJ5V0BL
2 - 114
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.184
0.253
0.201
0.239
0.335
0.190
0.337
0.212
0.348
0.241
0.338
0.250
0.198
0.273
0.214
0.258
0.350
0.204
0.352
0.225
0.365
0.256
0.355
0.265
0.306
0.416
0.326
0.410
0.540
0.344
0.552
0.369
0.579
0.401
0.573
0.412
0.326
0.447
0.346
0.441
0.562
0.366
0.573
0.391
0.604
0.424
0.597
0.435
0.558
0.815
0.593
0.872
1.162
0.692
1.176
0.710
1.202
0.737
1.194
0.750
0.586
0.880
0.623
0.938
1.202
0.740
1.216
0.759
1.244
0.789
1.236
0.801
0.020
0.022
0.020
0.021
0.020
0.021
0.020
0.022
0.020
0.022
0.020
0.021
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.024
0.029
0.024
0.029
0.024
0.029
0.024
0.029
0.024
0.030
0.024
0.029
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.033
0.042
0.033
0.042
0.033
0.042
0.033
0.042
0.033
0.042
0.033
0.042
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
Block Library
A13872EJ5V0BL
Symbol
A
B
C
D
E
F
A
B
C
D
E
F
Output
Fanin Symbol Fanout
1.0
1.0
1.0
1.0
1.0
1.0
Y
17
1.0
1.0
1.0
1.0
1.0
1.0
Y
34
2 - 115
Chapter 2 Function Block
Function
Block type
Drivability
Chapter 2 Function Block
1-1-1-1-2-Input AND-NOR
Normal
with inv. A
Name
cells
F465
5
Name
cells
with inv. B
Name
cells
with inv. C
Name
cells
with inv. D
Name
cells
with inv. E
Name
cells
Low Power
x1
Block
type
F465
IN
Path
→ OUT
A → Y
B → Y
x2
C → Y
x4
D → Y
x8
Block type
with inv. F
with inv. G
with inv. H
Drivability
Name
Name
Name
cells
cells
-
-
-
E → Y
cells
F → Y
Low Power
x1
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.213
0.368
0.228
0.372
0.239
0.376
0.217
0.242
0.301
0.254
0.288
0.331
0.348
0.589
0.368
0.619
0.382
0.674
0.374
0.539
0.483
0.451
0.470
0.557
0.603
1.057
0.642
1.223
0.666
1.406
0.623
0.893
0.927
0.946
0.906
1.047
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
Symbol
A
B
C
D
E
F
Output
Fanin Symbol Fanout
1.0
1.0
1.0
1.0
1.0
1.0
Y
x2
x4
x8
Logic Diagram for "Normal"
Logic Diagram for "with inv. A type"
Logic Diagram for "with inv. B type"
Logic Diagram for "with inv. C type"
Logic Diagram for "with inv. D type"
Logic Diagram for "with inv. E type"
Logic Diagram for "with inv. F type"
Logic Diagram for "with inv. G type"
Logic Diagram for "with inv. H type"
F H06
E
D
C
B
A
H05
H04
H03
H02
H01
N01 Y
Block Library
A13872EJ5V0BL
2 - 116
Block Library
A13872EJ5V0BL
2 - 117
34
Chapter 2 Function Block
Function
Block type
Drivability
Chapter 2 Function Block
4-4-4-4-Input AND-NOR
Normal
with inv. A
Name
cells
F466
10
Name
cells
with inv. B
Name
cells
with inv. C
Name
cells
with inv. D
Name
cells
with inv. E
Name
cells
Low Power
x1
Block
type
F466
IN
Path
→ OUT
A → Y
B → Y
x2
C → Y
x4
D → Y
x8
Block type
with inv. F
with inv. G
with inv. H
Drivability
Name
Name
Name
cells
cells
-
-
-
E → Y
cells
Low Power
F → Y
x1
G → Y
x2
H → Y
x4
x8
I → Y
Logic Diagram for "Normal"
Logic Diagram for "with inv. A type"
Logic Diagram for "with inv. B type"
P H16
O H15
N H14
M H13
L H12
K H11
J H10
I H09
H H08
G H07
F H06
E H05
D
C
B
A
J → Y
K → Y
L → Y
N01 Y
M → Y
H04
H03
H02
H01
N → Y
O → Y
Logic Diagram for "with inv. C type"
Logic Diagram for "with inv. D type"
Logic Diagram for "with inv. E type"
Logic Diagram for "with inv. F type"
Logic Diagram for "with inv. G type"
Logic Diagram for "with inv. H type"
Block Library
A13872EJ5V0BL
2 - 118
P → Y
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.367
0.275
0.369
0.301
0.380
0.340
0.374
0.357
0.564
0.320
0.567
0.343
0.580
0.381
0.572
0.397
0.390
0.261
0.392
0.285
0.402
0.321
0.394
0.335
0.597
0.302
0.597
0.326
0.611
0.359
0.602
0.363
0.683
0.744
0.696
0.798
0.723
0.893
0.719
0.935
1.034
0.930
1.048
0.985
1.083
1.087
1.074
1.129
0.731
0.671
0.744
0.720
0.770
0.802
0.767
0.837
1.082
0.865
1.096
0.915
1.130
1.008
1.120
1.030
1.325
1.184
1.338
1.225
1.362
1.295
1.354
1.330
2.639
1.745
2.656
1.803
2.687
1.867
2.678
1.914
1.366
1.033
1.380
1.071
1.402
1.132
1.397
1.163
2.732
1.595
2.746
1.638
2.782
1.710
2.771
1.728
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
Block Library
A13872EJ5V0BL
Symbol
A
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P
Output
Fanin Symbol Fanout
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Y
2 - 119
34
Chapter 2 Function Block
Chapter 2 Function Block
[MEMO]
[MEMO]
Block Library
A13872EJ5V0BL
2 - 120
Block Library
A13872EJ5V0BL
2 - 121
Chapter 2 Function Block
Chapter 2 Function Block
[MEMO]
2.6
OR-NAND
Block Library
A13872EJ5V0BL
2 - 122
Block Library
A13872EJ5V0BL
2 - 123
Chapter 2 Function Block
Function
Block type
Chapter 2 Function Block
1-4-Input OR-NAND
Normal
with inv. A
Drivability
Name
cells
Low Power
L430
4
x1
F430
5
Name
cells
with inv. B
Name
cells
with inv. C
Name
cells
with inv. D
Name
cells
with inv. E
Name
cells
Block
type
L430
IN
Path
→ OUT
A → Y
B → Y
x2
C → Y
x4
D → Y
x8
Block type
with inv. F
with inv. G
with inv. H
Drivability
Name
Name
Name
cells
cells
-
-
-
E → Y
cells
F430
Low Power
x1
A → Y
B → Y
x2
C → Y
x4
x8
D → Y
Logic Diagram for "Normal"
Logic Diagram for "with inv. A type"
Logic Diagram for "with inv. B type"
Logic Diagram for "with inv. C type"
Logic Diagram for "with inv. D type"
Logic Diagram for "with inv. E type"
Logic Diagram for "with inv. F type"
Logic Diagram for "with inv. G type"
Logic Diagram for "with inv. H type"
E
D
C
B
A
H05
H04
H03
H02
H01
E → Y
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.104
0.048
0.192
0.267
0.206
0.253
0.202
0.259
0.217
0.244
0.092
0.057
0.217
0.292
0.234
0.278
0.230
0.282
0.247
0.268
0.139
0.080
0.315
0.437
0.335
0.433
0.332
0.414
0.352
0.408
0.128
0.090
0.360
0.478
0.381
0.474
0.381
0.454
0.402
0.449
0.225
0.140
0.574
0.838
0.608
0.896
0.588
0.761
0.623
0.817
0.215
0.145
0.671
0.931
0.707
0.990
0.686
0.849
0.724
0.905
0.030
0.022
0.030
0.022
0.030
0.022
0.030
0.022
0.030
0.022
0.015
0.011
0.015
0.011
0.015
0.011
0.015
0.011
0.015
0.011
0.040
0.030
0.040
0.030
0.040
0.030
0.040
0.030
0.040
0.030
0.020
0.015
0.020
0.015
0.020
0.015
0.020
0.015
0.020
0.015
0.061
0.042
0.061
0.042
0.061
0.042
0.061
0.042
0.061
0.042
0.031
0.021
0.031
0.021
0.031
0.021
0.031
0.021
0.031
0.021
Symbol
A
B
C
D
E
A
B
C
D
E
Output
Fanin Symbol Fanout
1.0
1.0
1.0
1.0
1.0
Y
13
2.1
1.0
1.0
1.0
1.0
Y
26
N01 Y
Block Library
A13872EJ5V0BL
2 - 124
Block Library
A13872EJ5V0BL
2 - 125
Chapter 2 Function Block
Function
Block type
Chapter 2 Function Block
1-2-Input OR-NAND
Normal
with inv. A
Drivability
Name
cells
Low Power
L431
2
x1
F431
3
Name
cells
with inv. B
Name
cells
with inv. C
Name
cells
with inv. D
Name
cells
with inv. E
Name
cells
Block
type
L431
IN
Path
→ OUT
A → Y
B → Y
x2
C → Y
x4
F431
x8
Block type
with inv. F
with inv. G
with inv. H
Drivability
Name
Name
Name
cells
cells
-
-
-
A → Y
B → Y
cells
C → Y
Low Power
x1
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.097
0.049
0.087
0.121
0.115
0.115
0.095
0.045
0.098
0.108
0.098
0.108
0.204
0.086
0.128
0.173
0.181
0.212
0.166
0.082
0.152
0.178
0.152
0.178
0.388
0.146
0.210
0.225
0.360
0.397
0.323
0.164
0.303
0.326
0.303
0.326
0.024
0.022
0.029
0.042
0.031
0.042
0.013
0.011
0.015
0.018
0.015
0.018
0.042
0.030
0.040
0.058
0.042
0.058
0.021
0.015
0.021
0.026
0.021
0.026
0.065
0.042
0.061
0.082
0.064
0.082
0.032
0.022
0.032
0.039
0.032
0.039
Symbol
A
B
C
A
B
C
Output
Fanin Symbol Fanout
1.0
1.0
1.0
Y
7
2.1
2.0
2.0
Y
14
x2
x4
x8
Logic Diagram for "Normal"
Logic Diagram for "with inv. A type"
Logic Diagram for "with inv. B type"
Logic Diagram for "with inv. C type"
Logic Diagram for "with inv. D type"
Logic Diagram for "with inv. E type"
Logic Diagram for "with inv. F type"
Logic Diagram for "with inv. G type"
Logic Diagram for "with inv. H type"
C H03
B H02
N01 Y
A H01
Block Library
A13872EJ5V0BL
2 - 126
Block Library
A13872EJ5V0BL
2 - 127
Chapter 2 Function Block
Function
Block type
Chapter 2 Function Block
1-1-2-Input OR-NAND
Normal
with inv. A
Drivability
Name
cells
Low Power
L432
2
x1
F432
4
Name
cells
with inv. B
Name
cells
with inv. C
Name
cells
with inv. D
Name
cells
with inv. E
Name
cells
Block
type
L432
IN
Path
→ OUT
A → Y
B → Y
x2
C → Y
x4
D → Y
x8
Block type
with inv. F
with inv. G
with inv. H
Drivability
Name
Name
Name
cells
cells
-
-
-
F432
A → Y
cells
Low Power
B → Y
x1
C → Y
x2
D → Y
x4
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.131
0.055
0.118
0.071
0.123
0.144
0.145
0.125
0.123
0.062
0.122
0.062
0.136
0.138
0.136
0.138
0.258
0.106
0.254
0.124
0.213
0.235
0.250
0.235
0.229
0.112
0.230
0.112
0.231
0.236
0.231
0.236
0.605
0.204
0.600
0.219
0.465
0.390
0.587
0.449
0.523
0.207
0.522
0.207
0.523
0.419
0.523
0.419
0.035
0.022
0.035
0.021
0.041
0.038
0.041
0.038
0.018
0.011
0.018
0.011
0.020
0.019
0.020
0.019
0.058
0.030
0.058
0.030
0.058
0.053
0.058
0.053
0.029
0.015
0.029
0.015
0.029
0.027
0.029
0.027
0.093
0.042
0.093
0.042
0.093
0.077
0.093
0.077
0.047
0.021
0.047
0.021
0.047
0.039
0.047
0.039
Symbol
A
B
C
D
A
B
C
D
Output
Fanin Symbol Fanout
1.0
1.0
1.0
1.0
Y
5
2.1
2.1
2.0
2.0
Y
12
x8
Logic Diagram for "Normal"
Logic Diagram for "with inv. A type"
Logic Diagram for "with inv. B type"
Logic Diagram for "with inv. C type"
Logic Diagram for "with inv. D type"
Logic Diagram for "with inv. E type"
Logic Diagram for "with inv. F type"
Logic Diagram for "with inv. G type"
Logic Diagram for "with inv. H type"
D H04
C H03
B H02
A H01
N01 Y
Block Library
A13872EJ5V0BL
2 - 128
Block Library
A13872EJ5V0BL
2 - 129
Chapter 2 Function Block
Function
Block type
Chapter 2 Function Block
1-3-Input OR-NAND
Normal
with inv. A
Drivability
Name
cells
Low Power
L433
2
x1
F433
4
Name
cells
with inv. B
Name
cells
with inv. C
Name
cells
with inv. D
Name
cells
with inv. E
Name
cells
Block
type
L433
IN
Path
→ OUT
A → Y
B → Y
x2
C → Y
x4
D → Y
x8
Block type
with inv. F
with inv. G
with inv. H
Drivability
Name
Name
Name
cells
cells
-
-
-
F433
A → Y
cells
Low Power
B → Y
x1
C → Y
x2
D → Y
x4
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.093
0.050
0.085
0.136
0.114
0.161
0.119
0.154
0.080
0.039
0.103
0.165
0.116
0.179
0.103
0.166
0.223
0.087
0.127
0.189
0.184
0.295
0.195
0.305
0.187
0.071
0.154
0.270
0.181
0.317
0.154
0.272
0.428
0.146
0.208
0.208
0.367
0.558
0.386
0.617
0.362
0.134
0.268
0.417
0.354
0.572
0.268
0.418
0.023
0.022
0.030
0.057
0.031
0.058
0.031
0.058
0.012
0.011
0.016
0.029
0.015
0.029
0.016
0.029
0.042
0.030
0.040
0.080
0.042
0.081
0.042
0.081
0.021
0.015
0.022
0.041
0.021
0.041
0.022
0.041
0.066
0.042
0.061
0.116
0.065
0.117
0.066
0.117
0.034
0.022
0.034
0.059
0.033
0.059
0.034
0.059
Symbol
A
B
C
D
A
B
C
D
Output
Fanin Symbol Fanout
1.0
1.0
1.0
1.0
Y
4
2.1
2.0
2.1
2.1
Y
7
x8
Logic Diagram for "Normal"
Logic Diagram for "with inv. A type"
Logic Diagram for "with inv. B type"
Logic Diagram for "with inv. C type"
Logic Diagram for "with inv. D type"
Logic Diagram for "with inv. E type"
Logic Diagram for "with inv. F type"
Logic Diagram for "with inv. G type"
Logic Diagram for "with inv. H type"
D H04
C H03
B H02
N01 Y
A H01
Block Library
A13872EJ5V0BL
2 - 130
Block Library
A13872EJ5V0BL
2 - 131
Chapter 2 Function Block
Function
Block type
Chapter 2 Function Block
2-2-Input OR-NAND
Normal
with inv. A
Drivability
Name
cells
Low Power
L434
2
x1
F434
4
Name
cells
with inv. B
Name
cells
with inv. C
Name
cells
with inv. D
Name
cells
with inv. E
Name
cells
Block
type
L434
IN
Path
→ OUT
A → Y
B → Y
x2
C → Y
x4
D → Y
x8
Block type
with inv. F
with inv. G
with inv. H
Drivability
Name
Name
Name
cells
cells
-
-
-
F434
A → Y
cells
Low Power
B → Y
x1
C → Y
x2
D → Y
x4
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.127
0.113
0.141
0.095
0.124
0.151
0.135
0.133
0.114
0.084
0.115
0.084
0.124
0.142
0.124
0.142
0.241
0.193
0.266
0.191
0.231
0.265
0.259
0.264
0.210
0.154
0.210
0.154
0.217
0.263
0.217
0.263
0.479
0.351
0.558
0.408
0.454
0.419
0.535
0.479
0.443
0.346
0.444
0.346
0.434
0.446
0.434
0.446
0.025
0.038
0.025
0.038
0.023
0.037
0.023
0.037
0.013
0.019
0.013
0.019
0.012
0.019
0.012
0.019
0.041
0.053
0.041
0.053
0.041
0.053
0.041
0.053
0.021
0.027
0.021
0.027
0.021
0.027
0.021
0.027
0.063
0.078
0.063
0.078
0.063
0.077
0.063
0.077
0.032
0.039
0.032
0.039
0.032
0.039
0.032
0.039
Symbol
A
B
C
D
A
B
C
D
Output
Fanin Symbol Fanout
1.0
1.0
1.0
1.0
Y
5
2.0
2.0
2.0
2.0
Y
11
x8
Logic Diagram for "Normal"
Logic Diagram for "with inv. A type"
Logic Diagram for "with inv. B type"
Logic Diagram for "with inv. C type"
Logic Diagram for "with inv. D type"
Logic Diagram for "with inv. E type"
Logic Diagram for "with inv. F type"
Logic Diagram for "with inv. G type"
Logic Diagram for "with inv. H type"
D H04
C H03
N01 Y
B H02
A H01
Block Library
A13872EJ5V0BL
2 - 132
Block Library
A13872EJ5V0BL
2 - 133
Chapter 2 Function Block
Function
Block type
Drivability
Chapter 2 Function Block
2-3-Input OR-NAND
Normal
with inv. A
Name
cells
F435
5
Name
cells
with inv. B
Name
cells
with inv. C
Name
cells
with inv. D
Name
cells
with inv. E
Name
cells
Low Power
x1
Block
type
F435
IN
Path
→ OUT
A → Y
B → Y
x2
C → Y
x4
D → Y
x8
Block type
with inv. F
with inv. G
with inv. H
Drivability
Name
Name
Name
cells
cells
-
-
-
cells
E → Y
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.104
0.081
0.104
0.081
0.130
0.219
0.138
0.234
0.130
0.219
0.214
0.141
0.214
0.141
0.226
0.404
0.254
0.451
0.226
0.405
0.430
0.299
0.429
0.300
0.425
0.623
0.512
0.780
0.425
0.625
0.012
0.019
0.012
0.019
0.012
0.029
0.012
0.029
0.012
0.029
0.021
0.027
0.021
0.027
0.021
0.041
0.021
0.041
0.021
0.041
0.033
0.039
0.033
0.039
0.033
0.059
0.033
0.059
0.033
0.059
Symbol
A
B
C
D
E
Output
Fanin Symbol Fanout
2.1
2.1
2.1
2.1
2.1
Y
Low Power
x1
x2
x4
x8
Logic Diagram for "Normal"
Logic Diagram for "with inv. A type"
Logic Diagram for "with inv. B type"
Logic Diagram for "with inv. C type"
Logic Diagram for "with inv. D type"
Logic Diagram for "with inv. E type"
Logic Diagram for "with inv. F type"
Logic Diagram for "with inv. G type"
Logic Diagram for "with inv. H type"
E H05
D H04
C H03
N01 Y
B H02
A H01
Block Library
A13872EJ5V0BL
2 - 134
Block Library
A13872EJ5V0BL
2 - 135
4
Chapter 2 Function Block
Function
Block type
Chapter 2 Function Block
3-3-Input OR-NAND
Normal
with inv. A
Drivability
Name
cells
Low Power
L436
3
x1
F436
6
Name
cells
with inv. B
Name
cells
with inv. C
Name
cells
with inv. D
Name
cells
with inv. E
Name
cells
Block
type
L436
IN
Path
→ OUT
A → Y
B → Y
x2
C → Y
x4
D → Y
x8
Block type
with inv. F
with inv. G
with inv. H
Drivability
Name
Name
Name
cells
cells
-
-
-
E → Y
cells
F → Y
Low Power
x1
F436
A → Y
x2
B → Y
x4
x8
C → Y
Logic Diagram for "Normal"
Logic Diagram for "with inv. A type"
Logic Diagram for "with inv. B type"
F H06
E H05
D H04
D → Y
E → Y
N01 Y
F → Y
C H03
B H02
A H01
Logic Diagram for "with inv. C type"
Logic Diagram for "with inv. D type"
Logic Diagram for "with inv. E type"
Logic Diagram for "with inv. F type"
Logic Diagram for "with inv. G type"
Logic Diagram for "with inv. H type"
Block Library
A13872EJ5V0BL
2 - 136
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.099
0.106
0.124
0.130
0.128
0.123
0.126
0.209
0.147
0.236
0.152
0.228
0.103
0.116
0.117
0.128
0.105
0.115
0.142
0.248
0.150
0.264
0.142
0.249
0.241
0.167
0.304
0.270
0.325
0.280
0.253
0.394
0.325
0.504
0.345
0.516
0.253
0.209
0.276
0.251
0.253
0.208
0.283
0.484
0.311
0.530
0.283
0.484
0.446
0.192
0.670
0.533
0.721
0.595
0.442
0.402
0.668
0.762
0.724
0.826
0.518
0.381
0.606
0.530
0.518
0.380
0.529
0.645
0.618
0.801
0.530
0.647
0.023
0.057
0.023
0.058
0.023
0.058
0.021
0.058
0.021
0.058
0.021
0.058
0.012
0.029
0.012
0.029
0.012
0.029
0.011
0.029
0.011
0.029
0.011
0.029
0.042
0.082
0.042
0.082
0.043
0.082
0.042
0.081
0.042
0.082
0.042
0.082
0.022
0.041
0.022
0.042
0.022
0.041
0.021
0.041
0.021
0.041
0.021
0.041
0.066
0.119
0.066
0.119
0.067
0.119
0.066
0.119
0.066
0.119
0.066
0.119
0.034
0.061
0.034
0.060
0.034
0.060
0.034
0.060
0.034
0.060
0.034
0.060
Block Library
A13872EJ5V0BL
Symbol
A
B
C
D
E
F
A
B
C
D
E
F
Output
Fanin Symbol Fanout
1.0
1.0
1.0
1.0
1.0
1.0
Y
1
2.1
2.1
2.1
2.1
2.1
2.1
Y
3
2 - 137
Chapter 2 Function Block
Function
Block type
Drivability
Chapter 2 Function Block
1-2-2-Input OR-NAND
Normal
with inv. A
Name
cells
F437
5
Name
cells
with inv. B
Name
cells
with inv. C
Name
cells
with inv. D
Name
cells
with inv. E
Name
cells
Low Power
x1
Block
type
F437
IN
Path
→ OUT
A → Y
B → Y
x2
C → Y
x4
D → Y
x8
Block type
with inv. F
with inv. G
with inv. H
Drivability
Name
Name
Name
cells
cells
-
-
-
cells
E → Y
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.138
0.066
0.148
0.129
0.148
0.129
0.171
0.178
0.171
0.178
0.296
0.123
0.306
0.234
0.306
0.234
0.333
0.326
0.333
0.326
0.721
0.243
0.735
0.467
0.735
0.467
0.750
0.556
0.750
0.556
0.016
0.011
0.018
0.019
0.018
0.019
0.018
0.019
0.018
0.019
0.030
0.015
0.030
0.027
0.030
0.027
0.030
0.027
0.030
0.027
0.048
0.022
0.048
0.039
0.048
0.039
0.048
0.039
0.048
0.039
Symbol
A
B
C
D
E
Output
Fanin Symbol Fanout
2.1
2.0
2.0
2.0
2.0
Y
Low Power
x1
x2
x4
x8
Logic Diagram for "Normal"
Logic Diagram for "with inv. A type"
Logic Diagram for "with inv. B type"
Logic Diagram for "with inv. C type"
Logic Diagram for "with inv. D type"
Logic Diagram for "with inv. E type"
Logic Diagram for "with inv. F type"
Logic Diagram for "with inv. G type"
Logic Diagram for "with inv. H type"
E H05
D H04
C H03
N01 Y
B H02
A H01
Block Library
A13872EJ5V0BL
2 - 138
Block Library
A13872EJ5V0BL
2 - 139
8
Chapter 2 Function Block
Function
Block type
Drivability
Chapter 2 Function Block
2-2-2-Input OR-NAND
Normal
with inv. A
Name
cells
F438
6
Name
cells
with inv. B
Name
cells
with inv. C
Name
cells
with inv. D
Name
cells
with inv. E
Name
cells
Low Power
x1
Block
type
F438
IN
Path
→ OUT
A → Y
B → Y
x2
C → Y
x4
D → Y
x8
Block type
with inv. F
with inv. G
with inv. H
Drivability
Name
Name
Name
cells
cells
-
-
-
E → Y
cells
F → Y
Low Power
x1
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.169
0.127
0.169
0.127
0.174
0.165
0.175
0.165
0.185
0.215
0.185
0.215
0.379
0.240
0.379
0.240
0.398
0.317
0.399
0.316
0.421
0.422
0.421
0.422
0.932
0.511
0.932
0.511
0.934
0.577
0.937
0.577
0.956
0.678
0.956
0.678
0.015
0.019
0.015
0.019
0.014
0.019
0.014
0.019
0.014
0.019
0.014
0.019
0.030
0.027
0.030
0.027
0.029
0.027
0.029
0.027
0.030
0.027
0.030
0.027
0.047
0.039
0.047
0.039
0.047
0.039
0.047
0.039
0.047
0.039
0.047
0.039
Symbol
A
B
C
D
E
F
Output
Fanin Symbol Fanout
2.1
2.1
2.0
2.0
2.0
2.0
Y
x2
x4
x8
Logic Diagram for "Normal"
Logic Diagram for "with inv. A type"
Logic Diagram for "with inv. B type"
Logic Diagram for "with inv. C type"
Logic Diagram for "with inv. D type"
Logic Diagram for "with inv. E type"
Logic Diagram for "with inv. F type"
Logic Diagram for "with inv. G type"
Logic Diagram for "with inv. H type"
F H06
E H05
D H04
N01 Y
C H03
B H02
A H01
Block Library
A13872EJ5V0BL
2 - 140
Block Library
A13872EJ5V0BL
2 - 141
4
Chapter 2 Function Block
Function
Block type
Chapter 2 Function Block
1-5-Input OR-NAND
Normal
with inv. A
Drivability
Name
cells
Low Power
L439
5
x1
F439
6
Name
cells
with inv. B
Name
cells
with inv. C
Name
cells
with inv. D
Name
cells
with inv. E
Name
cells
Block
type
L439
IN
Path
→ OUT
A → Y
B → Y
x2
C → Y
x4
D → Y
x8
Block type
with inv. F
with inv. G
with inv. H
Drivability
Name
Name
Name
cells
cells
-
-
-
E → Y
cells
F → Y
Low Power
x1
F439
A → Y
x2
B → Y
x4
x8
C → Y
Logic Diagram for "Normal"
F
E
D
C
B
A
H06
H05
H04
H03
H02
H01
Logic Diagram for "with inv. A type"
Logic Diagram for "with inv. B type"
D → Y
E → Y
F → Y
N01 Y
Logic Diagram for "with inv. C type"
Logic Diagram for "with inv. D type"
Logic Diagram for "with inv. E type"
Logic Diagram for "with inv. F type"
Logic Diagram for "with inv. G type"
Logic Diagram for "with inv. H type"
Block Library
A13872EJ5V0BL
2 - 142
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.104
0.048
0.189
0.266
0.206
0.252
0.221
0.345
0.237
0.348
0.246
0.350
0.094
0.057
0.213
0.285
0.230
0.273
0.247
0.374
0.262
0.377
0.273
0.380
0.139
0.080
0.315
0.435
0.335
0.430
0.359
0.536
0.379
0.565
0.393
0.619
0.129
0.090
0.358
0.470
0.378
0.466
0.404
0.582
0.426
0.612
0.439
0.665
0.225
0.139
0.575
0.833
0.609
0.892
0.610
0.898
0.649
1.058
0.666
1.240
0.215
0.145
0.667
0.918
0.703
0.977
0.702
0.994
0.743
1.153
0.767
1.335
0.030
0.022
0.030
0.022
0.030
0.022
0.030
0.022
0.030
0.022
0.030
0.022
0.015
0.011
0.015
0.011
0.015
0.011
0.015
0.011
0.015
0.011
0.015
0.011
0.040
0.030
0.041
0.030
0.041
0.030
0.040
0.030
0.040
0.030
0.040
0.030
0.020
0.015
0.020
0.015
0.020
0.015
0.020
0.015
0.020
0.015
0.020
0.015
0.061
0.042
0.061
0.042
0.061
0.042
0.061
0.042
0.061
0.042
0.061
0.042
0.031
0.021
0.031
0.021
0.031
0.021
0.031
0.021
0.031
0.021
0.031
0.021
Block Library
A13872EJ5V0BL
Symbol
A
B
C
D
E
F
A
B
C
D
E
F
Output
Fanin Symbol Fanout
1.0
1.0
1.0
1.0
1.0
1.0
Y
13
2.1
1.0
1.0
1.0
1.0
1.0
Y
26
2 - 143
Chapter 2 Function Block
Function
Block type
Chapter 2 Function Block
2-4-Input OR-NAND
Normal
with inv. A
Drivability
Name
cells
Low Power
L450
5
x1
F450
6
Name
cells
with inv. B
Name
cells
with inv. C
Name
cells
with inv. D
Name
cells
with inv. E
Name
cells
Block
type
L450
IN
Path
→ OUT
A → Y
B → Y
x2
C → Y
x4
D → Y
x8
Block type
with inv. F
with inv. G
with inv. H
Drivability
Name
Name
Name
cells
cells
-
-
-
E → Y
cells
F → Y
Low Power
x1
F450
A → Y
x2
B → Y
x4
x8
C → Y
Logic Diagram for "Normal"
F
E
D
C
Logic Diagram for "with inv. A type"
Logic Diagram for "with inv. B type"
H06
H05
H04
H03
D → Y
E → Y
F → Y
N01 Y
B H02
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.115
0.112
0.085
0.119
0.190
0.256
0.206
0.243
0.210
0.255
0.227
0.240
0.098
0.107
0.098
0.107
0.214
0.282
0.230
0.267
0.228
0.271
0.244
0.257
0.184
0.211
0.129
0.171
0.392
0.426
0.412
0.421
0.420
0.413
0.441
0.408
0.158
0.178
0.158
0.178
0.392
0.468
0.412
0.464
0.414
0.443
0.435
0.437
0.366
0.393
0.214
0.222
0.800
0.826
0.835
0.885
0.822
0.764
0.859
0.822
0.317
0.323
0.317
0.323
0.801
0.942
0.838
1.000
0.817
0.858
0.855
0.915
0.031
0.042
0.030
0.042
0.024
0.022
0.024
0.022
0.024
0.022
0.024
0.022
0.015
0.019
0.015
0.019
0.013
0.011
0.013
0.011
0.013
0.011
0.013
0.011
0.042
0.058
0.040
0.058
0.042
0.030
0.042
0.030
0.042
0.030
0.042
0.030
0.021
0.027
0.021
0.027
0.021
0.016
0.021
0.016
0.021
0.016
0.021
0.016
0.065
0.082
0.062
0.082
0.065
0.043
0.065
0.043
0.064
0.043
0.065
0.043
0.032
0.039
0.032
0.039
0.032
0.022
0.032
0.022
0.032
0.022
0.032
0.022
Symbol
A
B
C
D
E
F
A
B
C
D
E
F
Output
Fanin Symbol Fanout
1.0
1.0
1.0
1.0
1.0
1.0
Y
7
2.0
2.0
1.0
1.0
1.0
1.0
Y
14
A H01
Logic Diagram for "with inv. C type"
Logic Diagram for "with inv. D type"
Logic Diagram for "with inv. E type"
Logic Diagram for "with inv. F type"
Logic Diagram for "with inv. G type"
Logic Diagram for "with inv. H type"
Block Library
A13872EJ5V0BL
2 - 144
Block Library
A13872EJ5V0BL
2 - 145
Chapter 2 Function Block
Function
Block type
Chapter 2 Function Block
4-4-Input OR-NAND
Normal
with inv. A
Drivability
Name
cells
Low Power
L451
7
x1
F451
8
Name
cells
with inv. B
Name
cells
with inv. C
Name
cells
with inv. D
Name
cells
with inv. E
Name
cells
Block
type
L451
IN
Path
→ OUT
A → Y
B → Y
x2
C → Y
x4
D → Y
x8
Block type
with inv. F
with inv. G
with inv. H
Drivability
Name
Name
Name
cells
cells
-
-
-
E → Y
cells
Low Power
F → Y
x1
G → Y
x2
H → Y
x4
x8
F451
Logic Diagram for "Normal"
H
G
F
E
H08
H07
H06
H05
D
C
B
A
H04
H03
H02
H01
Logic Diagram for "with inv. A type"
Logic Diagram for "with inv. B type"
A → Y
B → Y
C → Y
D → Y
N01 Y
E → Y
F → Y
G → Y
Logic Diagram for "with inv. C type"
Logic Diagram for "with inv. D type"
Logic Diagram for "with inv. E type"
Logic Diagram for "with inv. F type"
Logic Diagram for "with inv. G type"
Logic Diagram for "with inv. H type"
Block Library
A13872EJ5V0BL
2 - 146
H → Y
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.188
0.250
0.205
0.237
0.208
0.250
0.226
0.234
0.192
0.266
0.206
0.252
0.205
0.261
0.221
0.245
0.218
0.293
0.235
0.279
0.235
0.289
0.253
0.272
0.220
0.295
0.237
0.280
0.234
0.285
0.250
0.270
0.320
0.412
0.341
0.408
0.348
0.400
0.368
0.395
0.319
0.436
0.339
0.432
0.336
0.418
0.358
0.412
0.367
0.481
0.386
0.476
0.388
0.462
0.411
0.456
0.366
0.482
0.387
0.478
0.387
0.457
0.408
0.452
0.614
0.807
0.649
0.866
0.636
0.746
0.673
0.803
0.580
0.837
0.614
0.895
0.596
0.766
0.631
0.822
0.679
0.935
0.715
0.991
0.698
0.859
0.737
0.917
0.680
0.936
0.716
0.995
0.696
0.855
0.733
0.911
0.030
0.022
0.030
0.022
0.030
0.022
0.030
0.022
0.030
0.022
0.030
0.022
0.030
0.022
0.030
0.022
0.015
0.011
0.015
0.011
0.015
0.011
0.015
0.011
0.015
0.011
0.015
0.011
0.015
0.011
0.015
0.011
0.041
0.030
0.041
0.030
0.040
0.030
0.040
0.030
0.041
0.030
0.041
0.030
0.041
0.030
0.040
0.030
0.020
0.015
0.020
0.015
0.020
0.015
0.020
0.015
0.020
0.015
0.020
0.015
0.020
0.015
0.020
0.015
0.062
0.042
0.062
0.042
0.062
0.042
0.062
0.042
0.062
0.042
0.062
0.042
0.062
0.042
0.062
0.042
0.031
0.021
0.031
0.021
0.031
0.021
0.031
0.021
0.031
0.021
0.031
0.021
0.031
0.021
0.031
0.021
Block Library
A13872EJ5V0BL
Symbol
A
B
C
D
E
F
G
H
A
B
C
D
E
F
G
H
Output
Fanin Symbol Fanout
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Y
13
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Y
27
2 - 147
Chapter 2 Function Block
Function
Block type
Chapter 2 Function Block
1-1-3-Input OR-NAND
Normal
with inv. A
Drivability
Name
cells
Low Power
L452
4
x1
F452
5
Name
cells
with inv. B
Name
cells
with inv. C
Name
cells
with inv. D
Name
cells
with inv. E
Name
cells
Block
type
L452
IN
Path
→ OUT
A → Y
B → Y
x2
C → Y
x4
D → Y
x8
Block type
with inv. F
with inv. G
with inv. H
Drivability
Name
Name
Name
cells
cells
-
-
-
E → Y
cells
F452
Low Power
x1
A → Y
B → Y
x2
C → Y
x4
x8
D → Y
Logic Diagram for "Normal"
Logic Diagram for "with inv. A type"
Logic Diagram for "with inv. B type"
Logic Diagram for "with inv. C type"
Logic Diagram for "with inv. D type"
Logic Diagram for "with inv. E type"
Logic Diagram for "with inv. F type"
Logic Diagram for "with inv. G type"
Logic Diagram for "with inv. H type"
E
D
C
B
A
H05
H04
H03
H02
H01
E → Y
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.239
0.179
0.253
0.173
0.259
0.337
0.294
0.356
0.301
0.349
0.268
0.187
0.277
0.179
0.284
0.353
0.316
0.372
0.323
0.365
0.390
0.293
0.544
0.324
0.446
0.530
0.502
0.627
0.514
0.637
0.431
0.300
0.581
0.336
0.482
0.551
0.540
0.647
0.550
0.658
0.712
0.539
1.109
0.620
0.874
0.854
1.039
1.209
1.067
1.270
0.780
0.552
1.172
0.643
0.937
0.887
1.102
1.243
1.132
1.305
0.020
0.022
0.020
0.022
0.020
0.021
0.020
0.022
0.020
0.022
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.025
0.030
0.025
0.030
0.025
0.029
0.025
0.029
0.025
0.029
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.034
0.042
0.034
0.042
0.034
0.042
0.034
0.042
0.034
0.042
0.018
0.021
0.018
0.021
0.018
0.021
0.018
0.021
0.018
0.021
Symbol
A
B
C
D
E
A
B
C
D
E
Output
Fanin Symbol Fanout
1.0
1.0
1.0
1.0
1.0
Y
17
1.0
1.0
1.0
1.0
1.0
Y
34
N01 Y
Block Library
A13872EJ5V0BL
2 - 148
Block Library
A13872EJ5V0BL
2 - 149
Chapter 2 Function Block
Function
Block type
Chapter 2 Function Block
1-1-4-Input OR-NAND
Normal
with inv. A
Drivability
Name
cells
Low Power
L453
5
x1
F453
6
Name
cells
with inv. B
Name
cells
with inv. C
Name
cells
with inv. D
Name
cells
with inv. E
Name
cells
Block
type
L453
IN
Path
→ OUT
A → Y
B → Y
x2
C → Y
x4
D → Y
x8
Block type
with inv. F
with inv. G
with inv. H
Drivability
Name
Name
Name
cells
cells
-
-
-
E → Y
cells
F → Y
Low Power
x1
F453
A → Y
x2
B → Y
x4
x8
C → Y
Logic Diagram for "Normal"
F
E
D
C
B
A
H06
H05
H04
H03
H02
H01
Logic Diagram for "with inv. A type"
Logic Diagram for "with inv. B type"
D → Y
E → Y
F → Y
N01 Y
Logic Diagram for "with inv. C type"
Logic Diagram for "with inv. D type"
Logic Diagram for "with inv. E type"
Logic Diagram for "with inv. F type"
Logic Diagram for "with inv. G type"
Logic Diagram for "with inv. H type"
Block Library
A13872EJ5V0BL
2 - 150
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.168
0.069
0.159
0.084
0.277
0.312
0.291
0.298
0.284
0.302
0.300
0.288
0.111
0.061
0.121
0.071
0.235
0.302
0.251
0.287
0.249
0.292
0.266
0.278
0.272
0.129
0.273
0.146
0.488
0.520
0.508
0.514
0.499
0.494
0.522
0.488
0.165
0.104
0.177
0.118
0.400
0.496
0.421
0.492
0.420
0.473
0.442
0.467
0.659
0.267
0.653
0.279
1.039
1.003
1.072
1.062
1.049
0.924
1.083
0.981
0.346
0.184
0.359
0.193
0.808
0.973
0.843
1.031
0.823
0.892
0.860
0.949
0.041
0.022
0.041
0.021
0.041
0.022
0.041
0.022
0.041
0.022
0.041
0.022
0.020
0.011
0.020
0.011
0.021
0.011
0.021
0.011
0.021
0.011
0.021
0.011
0.058
0.030
0.058
0.029
0.058
0.030
0.058
0.030
0.058
0.030
0.058
0.030
0.029
0.015
0.029
0.015
0.029
0.016
0.029
0.016
0.029
0.015
0.029
0.015
0.093
0.042
0.093
0.042
0.093
0.042
0.093
0.042
0.093
0.042
0.093
0.042
0.047
0.021
0.047
0.021
0.047
0.022
0.047
0.022
0.047
0.022
0.047
0.022
Block Library
A13872EJ5V0BL
Symbol
A
B
C
D
E
F
A
B
C
D
E
F
Output
Fanin Symbol Fanout
1.0
1.0
1.0
1.0
1.0
1.0
Y
5
2.1
2.1
1.0
1.0
1.0
1.0
Y
15
2 - 151
Chapter 2 Function Block
Function
Block type
Drivability
Chapter 2 Function Block
4-4-4-Input OR-NAND
Normal
with inv. A
Name
cells
F457
10
Name
cells
with inv. B
Name
cells
with inv. C
Name
cells
with inv. D
Name
cells
with inv. E
Name
cells
Low Power
x1
Block
type
F457
IN
Path
→ OUT
A → Y
B → Y
x2
C → Y
x4
D → Y
x8
Block type
with inv. F
with inv. G
with inv. H
Drivability
Name
Name
Name
cells
cells
-
-
-
E → Y
cells
Low Power
F → Y
x1
G → Y
x2
H → Y
x4
x8
I → Y
Logic Diagram for "Normal"
L
K
J
I
H12
H11
H10
H09
H
G
F
E
H08
H07
H06
H05
D
C
B
A
H04
H03
H02
H01
Logic Diagram for "with inv. A type"
Logic Diagram for "with inv. B type"
J → Y
K → Y
L → Y
N01
Y
Logic Diagram for "with inv. C type"
Logic Diagram for "with inv. D type"
Logic Diagram for "with inv. E type"
Logic Diagram for "with inv. F type"
Logic Diagram for "with inv. G type"
Logic Diagram for "with inv. H type"
Block Library
A13872EJ5V0BL
2 - 152
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.358
0.333
0.373
0.318
0.381
0.317
0.398
0.304
0.401
0.367
0.415
0.350
0.431
0.353
0.443
0.336
0.445
0.391
0.456
0.375
0.466
0.364
0.478
0.350
0.582
0.559
0.602
0.554
0.617
0.525
0.639
0.518
0.912
0.649
0.927
0.645
0.969
0.617
0.986
0.611
1.022
0.737
1.036
0.732
1.070
0.684
1.087
0.680
0.981
1.100
1.019
1.157
1.008
0.998
1.047
1.055
1.595
1.341
1.622
1.399
1.642
1.235
1.671
1.293
1.885
1.581
1.914
1.637
1.922
1.443
1.954
1.498
0.011
0.011
0.011
0.011
0.011
0.011
0.011
0.011
0.011
0.011
0.011
0.011
0.011
0.011
0.011
0.011
0.011
0.011
0.011
0.011
0.011
0.011
0.011
0.011
0.014
0.015
0.014
0.015
0.014
0.015
0.014
0.015
0.015
0.015
0.015
0.015
0.016
0.015
0.016
0.015
0.015
0.016
0.015
0.016
0.016
0.016
0.016
0.016
0.020
0.022
0.020
0.022
0.020
0.022
0.020
0.022
0.022
0.022
0.022
0.022
0.022
0.022
0.022
0.022
0.022
0.023
0.022
0.023
0.022
0.023
0.022
0.023
Block Library
A13872EJ5V0BL
Symbol
A
B
C
D
E
F
G
H
I
J
K
L
Output
Fanin Symbol Fanout
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Y
2 - 153
31
Chapter 2 Function Block
Function
Block type
Chapter 2 Function Block
1-1-1-2-Input OR-NAND
Normal
with inv. A
Drivability
Name
cells
Low Power
L458
3
x1
F458
5
Name
cells
with inv. B
Name
cells
with inv. C
Name
cells
with inv. D
Name
cells
with inv. E
Name
cells
Block
type
L458
IN
Path
→ OUT
A → Y
B → Y
x2
C → Y
x4
D → Y
x8
Block type
with inv. F
with inv. G
with inv. H
Drivability
Name
Name
Name
cells
cells
-
-
-
E → Y
cells
F458
Low Power
x1
A → Y
B → Y
x2
C → Y
x4
x8
D → Y
Logic Diagram for "Normal"
Logic Diagram for "with inv. A type"
Logic Diagram for "with inv. B type"
Logic Diagram for "with inv. C type"
Logic Diagram for "with inv. D type"
Logic Diagram for "with inv. E type"
Logic Diagram for "with inv. F type"
Logic Diagram for "with inv. G type"
Logic Diagram for "with inv. H type"
E H05
D
C
B
A
H04
H03
H02
H01
E → Y
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.137
0.053
0.135
0.068
0.141
0.089
0.163
0.185
0.219
0.182
0.160
0.057
0.168
0.080
0.160
0.093
0.199
0.166
0.197
0.166
0.348
0.104
0.362
0.122
0.396
0.155
0.280
0.290
0.404
0.338
0.297
0.114
0.329
0.144
0.341
0.159
0.356
0.292
0.356
0.292
0.950
0.205
0.965
0.219
1.001
0.246
0.600
0.421
1.000
0.600
0.780
0.234
0.815
0.257
0.829
0.275
0.849
0.521
0.849
0.521
0.046
0.022
0.046
0.022
0.046
0.022
0.051
0.042
0.053
0.043
0.025
0.011
0.025
0.011
0.025
0.011
0.027
0.019
0.027
0.019
0.076
0.030
0.076
0.030
0.076
0.030
0.075
0.058
0.076
0.059
0.039
0.015
0.039
0.015
0.039
0.015
0.039
0.027
0.039
0.027
0.126
0.042
0.126
0.042
0.126
0.042
0.123
0.083
0.126
0.082
0.064
0.021
0.064
0.021
0.064
0.021
0.064
0.039
0.064
0.039
Symbol
A
B
C
D
E
A
B
C
D
E
Output
Fanin Symbol Fanout
1.0
1.0
1.0
1.0
1.0
Y
1
2.1
2.0
2.0
2.1
2.0
Y
5
N01 Y
Block Library
A13872EJ5V0BL
2 - 154
Block Library
A13872EJ5V0BL
2 - 155
Chapter 2 Function Block
Function
Block type
Chapter 2 Function Block
1-1-1-3-Input OR-NAND
Normal
with inv. A
Drivability
Name
cells
Low Power
L459
5
x1
F459
5
Name
cells
with inv. B
Name
cells
with inv. C
Name
cells
with inv. D
Name
cells
with inv. E
Name
cells
Block
type
L459
IN
Path
→ OUT
A → Y
B → Y
x2
C → Y
x4
D → Y
x8
Block type
with inv. F
with inv. G
with inv. H
Drivability
Name
Name
Name
cells
cells
-
-
-
E → Y
cells
F → Y
Low Power
x1
F459
A → Y
x2
B → Y
x4
x8
C → Y
Logic Diagram for "Normal"
F
E
D
C
B
A
H06
H05
H04
H03
H02
H01
Logic Diagram for "with inv. A type"
Logic Diagram for "with inv. B type"
D → Y
E → Y
N01 Y
F → Y
Logic Diagram for "with inv. C type"
Logic Diagram for "with inv. D type"
Logic Diagram for "with inv. E type"
Logic Diagram for "with inv. F type"
Logic Diagram for "with inv. G type"
Logic Diagram for "with inv. H type"
Block Library
A13872EJ5V0BL
2 - 156
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.278
0.163
0.263
0.188
0.259
0.175
0.264
0.341
0.298
0.361
0.305
0.353
0.304
0.171
0.287
0.193
0.279
0.179
0.286
0.356
0.319
0.377
0.327
0.369
0.448
0.279
0.424
0.306
0.551
0.326
0.453
0.536
0.511
0.633
0.521
0.643
0.487
0.288
0.463
0.316
0.583
0.336
0.486
0.554
0.543
0.655
0.554
0.663
0.835
0.527
0.804
0.548
1.119
0.623
0.886
0.863
1.051
1.218
1.078
1.280
0.902
0.542
0.870
0.562
1.179
0.642
0.946
0.893
1.109
1.250
1.136
1.307
0.020
0.022
0.020
0.022
0.020
0.021
0.020
0.021
0.020
0.021
0.020
0.021
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.025
0.030
0.025
0.030
0.025
0.030
0.025
0.029
0.025
0.029
0.025
0.029
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.034
0.042
0.034
0.042
0.035
0.042
0.034
0.042
0.035
0.042
0.035
0.042
0.018
0.021
0.018
0.021
0.018
0.021
0.018
0.021
0.018
0.021
0.018
0.021
Block Library
A13872EJ5V0BL
Symbol
A
B
C
D
E
F
A
B
C
D
E
F
Output
Fanin Symbol Fanout
1.0
1.0
1.0
1.0
1.0
1.0
Y
17
1.0
1.0
1.0
1.0
1.0
1.0
Y
34
2 - 157
Chapter 2 Function Block
Function
Block type
Drivability
Chapter 2 Function Block
1-1-1-1-2-Input OR-NAND
Normal
with inv. A
Name
cells
F490
5
Name
cells
with inv. B
Name
cells
with inv. C
Name
cells
with inv. D
Name
cells
with inv. E
Name
cells
Low Power
x1
Block
type
F490
IN
Path
→ OUT
A → Y
B → Y
x2
C → Y
x4
D → Y
x8
Block type
with inv. F
with inv. G
with inv. H
Drivability
Name
Name
Name
cells
cells
-
-
-
E → Y
cells
F → Y
Low Power
x1
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.372
0.180
0.365
0.203
0.361
0.233
0.291
0.186
0.296
0.321
0.332
0.314
0.606
0.320
0.603
0.346
0.605
0.382
0.575
0.340
0.495
0.497
0.553
0.535
1.252
0.638
1.247
0.656
1.246
0.687
1.149
0.649
0.959
0.827
1.120
1.006
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.018
0.021
0.018
0.021
0.018
0.021
0.018
0.021
0.018
0.021
0.018
0.021
Symbol
A
B
C
D
E
F
Output
Fanin Symbol Fanout
1.0
1.0
1.0
1.0
1.0
1.0
Y
x2
x4
x8
Logic Diagram for "Normal"
Logic Diagram for "with inv. A type"
Logic Diagram for "with inv. B type"
Logic Diagram for "with inv. C type"
Logic Diagram for "with inv. D type"
Logic Diagram for "with inv. E type"
Logic Diagram for "with inv. F type"
Logic Diagram for "with inv. G type"
Logic Diagram for "with inv. H type"
F H06
E
D
C
B
A
H05
H04
H03
H02
H01
N01 Y
Block Library
A13872EJ5V0BL
2 - 158
Block Library
A13872EJ5V0BL
2 - 159
35
Chapter 2 Function Block
Function
Block type
Chapter 2 Function Block
1-2-3-Input OR-NAND
Normal
with inv. A
Drivability
Name
cells
Low Power
L491
5
x1
F491
5
Name
cells
with inv. B
Name
cells
with inv. C
Name
cells
with inv. D
Name
cells
with inv. E
Name
cells
Block
type
L491
IN
Path
→ OUT
A → Y
B → Y
x2
C → Y
x4
D → Y
x8
Block type
with inv. F
with inv. G
with inv. H
Drivability
Name
Name
Name
cells
cells
-
-
-
E → Y
cells
F → Y
Low Power
x1
F491
A → Y
x2
B → Y
x4
x8
C → Y
Logic Diagram for "Normal"
Logic Diagram for "with inv. A type"
Logic Diagram for "with inv. B type"
F H06
E H05
D H04
D → Y
E → Y
F → Y
C H03
N01 Y
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.244
0.183
0.271
0.251
0.288
0.233
0.296
0.432
0.308
0.437
0.320
0.443
0.265
0.186
0.312
0.290
0.327
0.272
0.317
0.457
0.330
0.461
0.343
0.470
0.397
0.298
0.588
0.464
0.624
0.461
0.571
0.765
0.605
0.805
0.653
0.868
0.430
0.300
0.651
0.526
0.685
0.524
0.618
0.802
0.651
0.841
0.700
0.905
0.722
0.545
1.257
0.948
1.365
1.007
1.150
1.268
1.244
1.440
1.376
1.621
0.780
0.550
1.346
1.025
1.450
1.085
1.222
1.332
1.314
1.502
1.452
1.688
0.020
0.022
0.020
0.022
0.020
0.022
0.020
0.021
0.020
0.021
0.020
0.021
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.025
0.030
0.025
0.030
0.025
0.030
0.025
0.029
0.025
0.029
0.025
0.029
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.034
0.042
0.034
0.042
0.034
0.042
0.034
0.042
0.034
0.042
0.034
0.042
0.018
0.021
0.018
0.021
0.018
0.021
0.018
0.021
0.018
0.021
0.018
0.021
Symbol
A
B
C
D
E
F
A
B
C
D
E
F
Output
Fanin Symbol Fanout
1.0
1.0
1.0
1.0
1.0
1.0
Y
16
1.0
1.0
1.0
1.0
1.0
1.0
Y
34
B H02
A H01
Logic Diagram for "with inv. C type"
Logic Diagram for "with inv. D type"
Logic Diagram for "with inv. E type"
Logic Diagram for "with inv. F type"
Logic Diagram for "with inv. G type"
Logic Diagram for "with inv. H type"
Block Library
A13872EJ5V0BL
2 - 160
Block Library
A13872EJ5V0BL
2 - 161
Chapter 2 Function Block
Function
Block type
Chapter 2 Function Block
3-3-3-Input OR-NAND
Normal
with inv. A
Drivability
Name
cells
Low Power
L493
6
x1
F493
7
Name
cells
with inv. B
Name
cells
with inv. C
Name
cells
with inv. D
Name
cells
with inv. E
Name
cells
Block
type
L493
IN
Path
→ OUT
A → Y
B → Y
x2
C → Y
x4
D → Y
x8
Block type
with inv. F
with inv. G
with inv. H
Drivability
Name
Name
Name
cells
cells
-
-
-
E → Y
cells
Low Power
F → Y
x1
G → Y
x2
H → Y
x4
x8
I → Y
Logic Diagram for "Normal"
Logic Diagram for "with inv. A type"
Logic Diagram for "with inv. B type"
I H09
H H08
G H07
F H06
E H05
D H04
F493
A → Y
B → Y
C → Y
N01 Y
D → Y
C H03
B H02
A H01
E → Y
F → Y
Logic Diagram for "with inv. C type"
Logic Diagram for "with inv. D type"
Logic Diagram for "with inv. E type"
G → Y
H → Y
I → Y
Logic Diagram for "with inv. F type"
Logic Diagram for "with inv. G type"
Block Library
A13872EJ5V0BL
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.245
0.305
0.262
0.308
0.273
0.310
0.281
0.339
0.312
0.363
0.317
0.355
0.295
0.455
0.314
0.478
0.316
0.471
0.266
0.317
0.283
0.320
0.294
0.323
0.330
0.406
0.344
0.412
0.357
0.420
0.334
0.525
0.346
0.531
0.355
0.542
0.412
0.481
0.433
0.510
0.449
0.564
0.601
0.596
0.678
0.695
0.702
0.704
0.616
0.766
0.699
0.872
0.722
0.879
0.443
0.497
0.464
0.527
0.481
0.581
0.686
0.727
0.722
0.765
0.773
0.826
0.707
0.912
0.744
0.952
0.796
1.016
0.735
0.815
0.776
0.973
0.800
1.155
1.167
0.985
1.407
1.340
1.466
1.405
1.163
1.092
1.402
1.454
1.467
1.518
0.791
0.845
0.831
1.004
0.863
1.187
1.379
1.319
1.494
1.487
1.652
1.671
1.380
1.451
1.491
1.621
1.653
1.801
0.020
0.022
0.020
0.022
0.020
0.022
0.020
0.022
0.020
0.022
0.020
0.022
0.020
0.022
0.020
0.022
0.020
0.022
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.025
0.030
0.025
0.030
0.025
0.030
0.025
0.030
0.025
0.030
0.025
0.030
0.025
0.030
0.025
0.030
0.025
0.030
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.034
0.042
0.034
0.042
0.034
0.042
0.034
0.042
0.034
0.042
0.034
0.042
0.034
0.042
0.034
0.042
0.034
0.042
0.018
0.021
0.018
0.021
0.018
0.021
0.018
0.021
0.018
0.021
0.018
0.021
0.018
0.021
0.018
0.021
0.018
0.021
Symbol
A
B
C
D
E
F
G
H
I
A
B
C
D
E
F
G
H
I
Output
Fanin Symbol Fanout
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Y
16
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Y
34
Logic Diagram for "with inv. H type"
2 - 162
Block Library
A13872EJ5V0BL
2 - 163
Chapter 2 Function Block
Function
Block type
Drivability
Chapter 2 Function Block
1-1-2-2-Input OR-NAND
Normal
with inv. A
Name
cells
F495
6
Name
cells
with inv. B
Name
cells
with inv. C
Name
cells
with inv. D
Name
cells
with inv. E
Name
cells
Low Power
x1
Block
type
F495
IN
Path
→ OUT
A → Y
B → Y
x2
C → Y
x4
D → Y
x8
Block type
with inv. F
with inv. G
with inv. H
Drivability
Name
Name
Name
cells
cells
-
-
-
E → Y
cells
F → Y
Low Power
x1
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.164
0.065
0.163
0.087
0.191
0.155
0.191
0.155
0.222
0.193
0.222
0.193
0.366
0.128
0.398
0.158
0.424
0.288
0.424
0.288
0.456
0.354
0.456
0.354
1.018
0.267
1.048
0.290
1.085
0.553
1.085
0.553
1.103
0.623
1.103
0.623
0.022
0.011
0.022
0.011
0.024
0.019
0.024
0.019
0.025
0.019
0.025
0.019
0.039
0.015
0.039
0.015
0.039
0.027
0.039
0.027
0.039
0.028
0.039
0.028
0.064
0.021
0.064
0.021
0.064
0.039
0.064
0.039
0.064
0.039
0.064
0.039
Symbol
A
B
C
D
E
F
Output
Fanin Symbol Fanout
2.1
2.0
2.0
2.0
2.0
2.0
Y
x2
x4
x8
Logic Diagram for "Normal"
Logic Diagram for "with inv. A type"
Logic Diagram for "with inv. B type"
Logic Diagram for "with inv. C type"
Logic Diagram for "with inv. D type"
Logic Diagram for "with inv. E type"
Logic Diagram for "with inv. F type"
Logic Diagram for "with inv. G type"
Logic Diagram for "with inv. H type"
F H06
E H05
D H04
N01 Y
C H03
B H02
A H01
Block Library
A13872EJ5V0BL
2 - 164
Block Library
A13872EJ5V0BL
2 - 165
2
Chapter 2 Function Block
Function
Block type
Drivability
Chapter 2 Function Block
3-3-3-3-Input OR-NAND
Normal
with inv. A
Name
cells
F496
8
Name
cells
with inv. B
Name
cells
with inv. C
Name
cells
with inv. D
Name
cells
with inv. E
Name
cells
Low Power
x1
Block
type
F496
IN
Path
→ OUT
A → Y
B → Y
x2
C → Y
x4
D → Y
x8
Block type
with inv. F
with inv. G
with inv. H
Drivability
Name
Name
Name
cells
cells
-
-
-
E → Y
cells
Low Power
F → Y
x1
G → Y
x2
H → Y
x4
x8
I → Y
Logic Diagram for "Normal"
Logic Diagram for "with inv. A type"
Logic Diagram for "with inv. B type"
L H12
K H11
J H10
J → Y
K → Y
I H09
H H08
G H07
L → Y
N01 Y
F H06
E H05
D H04
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.327
0.373
0.343
0.378
0.358
0.387
0.336
0.459
0.349
0.464
0.360
0.475
0.330
0.403
0.345
0.408
0.356
0.418
0.331
0.487
0.342
0.492
0.350
0.503
0.698
0.663
0.737
0.701
0.793
0.761
0.721
0.848
0.758
0.888
0.815
0.953
0.685
0.723
0.723
0.761
0.774
0.823
0.706
0.897
0.741
0.939
0.792
1.003
1.386
1.193
1.510
1.359
1.683
1.548
1.388
1.343
1.508
1.513
1.691
1.699
1.379
1.314
1.493
1.481
1.649
1.669
1.376
1.430
1.487
1.600
1.646
1.788
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.018
0.021
0.018
0.021
0.018
0.021
0.018
0.021
0.018
0.021
0.018
0.021
0.018
0.021
0.018
0.021
0.018
0.021
0.018
0.021
0.018
0.021
0.018
0.021
Symbol
A
B
C
D
E
F
G
H
I
J
K
L
Output
Fanin Symbol Fanout
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Y
C H03
B H02
A H01
Logic Diagram for "with inv. C type"
Logic Diagram for "with inv. D type"
Logic Diagram for "with inv. E type"
Logic Diagram for "with inv. F type"
Logic Diagram for "with inv. G type"
Logic Diagram for "with inv. H type"
Block Library
A13872EJ5V0BL
2 - 166
Block Library
A13872EJ5V0BL
2 - 167
34
Chapter 2 Function Block
Function
Block type
Drivability
Chapter 2 Function Block
4-4-4-4-Input OR-NAND
Normal
with inv. A
Name
cells
F498
14
Name
cells
with inv. B
Name
cells
with inv. C
Name
cells
with inv. D
Name
cells
with inv. E
Name
cells
Low Power
x1
Block
type
F498
IN
Path
→ OUT
A → Y
B → Y
x2
C → Y
x4
D → Y
x8
Block type
with inv. F
with inv. G
with inv. H
Drivability
Name
Name
Name
cells
cells
-
-
-
E → Y
cells
Low Power
F → Y
x1
G → Y
x2
H → Y
x4
x8
I → Y
Logic Diagram for "Normal"
Logic Diagram for "with inv. A type"
Logic Diagram for "with inv. B type"
P H16
O H15
N H14
M H13
L
K
J
I
H
G
F
E
D
C
B
A
K → Y
H12
H11
H10
H09
H08
H07
H06
H05
H04
H03
H02
H01
J → Y
L → Y
N01 Y
M → Y
N → Y
O → Y
Logic Diagram for "with inv. C type"
Logic Diagram for "with inv. D type"
Logic Diagram for "with inv. E type"
Logic Diagram for "with inv. F type"
Logic Diagram for "with inv. G type"
Logic Diagram for "with inv. H type"
Block Library
A13872EJ5V0BL
2 - 168
P → Y
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.316
0.343
0.332
0.328
0.336
0.323
0.352
0.308
0.332
0.363
0.346
0.347
0.348
0.342
0.360
0.327
0.318
0.344
0.333
0.328
0.335
0.324
0.351
0.308
0.331
0.363
0.345
0.347
0.349
0.343
0.362
0.328
0.658
0.592
0.678
0.588
0.693
0.552
0.713
0.547
0.704
0.646
0.722
0.642
0.742
0.604
0.759
0.598
0.657
0.595
0.679
0.589
0.692
0.553
0.713
0.547
0.705
0.646
0.721
0.643
0.742
0.604
0.759
0.599
1.154
1.161
1.191
1.219
1.181
1.048
1.218
1.104
1.315
1.352
1.345
1.409
1.342
1.228
1.373
1.287
1.156
1.162
1.192
1.220
1.181
1.049
1.219
1.105
1.316
1.352
1.345
1.410
1.342
1.232
1.375
1.288
0.015
0.011
0.015
0.011
0.015
0.011
0.015
0.011
0.015
0.011
0.015
0.011
0.015
0.011
0.015
0.011
0.015
0.011
0.015
0.011
0.015
0.011
0.015
0.011
0.015
0.011
0.015
0.011
0.015
0.011
0.015
0.011
0.021
0.015
0.021
0.015
0.021
0.015
0.021
0.015
0.021
0.015
0.021
0.015
0.021
0.015
0.021
0.015
0.021
0.015
0.021
0.015
0.021
0.015
0.021
0.015
0.021
0.015
0.021
0.015
0.021
0.015
0.021
0.015
0.032
0.022
0.032
0.022
0.032
0.022
0.032
0.022
0.032
0.022
0.032
0.022
0.032
0.022
0.032
0.022
0.032
0.022
0.032
0.022
0.032
0.022
0.032
0.022
0.032
0.022
0.032
0.022
0.032
0.022
0.032
0.022
Block Library
A13872EJ5V0BL
Symbol
A
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P
Output
Fanin Symbol Fanout
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Y
2 - 169
25
Chapter 2 Function Block
Chapter 2 Function Block
[MEMO]
[MEMO]
Block Library
A13872EJ5V0BL
2 - 170
Block Library
A13872EJ5V0BL
2 - 171
Chapter 2 Function Block
Chapter 2 Function Block
[MEMO]
2.7
Exclusive OR, Exclusive NOR
Block Library
A13872EJ5V0BL
2 - 172
Block Library
A13872EJ5V0BL
2 - 173
Chapter 2 Function Block
Chapter 2 Function Block
2-Input Exclusive OR
Function
Block
type
Standard type
Block type
Normal
Drivability
Name
High speed
cells
Low Power
L511
3
x1
F511
4
Name
L511
IN
Path
→ OUT
A → Y
cells
B → Y
x2
x4
F511
Logic Diagram
A
H01
B
H02
N01
Y
A → Y
B → Y
(HH)
(HL)
(LH)
(LL)
(HH)
(HL)
(LH)
(LL)
(HH)
(HL)
(LH)
(LL)
(HH)
(HL)
(LH)
(LL)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.187
0.233
0.186
0.242
0.155
0.216
0.246
0.252
0.203
0.248
0.202
0.267
0.168
0.229
0.263
0.274
0.308
0.365
0.324
0.408
0.246
0.339
0.416
0.374
0.334
0.386
0.346
0.449
0.263
0.360
0.442
0.410
0.624
0.677
0.650
0.745
0.443
0.640
0.832
0.573
0.675
0.709
0.700
0.814
0.483
0.671
0.888
0.639
0.022
0.020
0.022
0.020
0.022
0.020
0.022
0.020
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.030
0.025
0.030
0.025
0.030
0.024
0.030
0.025
0.015
0.012
0.015
0.013
0.015
0.012
0.015
0.013
0.043
0.033
0.042
0.035
0.042
0.033
0.043
0.035
0.022
0.017
0.022
0.018
0.022
0.017
0.022
0.018
Symbol
A
B
A
B
Output
Fanin Symbol Fanout
2.0
2.0
Y
16
2.0
2.0
Y
33
Truth Table
A
B
Y
0
0
0
0
1
1
1
0
1
1
1
0
Block Library
A13872EJ5V0BL
2 - 174
Block Library
A13872EJ5V0BL
2 - 175
Chapter 2 Function Block
Chapter 2 Function Block
3-Input Exclusive OR
Function
Block
type
Standard type
Block type
Normal
Drivability
Name
High speed
cells
Low Power
L516
6
x1
F516
7
Name
L516
IN
Path
→ OUT
A → Y
cells
B → Y
x2
x4
C → Y
Logic Diagram
A
B
C
H01
H02
H03
N01
Y
F516
A → Y
B → Y
C → Y
(HH)
(HL)
(LH)
(LL)
(HH)
(HL)
(LH)
(LL)
(HH)
(HL)
(LH)
(LL)
(HH)
(HL)
(LH)
(LL)
(HH)
(HL)
(LH)
(LL)
(HH)
(HL)
(LH)
(LL)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.428
0.370
0.332
0.445
0.326
0.351
0.319
0.330
0.237
0.318
0.278
0.251
0.442
0.400
0.357
0.451
0.341
0.361
0.333
0.344
0.245
0.323
0.283
0.255
0.720
0.584
0.586
0.784
0.529
0.588
0.560
0.560
0.361
0.524
0.469
0.413
0.743
0.628
0.625
0.797
0.552
0.607
0.581
0.592
0.372
0.535
0.478
0.420
1.409
1.082
1.164
1.537
0.985
1.108
1.097
1.072
0.650
0.982
0.907
0.782
1.453
1.156
1.234
1.566
1.035
1.147
1.141
1.134
0.675
1.006
0.932
0.802
0.021
0.020
0.021
0.020
0.021
0.020
0.021
0.020
0.021
0.020
0.021
0.021
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.011
0.029
0.026
0.030
0.026
0.030
0.026
0.030
0.026
0.030
0.026
0.030
0.026
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.014
0.042
0.035
0.042
0.036
0.042
0.036
0.042
0.035
0.042
0.036
0.042
0.036
0.022
0.018
0.022
0.019
0.022
0.019
0.022
0.019
0.022
0.019
0.022
0.019
Symbol
A
B
C
A
B
C
Output
Fanin Symbol Fanout
1.0
1.0
1.0
Y
16
1.0
1.0
1.0
Y
34
Truth Table
A
B
C
Y
0
0
0
0
0
0
1
1
0
1
0
1
0
1
1
0
1
0
0
1
1
0
1
0
1
1
0
0
1
1
1
1
Block Library
A13872EJ5V0BL
2 - 176
Block Library
A13872EJ5V0BL
2 - 177
Chapter 2 Function Block
Chapter 2 Function Block
2-Input Exclusive NOR
Function
Block
type
Standard type
Block type
Normal
Drivability
Name
High speed
cells
Low Power
L512
3
x1
F512
4
Name
L512
IN
Path
→ OUT
A → Y
cells
B → Y
x2
x4
F512
Logic Diagram
A
A → Y
H01
N01
Y
B → Y
B H02
(HH)
(HL)
(LH)
(LL)
(HH)
(HL)
(LH)
(LL)
(HH)
(HL)
(LH)
(LL)
(HH)
(HL)
(LH)
(LL)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.187
0.219
0.226
0.245
0.202
0.298
0.211
0.172
0.203
0.243
0.239
0.269
0.219
0.326
0.224
0.192
0.309
0.376
0.363
0.417
0.324
0.490
0.357
0.313
0.332
0.411
0.379
0.457
0.344
0.530
0.372
0.347
0.628
0.681
0.673
0.770
0.651
0.812
0.725
0.660
0.678
0.738
0.703
0.841
0.699
0.881
0.756
0.718
0.022
0.020
0.022
0.020
0.022
0.020
0.022
0.020
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.030
0.025
0.029
0.025
0.030
0.026
0.029
0.025
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.043
0.035
0.042
0.035
0.043
0.035
0.042
0.035
0.022
0.018
0.021
0.018
0.022
0.018
0.021
0.018
Symbol
A
B
A
B
Output
Fanin Symbol Fanout
2.0
2.0
Y
16
2.0
2.0
Y
33
Truth Table
A
B
Y
0
0
1
0
1
0
1
0
0
1
1
1
Block Library
A13872EJ5V0BL
2 - 178
Block Library
A13872EJ5V0BL
2 - 179
Chapter 2 Function Block
Chapter 2 Function Block
3-Input Exclusive NOR
Function
Block
type
Standard type
Block type
Normal
Drivability
Name
High speed
cells
Low Power
L517
7
x1
F517
7
Name
L517
IN
Path
→ OUT
A → Y
cells
B → Y
x2
x4
C → Y
Logic Diagram
A H01
B H02
C H03
N01
Y
F517
A → Y
B → Y
C → Y
(HH)
(HL)
(LH)
(LL)
(HH)
(HL)
(LH)
(LL)
(HH)
(HL)
(LH)
(LL)
(HH)
(HL)
(LH)
(LL)
(HH)
(HL)
(LH)
(LL)
(HH)
(HL)
(LH)
(LL)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.428
0.368
0.334
0.448
0.327
0.353
0.322
0.330
0.237
0.318
0.279
0.250
0.442
0.398
0.359
0.452
0.341
0.362
0.336
0.347
0.245
0.323
0.283
0.255
0.719
0.588
0.582
0.782
0.528
0.586
0.556
0.562
0.360
0.525
0.468
0.413
0.741
0.632
0.622
0.796
0.551
0.604
0.578
0.591
0.372
0.535
0.478
0.420
1.406
1.089
1.157
1.535
0.985
1.104
1.091
1.083
0.650
0.982
0.908
0.782
1.451
1.164
1.228
1.565
1.034
1.142
1.135
1.138
0.675
1.005
0.932
0.802
0.021
0.020
0.021
0.020
0.021
0.020
0.021
0.020
0.021
0.020
0.021
0.021
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.011
0.029
0.026
0.030
0.026
0.030
0.026
0.030
0.026
0.030
0.026
0.030
0.026
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.014
0.042
0.035
0.042
0.036
0.042
0.036
0.042
0.035
0.042
0.036
0.042
0.036
0.022
0.018
0.022
0.019
0.022
0.019
0.022
0.019
0.022
0.019
0.022
0.019
Symbol
A
B
C
A
B
C
Output
Fanin Symbol Fanout
1.0
1.0
1.0
Y
16
1.0
1.0
1.0
Y
33
Truth Table
A
B
C
Y
0
0
0
1
0
0
1
0
0
1
0
0
0
1
1
1
1
0
0
0
1
0
1
1
1
1
0
1
1
1
1
0
Block Library
A13872EJ5V0BL
2 - 180
Block Library
A13872EJ5V0BL
2 - 181
Chapter 2 Function Block
Chapter 2 Function Block
[MEMO]
[MEMO]
Block Library
A13872EJ5V0BL
2 - 182
Block Library
A13872EJ5V0BL
2 - 183
Chapter 2 Function Block
Chapter 2 Function Block
[MEMO]
2.8
Adder, 3-State Buffer, Decoder, Multiplexer, Generator
Block Library
A13872EJ5V0BL
2 - 184
Block Library
A13872EJ5V0BL
2 - 185
Chapter 2 Function Block
Chapter 2 Function Block
1-Bit Full Adder
Function
Block
type
Standard type
Block type
Normal
Drivability
High speed
Name
cells
F521
9
Name
F521
IN
Path
→ OUT
A → S
cells
Low Power
x1
A → COUT
x2
B → S
x4
Logic Diagram
A
H01
N02
B → COUT
COUT
CIN → S
B H02
CIN H03
N01
CIN → COUT
S
(HH)
(HL)
(LH)
(LL)
(HH)
(LL)
(HH)
(HL)
(LH)
(LL)
(HH)
(LL)
(HH)
(HL)
(LH)
(LL)
(HH)
(LL)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.410
0.481
0.479
0.519
0.357
0.247
0.445
0.484
0.483
0.515
0.394
0.216
0.382
0.470
0.339
0.345
0.271
0.287
0.787
0.832
1.078
1.169
0.780
0.807
0.760
0.853
1.008
1.111
0.754
0.883
0.621
0.703
0.551
0.571
0.406
0.472
1.548
1.570
2.172
2.268
1.524
1.391
1.530
1.641
1.954
2.072
1.495
1.575
1.218
1.157
1.004
1.098
0.735
0.886
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.011
0.011
0.010
0.011
0.011
0.015
0.013
0.015
0.013
0.016
0.013
0.015
0.013
0.015
0.013
0.016
0.013
0.015
0.013
0.015
0.012
0.015
0.014
0.022
0.018
0.022
0.018
0.023
0.018
0.022
0.018
0.022
0.018
0.023
0.018
0.022
0.018
0.022
0.017
0.022
0.019
Symbol
A
B
CIN
Output
Fanin Symbol Fanout
1.7
2.0
1.0
S
COUT
Truth Table
A
B
CIN
S
COUT
0
0
0
0
0
0
1
0
1
0
1
0
0
1
0
1
1
0
0
1
0
0
1
1
0
0
1
1
0
1
1
0
1
0
1
1
1
1
1
1
Block Library
A13872EJ5V0BL
2 - 186
Block Library
A13872EJ5V0BL
2 - 187
33
32
Chapter 2 Function Block
Chapter 2 Function Block
4-Bit Full Adder
Function
Standard type
Block type
Normal
Drivability
Block
type
High speed
Name
cells
F523
32
Name
F523
IN
Path
→ OUT
A1 → S1
cells
Low Power
x1
A1 → S2
x2
x4
A1 → S3
Logic Diagram
B4
A4
B3
A3
B2
A2
B1
A1
CIN
H08
H07
H06
H05
H04
H03
H02
H01
H09
N05 COUT
A1 → S4
N04 S4
N03 S3
A1 → COUT
B1 → S1
N02 S2
N01 S1
B1 → S2
B1 → S3
Truth Table
B1 → S4
An
Bn
CIN
Sn
COUT
0
0
0
0
0
0
1
0
1
0
1
0
0
1
0
1
1
0
0
1
0
0
1
1
0
0
1
1
0
1
1
0
1
0
1
1
1
1
1
1
B1 → COUT
A2 → S2
A2 → S3
(Condition of one stage, n=1,2,3 4)
A2 → S4
A2 → COUT
B2 → S2
B2 → S3
Block Library
A13872EJ5V0BL
2 - 188
(HH)
(HL)
(LH)
(LL)
(HH)
(HL)
(LH)
(LL)
(HH)
(HL)
(LH)
(LL)
(HH)
(HL)
(LH)
(LL)
(HH)
(LL)
(HH)
(HL)
(LH)
(LL)
(HH)
(HL)
(LH)
(LL)
(HH)
(HL)
(LH)
(LL)
(HH)
(HL)
(LH)
(LL)
(HH)
(LL)
(HH)
(HL)
(LH)
(LL)
(HH)
(HL)
(LH)
(LL)
(HH)
(HL)
(LH)
(LL)
(HH)
(LL)
(HH)
(HL)
(LH)
(LL)
(HH)
(HL)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.424
0.519
0.810
0.537
0.723
1.292
0.730
0.474
0.974
1.476
0.876
0.665
1.239
1.579
0.976
0.851
1.302
0.865
0.457
0.498
0.774
0.529
0.701
1.270
0.745
0.492
0.953
1.455
0.885
0.678
1.217
1.558
0.985
0.864
1.281
0.874
0.422
0.511
0.784
0.536
0.733
1.131
0.665
0.481
0.964
1.243
0.768
0.654
0.996
0.655
0.457
0.490
0.751
0.530
0.712
1.110
0.717
0.853
1.352
0.874
1.207
2.030
1.241
0.806
1.638
2.418
1.538
1.144
2.110
2.625
1.741
1.481
2.207
1.531
0.783
0.827
1.273
0.917
1.181
2.004
1.260
0.831
1.613
2.392
1.553
1.157
2.084
2.600
1.757
1.495
2.182
1.546
0.713
0.842
1.318
0.871
1.222
1.816
1.134
0.818
1.625
2.039
1.340
1.131
1.667
1.136
0.782
0.817
1.241
0.915
1.197
1.790
1.454
1.667
2.673
1.585
2.394
3.804
2.343
1.564
3.315
4.776
3.068
2.255
4.360
5.315
3.601
3.002
4.624
3.140
1.652
1.637
2.421
1.765
2.366
3.774
2.333
1.575
3.286
4.746
3.070
2.237
4.331
5.286
3.598
2.996
4.595
3.140
1.450
1.647
2.633
1.581
2.420
3.478
2.176
1.580
3.294
4.036
2.698
2.242
3.421
2.266
1.646
1.619
2.385
1.759
2.392
3.449
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.013
0.015
0.011
0.010
0.011
0.010
0.011
0.011
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.013
0.015
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.012
0.014
0.011
0.010
0.011
0.010
0.011
0.010
0.015
0.012
0.015
0.012
0.015
0.013
0.015
0.012
0.015
0.013
0.015
0.012
0.015
0.013
0.015
0.012
0.019
0.021
0.015
0.012
0.015
0.012
0.015
0.013
0.015
0.012
0.015
0.013
0.015
0.012
0.015
0.013
0.015
0.012
0.019
0.021
0.015
0.012
0.015
0.012
0.015
0.013
0.015
0.012
0.015
0.013
0.015
0.012
0.018
0.020
0.015
0.012
0.015
0.012
0.015
0.013
0.021
0.017
0.022
0.017
0.021
0.019
0.022
0.017
0.021
0.019
0.022
0.017
0.021
0.018
0.022
0.017
0.029
0.031
0.021
0.017
0.022
0.017
0.021
0.019
0.022
0.017
0.021
0.019
0.022
0.017
0.021
0.018
0.022
0.017
0.029
0.031
0.021
0.017
0.022
0.017
0.021
0.018
0.022
0.017
0.021
0.018
0.022
0.017
0.027
0.029
0.022
0.017
0.022
0.017
0.021
0.018
Block Library
A13872EJ5V0BL
Symbol
A1
B1
A2
B2
A3
B3
A4
B4
CIN
Output
Fanin Symbol Fanout
1.7
2.1
1.7
2.1
1.7
2.1
1.7
2.0
2.1
S1
S2
S3
S4
COUT
2 - 189
31
30
29
28
18
Chapter 2 Function Block
Block
type
IN
Path
→ OUT
B2 → S4
B2 → COUT
A3 → S3
A3 → S4
A3 → COUT
B3 → S3
B3 → S4
B3 → COUT
A4 → S4
A4 → COUT
B4 → S4
B4 → COUT
CIN → S1
CIN → S2
CIN → S3
CIN → S4
(LH)
(LL)
(HH)
(HL)
(LH)
(LL)
(HH)
(LL)
(HH)
(HL)
(LH)
(LL)
(HH)
(HL)
(LH)
(LL)
(HH)
(LL)
(HH)
(HL)
(LH)
(LL)
(HH)
(HL)
(LH)
(LL)
(HH)
(LL)
(HH)
(HL)
(LH)
(LL)
(HH)
(LL)
(HH)
(HL)
(LH)
(LL)
(HH)
(LL)
(HH)
(HL)
(LH)
(LL)
(HH)
(HL)
(LH)
(LL)
(HH)
(HL)
(LH)
(LL)
(HH)
(HL)
(LH)
(LL)
Switching speed
t LD0 (ns)
Chapter 2 Function Block
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.681
0.498
0.943
1.221
0.784
0.669
0.975
0.670
0.424
0.519
0.741
0.537
0.723
0.948
0.564
0.474
0.729
0.456
0.459
0.497
0.712
0.529
0.702
0.927
0.578
0.491
0.708
0.473
0.422
0.511
0.652
0.536
0.495
0.279
0.457
0.490
0.629
0.530
0.475
0.295
0.315
0.427
0.361
0.298
0.422
0.684
0.551
0.396
0.580
0.908
0.708
0.540
0.773
1.023
0.814
0.698
1.153
0.839
1.600
2.014
1.364
1.144
1.642
1.154
0.718
0.852
1.260
0.874
1.208
1.536
0.966
0.806
1.201
0.784
0.784
0.827
1.190
0.916
1.183
1.511
0.980
0.831
1.176
0.803
0.715
0.843
1.127
0.871
0.806
0.467
0.783
0.817
1.065
0.915
0.780
0.488
0.514
0.666
0.571
0.488
0.684
1.020
0.951
0.665
0.960
1.447
1.282
0.931
1.305
1.674
1.493
1.245
2.175
1.589
3.266
4.008
2.732
2.229
3.393
2.280
1.454
1.665
2.546
1.584
2.399
2.959
1.886
1.567
2.405
1.522
1.650
1.636
2.320
1.762
2.371
2.930
1.875
1.577
2.376
1.513
1.449
1.648
2.327
1.581
1.561
0.883
1.646
1.621
2.121
1.760
1.533
0.894
0.965
1.160
1.072
0.923
1.301
1.822
1.879
1.291
1.883
2.721
2.669
1.885
2.636
3.286
3.204
2.623
0.011
0.010
0.011
0.010
0.011
0.010
0.012
0.015
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.012
0.012
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.012
0.012
0.011
0.010
0.011
0.010
0.011
0.011
0.011
0.010
0.011
0.010
0.011
0.011
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.015
0.012
0.015
0.013
0.015
0.012
0.018
0.020
0.015
0.012
0.015
0.012
0.015
0.013
0.015
0.012
0.017
0.016
0.015
0.012
0.015
0.012
0.015
0.013
0.015
0.012
0.017
0.016
0.015
0.012
0.015
0.012
0.016
0.013
0.015
0.012
0.015
0.012
0.016
0.013
0.015
0.013
0.015
0.012
0.015
0.013
0.016
0.012
0.015
0.013
0.016
0.012
0.015
0.013
0.015
0.012
0.022
0.017
0.021
0.018
0.022
0.017
0.027
0.030
0.021
0.017
0.022
0.017
0.021
0.018
0.022
0.017
0.025
0.022
0.022
0.017
0.022
0.017
0.021
0.018
0.022
0.017
0.025
0.023
0.022
0.017
0.021
0.017
0.023
0.018
0.022
0.017
0.021
0.017
0.023
0.018
0.021
0.018
0.022
0.017
0.021
0.019
0.022
0.017
0.021
0.018
0.022
0.017
0.021
0.018
0.022
0.017
Block Library
A13872EJ5V0BL
Symbol
Output
Fanin Symbol Fanout
Block
type
IN
Path
→ OUT
CIN → COUT
2 - 190
(HH)
(LL)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.783
0.699
1.313
1.280
2.692
2.747
0.012
0.015
0.017
0.021
0.026
0.031
Block Library
A13872EJ5V0BL
Symbol
Output
Fanin Symbol Fanout
2 - 191
Chapter 2 Function Block
4-Bit Look Ahead Carry Generator
Function
Block
type
Standard type
Block type
Normal
Drivability
Chapter 2 Function Block
High speed
Name
cells
F526
34
Name
F526
cells
Low Power
x1
x2
x4
Logic Diagram
Y3
X3
Y2
X2
Y1
X1
Y0
X0
CNB
H08
H07
H06
H05
H04
H03
H02
H01
H09
N05 X
N04 Y
N03 CN+ZB
N02 CN+YB
N01 CN+XB
Truth Table
Y3
Y2
0
X
X
X
X
0
X
X
Y2
Y1
0
X
X
X
X
0
X
X
Y1
Y0
0
X
X
Y1
Y0
X3
X
X
X
X
X
0
0
X
0
0
0
X
All other combinations
Y0
X2
X1
X
X
X
X
0
X
0
0
0
X
0
0
All other combinations
X1
X0
CnB
X
X
X
X
0
0
X
X
X
0
0
1
All other combinations
X2
X1
Y
X
X
0
0
X
X
X
0
0
0
0
0
1
X0
CnB
Cn+zB
X
X
X
0
X
X
X
1
1
1
1
1
0
Y0
X0
CnB
Cn+xB
0
X
X
X
0
1
All other combinations
X3
X2
X1
1
1
0
X0
X
0
0
0
0
All other combinations
0
1
Cn+yB
1
1
1
0
Block Library
IN
Path
→ OUT
X0 → CN+XB (HL)
(LH)
X0 → CN+YB (HL)
(LH)
X0 → CN+ZB (HL)
(LH)
(HH)
X0 → X
(LL)
Y0 → CN+XB (HL)
(LH)
Y0 → CN+YB (HL)
(LH)
Y0 → CN+ZB (HL)
(LH)
(HH)
Y0 → Y
(LL)
X1 → CN+YB (HL)
(LH)
X1 → CN+ZB (HL)
(LH)
(HH)
X1 → Y
(LL)
(HH)
X1 → X
(LL)
Y1 → CN+YB (HL)
(LH)
Y1 → CN+ZB (HL)
(LH)
(HH)
Y1 → Y
(LL)
X2 → CN+ZB (HL)
(LH)
(HH)
X2 → Y
(LL)
(HH)
X2 → X
(LL)
Y2 → CN+ZB (HL)
(LH)
(HH)
Y2 → Y
(LL)
(HH)
X3 → Y
(LL)
(HH)
X3 → X
(LL)
(HH)
Y3 → Y
(LL)
CNB → CN+XB (HH)
(LL)
CNB → CN+YB (HH)
(LL)
CNB → CN+ZB (HH)
(LL)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.129
0.148
0.336
0.241
0.557
0.516
0.142
0.348
0.126
0.103
0.317
0.255
0.347
0.300
0.453
0.329
0.267
0.226
0.345
0.289
0.331
0.275
0.156
0.364
0.241
0.242
0.305
0.254
0.319
0.251
0.366
0.276
0.300
0.270
0.167
0.390
0.316
0.321
0.288
0.292
0.309
0.252
0.168
0.387
0.278
0.294
0.252
0.224
0.399
0.403
0.537
0.443
0.196
0.229
0.542
0.423
0.976
0.910
0.221
0.521
0.262
0.248
0.565
0.465
0.920
0.754
0.840
0.616
0.419
0.383
0.585
0.500
0.541
0.436
0.241
0.580
0.559
0.497
0.932
0.792
0.906
0.587
0.613
0.507
0.506
0.465
0.257
0.703
1.076
0.941
0.947
0.653
0.518
0.461
0.257
0.715
0.937
0.669
0.415
0.370
0.659
0.676
0.837
0.746
0.361
0.361
1.094
0.791
2.329
1.732
0.353
0.807
0.575
0.477
1.118
0.933
2.391
1.511
2.183
1.325
0.747
0.683
1.278
1.034
1.146
0.769
0.395
1.051
1.121
0.951
2.386
1.535
2.352
1.209
1.342
1.134
1.138
0.953
0.419
1.430
2.521
1.672
2.388
1.269
1.167
1.039
0.414
1.491
2.379
1.282
0.744
0.747
1.199
1.336
1.359
1.476
0.015
0.021
0.010
0.029
0.010
0.011
0.011
0.011
0.015
0.016
0.010
0.029
0.010
0.011
0.011
0.015
0.010
0.029
0.010
0.011
0.011
0.015
0.011
0.011
0.010
0.029
0.010
0.011
0.011
0.015
0.010
0.011
0.011
0.015
0.011
0.011
0.010
0.011
0.011
0.015
0.011
0.015
0.011
0.011
0.011
0.015
0.021
0.015
0.029
0.010
0.011
0.010
0.020
0.029
0.013
0.041
0.012
0.015
0.015
0.015
0.020
0.023
0.013
0.041
0.012
0.015
0.016
0.021
0.013
0.041
0.012
0.015
0.016
0.021
0.015
0.015
0.013
0.041
0.012
0.015
0.016
0.021
0.012
0.015
0.016
0.021
0.015
0.015
0.012
0.015
0.016
0.021
0.015
0.021
0.015
0.015
0.016
0.021
0.029
0.020
0.041
0.013
0.015
0.012
0.031
0.041
0.018
0.059
0.017
0.022
0.021
0.022
0.031
0.032
0.018
0.059
0.017
0.022
0.025
0.033
0.017
0.059
0.017
0.022
0.023
0.033
0.021
0.022
0.018
0.059
0.017
0.022
0.025
0.033
0.017
0.022
0.023
0.033
0.022
0.022
0.017
0.022
0.025
0.033
0.022
0.032
0.022
0.022
0.025
0.032
0.041
0.031
0.059
0.018
0.022
0.017
Symbol
X0
Y0
X1
Y1
X2
Y2
X3
Y3
CNB
Output
Fanin Symbol Fanout
7.1
10.9
5.4
9.1
3.9
7.7
2.8
4.3
2.1
CN+XB
CN+YB
CN+ZB
Y
X
F526
A13872EJ5V0BL
2 - 192
Block Library
A13872EJ5V0BL
2 - 193
11
10
34
22
34
Chapter 2 Function Block
Chapter 2 Function Block
4-Bit Carry Look Ahead Adder
Function
Block
type
Standard type
Block type
Normal
Drivability
High speed
Name
cells
F527
69
Name
F527
cells
Low Power
x1
x2
x4
Logic Diagram
B3
A3
B2
A2
B1
A1
B0
A0
CINB
H08
H07
H06
H05
H04
H03
H02
H01
H09
N07
N06
N05
N04
N03
N02
N01
Y
X
COUTB
S3
S2
S1
S0
Truth Table
A0
B0
A1
B1
A2
B2
A3
B3
*1
S0
S1
S2
S3
*2
X
Y
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
1
0
1
0
1
0
0
1
1
1
1
0
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
1
1
1
1
0
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
1
0
1
0
1
0
1
1
1
0
1
1
1
0
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
1
(n=0,1,2,3) , *1:CinB , *2:CoutB
Sn=(An+Bn+CinB)
X=(A0¥B0)+(A1¥B1)+(A2¥B2)+(A3¥B3)
Y=1:(An+Bn)>=1111
Y=0:(An+Bn)<1111
Block Library
A13872EJ5V0BL
2 - 194
IN
Path
→ OUT
A0 → F0
(HH)
(HL)
(LH)
(LL)
(HH)
A0 → F1
(HL)
(LH)
(LL)
(HH)
A0 → F2
(HL)
(LH)
(LL)
(HH)
A0 → F3
(HL)
(LH)
(LL)
(HL)
A0 → COUTB
(LH)
(HH)
A0 → X
(LL)
(HH)
A0 → Y
(LL)
(HH)
B0 → F0
(HL)
(LH)
(LL)
(HH)
B0 → F1
(HL)
(LH)
(LL)
(HH)
B0 → F2
(HL)
(LH)
(LL)
(HH)
B0 → F3
(HL)
(LH)
(LL)
B0 → COUTB (HL)
(LH)
(HH)
B0 → X
(LL)
(HH)
B0 → Y
(LL)
(HH)
A1 → F1
(HL)
(LH)
(LL)
(HH)
A1 → F2
(HL)
(LH)
(LL)
(HH)
A1 → F3
(HL)
(LH)
(LL)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.461
0.513
0.509
0.498
0.467
0.486
0.488
0.489
0.693
0.717
0.708
0.725
0.800
0.826
0.817
0.837
0.877
0.855
0.311
0.314
0.811
0.821
0.471
0.519
0.484
0.504
0.482
0.502
0.472
0.488
0.707
0.733
0.692
0.710
0.816
0.841
0.801
0.822
0.893
0.839
0.311
0.315
0.827
0.805
0.488
0.536
0.546
0.514
0.516
0.542
0.496
0.513
0.698
0.724
0.676
0.693
0.890
0.917
0.933
0.951
0.940
0.807
0.791
0.923
1.163
1.200
1.154
1.195
1.348
1.386
1.350
1.389
1.454
1.409
0.507
0.535
1.348
1.350
0.891
0.937
0.960
0.940
0.943
0.827
0.786
0.923
1.183
1.220
1.150
1.190
1.368
1.406
1.345
1.385
1.474
1.404
0.508
0.535
1.367
1.345
0.942
0.959
0.968
1.017
0.895
0.932
0.821
0.861
1.195
1.232
1.110
1.150
1.705
1.755
1.773
1.815
1.814
1.528
1.513
1.732
2.308
2.337
2.201
2.268
2.670
2.694
2.611
2.672
2.860
2.698
0.925
1.068
2.629
2.569
1.705
1.794
1.839
1.812
1.815
1.568
1.571
1.732
2.348
2.377
2.259
2.326
2.711
2.734
2.669
2.730
2.900
2.756
0.927
1.068
2.669
2.627
1.792
1.820
1.816
1.936
1.879
1.911
1.614
1.681
2.459
2.483
2.130
2.194
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.015
0.011
0.011
0.026
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.015
0.011
0.011
0.026
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.020
0.015
0.015
0.037
0.016
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.020
0.015
0.015
0.037
0.016
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.022
0.018
0.022
0.018
0.021
0.018
0.022
0.018
0.021
0.018
0.022
0.018
0.021
0.018
0.022
0.018
0.030
0.021
0.022
0.062
0.023
0.017
0.022
0.018
0.022
0.018
0.021
0.017
0.022
0.018
0.021
0.018
0.022
0.018
0.021
0.018
0.022
0.018
0.030
0.021
0.022
0.062
0.023
0.017
0.022
0.018
0.022
0.018
0.021
0.018
0.022
0.018
0.021
0.018
0.022
0.018
Block Library
A13872EJ5V0BL
Symbol
A0
B0
A1
B1
A2
B2
A3
B3
CINB
Output
Fanin Symbol Fanout
2.9
3.0
2.9
3.1
2.9
3.1
2.8
3.0
2.1
F0
F1
F2
F3
COUTB
X
Y
2 - 195
31
31
31
31
25
8
28
Chapter 2 Function Block
Block
type
Switching speed
t LD0 (ns)
Chapter 2 Function Block
Input
t1
Path
→ OUT
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A1 → COUTB (HL)
(LH)
(HH)
A1 → X
(LL)
(HH)
A1 → Y
(LL)
(HH)
B1 → F1
(HL)
(LH)
(LL)
(HH)
B1 → F2
(HL)
(LH)
(LL)
(HH)
B1 → F3
(HL)
(LH)
(LL)
B1 → COUTB (HL)
(LH)
(HH)
B1 → X
(LL)
(HH)
B1 → Y
(LL)
(HH)
A2 → F2
(HL)
(LH)
(LL)
(HH)
A2 → F3
(HL)
(LH)
(LL)
A2 → COUTB (HL)
(LH)
(HH)
A2 → X
(LL)
(HH)
A2 → Y
(LL)
(HH)
B2 → F2
(HL)
(LH)
(LL)
(HH)
B2 → F3
(HL)
(LH)
(LL)
B2 → COUTB (HL)
(LH)
(HH)
B2 → X
(LL)
(HH)
B2 → Y
(LL)
(HH)
A3 → F3
(HL)
(LH)
(LL)
0.840
0.772
0.329
0.326
0.777
0.736
0.498
0.542
0.522
0.522
0.532
0.557
0.482
0.498
0.714
0.740
0.662
0.679
0.856
0.758
0.328
0.326
0.793
0.722
0.458
0.516
0.516
0.491
0.545
0.571
0.494
0.514
0.774
0.665
0.327
0.321
0.711
0.627
0.468
0.523
0.493
0.499
0.561
0.587
0.481
0.500
0.790
0.651
0.327
0.321
0.727
0.613
0.425
0.459
0.453
0.461
1.409
1.272
0.512
0.535
1.302
1.211
0.944
0.978
0.995
1.003
0.915
0.952
0.817
0.857
1.215
1.253
1.105
1.145
1.429
1.268
0.511
0.535
1.322
1.207
0.892
0.907
0.922
0.963
0.949
0.989
0.815
0.859
1.307
1.082
0.510
0.528
1.200
1.018
0.895
0.926
0.948
0.951
0.969
1.009
0.812
0.855
1.327
1.079
0.509
0.528
1.220
1.014
0.804
0.848
0.868
0.866
2.802
2.429
0.947
1.074
2.575
2.300
1.793
1.858
1.883
1.932
1.919
1.950
1.674
1.741
2.498
2.521
2.191
2.253
2.841
2.489
0.942
1.074
2.612
2.359
1.719
1.734
1.738
1.856
2.057
2.082
1.597
1.668
2.683
2.025
0.943
1.064
2.451
1.894
1.718
1.772
1.805
1.852
2.095
2.121
1.657
1.728
2.721
2.085
0.939
1.064
2.490
1.954
1.563
1.636
1.653
1.693
0.015
0.011
0.011
0.026
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.015
0.011
0.011
0.026
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.015
0.011
0.011
0.026
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.015
0.011
0.011
0.026
0.011
0.010
0.011
0.010
0.011
0.010
0.020
0.015
0.015
0.037
0.016
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.020
0.015
0.015
0.037
0.016
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.020
0.015
0.015
0.037
0.016
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.020
0.015
0.015
0.037
0.016
0.013
0.015
0.013
0.015
0.013
0.030
0.021
0.022
0.061
0.023
0.017
0.022
0.018
0.022
0.018
0.021
0.018
0.022
0.018
0.021
0.017
0.022
0.018
0.030
0.021
0.022
0.061
0.023
0.017
0.022
0.018
0.022
0.018
0.021
0.018
0.022
0.018
0.030
0.021
0.022
0.061
0.023
0.017
0.022
0.018
0.022
0.018
0.021
0.018
0.022
0.018
0.030
0.021
0.022
0.061
0.023
0.017
0.022
0.018
0.022
0.018
IN
Block Library
A13872EJ5V0BL
Symbol
Output
Fanin Symbol Fanout
Block
type
IN
Path
→ OUT
A3 → COUTB (HL)
(LH)
(HH)
A3 → X
(LL)
(HH)
A3 → Y
(LL)
(HH)
B3 → F3
(HL)
(LH)
(LL)
B3 → COUTB (HL)
(LH)
(HH)
B3 → X
(LL)
(HH)
B3 → Y
(LL)
(HH)
CINB → F0
(HL)
(LH)
(LL)
(HH)
CINB → F1
(HL)
(LH)
(LL)
(HH)
CINB → F2
(HL)
(LH)
(LL)
(HH)
CINB → F3
(HL)
(LH)
(LL)
CINB → COUTB (HH)
(LL)
2 - 196
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.590
0.466
0.279
0.277
0.526
0.430
0.434
0.464
0.427
0.468
0.605
0.452
0.278
0.277
0.542
0.416
0.382
0.413
0.353
0.361
0.554
0.571
0.531
0.546
0.676
0.696
0.643
0.666
0.743
0.766
0.717
0.742
0.625
0.437
1.012
0.757
0.436
0.464
0.903
0.692
0.807
0.866
0.895
0.857
1.032
0.753
0.435
0.465
0.923
0.688
0.611
0.667
0.567
0.577
0.893
0.930
0.867
0.890
1.123
1.164
1.077
1.115
1.235
1.275
1.205
1.244
1.068
0.693
2.186
1.424
0.812
0.972
1.954
1.292
1.562
1.672
1.720
1.691
2.221
1.485
0.811
0.971
1.993
1.352
1.119
1.203
1.058
1.047
1.646
1.714
1.635
1.644
2.165
2.228
2.128
2.157
2.389
2.448
2.402
2.427
2.233
1.242
0.015
0.011
0.011
0.026
0.011
0.010
0.011
0.010
0.011
0.010
0.015
0.011
0.011
0.026
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.015
0.020
0.015
0.015
0.037
0.016
0.013
0.015
0.013
0.015
0.013
0.020
0.015
0.015
0.037
0.016
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.020
0.030
0.021
0.021
0.061
0.023
0.017
0.022
0.018
0.022
0.018
0.030
0.021
0.021
0.061
0.023
0.017
0.022
0.018
0.021
0.017
0.022
0.018
0.021
0.018
0.022
0.018
0.021
0.018
0.022
0.018
0.021
0.018
0.023
0.031
Block Library
A13872EJ5V0BL
Symbol
Output
Fanin Symbol Fanout
2 - 197
Chapter 2 Function Block
Chapter 2 Function Block
3-State Buffer
Function
Buffer type
Block type
with EN
Drivability
Name
Inverter type
with ENB
cells
Name
Block
type
with EN
cells
with ENB
L531
Name
cells
Name
cells
A → Y
EN → Y
Low Power
L531
4
L532
4
x1
F531
5
F532
5
F541
6
F542
6
x2
F533
7
F534
7
F543
8
F544
8
x4
F53F
11
F53G
11
F54F
12
F54G
12
F531
x8
A → Y
EN → Y
Logic Diagram for "Buffer with EN"
Logic Diagram for "Buffer with ENB"
F533
A
IN
Path
→ OUT
H01
N01
A
Y
H01
N01
EN → Y
Y
F53F
ENB H02
EN H02
A → Y
A → Y
EN → Y
L532
Logic Diagram for "Inverter with EN"
A
H01
Logic Diagram for "Inverter with ENB"
N01
Y
A
H01
N01
A → Y
ENB → Y
Y
F532
A → Y
ENB → Y
ENB H02
EN H02
F534
A → Y
ENB → Y
Truth Table
F53G
With EN
A → Y
With ENB
A
EN
Y
Y*
A
ENB
Y
Y*
0
1
0
1
0
0
0
1
1
1
1
0
1
0
1
0
X
0
Z
Z
X
1
Z
Z
ENB → Y
F541
A → Y
EN → Y
X:Irrelevant
Z:High Impedance
*:Inverter type
Block Library
A13872EJ5V0BL
2 - 198
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HL)
(LH)
(HZ)
(LZ)
(ZH)
(ZL)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.164
0.176
0.346
0.221
0.291
0.254
0.143
0.164
0.337
0.231
0.271
0.244
0.173
0.194
0.402
0.260
0.289
0.265
0.230
0.262
0.532
0.329
0.328
0.320
0.157
0.185
0.284
0.293
0.215
0.315
0.141
0.167
0.286
0.301
0.196
0.297
0.170
0.200
0.336
0.335
0.209
0.322
0.225
0.271
0.444
0.414
0.242
0.388
0.252
0.213
0.347
0.233
0.278
0.246
0.255
0.273
0.500
0.339
0.465
0.416
0.222
0.249
0.499
0.349
0.432
0.392
0.263
0.295
0.583
0.389
0.469
0.429
0.343
0.404
0.754
0.478
0.541
0.522
0.245
0.287
0.395
0.445
0.351
0.529
0.218
0.254
0.402
0.452
0.324
0.497
0.256
0.304
0.471
0.497
0.350
0.539
0.334
0.420
0.620
0.596
0.413
0.652
0.390
0.351
0.509
0.352
0.443
0.395
0.463
0.492
0.832
0.608
0.858
0.775
0.437
0.397
0.875
0.589
0.837
0.671
0.538
0.453
1.044
0.627
0.940
0.702
0.738
0.599
1.380
0.721
1.140
0.801
0.446
0.513
0.610
0.783
0.664
1.010
0.430
0.404
0.667
0.761
0.652
0.894
0.524
0.467
0.819
0.810
0.742
0.934
0.713
0.628
1.133
0.914
0.931
1.053
0.643
0.723
0.888
0.594
0.852
0.678
0.022
0.020
0.030
0.025
0.042
0.035
0.022
0.020
0.011
0.010
0.030
0.025
0.015
0.013
0.042
0.035
0.022
0.017
0.011
0.010
0.006
0.005
0.015
0.013
0.008
0.007
0.022
0.018
0.011
0.009
0.006
0.005
0.003
0.003
0.008
0.007
0.004
0.004
0.011
0.009
0.006
0.005
0.003
0.003
0.022
0.020
0.004
0.004
0.030
0.025
0.006
0.005
0.042
0.035
0.022
0.020
0.011
0.010
0.030
0.025
0.015
0.013
0.042
0.035
0.022
0.017
0.011
0.010
0.006
0.005
0.015
0.013
0.008
0.007
0.022
0.018
0.011
0.009
0.006
0.005
0.003
0.003
0.008
0.007
0.004
0.004
0.011
0.009
0.006
0.005
0.003
0.003
0.010
0.011
0.004
0.004
0.013
0.015
0.006
0.005
0.017
0.022
0.011
0.010
0.015
0.013
0.022
0.018
Block Library
A13872EJ5V0BL
Symbol
A
EN
Y
Output
Fanin Symbol Fanout
2.1
1.0
0.5
Y
17
A
EN
Y
2.1
1.0
0.5
Y
34
A
EN
Y
2.1
1.0
1.0
Y
67
A
EN
Y
2.1
1.0
2.7
Y
125
A
ENB
Y
2.1
1.0
0.5
Y
17
A
ENB
Y
2.1
1.0
0.5
Y
34
A
ENB
Y
2.1
1.0
1.0
Y
67
A
ENB
Y
2.1
1.0
2.7
Y
126
A
EN
Y
1.0
1.0
0.5
Y
34
2 - 199
Chapter 2 Function Block
Block
type
F543
IN
Path
→ OUT
A → Y
EN → Y
F54F
A → Y
EN → Y
F542
A → Y
ENB → Y
F544
A → Y
ENB → Y
F54G
A → Y
ENB → Y
(HL)
(LH)
(HZ)
(LZ)
(ZH)
(ZL)
(HL)
(LH)
(HZ)
(LZ)
(ZH)
(ZL)
(HL)
(LH)
(HZ)
(LZ)
(ZH)
(ZL)
(HL)
(LH)
(HZ)
(LZ)
(ZH)
(ZL)
(HL)
(LH)
(HZ)
(LZ)
(ZH)
(ZL)
Chapter 2 Function Block
[MEMO]
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.284
0.236
0.398
0.272
0.293
0.275
0.355
0.285
0.507
0.347
0.326
0.334
0.252
0.213
0.295
0.303
0.202
0.299
0.284
0.236
0.347
0.340
0.216
0.327
0.355
0.285
0.457
0.414
0.249
0.391
0.442
0.387
0.582
0.404
0.474
0.443
0.556
0.466
0.732
0.500
0.538
0.543
0.390
0.351
0.410
0.456
0.330
0.498
0.442
0.387
0.483
0.504
0.360
0.547
0.556
0.466
0.631
0.597
0.424
0.650
0.708
0.822
1.046
0.648
0.945
0.724
0.864
1.020
1.364
0.753
1.133
0.833
0.643
0.723
0.675
0.767
0.663
0.899
0.708
0.822
0.832
0.819
0.758
0.945
0.863
1.020
1.146
0.915
0.949
1.055
0.005
0.006
0.007
0.008
0.009
0.011
0.006
0.005
0.003
0.003
0.008
0.007
0.004
0.004
0.011
0.009
0.005
0.006
0.003
0.003
0.010
0.011
0.004
0.004
0.013
0.015
0.006
0.005
0.017
0.022
0.011
0.010
0.005
0.006
0.015
0.013
0.007
0.008
0.022
0.018
0.009
0.011
0.006
0.005
0.003
0.003
0.008
0.007
0.004
0.004
0.011
0.009
0.005
0.006
0.003
0.003
0.004
0.004
0.006
0.005
Block Library
A13872EJ5V0BL
Symbol
A
EN
Y
Output
Fanin Symbol Fanout
1.0
1.0
1.0
Y
67
A
EN
Y
1.0
1.0
2.6
Y
125
A
ENB
Y
1.0
1.0
0.5
Y
34
A
ENB
Y
1.0
1.0
1.0
Y
67
A
ENB
Y
1.0
1.0
2.6
Y
125
2 - 200
Block Library
A13872EJ5V0BL
2 - 201
Chapter 2 Function Block
Chapter 2 Function Block
2 to 4 Decoder
Function
Positive output type
Block type
Normal
Drivability
Name
with ENB
cells
Name
Negative output type
with EN
cells
Block
type
Name
Normal
cells
Name
with ENB
cells
Low Power
L560
6
L561
6
x1
F560
10
F561
10
Name
cells
with EN
Name
L560
cells
IN
Path
→ OUT
A → Y0
A → Y1
A → Y2
x2
A → Y3
x4
Logic Diagram
B → Y0
for "Positive output type"
for "Positive output with ENB"
for "Positive output with EN"
B → Y1
A
B
H01
H02
N01
N02
N03
N04
Y0
Y1
Y2
Y3
B → Y2
B → Y3
F560
A → Y0
A → Y1
A → Y2
A → Y3
for "Negative output type"
for "Negative output with ENB"
B → Y0
for "Negative output with EN"
B → Y1
A H01
B H02
N01
N02
N03
N04
Y0B
Y1B
Y2B
Y3B
B → Y2
B → Y3
L561
A → Y0B
A → Y1B
A → Y2B
A → Y3B
Truth Table
B → Y0B
A
B
ENB
Y0
Y1
Y2
Y3
Y0B
Y1B
Y2B
Y3B
B → Y1B
0
0
0
1
0
0
0
0
1
1
1
B → Y2B
1
0
0
0
1
0
0
1
0
1
1
0
1
0
0
0
1
0
1
1
0
1
1
1
0
0
0
0
1
1
1
1
0
X
X
1
0
0
0
0
1
1
1
1
B → Y3B
F561
A → Y0B
A → Y1B
X:Irrelevant
A → Y2B
A → Y3B
Block Library
A13872EJ5V0BL
2 - 202
(HL)
(LH)
(HH)
(LL)
(HL)
(LH)
(HH)
(LL)
(HL)
(LH)
(HL)
(LH)
(HH)
(LL)
(HH)
(LL)
(HL)
(LH)
(HH)
(LL)
(HL)
(LH)
(HH)
(LL)
(HL)
(LH)
(HL)
(LH)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HL)
(LH)
(HH)
(LL)
(HL)
(LH)
(HH)
(LL)
(HH)
(LL)
(HL)
(LH)
(HL)
(LH)
(HH)
(LL)
(HL)
(LH)
(HH)
(LL)
(HL)
(LH)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.273
0.261
0.193
0.182
0.275
0.264
0.193
0.182
0.291
0.268
0.291
0.268
0.196
0.198
0.193
0.196
0.258
0.276
0.372
0.334
0.263
0.281
0.368
0.330
0.291
0.280
0.294
0.283
0.375
0.364
0.370
0.359
0.175
0.194
0.283
0.244
0.175
0.194
0.280
0.242
0.192
0.186
0.194
0.188
0.283
0.266
0.282
0.265
0.332
0.391
0.320
0.238
0.332
0.391
0.320
0.237
0.419
0.420
0.288
0.285
0.421
0.424
0.288
0.285
0.444
0.437
0.444
0.437
0.302
0.309
0.298
0.307
0.392
0.450
0.590
0.537
0.399
0.457
0.585
0.532
0.432
0.441
0.436
0.446
0.576
0.575
0.569
0.569
0.257
0.311
0.441
0.392
0.257
0.310
0.437
0.389
0.279
0.285
0.281
0.289
0.425
0.419
0.426
0.418
0.514
0.634
0.496
0.378
0.514
0.634
0.496
0.378
0.730
0.771
0.488
0.507
0.733
0.777
0.488
0.507
0.781
0.834
0.781
0.834
0.550
0.556
0.544
0.552
0.685
0.876
1.111
0.990
0.694
0.887
1.102
0.984
0.725
0.817
0.731
0.825
1.046
1.028
1.035
1.019
0.431
0.585
0.809
0.721
0.431
0.585
0.805
0.718
0.452
0.509
0.455
0.514
0.744
0.749
0.744
0.749
0.919
1.171
0.882
0.692
0.919
1.171
0.882
0.692
0.020
0.038
0.038
0.020
0.020
0.038
0.038
0.020
0.020
0.038
0.020
0.038
0.038
0.020
0.038
0.020
0.010
0.011
0.011
0.010
0.010
0.011
0.011
0.010
0.010
0.011
0.010
0.011
0.011
0.010
0.011
0.010
0.022
0.030
0.030
0.022
0.022
0.030
0.030
0.022
0.022
0.029
0.022
0.029
0.029
0.022
0.029
0.022
0.011
0.010
0.010
0.011
0.011
0.010
0.010
0.011
0.025
0.053
0.053
0.025
0.025
0.053
0.053
0.025
0.025
0.053
0.025
0.053
0.053
0.025
0.053
0.025
0.012
0.015
0.016
0.012
0.012
0.015
0.015
0.012
0.012
0.015
0.013
0.016
0.015
0.013
0.015
0.012
0.030
0.041
0.041
0.030
0.030
0.041
0.041
0.030
0.030
0.040
0.030
0.040
0.040
0.029
0.040
0.029
0.015
0.013
0.013
0.015
0.015
0.013
0.013
0.015
0.033
0.077
0.077
0.034
0.033
0.077
0.077
0.034
0.034
0.077
0.034
0.077
0.077
0.034
0.077
0.034
0.017
0.022
0.022
0.017
0.017
0.022
0.022
0.017
0.017
0.022
0.017
0.022
0.022
0.017
0.022
0.017
0.042
0.062
0.062
0.042
0.042
0.062
0.062
0.042
0.042
0.062
0.042
0.061
0.061
0.042
0.061
0.042
0.021
0.018
0.018
0.021
0.021
0.018
0.018
0.021
Block Library
A13872EJ5V0BL
Symbol
A
B
Output
Fanin Symbol Fanout
1.0
1.0
Y0
Y1
Y2
Y3
8
8
8
8
A
B
1.0
1.0
Y0
Y1
Y2
Y3
34
34
34
34
A
B
1.0
1.0
Y0B
Y1B
Y2B
Y3B
13
13
13
13
A
B
1.0
1.0
Y0B
Y1B
Y2B
Y3B
35
35
35
35
2 - 203
Chapter 2 Function Block
Block
type
IN
Path
→ OUT
B → Y0B
B → Y1B
B → Y2B
B → Y3B
(HH)
(LL)
(HH)
(LL)
(HL)
(LH)
(HL)
(LH)
Chapter 2 Function Block
[MEMO]
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.361
0.405
0.361
0.405
0.322
0.259
0.322
0.259
0.558
0.662
0.558
0.661
0.508
0.413
0.508
0.412
1.002
1.249
1.002
1.250
0.943
0.760
0.943
0.759
0.011
0.010
0.011
0.010
0.010
0.011
0.010
0.011
0.015
0.013
0.015
0.013
0.013
0.015
0.013
0.015
0.021
0.018
0.021
0.018
0.018
0.021
0.018
0.021
Block Library
A13872EJ5V0BL
Symbol
Output
Fanin Symbol Fanout
2 - 204
Block Library
A13872EJ5V0BL
2 - 205
Chapter 2 Function Block
Chapter 2 Function Block
2 to 1 Multiplexer (Positive Out)
Function
High-speed type
Standard type
Block type
Normal
Drivability
Name
with ENB
cells
Name
with EN
cells
Low Power
L565
3
L571
4
x1
F565
4
F571
6
Block
type
Name
cells
Normal
Name
cells
with ENB
Name
cells
with EN
Name
L565
cells
IN
Path
→ OUT
D0 → Y
D1 → Y
A → Y
x2
x4
Logic Diagram
F565
for "Standard type"
for "Standard type with ENB"
D0 → Y
for "Standard type with EN"
D1 → Y
D0 H01
D1 H02
D0 H01
A → Y
D1 H02
N01 Y
N01 Y
A H03
A H03
L571
ENB H04
D0 → Y
D1 → Y
A → Y
for "High-speed typee"
for "High-speed type with ENB"
ENB → Y
for "High-speed type with EN"
F571
D0 → Y
D1 → Y
A → Y
ENB → Y
(HH)
(LL)
(HH)
(LL)
(HH)
(HL)
(LH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(HL)
(LH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(HL)
(LH)
(LL)
(HL)
(LH)
(HH)
(LL)
(HH)
(LL)
(HH)
(HL)
(LH)
(LL)
(HL)
(LH)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.222
0.230
0.221
0.223
0.159
0.217
0.184
0.181
0.227
0.233
0.225
0.231
0.270
0.277
0.244
0.276
0.226
0.216
0.231
0.219
0.271
0.261
0.242
0.265
0.093
0.065
0.375
0.344
0.373
0.343
0.414
0.386
0.385
0.387
0.227
0.218
0.340
0.377
0.337
0.372
0.248
0.329
0.297
0.275
0.345
0.385
0.342
0.383
0.436
0.441
0.395
0.460
0.354
0.363
0.360
0.369
0.447
0.405
0.398
0.445
0.128
0.114
0.607
0.578
0.604
0.575
0.693
0.619
0.645
0.653
0.354
0.355
0.616
0.707
0.608
0.701
0.428
0.581
0.555
0.482
0.631
0.729
0.627
0.724
0.813
0.786
0.747
0.877
0.651
0.690
0.659
0.700
0.836
0.716
0.751
0.846
0.195
0.263
1.181
1.110
1.176
1.106
1.356
1.129
1.274
1.254
0.604
0.678
0.022
0.020
0.022
0.020
0.022
0.020
0.022
0.020
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.038
0.020
0.038
0.020
0.038
0.020
0.038
0.020
0.020
0.037
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.010
0.011
0.030
0.026
0.030
0.026
0.030
0.026
0.030
0.026
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.053
0.026
0.053
0.026
0.053
0.026
0.053
0.026
0.024
0.053
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.012
0.015
0.042
0.035
0.042
0.035
0.042
0.035
0.042
0.035
0.022
0.019
0.022
0.019
0.022
0.018
0.022
0.019
0.077
0.036
0.077
0.036
0.077
0.035
0.078
0.035
0.033
0.077
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.017
0.022
Symbol
D0
D1
A
Output
Fanin Symbol Fanout
1.0
1.0
2.1
Y
16
D0
D1
A
1.0
1.0
1.0
Y
34
D0
D1
A
ENB
1.0
1.0
1.0
1.0
Y
8
D0
D1
A
ENB
1.0
1.0
1.0
1.0
Y
34
Truth Table
D0
D1
A
ENB
Y
X
X
X
1
0
YB
1
A
X
0
0
A
AB
X
B
1
0
B
BB
X:Irrelevant
Block Library
A13872EJ5V0BL
2 - 206
Block Library
A13872EJ5V0BL
2 - 207
Chapter 2 Function Block
Chapter 2 Function Block
4 to 1 Multiplexer (Positive Out)
Function
High-speed type
Standard type
Block type
Normal
Drivability
with ENB
with EN
Name
cells
Name
cells
F564
8
F570
10
Block
type
Name
Normal
cells
Name
cells
with ENB
Name
cells
with EN
Name
F564
cells
IN
Path
→ OUT
D0 → Y
D1 → Y
Low Power
x1
D2 → Y
x2
D3 → Y
x4
Logic Diagram
A → Y
for "Standard type"
D0
D1
D2
D3
H01
H02
H03
H04
for "Standard type with ENB"
D0
D1
D2
D3
A
B
ENB
N01 Y
A H05
B H06
H01
H02
H03
H04
H05
H06
H07
for "Standard type with EN"
B → Y
N01 Y
F570
D0 → Y
D1 → Y
D2 → Y
D3 → Y
for "High-speed typee"
for "High-speed type with ENB"
for "High-speed type with EN"
A → Y
B → Y
ENB → Y
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(HL)
(LH)
(LL)
(HH)
(HL)
(LH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(HL)
(LH)
(LL)
(HH)
(HL)
(LH)
(LL)
(HL)
(LH)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.332
0.338
0.331
0.335
0.331
0.336
0.326
0.330
0.404
0.403
0.370
0.398
0.291
0.284
0.262
0.283
0.480
0.442
0.479
0.440
0.475
0.437
0.476
0.439
0.550
0.510
0.516
0.506
0.440
0.399
0.406
0.398
0.227
0.218
0.534
0.584
0.531
0.579
0.530
0.581
0.525
0.572
0.673
0.686
0.631
0.697
0.473
0.460
0.425
0.483
0.789
0.766
0.786
0.764
0.779
0.758
0.782
0.761
0.927
0.873
0.884
0.885
0.733
0.647
0.678
0.680
0.353
0.355
1.046
1.161
1.043
1.151
1.044
1.158
1.034
1.143
1.313
1.320
1.259
1.391
0.897
0.833
0.812
0.921
1.580
1.532
1.577
1.529
1.566
1.520
1.572
1.526
1.847
1.691
1.787
1.771
1.440
1.177
1.341
1.309
0.603
0.677
0.011
0.011
0.011
0.011
0.011
0.011
0.011
0.011
0.011
0.011
0.011
0.011
0.011
0.011
0.011
0.011
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.010
0.011
0.016
0.015
0.016
0.015
0.016
0.015
0.016
0.015
0.016
0.015
0.016
0.015
0.016
0.014
0.016
0.015
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.012
0.015
0.023
0.021
0.023
0.021
0.023
0.021
0.023
0.021
0.023
0.021
0.023
0.021
0.023
0.020
0.023
0.021
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.017
0.022
Symbol
D0
D1
D2
D3
A
B
D0
D1
D2
D3
A
B
ENB
Output
Fanin Symbol Fanout
1.0
1.0
1.0
1.0
1.0
1.0
Y
32
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Y
34
Truth Table
D0
D1
D2
D3
A
B
ENB
Y
X
X
X
X
X
X
1
0
YB
1
A
X
X
X
0
0
0
A
AB
X
B
X
X
1
0
0
B
BB
X
X
C
X
0
1
0
C
CB
X
X
X
D
1
1
0
D
DB
X:Irrelevant
Block Library
A13872EJ5V0BL
2 - 208
Block Library
A13872EJ5V0BL
2 - 209
Chapter 2 Function Block
Chapter 2 Function Block
8 to 1 Multiplexer (Positive Out)
Function
Normal
Drivability
High-speed type
Standard type
Block type
with ENB
with EN
Name
cells
Name
cells
F563
18
F569
18
Block
type
Name
Normal
cells
Name
with ENB
cells
Name
cells
with EN
Name
F563
cells
IN
Path
→ OUT
D0 → Y
D1 → Y
Low Power
x1
D2 → Y
x2
D3 → Y
x4
Logic Diagram
D4 → Y
for "Standard type"
for "Standard type with ENB"
for "Standard type with EN"
D5 → Y
D0
D1
D2
D3
D4
D5
D6
D7
A
B
C
H01
H02
H03
H04
H05
H06
H07
H08
H09
H10
H11
D0
D1
D2
D3
D4
D5
D6
D7
A
B
C
ENB
N01 Y
for "High-speed typee"
H01
H02
H03
H04
H05
H06
H07
H08
H09
H10
H11
H12
D6 → Y
D7 → Y
N01 Y
A → Y
B → Y
for "High-speed type with ENB"
C → Y
for "High-speed type with EN"
F569
D0 → Y
D1 → Y
D2 → Y
D3 → Y
D4 → Y
D5 → Y
Truth Table
D6 → Y
D0
D1
D2
D3
D4
D5
D6
D7
A
B
C
ENB
Y
YB
X
X
X
X
X
X
X
X
X
X
X
1
0
1
A
X
X
X
X
X
X
X
0
0
0
0
A
AB
X
B
X
X
X
X
X
X
1
0
0
0
B
BB
X
X
C
X
X
X
X
X
0
1
0
0
C
CB
X
X
X
D
X
X
X
X
1
1
0
0
D
DB
X
X
X
X
E
X
X
X
0
0
1
0
E
EB
X
X
X
X
X
F
X
X
1
0
1
0
F
FB
X
X
X
X
X
X
G
X
0
1
1
0
G
GB
X
X
X
X
X
X
X
H
1
1
1
0
H
HB
D7 → Y
A → Y
B → Y
C → Y
X:Irrelevant
Block Library
A13872EJ5V0BL
2 - 210
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(HL)
(LH)
(LL)
(HH)
(HL)
(LH)
(LL)
(HH)
(HL)
(LH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(HL)
(LH)
(LL)
(HH)
(HL)
(LH)
(LL)
(HH)
(HL)
(LH)
(LL)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.479
0.522
0.476
0.520
0.477
0.521
0.472
0.516
0.475
0.520
0.471
0.515
0.472
0.516
0.467
0.511
0.610
0.645
0.557
0.643
0.459
0.472
0.418
0.477
0.320
0.393
0.371
0.314
0.603
0.562
0.601
0.562
0.596
0.556
0.597
0.557
0.588
0.551
0.587
0.548
0.585
0.545
0.586
0.546
0.749
0.702
0.699
0.698
0.593
0.540
0.553
0.539
0.352
0.338
0.355
0.310
0.780
0.920
0.777
0.919
0.778
0.917
0.771
0.908
0.776
0.915
0.770
0.905
0.771
0.909
0.763
0.899
1.023
1.110
0.963
1.146
0.762
0.760
0.697
0.836
0.509
0.627
0.610
0.513
1.012
0.977
1.013
0.976
1.003
0.967
1.005
0.969
0.992
0.960
0.991
0.958
0.987
0.951
0.990
0.954
1.265
1.175
1.199
1.214
1.006
0.878
0.942
0.931
0.572
0.553
0.610
0.506
1.536
1.862
1.533
1.852
1.536
1.856
1.525
1.841
1.530
1.847
1.521
1.833
1.523
1.838
1.513
1.822
1.997
2.122
1.913
2.304
1.479
1.433
1.359
1.642
0.926
1.153
1.144
0.958
2.032
1.950
2.032
1.948
2.018
1.934
2.020
1.937
2.000
1.920
2.000
1.918
1.994
1.907
1.997
1.911
2.504
2.221
2.415
2.408
1.984
1.620
1.870
1.802
1.090
1.033
1.220
0.952
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.021
0.017
0.021
0.017
0.021
0.017
0.021
0.017
0.021
0.017
0.021
0.017
0.021
0.017
0.021
0.017
0.021
0.017
0.021
0.017
0.021
0.017
0.021
0.017
0.021
0.017
0.021
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
Block Library
A13872EJ5V0BL
Symbol
D0
D1
D2
D3
D4
D5
D6
D7
A
B
C
D0
D1
D2
D3
D4
D5
D6
D7
A
B
C
ENB
Output
Fanin Symbol Fanout
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Y
35
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Y
34
2 - 211
Chapter 2 Function Block
Block
type
IN
Path
→ OUT
ENB → Y
(HL)
(LH)
Chapter 2 Function Block
[MEMO]
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.221
0.209
0.348
0.347
0.597
0.663
0.010
0.011
0.012
0.015
0.017
0.022
Block Library
A13872EJ5V0BL
Symbol
Output
Fanin Symbol Fanout
2 - 212
Block Library
A13872EJ5V0BL
2 - 213
Chapter 2 Function Block
Chapter 2 Function Block
Quad 2 to 1 Multiplexer (Negative Out)
Function
High-speed type
Standard type
Block type
Normal
Drivability
Name
cells
with ENB
Name
with EN
cells
Low Power
L572
15
x1
F572
17
Block
type
Name
cells
Normal
Name
cells
with ENB
Name
cells
with EN
Name
L572
cells
IN
Path
→ OUT
D0 → Y0B
D1 → Y0B
D2 → Y1B
x2
D3 → Y1B
x4
Logic Diagram
D4 → Y2B
for "Standard type"
for "Standard type with ENB"
for "Standard type with EN"
D5 → Y2B
D0
D1
D2
D3
D4
D5
D6
D7
A
ENB
for "High-speed typee"
H01
H02
H03
H04
H05
H06
H07
H08
H09
H10
D6 → Y3B
N01 Y0B
N02 Y1B
D7 → Y3B
N03 Y2B
A → Y0B
N04 Y3B
A → Y1B
for "High-speed type with ENB"
A → Y2B
for "High-speed type with EN"
A → Y3B
ENB → Y0B
ENB → Y1B
ENB → Y2B
ENB → Y3B
Truth Table
F572
D0 → Y0B
Da
Da+1
A
ENB
Yn
YnB
D1 → Y0B
A
X
0
0
A
AB
D2 → Y1B
X
B
1
0
B
BB
X
X
X
1
0
1
D3 → Y1B
D4 → Y2B
X:Irrelevant
a=2*n(n=0 to 3)
D5 → Y2B
D6 → Y3B
D7 → Y3B
Block Library
A13872EJ5V0BL
2 - 214
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HH)
(HL)
(LH)
(LL)
(HH)
(HL)
(LH)
(LL)
(HH)
(HL)
(LH)
(LL)
(HH)
(HL)
(LH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
(HL)
(LH)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.328
0.253
0.332
0.256
0.328
0.254
0.334
0.257
0.328
0.254
0.334
0.257
0.327
0.253
0.331
0.257
0.388
0.493
0.415
0.427
0.392
0.494
0.416
0.430
0.391
0.494
0.416
0.429
0.388
0.493
0.415
0.427
0.137
0.172
0.135
0.169
0.136
0.170
0.137
0.172
0.354
0.266
0.358
0.270
0.357
0.269
0.363
0.273
0.355
0.266
0.358
0.270
0.357
0.269
0.361
0.273
0.524
0.434
0.529
0.439
0.524
0.435
0.531
0.442
0.524
0.435
0.530
0.442
0.524
0.433
0.529
0.438
0.590
0.805
0.706
0.706
0.596
0.807
0.708
0.711
0.595
0.807
0.708
0.710
0.590
0.805
0.706
0.706
0.219
0.285
0.217
0.281
0.217
0.282
0.219
0.285
0.565
0.454
0.568
0.458
0.568
0.456
0.575
0.465
0.565
0.454
0.569
0.459
0.568
0.456
0.572
0.461
0.978
0.846
0.985
0.853
0.980
0.848
0.987
0.860
0.979
0.847
0.990
0.858
0.978
0.846
0.984
0.852
1.052
1.520
1.350
1.343
1.062
1.523
1.354
1.350
1.060
1.522
1.354
1.349
1.052
1.520
1.350
1.343
0.380
0.587
0.379
0.582
0.379
0.583
0.380
0.587
1.050
0.878
1.058
0.886
1.053
0.883
1.065
0.897
1.050
0.878
1.058
0.886
1.053
0.883
1.059
0.890
0.020
0.021
0.020
0.021
0.020
0.022
0.020
0.021
0.020
0.021
0.020
0.022
0.020
0.021
0.020
0.021
0.023
0.020
0.023
0.020
0.023
0.020
0.023
0.020
0.023
0.020
0.023
0.020
0.023
0.020
0.023
0.020
0.023
0.020
0.023
0.020
0.023
0.020
0.023
0.020
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.025
0.029
0.025
0.029
0.025
0.030
0.025
0.029
0.025
0.029
0.025
0.030
0.025
0.029
0.025
0.029
0.032
0.026
0.032
0.026
0.032
0.025
0.032
0.025
0.032
0.025
0.032
0.025
0.032
0.026
0.032
0.026
0.032
0.025
0.032
0.025
0.032
0.025
0.032
0.025
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.034
0.042
0.034
0.042
0.034
0.042
0.034
0.042
0.034
0.042
0.034
0.042
0.034
0.042
0.034
0.042
0.044
0.035
0.044
0.035
0.044
0.035
0.044
0.035
0.044
0.035
0.044
0.035
0.044
0.035
0.044
0.035
0.044
0.035
0.044
0.035
0.044
0.035
0.044
0.035
0.018
0.021
0.018
0.021
0.018
0.021
0.018
0.021
0.018
0.021
0.018
0.021
0.018
0.021
0.018
0.021
Block Library
A13872EJ5V0BL
Symbol
D0
D1
D2
D3
D4
D5
D6
D7
A
ENB
D0
D1
D2
D3
D4
D5
D6
D7
A
ENB
Output
Fanin Symbol Fanout
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
4.7
Y0B
Y1B
Y2B
Y3B
16
16
16
16
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
4.7
Y0B
Y1B
Y2B
Y3B
34
34
34
34
2 - 215
Chapter 2 Function Block
Block
type
IN
Path
→ OUT
A → Y0B
A → Y1B
A → Y2B
A → Y3B
ENB → Y0B
ENB → Y1B
ENB → Y2B
ENB → Y3B
(HH)
(HL)
(LH)
(LL)
(HH)
(HL)
(LH)
(LL)
(HH)
(HL)
(LH)
(LL)
(HH)
(HL)
(LH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
Chapter 2 Function Block
[MEMO]
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.401
0.525
0.433
0.457
0.404
0.528
0.434
0.461
0.401
0.526
0.433
0.458
0.404
0.528
0.435
0.461
0.149
0.196
0.149
0.196
0.149
0.196
0.149
0.196
0.605
0.853
0.730
0.752
0.609
0.856
0.733
0.757
0.605
0.853
0.730
0.753
0.610
0.856
0.733
0.757
0.226
0.323
0.226
0.323
0.226
0.323
0.226
0.323
1.079
1.601
1.389
1.419
1.085
1.606
1.393
1.426
1.079
1.602
1.389
1.419
1.086
1.606
1.393
1.426
0.385
0.654
0.385
0.654
0.385
0.654
0.385
0.654
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.021
0.018
0.021
0.018
0.021
0.018
0.021
0.018
0.021
0.018
0.021
0.018
0.021
0.018
0.021
0.018
0.021
0.018
0.021
0.018
0.021
0.018
0.021
0.018
Block Library
A13872EJ5V0BL
Symbol
Output
Fanin Symbol Fanout
2 - 216
Block Library
A13872EJ5V0BL
2 - 217
Chapter 2 Function Block
Chapter 2 Function Block
8-Bit Odd Parity Generator
Function
Block
type
Standard type
Block type
Normal
Drivability
High speed
Name
cells
F581
19
Name
F581
IN
Path
→ OUT
A → YO
cells
Low Power
x1
B → YO
x2
x4
C → YO
Logic Diagram
A
B
C
D
E
F
G
H
H01
H02
H03
H04
H05
H06
H07
H08
D → YO
E → YO
F → YO
N01
YO
G → YO
H → YO
Truth Table
A
B
C
D
E
F
G
H
YO
Σ of 1’s at A through H is Odd
1
Σ of 1’s at A through H is Even
0
Block Library
A13872EJ5V0BL
2 - 218
(HH)
(HL)
(LH)
(LL)
(HH)
(HL)
(LH)
(LL)
(HH)
(HL)
(LH)
(LL)
(HH)
(HL)
(LH)
(LL)
(HH)
(HL)
(LH)
(LL)
(HH)
(HL)
(LH)
(LL)
(HH)
(HL)
(LH)
(LL)
(HH)
(HL)
(LH)
(LL)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.568
0.560
0.626
0.606
0.601
0.544
0.623
0.599
0.554
0.561
0.616
0.593
0.588
0.544
0.611
0.585
0.561
0.565
0.618
0.606
0.592
0.549
0.616
0.599
0.556
0.577
0.618
0.614
0.592
0.561
0.612
0.607
0.974
0.935
1.110
0.992
1.035
0.914
1.077
1.035
0.935
0.930
1.076
0.958
1.002
0.908
1.041
0.998
0.945
0.934
1.080
0.983
1.008
0.912
1.048
1.023
0.919
0.942
1.058
0.979
0.985
0.920
1.023
1.021
2.017
1.849
2.373
1.838
2.203
1.823
2.246
2.017
1.881
1.810
2.251
1.748
2.071
1.783
2.111
1.926
1.894
1.817
2.252
1.792
2.078
1.790
2.120
1.973
1.773
1.797
2.141
1.747
1.968
1.770
1.999
1.926
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
Block Library
A13872EJ5V0BL
Symbol
A
B
C
D
E
F
G
H
Output
Fanin Symbol Fanout
1.7
2.0
1.7
2.0
1.7
2.0
1.7
2.0
YO
2 - 219
33
Chapter 2 Function Block
Chapter 2 Function Block
8-Bit Even Parity Generator
Function
Block
type
Standard type
Block type
Normal
Drivability
High speed
Name
cells
F582
19
Name
F582
IN
Path
→ OUT
A → YE
cells
Low Power
x1
B → YE
x2
x4
C → YE
Logic Diagram
A
B
C
D
E
F
G
H
H01
H02
H03
H04
H05
H06
H07
H08
D → YE
E → YE
F → YE
N01
YE
G → YE
H → YE
Truth Table
A
B
C
D
E
F
G
H
YE
Σ of 1’s at A through H is Odd
0
Σ of 1’s at A through H is Even
1
Block Library
A13872EJ5V0BL
2 - 220
(HH)
(HL)
(LH)
(LL)
(HH)
(HL)
(LH)
(LL)
(HH)
(HL)
(LH)
(LL)
(HH)
(HL)
(LH)
(LL)
(HH)
(HL)
(LH)
(LL)
(HH)
(HL)
(LH)
(LL)
(HH)
(HL)
(LH)
(LL)
(HH)
(HL)
(LH)
(LL)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.538
0.533
0.584
0.591
0.522
0.566
0.578
0.588
0.540
0.524
0.571
0.586
0.523
0.559
0.563
0.582
0.553
0.622
0.595
0.681
0.537
0.655
0.589
0.678
0.564
0.622
0.601
0.683
0.548
0.659
0.595
0.678
0.913
0.913
0.969
1.049
0.891
0.975
1.013
1.017
0.907
0.886
0.935
1.026
0.885
0.952
0.976
0.992
0.923
1.038
0.972
1.175
0.901
1.102
1.013
1.141
0.929
1.023
0.965
1.162
0.907
1.089
1.007
1.127
1.875
1.859
1.864
2.213
1.847
2.046
2.043
2.086
1.835
1.743
1.774
2.115
1.809
1.934
1.950
1.975
1.841
1.985
1.816
2.348
1.812
2.164
1.995
2.214
1.816
1.885
1.766
2.254
1.788
2.081
1.945
2.112
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.011
0.011
0.011
0.011
0.011
0.011
0.011
0.011
0.011
0.011
0.011
0.011
0.011
0.011
0.011
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.022
0.018
0.022
0.018
0.022
0.018
0.022
0.018
0.022
0.018
0.022
0.018
0.022
0.018
0.022
0.018
0.022
0.019
0.022
0.019
0.022
0.019
0.022
0.019
0.022
0.019
0.022
0.019
0.022
0.019
0.022
0.019
Block Library
A13872EJ5V0BL
Symbol
A
B
C
D
E
F
G
H
Output
Fanin Symbol Fanout
1.7
2.0
1.7
2.0
1.7
2.0
1.7
2.0
YE
2 - 221
33
Chapter 2 Function Block
Chapter 2 Function Block
[MEMO]
[MEMO]
Block Library
A13872EJ5V0BL
2 - 222
Block Library
A13872EJ5V0BL
2 - 223
Chapter 2 Function Block
Chapter 2 Function Block
[MEMO]
2.9
RS-Latch, RS-F/F
Block Library
A13872EJ5V0BL
2 - 224
Block Library
A13872EJ5V0BL
2 - 225
Chapter 2 Function Block
Chapter 2 Function Block
RS-Latch
Function
Block
type
Standard type
Block type
Normal
Drivability
High speed
Name
cells
F595
5
Name
F595
S → Q
(HH)
(LL)
(HL)
(HL)
(HH)
(LL)
(HH)
(HL)
(HH)
(HL)
cells
S → QB
R → Q
R → QB
Low Power
x1
IN
Path
→ OUT
x2
G → Q
x4
G → QB
Logic Diagram
S H01
N01
Q
N02
QB
Set up time
Set up time
Hold time
Hold time
Min Pulse
R H02
G H03
S
R
S
R
G
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.234
0.305
0.529
0.529
0.233
0.305
0.251
0.539
0.251
0.540
0.900
0.910
0.000
0.000
0.833
0.379
0.516
0.853
0.853
0.379
0.515
0.393
0.864
0.394
0.863
0.785
0.944
1.587
1.580
0.783
0.946
0.794
1.593
0.796
1.591
1.460
1.480
0.000
0.000
2.158
0.011
0.011
0.011
0.011
0.011
0.011
0.011
0.011
0.011
0.011
0.015
0.014
0.014
0.014
0.015
0.014
0.015
0.014
0.015
0.014
0.022
0.019
0.019
0.019
0.022
0.019
0.022
0.019
0.022
0.019
Symbol
S
R
G
Output
Fanin Symbol Fanout
1.0
1.0
1.7
Q
QB
Truth Table
S
R
G
0
0
1
Q
QB
0
1
1
0
1
1
0
1
1
0
1
1
1
1
1
1
1
1->0
Undefined
X
X
0
Latch
Latch
X:Irrelevant
Block Library
A13872EJ5V0BL
2 - 226
Block Library
A13872EJ5V0BL
2 - 227
34
34
Chapter 2 Function Block
Chapter 2 Function Block
RS-F/F with R, S
Function
Standard type
Block type
Normal
Drivability
Block
type
High speed
Name
cells
F596
11
Name
F596
C → Q
cells
C → QB
Low Power
x1
IN
Path
→ OUT
R → Q
R → QB
S → Q
S → QB
Set up time
Set up time
Hold time
Hold time
Release time
Release time
Removal time
Removal time
Min Pulse
Min Pulse
Min Pulse
x2
x4
Logic Diagram
S
H05
SS H01
N01 Q
SR H02
C H03
(HH)
(HL)
(HH)
(HL)
(HL)
(HH)
(HH)
(HL)
SS
SR
SS
SR
R
S
R
S
C
R
S
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.374
0.476
0.607
0.639
0.418
0.215
0.171
0.436
0.640
0.680
0.180
0.320
0.380
0.110
0.430
0.750
0.841
0.749
0.670
0.575
0.779
1.009
1.021
0.759
0.374
0.253
0.867
1.039
1.454
1.933
1.868
1.430
0.647
0.428
1.587
1.940
2.170
0.020
0.090
1.220
0.000
0.310
1.220
2.303
1.943
1.959
0.011
0.010
0.011
0.011
0.010
0.011
0.011
0.011
0.015
0.013
0.015
0.014
0.013
0.015
0.015
0.015
0.022
0.019
0.021
0.020
0.018
0.022
0.022
0.021
Symbol
SS
SR
C
R
S
Output
Fanin Symbol Fanout
1.0
1.0
1.0
2.1
2.3
Q
QB
N02 QB
H04
R
Truth Table
SS
SR
R
S
0
0
C
0
0
Q
QB
Hold
1
0
0
0
1
X
1
0
0
0
0
X
X
0
0
X
X
X
0
1
1
0
X
X
X
1
0
0
1
X
X
X
1
1
1
1
1
Hold
← Prohibition
X:Irrelevant
Block Library
A13872EJ5V0BL
2 - 228
Block Library
A13872EJ5V0BL
2 - 229
35
34
Chapter 2 Function Block
Chapter 2 Function Block
[MEMO]
[MEMO]
Block Library
A13872EJ5V0BL
2 - 230
Block Library
A13872EJ5V0BL
2 - 231
Chapter 2 Function Block
Chapter 2 Function Block
[MEMO]
2.10 D-Latch
Block Library
A13872EJ5V0BL
2 - 232
Block Library
A13872EJ5V0BL
2 - 233
Chapter 2 Function Block
Function
D-Latch
Standard type
Block type
Normal
Drivability
Q output
Block
type
Low Gate type
QB output
Name
cells
Name
cells
Name
cells
F601
6
F601NQ
5
F601NB
5
Normal
Name
Low Power
x1
Chapter 2 Function Block
cells
Q output
QB output
Name
cells
L601
4
Name
F601
IN
Path
→ OUT
D → Q
(HH)
(LL)
(HL)
(LH)
(HH)
(HL)
(HH)
(HL)
cells
D → QB
G → Q
x2
G → QB
x4
Logic Diagram for "Normal"
D
H01
G H02
Truth Table for "Normal"
N01
N02
Q
QB
D
G
Q
QB
0
1
0
1
1
1
1
X
0
L601
Set up time
Hold time
Min Pulse
D → Q
F601NQ
Set up time
Hold time
Min Pulse
D → Q
D
D
G
(HH)
(LL)
(HH)
(HL)
G → Q
0
Latch
X:Irrelevant
D
D
G
(HH)
(LL)
(HH)
(HL)
G → Q
Logic Diagram for "Q output"
Truth Table for "Q output"
F601NB
D
H01
N01
Q
G H02
D
G
Q
0
1
0
1
1
1
X
0
Latch
Set up time
Hold time
Min Pulse
D → QB
D
D
G
(HL)
(LH)
(HH)
(HL)
G → QB
Set up time
Hold time
Min Pulse
D
D
G
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.432
0.436
0.340
0.310
0.476
0.480
0.354
0.385
0.600
0.250
0.639
0.251
0.260
0.288
0.295
0.600
0.270
0.450
0.271
0.280
0.313
0.323
0.610
0.260
0.480
0.337
0.306
0.353
0.383
0.590
0.280
0.516
0.699
0.738
0.536
0.521
0.790
0.774
0.558
0.629
1.319
1.415
0.987
0.995
1.505
1.427
1.009
1.174
1.000
0.010
1.836
0.696
0.816
0.870
0.862
1.010
0.100
1.195
0.765
0.901
0.949
0.978
1.080
0.050
1.316
0.984
0.990
1.012
1.172
0.970
0.070
1.501
0.012
0.010
0.010
0.012
0.012
0.010
0.012
0.010
0.016
0.013
0.013
0.016
0.016
0.013
0.016
0.013
0.022
0.017
0.017
0.022
0.022
0.017
0.022
0.017
0.022
0.021
0.022
0.021
0.030
0.027
0.030
0.027
0.043
0.037
0.043
0.037
0.012
0.011
0.012
0.011
0.016
0.014
0.016
0.014
0.010
0.012
0.012
0.010
0.013
0.016
0.016
0.013
0.383
0.430
0.467
0.478
0.416
0.470
0.508
0.529
0.534
0.517
0.558
0.628
Symbol
D
G
Output
Fanin Symbol Fanout
1.0
1.0
Q
QB
32
32
D
G
1.0
1.0
Q
16
0.023
0.019
0.023
0.019
D
G
1.0
1.0
Q
31
0.017
0.022
0.022
0.017
D
G
1.0
1.0
QB
32
X:Irrelevant
Logic Diagram for "QB output"
D
Truth Table for "QB output"
H01
G H02
N01
QB
D
G
QB
0
1
1
1
1
0
X
0
Latch
X:Irrelevant
Block Library
A13872EJ5V0BL
2 - 234
Block Library
A13872EJ5V0BL
2 - 235
Chapter 2 Function Block
Function
D-Latch, High Speed
Standard type
Block type
Normal
Drivability
Chapter 2 Function Block
Q output
Name
cells
F6R1
6
Name
Low Gate type
QB output
cells
Block
type
Name
Normal
cells
Name
cells
Q output
Name
cells
QB output
Name
D → Q
(HH)
(LL)
(HL)
(LH)
(HH)
(HL)
(HH)
(HL)
cells
D → QB
Low Power
x1
F6R1
IN
Path
→ OUT
G → Q
x2
G → QB
x4
Logic Diagram for "Normal"
D
H01
G H02
Truth Table for "Normal"
N01
N02
Q
QB
D
G
Q
QB
0
1
0
1
1
1
1
X
0
Set up time
Hold time
Min Pulse
D
D
G
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.258
0.266
0.384
0.361
0.298
0.305
0.399
0.424
0.650
0.260
0.556
0.391
0.438
0.601
0.610
0.480
0.495
0.664
0.690
0.715
0.828
1.120
1.193
0.895
0.903
1.263
1.300
1.210
0.070
1.630
0.011
0.011
0.010
0.011
0.011
0.011
0.011
0.010
0.015
0.014
0.013
0.015
0.015
0.014
0.015
0.013
0.022
0.020
0.017
0.021
0.022
0.020
0.021
0.017
Symbol
D
G
Output
Fanin Symbol Fanout
1.0
1.0
Q
QB
0
Latch
X:Irrelevant
Logic Diagram for "Q output"
Truth Table for "Q output"
Logic Diagram for "QB output"
Truth Table for "QB output"
Block Library
A13872EJ5V0BL
2 - 236
Block Library
A13872EJ5V0BL
2 - 237
34
35
Chapter 2 Function Block
Function
D-Latch with R
Standard type
Block type
Normal
Drivability
Q output
Block
type
Low Gate type
QB output
Normal
Name
cells
Name
cells
Name
cells
F602
6
F602NQ
6
F602NB
5
Name
Low Power
x1
Chapter 2 Function Block
cells
Q output
QB output
Name
cells
L602
5
Name
F602
IN
Path
→ OUT
D → Q
(HH)
(LL)
(HL)
(LH)
(HH)
(HL)
(HH)
(HL)
(HL)
(LH)
(HH)
(LL)
cells
D → QB
G → Q
x2
G → QB
x4
Logic Diagram for "Normal"
D
H01
Truth Table for "Normal"
N01
G H02
N02
Q
QB
R → Q
D
G
R
Q
QB
1
1
0
1
0
0
1
0
0
1
X
0
0
X
X
1
R → QB
Latch
0
1
L602
X:Irrelevant
H03
R
Set up time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
D → Q
D
D
R
R
G
R
(HH)
(LL)
(HH)
(HL)
(HL)
(LH)
G → Q
R → Q
Logic Diagram for "Q output"
D
H01
Truth Table for "Q output"
N01
Q
G H02
Logic Diagram for "QB output"
N01
H03
R
R
Q
1
0
1
0
1
0
0
X
0
0
Latch
X
X
1
0
F602NQ
QB
(HH)
(LL)
(HH)
(HL)
(HL)
(LH)
R → Q
D
G
R
QB
1
1
0
0
0
1
0
1
X
0
0
Latch
X
X
1
1
F602NB
A13872EJ5V0BL
Set up time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
D → QB
D
D
R
R
G
R
(HL)
(LH)
(HH)
(HL)
(HH)
(LL)
G → QB
R → QB
Set up time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
X:Irrelevant
Block Library
D
D
R
R
G
R
G → Q
Truth Table for "QB output"
H01
G H02
G
1
X:Irrelevant
H03
R
D
D
Set up time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
D → Q
2 - 238
D
D
R
R
G
R
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.514
0.428
0.402
0.292
0.557
0.473
0.338
0.445
0.310
0.354
0.178
0.242
0.650
0.210
0.470
0.340
0.690
0.627
0.414
0.369
0.446
0.411
0.241
0.251
0.570
0.250
0.390
0.420
0.574
0.472
0.379
0.281
0.376
0.330
0.333
0.398
0.750
0.240
0.680
0.190
0.514
0.519
0.402
0.293
0.338
0.445
0.178
0.243
0.610
0.220
0.440
0.370
0.579
0.503
0.840
0.724
0.641
0.494
0.930
0.758
0.530
0.732
0.578
0.598
0.259
0.398
1.600
1.379
1.181
0.947
1.783
1.389
0.961
1.364
1.039
1.207
0.439
0.789
1.110
0.000
0.620
0.190
2.112
1.428
1.274
1.218
1.444
1.233
0.915
0.870
0.930
0.000
0.340
0.470
1.769
1.188
1.255
0.942
1.214
1.030
1.019
1.409
1.490
0.000
1.580
0.000
1.545
1.620
1.186
0.949
0.963
1.369
0.440
0.794
1.000
0.000
0.520
0.300
1.697
1.005
0.011
0.010
0.010
0.011
0.011
0.010
0.011
0.010
0.010
0.011
0.011
0.010
0.015
0.013
0.013
0.015
0.015
0.013
0.015
0.013
0.013
0.015
0.015
0.013
0.021
0.017
0.019
0.021
0.021
0.017
0.021
0.019
0.018
0.021
0.022
0.019
0.021
0.020
0.021
0.020
0.020
0.021
0.029
0.025
0.029
0.025
0.026
0.029
0.042
0.034
0.042
0.034
0.036
0.042
0.012
0.011
0.012
0.011
0.010
0.012
0.017
0.014
0.017
0.014
0.014
0.017
0.010
0.011
0.011
0.010
0.011
0.010
0.013
0.015
0.015
0.013
0.015
0.013
0.672
0.633
0.752
0.672
0.507
0.425
0.606
0.480
0.614
0.542
0.591
0.682
0.643
0.495
0.531
0.733
0.259
0.401
Block Library
A13872EJ5V0BL
Symbol
D
G
R
Output
Fanin Symbol Fanout
1.0
1.0
1.0
Q
QB
35
35
D
G
R
1.0
1.0
1.0
Q
17
0.025
0.021
0.025
0.021
0.020
0.025
D
G
R
1.0
1.0
1.0
Q
29
0.019
0.021
0.021
0.019
0.022
0.019
D
G
R
1.0
1.0
1.0
QB
35
2 - 239
Chapter 2 Function Block
Function
D-Latch with R, High Speed
Standard type
Block type
Normal
Drivability
Chapter 2 Function Block
Q output
Name
cells
F6R2
7
Name
Low Gate type
QB output
cells
Block
type
Name
Normal
cells
Name
cells
Q output
Name
cells
QB output
Name
D → Q
(HH)
(LL)
(HL)
(LH)
(HH)
(HL)
(HH)
(HL)
(HL)
(LH)
(HH)
(LL)
cells
D → QB
Low Power
x1
F6R2
IN
Path
→ OUT
G → Q
x2
G → QB
x4
Logic Diagram for "Normal"
D
H01
Truth Table for "Normal"
N01
G H02
N02
H03
R
Q
QB
R → Q
D
G
R
Q
QB
1
1
0
1
0
0
1
0
0
1
X
0
0
X
X
1
R → QB
Set up time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
Latch
0
1
D
D
R
R
G
R
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.371
0.279
0.515
0.392
0.356
0.316
0.428
0.500
0.332
0.388
0.447
0.532
0.810
0.230
0.740
0.180
0.626
0.654
0.598
0.476
0.839
0.675
0.589
0.522
0.719
0.828
0.586
0.670
0.788
0.910
1.239
0.933
1.717
1.349
1.174
1.000
1.412
1.652
1.012
1.387
1.405
1.865
1.670
0.000
1.750
0.000
1.971
2.076
0.012
0.011
0.010
0.011
0.012
0.011
0.011
0.010
0.010
0.012
0.011
0.010
0.017
0.014
0.013
0.015
0.017
0.014
0.015
0.013
0.014
0.017
0.015
0.013
0.025
0.021
0.017
0.021
0.025
0.021
0.021
0.017
0.020
0.025
0.021
0.017
Symbol
D
G
R
Output
Fanin Symbol Fanout
1.0
1.0
1.0
Q
QB
X:Irrelevant
Logic Diagram for "Q output"
Truth Table for "Q output"
Logic Diagram for "QB output"
Truth Table for "QB output"
Block Library
A13872EJ5V0BL
2 - 240
Block Library
A13872EJ5V0BL
2 - 241
29
34
Chapter 2 Function Block
Function
D-Latch with RB
Standard type
Block type
Normal
Drivability
Chapter 2 Function Block
Low Gate type
Q output
QB output
Name
cells
Name
cells
Name
cells
F603
7
F603NQ
5
F603NB
6
Normal
Name
cells
Low Power
x1
Block
type
Q output
QB output
Name
cells
L603
5
Name
F603
IN
Path
→ OUT
D → Q
cells
D → QB
G → Q
x2
G → QB
x4
Logic Diagram for "Normal"
D
H01
Truth Table for "Normal"
N01
G H02
N02
Q
QB
RB → Q
D
G
RB
Q
QB
1
1
1
1
0
0
1
1
0
1
X
0
1
X
X
0
RB → QB
Latch
0
1
L603
X:Irrelevant
H03
RB
Set up time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
D → Q
G → Q
RB → Q
Logic Diagram for "Q output"
D
H01
Truth Table for "Q output"
N01
Q
G H02
Logic Diagram for "QB output"
N01
H03
RB
R
Q
1
1
1
0
1
1
0
X
0
1
Latch
X
X
0
0
F603NQ
G → Q
RB → Q
Truth Table for "QB output"
H01
G H02
G
1
X:Irrelevant
H03
RB
D
D
QB
D
G
R
QB
1
1
1
0
0
1
1
1
X
0
1
Latch
X
X
0
1
F603NB
A13872EJ5V0BL
Set up time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
D → QB
G → QB
RB → QB
Set up time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
X:Irrelevant
Block Library
Set up time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
D → Q
2 - 242
(HH)
(LL)
(HL)
(LH)
(HH)
(HL)
(HH)
(HL)
(HH)
(LL)
(HL)
(LH)
D
D
RB
RB
G
RB
(HH)
(LL)
(HH)
(HL)
(HH)
(LL)
D
D
RB
RB
G
RB
(HH)
(LL)
(HH)
(HL)
(HH)
(LL)
D
D
RB
RB
G
RB
(HL)
(LH)
(HH)
(HL)
(HL)
(LH)
D
D
RB
RB
G
RB
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.519
0.433
0.404
0.294
0.562
0.477
0.339
0.448
0.439
0.353
0.324
0.217
0.650
0.210
0.540
0.270
0.695
0.561
0.413
0.385
0.449
0.424
0.324
0.283
0.580
0.250
0.430
0.380
0.578
0.476
0.378
0.276
0.373
0.323
0.356
0.254
0.740
0.240
0.660
0.190
0.508
0.642
0.405
0.295
0.340
0.448
0.325
0.217
0.610
0.220
0.500
0.310
0.581
0.447
0.847
0.729
0.644
0.496
0.938
0.764
0.532
0.735
0.736
0.672
0.533
0.349
1.611
1.387
1.186
0.950
1.793
1.397
0.963
1.369
1.424
1.252
1.000
0.649
1.120
0.000
0.900
0.000
2.122
1.669
1.324
1.277
1.498
1.288
1.002
1.042
0.960
0.000
0.460
0.360
1.823
1.295
1.251
0.931
1.207
1.014
1.235
0.810
1.480
0.000
1.370
0.000
1.534
1.514
1.191
0.952
0.965
1.373
1.006
0.650
1.010
0.000
0.800
0.030
1.702
1.250
0.011
0.010
0.010
0.011
0.011
0.010
0.011
0.010
0.011
0.010
0.010
0.011
0.015
0.013
0.013
0.015
0.015
0.013
0.015
0.013
0.015
0.013
0.013
0.015
0.021
0.017
0.019
0.021
0.021
0.017
0.021
0.019
0.021
0.018
0.019
0.022
0.022
0.020
0.022
0.020
0.022
0.020
0.030
0.025
0.030
0.025
0.029
0.026
0.042
0.034
0.042
0.034
0.042
0.036
0.013
0.011
0.013
0.011
0.013
0.010
0.018
0.014
0.018
0.014
0.018
0.014
0.010
0.011
0.011
0.010
0.010
0.011
0.013
0.015
0.015
0.013
0.013
0.015
0.680
0.660
0.762
0.695
0.536
0.574
0.604
0.472
0.609
0.531
0.591
0.470
0.646
0.497
0.533
0.736
0.536
0.349
Block Library
A13872EJ5V0BL
Symbol
D
G
RB
Output
Fanin Symbol Fanout
1.0
1.0
1.0
Q
QB
35
35
D
G
RB
1.0
1.0
1.0
Q
17
0.026
0.021
0.026
0.021
0.026
0.020
D
G
RB
1.0
1.0
1.0
Q
28
0.019
0.021
0.021
0.019
0.019
0.022
D
G
RB
1.0
1.0
1.0
QB
35
2 - 243
Chapter 2 Function Block
Function
D-Latch with RB, High Speed
Standard type
Block type
Normal
Drivability
Chapter 2 Function Block
Low Gate type
Q output
Name
cells
F6R5
6
Name
Block
type
QB output
cells
Name
cells
Normal
Name
cells
Q output
Name
cells
QB output
Name
D → Q
cells
D → QB
Low Power
x1
F6R5
IN
Path
→ OUT
G → Q
x2
G → QB
x4
Logic Diagram for "Normal"
D
H01
Truth Table for "Normal"
N01
G H02
N02
H03
RB
Q
QB
RB → Q
D
G
RB
Q
QB
1
1
1
1
0
0
1
1
0
1
X
0
1
X
X
0
RB → QB
Set up time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
Latch
0
1
(HH)
(LL)
(HL)
(LH)
(HH)
(HL)
(HH)
(HL)
(HH)
(LL)
(HL)
(LH)
D
D
RB
RB
G
RB
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.370
0.278
0.501
0.379
0.356
0.314
0.415
0.485
0.342
0.256
0.472
0.348
0.790
0.230
0.720
0.190
0.612
0.761
0.596
0.474
0.818
0.657
0.587
0.520
0.702
0.809
0.575
0.471
0.797
0.639
1.235
0.929
1.686
1.323
1.172
0.997
1.387
1.622
1.208
0.811
1.659
1.159
1.640
0.000
1.530
0.000
1.942
1.938
0.012
0.011
0.010
0.011
0.012
0.011
0.011
0.010
0.012
0.010
0.010
0.011
0.017
0.014
0.013
0.015
0.017
0.014
0.015
0.013
0.017
0.014
0.013
0.015
0.025
0.021
0.017
0.021
0.025
0.021
0.021
0.017
0.025
0.020
0.017
0.021
Symbol
D
G
RB
Output
Fanin Symbol Fanout
1.0
1.0
1.0
Q
QB
X:Irrelevant
Logic Diagram for "Q output"
Truth Table for "Q output"
Logic Diagram for "QB output"
Truth Table for "QB output"
Block Library
A13872EJ5V0BL
2 - 244
Block Library
A13872EJ5V0BL
2 - 245
29
34
Chapter 2 Function Block
Function
D-Latch with SB
Standard type
Block type
Normal
Drivability
Chapter 2 Function Block
Block
type
Low Gate type
Q output
QB output
Name
cells
Name
cells
Name
cells
F60K
7
F60KNQ
6
F60KNB
5
Normal
Name
cells
Q output
Name
cells
QB output
Name
F60K
D → Q
cells
D → QB
Low Power
x1
IN
Path
→ OUT
G → Q
x2
G → QB
x4
Logic Diagram for "Normal"
Truth Table for "Normal"
SB
H03
D
H01
N01
G H02
N02
Q
QB
SB → Q
D
G
SB
Q
QB
0
1
1
0
1
1
1
1
1
0
X
0
1
X
X
0
SB → QB
Latch
1
0
F60KNQ
X:Irrelevant
Set up time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
D → Q
G → Q
SB → Q
Logic Diagram for "Q output"
Truth Table for "Q output"
SB
H03
D
H01
N01
Q
Logic Diagram for "QB output"
SB
Q
1
1
0
1
1
1
1
X
0
1
Latch
X
X
0
1
F60KNB
G → QB
SB → QB
Set up time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
Truth Table for "QB output"
SB
H03
H01
G H02
G
0
X:Irrelevant
G H02
D
D
N01
QB
Set up time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
D → QB
D
G
SB
QB
0
1
1
1
1
1
1
0
X
0
1
Latch
X
X
0
0
(HH)
(LL)
(HL)
(LH)
(HH)
(HL)
(HH)
(HL)
(HL)
(LH)
(HH)
(LL)
D
D
SB
SB
G
SB
(HH)
(LL)
(HH)
(HL)
(HL)
(LH)
D
D
SB
SB
G
SB
(HL)
(LH)
(HH)
(HL)
(HH)
(LL)
D
D
SB
SB
G
SB
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.271
0.445
0.407
0.566
0.314
0.370
0.489
0.450
0.527
0.276
0.647
0.417
0.910
0.270
0.920
0.010
0.648
0.730
0.272
0.453
0.312
0.375
0.534
0.275
0.860
0.270
0.870
0.010
0.530
0.616
0.323
0.348
0.390
0.371
0.201
0.183
0.630
0.280
0.420
0.390
0.550
0.406
0.415
0.713
0.641
0.931
0.504
0.577
0.792
0.728
0.882
0.437
1.101
0.672
0.739
1.271
1.166
1.747
0.915
1.012
1.469
1.340
1.646
0.765
2.122
1.234
1.850
0.050
2.230
0.000
1.812
2.359
0.742
1.291
0.914
1.026
1.665
0.768
1.700
0.050
2.070
0.000
1.368
1.904
0.935
1.191
1.201
1.121
0.580
0.480
1.130
0.080
0.410
0.410
1.538
0.879
0.011
0.013
0.010
0.011
0.011
0.013
0.011
0.010
0.013
0.011
0.011
0.010
0.016
0.017
0.013
0.015
0.016
0.017
0.015
0.013
0.017
0.016
0.015
0.013
0.022
0.025
0.017
0.021
0.022
0.025
0.021
0.017
0.025
0.023
0.021
0.017
0.011
0.013
0.011
0.013
0.013
0.011
0.016
0.017
0.015
0.017
0.017
0.016
0.022
0.026
0.022
0.025
0.026
0.023
0.010
0.011
0.011
0.010
0.011
0.010
0.013
0.015
0.015
0.013
0.015
0.013
0.017
0.022
0.022
0.017
0.022
0.017
0.417
0.723
0.502
0.584
0.893
0.439
0.510
0.596
0.629
0.605
0.306
0.285
Symbol
D
G
SB
Output
Fanin Symbol Fanout
1.0
1.0
1.0
Q
QB
32
34
D
G
SB
1.0
1.0
1.0
Q
32
D
G
SB
1.0
1.0
1.0
QB
34
X:Irrelevant
Block Library
A13872EJ5V0BL
2 - 246
Block Library
A13872EJ5V0BL
2 - 247
Chapter 2 Function Block
Function
D-Latch with RB, SB
Standard type
Block type
Normal
Drivability
Chapter 2 Function Block
Block
type
Low Gate type
Q output
QB output
Name
cells
Name
cells
Name
cells
F60J
7
F60JNQ
6
F60JNB
6
Normal
Name
Q output
cells
Name
cells
QB output
Name
F60J
D → Q
cells
D → QB
Low Power
x1
IN
Path
→ OUT
G → Q
x2
G → QB
x4
Logic Diagram for "Normal"
Truth Table for "Normal"
SB
H04
D H01
N01 Q
G H02
N02 QB
RB → Q
D
G
RB
SB
Q
QB
0
1
1
1
0
1
1
1
1
1
1
0
X
0
1
1
RB → QB
SB → Q
SB → QB
Latch
X
X
0
1
0
1
X
X
1
0
1
0
X
X
0
0
0
1
← Prohibition
X:Irrelevant
H03
RB
Logic Diagram for "Q output"
Truth Table for "Q output"
F60JNQ
SB
H04
D H01
N01 Q
G H02
Logic Diagram for "QB output"
RB
SB
Q
0
1
1
1
0
1
1
1
1
1
X
0
1
1
Latch
X
X
0
1
0
X
X
1
0
1
X
X
0
0
0
G → Q
RB → Q
SB → Q
← Prohibition
Truth Table for "QB output"
SB
H04
D H01
N01 QB
H03
RB
G
X:Irrelevant
H03
RB
G H02
D
D
G
RB
SB
QB
0
1
1
1
1
1
1
1
1
0
X
0
1
1
Latch
X
X
0
1
1
X
X
1
0
0
X
X
0
0
1
F60JNB
A13872EJ5V0BL
Set up time
Hold time
Release time
Release time
Removal time
Removal time
Min Pulse
Min Pulse
Min Pulse
D → QB
G → QB
RB → QB
SB → QB
Set up time
Hold time
Release time
Release time
Removal time
Removal time
← Prohibition
X:Irrelevant
Block Library
Set up time
Hold time
Release time
Release time
Removal time
Removal time
Min Pulse
Min Pulse
Min Pulse
D → Q
2 - 248
(HH)
(LL)
(HL)
(LH)
(HH)
(HL)
(HH)
(HL)
(HH)
(LL)
(HL)
(LH)
(HL)
(LH)
(HH)
(LL)
D
D
RB
SB
RB
SB
G
RB
SB
(HH)
(LL)
(HH)
(HL)
(HH)
(LL)
(HL)
(LH)
D
D
RB
SB
RB
SB
G
RB
SB
(HL)
(LH)
(HH)
(HL)
(HL)
(LH)
(HH)
(LL)
D
D
RB
SB
RB
SB
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.383
0.460
0.531
0.588
0.373
0.378
0.505
0.521
0.355
0.271
0.504
0.384
0.555
0.415
0.683
0.571
0.900
0.130
0.730
0.950
0.180
0.000
0.650
0.813
0.756
0.390
0.468
0.378
0.386
0.362
0.269
0.562
0.414
0.840
0.120
0.690
0.890
0.180
0.000
0.533
0.663
0.640
0.424
0.375
0.425
0.427
0.401
0.367
0.200
0.182
0.690
0.200
0.630
0.390
0.190
0.430
0.622
0.763
0.869
0.994
0.613
0.606
0.835
0.858
0.597
0.489
0.843
0.690
0.943
0.717
1.174
0.976
1.258
1.426
1.741
1.931
1.189
1.124
1.618
1.671
1.219
0.821
1.702
1.211
1.807
1.458
2.312
2.015
1.990
0.000
1.540
2.380
0.000
0.000
1.990
1.986
2.553
1.274
1.445
1.203
1.142
1.235
0.824
1.826
1.477
1.820
0.000
1.400
2.220
0.000
0.000
1.523
1.518
2.064
1.407
1.363
1.426
1.381
1.386
1.274
0.576
0.473
1.290
0.000
1.190
0.320
0.000
0.560
0.012
0.013
0.010
0.011
0.012
0.013
0.011
0.010
0.012
0.010
0.010
0.011
0.013
0.011
0.011
0.010
0.017
0.018
0.013
0.015
0.017
0.018
0.015
0.013
0.017
0.014
0.013
0.015
0.018
0.017
0.015
0.013
0.025
0.027
0.017
0.021
0.025
0.026
0.021
0.017
0.025
0.020
0.017
0.021
0.027
0.026
0.021
0.017
0.012
0.013
0.012
0.013
0.012
0.010
0.013
0.011
0.017
0.018
0.017
0.018
0.017
0.014
0.018
0.017
0.025
0.027
0.025
0.027
0.025
0.020
0.027
0.026
0.010
0.011
0.011
0.010
0.010
0.011
0.011
0.010
0.013
0.015
0.015
0.013
0.013
0.015
0.015
0.013
0.018
0.022
0.022
0.018
0.018
0.022
0.022
0.017
0.630
0.773
0.619
0.615
0.605
0.490
0.953
0.726
0.690
0.657
0.713
0.704
0.674
0.678
0.305
0.281
Block Library
A13872EJ5V0BL
Symbol
D
G
RB
SB
Output
Fanin Symbol Fanout
1.0
1.0
1.0
1.0
Q
QB
25
33
D
G
RB
SB
1.0
1.0
1.0
1.0
Q
25
D
G
RB
SB
1.0
1.0
1.0
1.0
QB
34
2 - 249
Chapter 2 Function Block
Block
type
IN
Path
→ OUT
Min Pulse
Min Pulse
Min Pulse
G
RB
SB
Switching speed
t LD0 (ns)
MIN.
TYP.
MAX.
Chapter 2 Function Block
[MEMO]
Input
t1
MIN.
TYP.
0.583
0.655
0.407
1.761
1.661
0.879
Block Library
A13872EJ5V0BL
MAX.
Symbol
Output
Fanin Symbol Fanout
2 - 250
Block Library
A13872EJ5V0BL
2 - 251
Chapter 2 Function Block
Function
D-Latch (GB)
Standard type
Block type
Normal
Drivability
Block
type
Low Gate type
Q output
QB output
Normal
Name
cells
Name
cells
Name
cells
F604
6
F604NQ
5
F604NB
5
Name
Low Power
x1
Chapter 2 Function Block
cells
Q output
QB output
Name
cells
L604
4
Name
F604
IN
Path
→ OUT
D → Q
cells
D → QB
GB → Q
x2
GB → QB
x4
Logic Diagram for "Normal"
D
H01
GB H02
Truth Table for "Normal"
N01
N02
Q
QB
D
GB
Q
QB
1
0
1
0
0
0
0
X
1
L604
Set up time
Hold time
Min Pulse
D → Q
F604NQ
Set up time
Hold time
Min Pulse
D → Q
GB → Q
1
Latch
X:Irrelevant
GB → Q
Logic Diagram for "Q output"
Truth Table for "Q output"
F604NB
D
H01
N01
Q
GB H02
D
GB
Q
1
0
1
0
0
0
X
1
Latch
Set up time
Hold time
Min Pulse
D → QB
GB → QB
Set up time
Hold time
Min Pulse
(HH)
(LL)
(HL)
(LH)
(LH)
(LL)
(LH)
(LL)
D
D
GB
(HH)
(LL)
(LH)
(LL)
D
D
GB
(HH)
(LL)
(LH)
(LL)
D
D
GB
(HL)
(LH)
(LH)
(LL)
D
D
GB
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.417
0.421
0.324
0.295
0.430
0.467
0.342
0.337
0.610
0.280
0.644
0.253
0.262
0.264
0.296
0.630
0.270
0.475
0.271
0.280
0.288
0.322
0.640
0.260
0.508
0.337
0.306
0.356
0.354
0.590
0.290
0.534
0.674
0.711
0.508
0.495
0.717
0.788
0.573
0.551
1.276
1.360
0.929
0.948
1.378
1.506
1.094
1.028
0.960
0.000
1.802
0.699
0.820
0.805
0.949
0.940
0.000
1.247
0.765
0.901
0.889
1.041
1.000
0.000
1.345
0.984
0.990
1.143
1.088
0.910
0.010
1.440
0.011
0.010
0.010
0.011
0.011
0.010
0.011
0.010
0.015
0.013
0.013
0.015
0.015
0.013
0.015
0.013
0.021
0.017
0.017
0.021
0.021
0.017
0.021
0.017
0.022
0.021
0.022
0.021
0.030
0.027
0.030
0.027
0.043
0.038
0.043
0.037
0.012
0.011
0.012
0.011
0.016
0.014
0.016
0.014
0.010
0.012
0.012
0.010
0.013
0.016
0.016
0.013
0.385
0.433
0.427
0.497
0.416
0.469
0.470
0.542
0.534
0.517
0.598
0.579
Symbol
D
GB
Output
Fanin Symbol Fanout
1.0
1.0
Q
QB
35
35
D
GB
1.0
1.0
Q
16
0.023
0.019
0.023
0.019
D
GB
1.0
1.0
Q
31
0.017
0.022
0.022
0.017
D
GB
1.0
1.0
QB
32
X:Irrelevant
Logic Diagram for "QB output"
D
Truth Table for "QB output"
H01
GB H02
N01
QB
D
GB
QB
1
0
0
0
0
1
X
1
Latch
X:Irrelevant
Block Library
A13872EJ5V0BL
2 - 252
Block Library
A13872EJ5V0BL
2 - 253
Chapter 2 Function Block
Function
D-Latch (GB), High Speed
Standard type
Block type
Normal
Drivability
Chapter 2 Function Block
Low Gate type
Q output
Name
cells
F6R8
6
Name
Block
type
QB output
cells
Name
Normal
cells
Name
cells
Q output
Name
cells
QB output
Name
D → Q
cells
D → QB
Low Power
x1
F6R8
IN
Path
→ OUT
GB → Q
x2
GB → QB
x4
Logic Diagram for "Normal"
D
H01
GB H02
Truth Table for "Normal"
N01
N02
Q
QB
D
GB
Q
QB
1
0
1
0
0
0
0
X
1
Set up time
Hold time
Min Pulse
(HH)
(LL)
(HL)
(LH)
(LH)
(LL)
(LH)
(LL)
D
D
GB
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.261
0.267
0.387
0.362
0.273
0.302
0.397
0.399
0.670
0.260
0.587
0.394
0.443
0.605
0.615
0.443
0.506
0.677
0.653
0.719
0.835
1.125
1.201
0.837
0.963
1.325
1.242
1.100
0.000
1.627
0.011
0.011
0.010
0.011
0.011
0.011
0.011
0.010
0.015
0.014
0.013
0.015
0.015
0.014
0.015
0.013
0.022
0.020
0.017
0.021
0.022
0.020
0.021
0.017
Symbol
D
GB
Output
Fanin Symbol Fanout
1.0
1.0
Q
QB
1
Latch
X:Irrelevant
Logic Diagram for "Q output"
Truth Table for "Q output"
Logic Diagram for "QB output"
Truth Table for "QB output"
Block Library
A13872EJ5V0BL
2 - 254
Block Library
A13872EJ5V0BL
2 - 255
34
35
Chapter 2 Function Block
Function
D-Latch (GB) with RB
Standard type
Block type
Normal
Drivability
Chapter 2 Function Block
Low Gate type
Q output
QB output
Name
cells
Name
cells
Name
cells
F605
7
F605NQ
5
F605NB
6
Normal
Name
cells
Low Power
x1
Block
type
Q output
QB output
Name
cells
L605
5
Name
F605
IN
Path
→ OUT
D → Q
cells
D → QB
GB → Q
x2
GB → QB
x4
Logic Diagram for "Normal"
D
H01
Truth Table for "Normal"
N01
GB H02
N02
Q
QB
RB → Q
D
GB
RB
Q
QB
1
0
1
1
0
0
0
1
0
1
X
1
1
X
X
0
RB → QB
Latch
0
1
L605
X:Irrelevant
H03
RB
Set up time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
D → Q
GB → Q
RB → Q
Logic Diagram for "Q output"
D
H01
Truth Table for "Q output"
N01
Q
GB H02
Logic Diagram for "QB output"
N01
H03
RB
RB
Q
0
1
1
0
0
1
0
X
1
1
Latch
X
X
0
0
F605NQ
GB → Q
RB → Q
Truth Table for "QB output"
H01
GB H02
GB
1
X:Irrelevant
H03
RB
D
D
QB
D
GB
RB
QB
1
0
1
0
0
0
1
1
X
1
1
Latch
X
X
0
1
F605NB
A13872EJ5V0BL
Set up time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
D → QB
GB → QB
RB → QB
Set up time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
X:Irrelevant
Block Library
Set up time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
D → Q
2 - 256
(HH)
(LL)
(HL)
(LH)
(LH)
(LL)
(LH)
(LL)
(HH)
(LL)
(HL)
(LH)
D
D
RB
RB
GB
RB
(HH)
(LL)
(LH)
(LL)
(HH)
(LL)
D
D
RB
RB
GB
RB
(HH)
(LL)
(LH)
(LL)
(HH)
(LL)
D
D
RB
RB
GB
RB
(HL)
(LH)
(LH)
(LL)
(HL)
(LH)
D
D
RB
RB
GB
RB
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.519
0.432
0.404
0.294
0.532
0.481
0.343
0.417
0.439
0.353
0.324
0.217
0.670
0.280
0.540
0.270
0.707
0.561
0.411
0.383
0.421
0.424
0.321
0.281
0.610
0.300
0.430
0.380
0.596
0.472
0.371
0.276
0.338
0.317
0.348
0.254
0.810
0.290
0.730
0.110
0.529
0.626
0.404
0.295
0.344
0.417
0.325
0.217
0.650
0.290
0.510
0.310
0.593
0.447
0.847
0.729
0.643
0.496
0.889
0.808
0.576
0.685
0.736
0.672
0.534
0.349
1.611
1.386
1.186
0.950
1.709
1.535
1.100
1.283
1.424
1.252
1.000
0.649
1.190
0.000
0.960
0.000
2.012
1.669
1.319
1.274
1.419
1.408
0.998
1.038
0.970
0.040
0.540
0.280
1.716
1.289
1.237
0.931
1.136
1.052
1.221
0.810
1.630
0.000
1.530
0.000
1.444
1.499
1.191
0.951
1.100
1.289
1.006
0.650
1.110
0.020
0.860
0.000
1.588
1.249
0.011
0.010
0.010
0.011
0.011
0.010
0.011
0.010
0.011
0.010
0.010
0.011
0.015
0.013
0.013
0.015
0.015
0.013
0.015
0.013
0.015
0.013
0.013
0.015
0.021
0.017
0.019
0.021
0.021
0.017
0.021
0.019
0.021
0.018
0.019
0.022
0.022
0.020
0.022
0.020
0.022
0.020
0.030
0.025
0.030
0.025
0.029
0.026
0.042
0.034
0.042
0.034
0.042
0.036
0.012
0.011
0.012
0.011
0.012
0.010
0.017
0.014
0.017
0.014
0.017
0.014
0.010
0.011
0.011
0.010
0.010
0.011
0.013
0.015
0.015
0.013
0.013
0.015
0.677
0.658
0.717
0.726
0.532
0.571
0.595
0.472
0.560
0.536
0.582
0.472
0.646
0.497
0.575
0.687
0.536
0.349
Block Library
A13872EJ5V0BL
Symbol
D
GB
RB
Output
Fanin Symbol Fanout
1.0
1.0
1.0
Q
QB
35
35
D
GB
RB
1.0
1.0
1.0
Q
17
0.025
0.021
0.025
0.021
0.025
0.020
D
GB
RB
1.0
1.0
1.0
Q
29
0.019
0.021
0.021
0.019
0.019
0.022
D
GB
RB
1.0
1.0
1.0
QB
35
2 - 257
Chapter 2 Function Block
Function
D-Latch (GB) with RB, High Speed
Standard type
Block type
Normal
Drivability
Chapter 2 Function Block
Low Gate type
Q output
Name
cells
F6R9
6
Name
Block
type
QB output
cells
Name
cells
Normal
Name
cells
Q output
Name
cells
QB output
Name
D → Q
cells
D → QB
Low Power
x1
F6R9
IN
Path
→ OUT
GB → Q
x2
GB → QB
x4
Logic Diagram for "Normal"
D
H01
Truth Table for "Normal"
N01
GB H02
N02
H03
RB
Q
QB
RB → Q
D
GB
RB
Q
QB
1
0
1
1
0
0
0
1
0
1
X
1
1
X
X
0
RB → QB
Set up time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
Latch
0
1
(HH)
(LL)
(HL)
(LH)
(LH)
(LL)
(LH)
(LL)
(HH)
(LL)
(HL)
(LH)
D
D
RB
RB
GB
RB
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.370
0.278
0.500
0.379
0.331
0.310
0.412
0.460
0.342
0.256
0.472
0.348
0.850
0.280
0.770
0.110
0.646
0.760
0.596
0.474
0.818
0.657
0.549
0.525
0.707
0.771
0.575
0.471
0.797
0.639
1.235
0.930
1.686
1.324
1.115
1.035
1.425
1.566
1.207
0.810
1.658
1.159
1.770
0.000
1.660
0.000
1.870
1.938
0.012
0.011
0.010
0.011
0.012
0.011
0.011
0.010
0.012
0.010
0.010
0.011
0.017
0.014
0.013
0.015
0.017
0.014
0.015
0.013
0.017
0.014
0.013
0.015
0.025
0.021
0.017
0.021
0.025
0.021
0.021
0.017
0.025
0.020
0.017
0.021
Symbol
D
GB
RB
Output
Fanin Symbol Fanout
1.0
1.0
1.0
Q
QB
X:Irrelevant
Logic Diagram for "Q output"
Truth Table for "Q output"
Logic Diagram for "QB output"
Truth Table for "QB output"
Block Library
A13872EJ5V0BL
2 - 258
Block Library
A13872EJ5V0BL
2 - 259
29
34
Chapter 2 Function Block
Chapter 2 Function Block
[MEMO]
[MEMO]
Block Library
A13872EJ5V0BL
2 - 260
Block Library
A13872EJ5V0BL
2 - 261
Chapter 2 Function Block
Chapter 2 Function Block
[MEMO]
2.11 D-F/F
Block Library
A13872EJ5V0BL
2 - 262
Block Library
A13872EJ5V0BL
2 - 263
Chapter 2 Function Block
Function
D-F/F
Standard type
Block type
Normal
Drivability
Q output
Block
type
Low Gate type
QB output
Name
cells
Name
cells
Name
cells
F641
8
F641NQ
7
F641NB
7
Normal
Name
Low Power
x1
Chapter 2 Function Block
cells
Q output
QB output
Name
cells
L641
6
Name
F641
H01
C H02
D
D
C
L641
Set up time
Hold time
Min Pulse
C → Q
D
D
C
F641NQ
Set up time
Hold time
Min Pulse
C → Q
D
D
C
F641NB
Set up time
Hold time
Min Pulse
C → QB
Set up time
Hold time
Min Pulse
D
D
C
N01
N02
Q
QB
Logic Diagram for "Q output"
H01
(HH)
(HL)
Truth Table for "Normal"
D
C
Q
QB
0
0
1
1
1
0
Hold
X
X:Irrelevant
D
(HH)
(HL)
(HH)
(HL)
C → QB
x4
D
C → Q
cells
x2
Logic Diagram for "Normal"
IN
Path
→ OUT
(HH)
(HL)
(HH)
(HL)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.358
0.401
0.491
0.481
0.570
0.370
0.669
0.358
0.401
0.560
0.350
0.567
0.358
0.400
0.570
0.370
0.566
0.329
0.338
0.570
0.370
0.528
0.551
0.652
0.813
0.762
0.994
1.211
1.552
1.397
1.090
0.310
1.924
0.992
1.212
0.860
0.140
1.584
0.993
1.211
1.100
0.310
1.584
0.989
0.953
1.040
0.310
1.362
0.011
0.010
0.011
0.010
0.015
0.013
0.015
0.013
0.021
0.017
0.021
0.017
0.022
0.020
0.030
0.025
0.042
0.034
0.011
0.010
0.015
0.013
0.011
0.011
0.015
0.014
0.551
0.651
0.550
0.650
0.529
0.537
Symbol
D
C
Output
Fanin Symbol Fanout
1.0
1.0
Q
QB
35
35
D
C
1.0
1.0
Q
17
0.021
0.017
D
C
1.0
1.0
Q
35
0.022
0.020
D
C
1.0
1.0
QB
34
Truth Table for "Q output"
N01
Q
D
C
C H02
Q
0
0
1
1
X
Hold
X:Irrelevant
Logic Diagram for "QB output"
D
Truth Table for "QB output"
D
H01
C
0
C H02
N01
QB
QB
1
1
0
X
Hold
X:Irrelevant
Block Library
A13872EJ5V0BL
2 - 264
Block Library
A13872EJ5V0BL
2 - 265
Chapter 2 Function Block
Function
D-F/F with R
Standard type
Block type
Normal
Drivability
Chapter 2 Function Block
Q output
Block
type
Low Gate type
QB output
Normal
Name
cells
Name
cells
Name
cells
F642
9
F642NQ
8
F642NB
8
Name
cells
Q output
Name
cells
QB output
Name
F642
F642NQ
R → Q
R → QB
Set up time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
C → Q
F642NB
R → Q
Set up time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
C → QB
x4
Logic Diagram for "Normal"
H01
Truth Table for "Normal"
N01
C H02
N02
Q
QB
D
R
Q
QB
0
0
0
1
1
0
1
0
X
0
X
Logic Diagram for "Q output"
H01
N01
Q
D
0
1
R → QB
Set up time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
C
R
Q
0
0
1
0
1
X
0
Hold
1
0
X
D
D
R
R
C
R
(HH)
(HL)
(HL)
D
D
R
R
C
R
(HH)
(HL)
(HH)
D
D
R
R
C
R
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.374
0.404
0.498
0.583
0.357
0.184
0.610
0.380
0.400
0.410
0.788
0.585
0.373
0.401
0.335
0.610
0.380
0.400
0.410
0.578
0.529
0.331
0.361
0.264
0.610
0.390
0.410
0.390
0.558
0.500
0.570
0.655
0.823
0.933
0.602
0.334
1.029
1.214
1.568
1.718
1.126
0.579
1.720
0.310
1.230
0.290
2.113
1.597
1.029
1.213
1.046
1.720
0.310
1.230
0.290
1.586
1.491
0.993
1.039
0.817
1.590
0.310
1.120
0.250
1.429
1.298
0.011
0.010
0.011
0.010
0.010
0.011
0.015
0.013
0.015
0.013
0.013
0.015
0.022
0.017
0.021
0.019
0.017
0.022
0.011
0.010
0.010
0.015
0.013
0.013
0.022
0.017
0.017
0.011
0.011
0.011
0.015
0.015
0.015
0.022
0.022
0.022
0.570
0.652
0.561
0.532
0.576
0.434
Symbol
D
C
R
Output
Fanin Symbol Fanout
1.0
1.0
2.2
Q
QB
35
34
D
C
R
1.0
1.0
2.2
Q
35
D
C
R
1.0
1.0
2.2
QB
34
X:Irrelevant
H03
R
Logic Diagram for "QB output"
Truth Table for "QB output"
D
H01
N01
QB
C
R
QB
1
0
0
1
0
0
X
0
Hold
1
1
X
H03
R
1
0
X
C H02
X
Hold
Truth Table for "Q output"
C H02
D
C
X:Irrelevant
H03
R
D
(HH)
(HL)
(HH)
(HL)
(HL)
(HH)
C → QB
x2
D
C → Q
cells
Low Power
x1
IN
Path
→ OUT
X
X:Irrelevant
Block Library
A13872EJ5V0BL
2 - 266
Block Library
A13872EJ5V0BL
2 - 267
Chapter 2 Function Block
Function
D-F/F with S
Standard type
Block type
Normal
Drivability
Chapter 2 Function Block
Q output
Block
type
Low Gate type
QB output
Normal
Name
cells
Name
cells
Name
cells
F643
9
F643NQ
8
F643NB
8
Name
cells
Q output
Name
cells
QB output
Name
F643
F643NQ
S → Q
S → QB
Set up time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
C → Q
F643NB
S → Q
Set up time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
C → QB
x4
Logic Diagram for "Normal"
Truth Table for "Normal"
S
H03
H01
D
N01
Q
S
Q
QB
0
0
0
1
1
0
1
0
X
0
X
C H02
N02
QB
Logic Diagram for "Q output"
H01
D
N01
Q
1
1
0
S → QB
Set up time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
S
Q
0
C
0
0
1
0
1
X
0
Hold
1
1
X
D
D
S
S
C
S
(HH)
(HL)
(HH)
D
D
S
S
C
S
(HH)
(HL)
(HL)
D
D
S
S
C
S
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.365
0.486
0.596
0.498
0.177
0.317
0.570
0.360
0.110
0.740
0.763
0.493
0.365
0.486
0.178
0.570
0.360
0.110
0.740
0.654
0.296
0.331
0.343
0.342
0.570
0.370
0.110
0.690
0.536
0.602
0.562
0.794
0.989
0.788
0.259
0.580
1.011
1.476
1.890
1.435
0.438
1.040
1.120
0.300
0.000
1.180
2.265
1.427
1.012
1.479
0.441
1.130
0.300
0.000
1.190
1.853
0.831
0.986
0.955
1.454
1.090
0.310
0.000
1.130
1.362
1.856
0.011
0.010
0.011
0.010
0.011
0.010
0.015
0.013
0.015
0.013
0.015
0.013
0.021
0.019
0.021
0.017
0.022
0.018
0.011
0.010
0.011
0.015
0.013
0.015
0.021
0.019
0.022
0.011
0.011
0.011
0.015
0.014
0.014
0.022
0.020
0.019
0.562
0.795
0.260
0.531
0.541
0.757
Symbol
D
C
S
Output
Fanin Symbol Fanout
1.0
1.0
2.2
Q
QB
35
35
D
C
S
1.0
1.0
2.2
Q
35
D
C
S
1.0
1.0
2.2
QB
34
X:Irrelevant
C H02
Logic Diagram for "QB output"
Truth Table for "QB output"
S
H03
D
H01
N01
QB
C
S
QB
1
0
0
1
0
0
X
0
Hold
1
0
X
C H02
X
Hold
X:Irrelevant
X
D
C
Truth Table for "Q output"
S
H03
D
(HH)
(HL)
(HH)
(HL)
(HH)
(HL)
C → QB
x2
D
C → Q
cells
Low Power
x1
IN
Path
→ OUT
X
X:Irrelevant
Block Library
A13872EJ5V0BL
2 - 268
Block Library
A13872EJ5V0BL
2 - 269
Chapter 2 Function Block
Function
D-F/F with R, S
Standard type
Block type
Normal
Drivability
Chapter 2 Function Block
Q output
Low Gate type
QB output
Normal
Name
cells
Name
cells
Name
cells
F644
10
F644NQ
9
F644NB
9
Name
Q output
cells
Low Power
x1
Block
type
QB output
Name
cells
L644
8
Name
F644
L644
R → Q
R → QB
S → Q
S → QB
Set up time
Hold time
Release time
Release time
Removal time
Removal time
Min Pulse
Min Pulse
Min Pulse
C → Q
F644NQ
R → Q
S → Q
Set up time
Hold time
Release time
Release time
Removal time
Removal time
Min Pulse
Min Pulse
Min Pulse
C → Q
F644NB
R → Q
S → Q
Set up time
Hold time
Release time
Release time
Removal time
Removal time
Min Pulse
Min Pulse
Min Pulse
C → QB
Truth Table for "Normal"
D H01
D
N01 Q
C H02
N02 QB
C
S
Q
QB
0
0
0
1
1
0
0
1
X
0
0
Logic Diagram for "Q output"
X
X
0
1
1
0
X
X
1
0
0
1
X
X
1
1
1
1
D
N01 Q
C H02
R
S
Q
0
C
0
0
0
1
0
0
1
X
0
0
Hold
X
X
0
1
1
X
X
1
0
0
X
X
1
1
1
← Prohibition
X:Irrelevant
H03
R
Logic Diagram for "QB output"
Truth Table for "QB output"
S
H04
D
D H01
C
R
S
QB
0
0
0
1
1
0
0
0
0
0
Hold
X
X
0
1
0
X
X
1
0
1
X
X
1
1
1
X
N01 QB
H03
R
← Prohibition
Truth Table for "Q output"
S
H04
C H02
0
Hold
X:Irrelevant
H03
R
D H01
R
0
R → QB
S → QB
Set up time
Hold time
Release time
Release time
Removal time
Removal time
Min Pulse
Min Pulse
Min Pulse
← Prohibition
X:Irrelevant
Block Library
A13872EJ5V0BL
(HH)
(HL)
(HH)
(HL)
(HL)
(HH)
(HH)
(HL)
C → QB
x4
S
H04
C → Q
cells
x2
Logic Diagram for "Normal"
IN
Path
→ OUT
2 - 270
D
D
R
S
R
S
C
R
S
(HH)
(HL)
(HL)
(HH)
D
D
R
S
R
S
C
R
S
(HH)
(HL)
(HL)
(HH)
D
D
R
S
R
S
C
R
S
(HH)
(HL)
(HH)
(HL)
D
D
R
S
R
S
C
R
S
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.383
0.482
0.577
0.591
0.419
0.184
0.173
0.381
0.600
0.380
0.380
0.100
0.430
0.760
0.794
0.688
0.628
0.383
0.480
0.403
0.174
0.590
0.380
0.380
0.100
0.430
0.760
0.647
0.607
0.272
0.382
0.482
0.406
0.173
0.590
0.380
0.380
0.110
0.430
0.760
0.650
0.612
0.284
0.335
0.368
0.266
0.453
0.600
0.390
0.390
0.100
0.420
0.700
0.567
0.500
0.724
0.587
0.787
0.966
0.947
0.723
0.337
0.255
0.788
1.057
1.467
1.860
1.744
1.368
0.582
0.431
1.451
1.710
0.310
1.220
0.000
0.320
1.220
2.232
1.849
1.826
1.052
1.452
1.239
0.440
1.690
0.310
1.200
0.000
0.320
1.220
1.826
1.687
0.789
1.055
1.472
1.265
0.430
1.710
0.320
1.220
0.000
0.320
1.220
1.845
1.711
0.812
0.993
1.060
0.808
1.858
1.590
0.320
1.100
0.000
0.300
1.150
1.451
1.286
2.250
0.011
0.010
0.011
0.010
0.010
0.011
0.011
0.010
0.015
0.013
0.015
0.013
0.013
0.015
0.015
0.014
0.021
0.019
0.021
0.019
0.018
0.022
0.022
0.021
0.022
0.020
0.020
0.021
0.030
0.026
0.026
0.030
0.042
0.036
0.036
0.042
0.011
0.010
0.010
0.011
0.015
0.013
0.013
0.015
0.011
0.011
0.011
0.011
0.015
0.015
0.015
0.015
0.587
0.781
0.662
0.260
0.586
0.789
0.671
0.254
0.536
0.587
0.432
0.955
Block Library
A13872EJ5V0BL
Symbol
D
C
R
S
Output
Fanin Symbol Fanout
1.0
1.0
2.1
2.3
Q
QB
35
34
D
C
R
S
1.0
1.0
2.1
2.3
Q
17
0.022
0.019
0.019
0.022
D
C
R
S
1.0
1.0
2.1
2.3
Q
35
0.022
0.022
0.022
0.022
D
C
R
S
1.0
1.0
2.1
2.3
QB
33
2 - 271
Chapter 2 Function Block
Function
D-F/F with RB
Standard type
Block type
Normal
Drivability
Chapter 2 Function Block
Low Gate type
Q output
QB output
Name
cells
Name
cells
Name
cells
F615
9
F615NQ
8
F615NB
8
Normal
Name
cells
Low Power
x1
Block
type
Q output
QB output
Name
cells
L645
7
Name
F615
C → QB
L645
RB → Q
RB → QB
Set up time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
C → Q
F615NQ
RB → Q
Set up time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
C → Q
F615NB
RB → Q
Set up time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
C → QB
x4
D
H01
Truth Table for "Normal"
N01
C H02
N02
Q
QB
D
RB
Q
QB
0
1
0
1
1
1
1
0
X
1
X
Logic Diagram for "Q output"
H01
N01
Q
D
1
C
RB
Q
1
0
1
1
1
X
1
Hold
0
0
X
RB → QB
Set up time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
X:Irrelevant
H03
RB
Logic Diagram for "QB output"
(HH)
(HL)
(HH)
(HL)
(LL)
(LH)
D
D
RB
RB
C
RB
(HH)
(HL)
(LL)
D
D
RB
RB
C
RB
(HH)
(HL)
(LL)
D
D
RB
RB
C
RB
(HH)
(HL)
(LH)
D
D
RB
RB
C
RB
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.425
0.424
0.523
0.559
0.199
0.305
0.580
0.380
0.190
0.670
0.751
0.547
0.404
0.406
0.183
0.580
0.380
0.190
0.670
0.596
0.358
0.427
0.425
0.199
0.580
0.380
0.190
0.670
0.619
0.386
0.353
0.359
0.327
0.580
0.380
0.170
0.630
0.552
0.628
0.675
0.688
0.860
0.905
0.311
0.567
1.282
1.278
1.624
1.728
0.535
1.029
1.140
0.310
0.000
1.010
2.111
1.338
1.202
1.218
0.480
1.130
0.310
0.000
1.010
1.594
0.760
1.290
1.282
0.540
1.140
0.310
0.000
1.010
1.671
0.841
1.055
1.012
1.447
1.120
0.310
0.000
0.960
1.432
1.747
0.012
0.010
0.012
0.010
0.010
0.012
0.016
0.013
0.016
0.013
0.013
0.016
0.023
0.017
0.022
0.017
0.017
0.022
0.022
0.020
0.020
0.030
0.025
0.025
0.043
0.034
0.034
0.012
0.010
0.010
0.016
0.013
0.013
0.012
0.011
0.012
0.016
0.014
0.016
0.638
0.656
0.285
0.678
0.689
0.315
0.567
0.570
0.750
Symbol
D
C
RB
Output
Fanin Symbol Fanout
1.0
1.0
2.2
Q
QB
31
31
D
C
RB
1.0
1.0
2.3
Q
16
0.023
0.017
0.017
D
C
RB
1.0
1.0
2.2
Q
31
0.023
0.020
0.023
D
C
RB
1.0
1.0
2.3
QB
31
Truth Table for "QB output"
D
H01
N01
QB
C
RB
QB
1
0
1
1
1
0
X
1
Hold
0
1
X
H03
RB
0
0
X
C H02
0
Truth Table for "Q output"
C H02
D
X
Hold
X:Irrelevant
H03
RB
D
C
C → Q
cells
x2
Logic Diagram for "Normal"
IN
Path
→ OUT
X
X:Irrelevant
Block Library
A13872EJ5V0BL
2 - 272
Block Library
A13872EJ5V0BL
2 - 273
Chapter 2 Function Block
Function
D-F/F with SB
Standard type
Block type
Normal
Drivability
Chapter 2 Function Block
Block
type
Low Gate type
Q output
QB output
Name
cells
Name
cells
Name
cells
F616
9
F616NQ
8
F616NB
8
Normal
Name
cells
Q output
Name
cells
QB output
Name
F616
C → QB
F616NQ
SB → Q
SB → QB
Set up time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
C → Q
F616NB
SB → Q
Set up time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
C → QB
x2
x4
Logic Diagram for "Normal"
Truth Table for "Normal"
SB
H03
D
H01
D
N01
Q
SB
Q
QB
0
1
0
1
1
1
1
0
X
1
X
C H02
N02
QB
Logic Diagram for "Q output"
H01
D
N01
Q
0
1
0
SB → QB
Set up time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
SB
Q
0
C
1
0
1
1
1
X
1
Hold
0
1
X
(HH)
(HL)
(HH)
(HL)
(LH)
(LL)
D
D
SB
SB
C
SB
(HH)
(HL)
(LH)
D
D
SB
SB
C
SB
(HH)
(HL)
(LL)
D
D
SB
SB
C
SB
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.360
0.422
0.575
0.489
0.335
0.190
0.590
0.350
0.450
0.360
0.740
0.579
0.360
0.420
0.313
0.590
0.350
0.450
0.360
0.588
0.541
0.366
0.340
0.279
0.610
0.350
0.460
0.340
0.533
0.524
0.553
0.686
0.968
0.774
0.619
0.386
0.996
1.294
1.923
1.411
1.170
0.660
1.200
0.290
0.560
0.370
2.295
1.505
0.998
1.291
1.057
1.210
0.280
0.570
0.370
1.667
1.381
1.121
0.960
0.938
1.230
0.290
0.590
0.330
1.495
1.276
0.011
0.010
0.011
0.010
0.011
0.010
0.015
0.013
0.015
0.013
0.015
0.013
0.021
0.017
0.021
0.017
0.021
0.018
0.011
0.010
0.011
0.015
0.013
0.015
0.021
0.017
0.021
0.011
0.011
0.010
0.016
0.014
0.014
0.023
0.020
0.019
0.554
0.684
0.564
0.592
0.541
0.507
Symbol
D
C
SB
Output
Fanin Symbol Fanout
1.0
1.0
2.2
Q
QB
35
34
D
C
SB
1.0
1.0
2.2
Q
35
D
C
SB
1.0
1.0
2.2
QB
32
X:Irrelevant
C H02
Logic Diagram for "QB output"
Truth Table for "QB output"
SB
H03
D
H01
N01
QB
C
SB
QB
1
0
1
1
1
0
X
1
Hold
0
0
X
C H02
X
Hold
X:Irrelevant
X
D
C
Truth Table for "Q output"
SB
H03
D
C → Q
cells
Low Power
x1
IN
Path
→ OUT
X
X:Irrelevant
Block Library
A13872EJ5V0BL
2 - 274
Block Library
A13872EJ5V0BL
2 - 275
Chapter 2 Function Block
Function
D-F/F with RB, SB
Standard type
Block type
Normal
Drivability
Chapter 2 Function Block
Low Gate type
Q output
QB output
Name
cells
Name
cells
Name
cells
F647
10
F647NQ
9
F647NB
9
Normal
Name
Q output
cells
Low Power
x1
Block
type
QB output
Name
cells
L647
8
Name
F647
C → QB
L647
RB → Q
RB → QB
SB → Q
SB → QB
Set up time
Hold time
Release time
Release time
Removal time
Removal time
Min Pulse
Min Pulse
Min Pulse
C → Q
F647NQ
RB → Q
SB → Q
Set up time
Hold time
Release time
Release time
Removal time
Removal time
Min Pulse
Min Pulse
Min Pulse
C → Q
F647NB
RB → Q
SB → Q
Set up time
Hold time
Release time
Release time
Removal time
Removal time
Min Pulse
Min Pulse
Min Pulse
C → QB
x4
Truth Table for "Normal"
SB
H04
D H01
D
N01 Q
C H02
N02 QB
C
SB
Q
QB
1
1
0
1
1
1
1
1
X
1
1
Logic Diagram for "Q output"
X
X
0
1
0
1
X
X
1
0
1
0
X
X
0
0
0
0
D
N01 Q
C H02
RB
SB
Q
0
C
1
1
0
1
1
1
1
X
1
1
Hold
X
X
0
1
0
X
X
1
0
1
X
X
0
0
0
← Prohibition
X:Irrelevant
H03
RB
Logic Diagram for "QB output"
Truth Table for "QB output"
SB
H04
D
D H01
C
RB
SB
QB
0
1
1
1
1
1
1
0
1
1
Hold
X
X
0
1
1
X
X
1
0
0
X
X
0
0
0
X
N01 QB
H03
RB
← Prohibition
Truth Table for "Q output"
SB
H04
C H02
0
Hold
X:Irrelevant
H03
RB
D H01
RB
0
RB → QB
SB → QB
Set up time
Hold time
Release time
Release time
Removal time
Removal time
Min Pulse
Min Pulse
Min Pulse
← Prohibition
X:Irrelevant
Block Library
A13872EJ5V0BL
C → Q
cells
x2
Logic Diagram for "Normal"
IN
Path
→ OUT
2 - 276
(HH)
(HL)
(HH)
(HL)
(LL)
(LH)
(LH)
(LL)
D
D
RB
SB
RB
SB
C
RB
SB
(HH)
(HL)
(LL)
(LH)
D
D
RB
SB
RB
SB
C
RB
SB
(HH)
(HL)
(LL)
(LH)
D
D
RB
SB
RB
SB
C
RB
SB
(HH)
(HL)
(LH)
(LL)
D
D
RB
SB
RB
SB
C
RB
SB
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.412
0.427
0.575
0.540
0.176
0.329
0.382
0.187
0.570
0.360
0.180
0.420
0.690
0.390
0.743
0.603
0.658
0.413
0.427
0.183
0.359
0.580
0.360
0.180
0.420
0.700
0.390
0.596
0.357
0.608
0.409
0.422
0.178
0.358
0.580
0.360
0.180
0.420
0.700
0.390
0.591
0.354
0.608
0.373
0.342
0.374
0.274
0.590
0.360
0.150
0.440
0.650
0.380
0.541
0.713
0.520
0.653
0.694
0.968
0.874
0.273
0.677
0.727
0.385
1.237
1.302
1.920
1.662
0.463
1.334
1.423
0.654
1.160
0.300
0.000
0.510
1.080
0.440
2.296
1.640
1.769
1.223
1.299
0.477
1.267
1.180
0.290
0.000
0.530
1.090
0.440
1.677
0.754
1.600
1.236
1.295
0.467
1.285
1.170
0.290
0.000
0.530
1.090
0.440
1.673
0.757
1.618
1.135
0.958
1.808
0.920
1.210
0.290
0.000
0.560
1.010
0.400
1.510
2.114
1.254
0.011
0.010
0.011
0.010
0.010
0.011
0.011
0.010
0.015
0.013
0.015
0.013
0.013
0.015
0.015
0.013
0.022
0.017
0.021
0.017
0.017
0.022
0.022
0.018
0.022
0.020
0.020
0.022
0.030
0.025
0.025
0.030
0.043
0.034
0.034
0.042
0.011
0.010
0.010
0.011
0.015
0.013
0.013
0.015
0.011
0.011
0.011
0.011
0.016
0.014
0.016
0.014
0.652
0.693
0.284
0.654
0.651
0.687
0.276
0.654
0.601
0.543
0.889
0.499
Block Library
A13872EJ5V0BL
Symbol
D
C
RB
SB
Output
Fanin Symbol Fanout
1.0
1.0
2.3
2.1
Q
QB
34
32
D
C
RB
SB
1.0
1.0
2.3
2.2
Q
16
0.022
0.017
0.017
0.022
D
C
RB
SB
1.0
1.0
2.3
2.2
Q
34
0.023
0.020
0.023
0.020
D
C
RB
SB
1.0
1.0
2.3
2.2
QB
32
2 - 277
Chapter 2 Function Block
Function
D-F/F (CB)
Standard type
Block type
Normal
Drivability
Block
type
Low Gate type
Q output
QB output
Normal
Name
cells
Name
cells
Name
cells
F661
8
F661NQ
7
F661NB
7
Name
Low Power
x1
Chapter 2 Function Block
cells
Q output
QB output
Name
cells
L661
6
Name
F661
CB → QB
x4
D
H01
CB H02
CB → Q
cells
L661
Set up time
Hold time
Min Pulse
CB → Q
F661NQ
Set up time
Hold time
Min Pulse
CB → Q
F661NB
Set up time
Hold time
Min Pulse
CB → QB
x2
Logic Diagram for "Normal"
IN
Path
→ OUT
Truth Table for "Normal"
N01
N02
Q
QB
D
CB
Q
QB
0
0
1
1
1
0
Hold
X
X:Irrelevant
Set up time
Hold time
Min Pulse
Logic Diagram for "Q output"
D
H01
(LH)
(LL)
(LH)
(LL)
D
D
CB
(LH)
(LL)
D
D
CB
(LH)
(LL)
D
D
CB
(LH)
(LL)
D
D
CB
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.376
0.354
0.447
0.502
0.560
0.370
0.706
0.374
0.353
0.570
0.370
0.579
0.375
0.353
0.560
0.370
0.580
0.293
0.335
0.570
0.370
0.549
0.629
0.579
0.745
0.844
1.199
1.085
1.434
1.610
0.990
0.370
1.933
1.195
1.087
0.990
0.370
1.518
1.197
1.087
0.990
0.370
1.521
0.909
1.069
0.990
0.380
1.399
0.011
0.010
0.011
0.010
0.015
0.013
0.015
0.013
0.021
0.017
0.021
0.017
0.022
0.020
0.030
0.025
0.042
0.034
0.011
0.010
0.015
0.013
0.011
0.011
0.016
0.014
0.628
0.580
0.628
0.580
0.480
0.561
Symbol
D
CB
Output
Fanin Symbol Fanout
1.0
1.0
Q
QB
35
35
D
CB
1.0
1.0
Q
17
0.021
0.017
D
CB
1.0
1.0
Q
35
0.022
0.020
D
CB
1.0
1.0
QB
34
Truth Table for "Q output"
N01
Q
D
CB
CB H02
Q
0
0
1
1
X
Hold
X:Irrelevant
Logic Diagram for "QB output"
D
Truth Table for "QB output"
D
H01
0
CB H02
N01
QB
CB
QB
1
1
0
X
Hold
X:Irrelevant
Block Library
A13872EJ5V0BL
2 - 278
Block Library
A13872EJ5V0BL
2 - 279
Chapter 2 Function Block
Function
D-F/F (CB) with RB
Standard type
Block type
Normal
Drivability
Chapter 2 Function Block
Block
type
Low Gate type
Q output
QB output
Name
cells
Name
cells
Name
cells
F665
9
F665NQ
8
F665NB
8
Normal
Name
cells
Q output
Name
cells
QB output
Name
F665
CB → QB
F665NQ
RB → Q
RB → QB
Set up time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
CB → Q
F665NB
RB → Q
Set up time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
CB → QB
x2
x4
Logic Diagram for "Normal"
D
H01
Truth Table for "Normal"
N01
CB H02
N02
Q
QB
D
RB
Q
QB
0
1
0
1
1
1
1
0
X
1
X
H03
RB
H01
N01
Q
D
0
1
RB → QB
Set up time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
CB
RB
Q
1
0
1
1
1
X
1
Hold
0
0
X
(LH)
(LL)
(LH)
(LL)
(LL)
(LH)
D
D
RB
RB
CB
RB
(LH)
(LL)
(LL)
D
D
RB
RB
CB
RB
(LH)
(LL)
(LH)
D
D
RB
RB
CB
RB
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.447
0.376
0.476
0.582
0.199
0.304
0.570
0.360
0.180
0.670
0.789
0.546
0.449
0.377
0.199
0.570
0.360
0.180
0.670
0.656
0.384
0.317
0.358
0.325
0.580
0.370
0.170
0.630
0.575
0.633
0.759
0.616
0.789
0.988
0.310
0.566
1.496
1.154
1.504
1.942
0.533
1.026
1.020
0.370
0.000
1.140
2.264
1.335
1.501
1.160
0.537
1.020
0.370
0.000
1.140
1.824
0.837
0.975
1.143
1.454
1.010
0.390
0.000
1.070
1.474
1.754
0.012
0.010
0.012
0.010
0.010
0.012
0.016
0.013
0.016
0.013
0.013
0.016
0.023
0.017
0.022
0.017
0.017
0.022
0.012
0.010
0.010
0.016
0.013
0.013
0.023
0.017
0.017
0.012
0.011
0.012
0.016
0.014
0.016
0.023
0.020
0.023
0.761
0.618
0.313
0.518
0.601
0.754
Symbol
D
CB
RB
Output
Fanin Symbol Fanout
1.0
1.0
2.2
Q
QB
31
31
D
CB
RB
1.0
1.0
2.3
Q
31
D
CB
RB
1.0
1.0
2.3
QB
31
X:Irrelevant
H03
RB
Logic Diagram for "QB output"
Truth Table for "QB output"
D
H01
N01
QB
CB
RB
QB
1
0
1
1
1
0
X
1
Hold
0
1
X
H03
RB
0
0
X
CB H02
X
Hold
Truth Table for "Q output"
CB H02
D
CB
X:Irrelevant
Logic Diagram for "Q output"
D
CB → Q
cells
Low Power
x1
IN
Path
→ OUT
X
X:Irrelevant
Block Library
A13872EJ5V0BL
2 - 280
Block Library
A13872EJ5V0BL
2 - 281
Chapter 2 Function Block
Function
D-F/F (CB) with SB
Standard type
Block type
Normal
Drivability
Chapter 2 Function Block
Block
type
Low Gate type
Q output
QB output
Name
cells
Name
cells
Name
cells
F666
9
F666NQ
8
F666NB
8
Normal
Name
cells
Q output
Name
cells
QB output
Name
F666
CB → QB
F666NQ
SB → Q
SB → QB
Set up time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
CB → Q
F666NB
SB → Q
Set up time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
CB → QB
x2
x4
Logic Diagram for "Normal"
Truth Table for "Normal"
SB
H03
D
H01
D
N01
Q
SB
Q
QB
0
1
0
1
1
1
1
0
X
1
X
CB H02
N02
QB
Logic Diagram for "Q output"
H01
D
N01
Q
0
1
0
SB → QB
Set up time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
SB
Q
0
CB
1
0
1
1
1
X
1
Hold
0
1
X
(LH)
(LL)
(LH)
(LL)
(LH)
(LL)
D
D
SB
SB
CB
SB
(LH)
(LL)
(LH)
D
D
SB
SB
CB
SB
(LH)
(LL)
(LL)
D
D
SB
SB
CB
SB
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.374
0.366
0.518
0.501
0.334
0.212
0.610
0.380
0.420
0.400
0.724
0.671
0.373
0.366
0.312
0.610
0.380
0.420
0.400
0.574
0.536
0.323
0.333
0.279
0.620
0.390
0.430
0.380
0.545
0.520
0.624
0.605
0.885
0.841
0.659
0.423
1.189
1.145
1.774
1.598
1.230
0.712
1.310
0.390
0.730
0.430
2.107
1.574
1.187
1.147
1.048
1.310
0.390
0.730
0.430
1.509
1.372
1.022
1.061
0.929
1.300
0.390
0.710
0.410
1.391
1.267
0.011
0.010
0.011
0.010
0.011
0.010
0.015
0.013
0.015
0.013
0.015
0.013
0.021
0.017
0.021
0.017
0.021
0.018
0.011
0.010
0.011
0.015
0.013
0.015
0.021
0.017
0.021
0.011
0.011
0.010
0.016
0.014
0.014
0.023
0.020
0.019
0.623
0.604
0.558
0.532
0.558
0.502
Symbol
D
CB
SB
Output
Fanin Symbol Fanout
1.0
1.0
2.2
Q
QB
35
34
D
CB
SB
1.0
1.0
2.2
Q
35
D
CB
SB
1.0
1.0
2.2
QB
32
X:Irrelevant
CB H02
Logic Diagram for "QB output"
Truth Table for "QB output"
SB
H03
D
H01
N01
QB
CB
SB
QB
1
0
1
1
1
0
X
1
Hold
0
0
X
CB H02
X
Hold
X:Irrelevant
X
D
CB
Truth Table for "Q output"
SB
H03
D
CB → Q
cells
Low Power
x1
IN
Path
→ OUT
X
X:Irrelevant
Block Library
A13872EJ5V0BL
2 - 282
Block Library
A13872EJ5V0BL
2 - 283
Chapter 2 Function Block
Function
D-F/F (CB) with RB, SB
Standard type
Block type
Normal
Drivability
Chapter 2 Function Block
Low Gate type
Q output
QB output
Name
cells
Name
cells
Name
cells
F667
10
F667NQ
9
F667NB
9
Normal
Name
Q output
cells
Low Power
x1
Block
type
QB output
Name
cells
L667
8
Name
F667
CB → QB
L667
RB → Q
RB → QB
SB → Q
SB → QB
Set up time
Hold time
Release time
Release time
Removal time
Removal time
Min Pulse
Min Pulse
Min Pulse
CB → Q
F667NQ
RB → Q
SB → Q
Set up time
Hold time
Release time
Release time
Removal time
Removal time
Min Pulse
Min Pulse
Min Pulse
CB → Q
F667NB
RB → Q
SB → Q
Set up time
Hold time
Release time
Release time
Removal time
Removal time
Min Pulse
Min Pulse
Min Pulse
CB → QB
x4
Truth Table for "Normal"
SB
H04
D H01
D
N01 Q
CB H02
N02 QB
CB
SB
Q
QB
1
1
0
1
1
1
1
1
X
1
1
Logic Diagram for "Q output"
X
X
0
1
0
1
X
X
1
0
1
0
X
X
0
0
0
0
D
N01 Q
CB H02
RB
SB
Q
0
CB
1
1
0
1
1
1
1
X
1
1
Hold
X
X
0
1
0
X
X
1
0
1
X
X
0
0
0
← Prohibition
X:Irrelevant
H03
RB
Logic Diagram for "QB output"
Truth Table for "QB output"
SB
H04
D
D H01
CB
RB
SB
QB
0
1
1
1
1
1
1
0
1
1
Hold
X
X
0
1
1
X
X
1
0
0
X
X
0
0
0
X
N01 QB
H03
RB
← Prohibition
Truth Table for "Q output"
SB
H04
CB H02
0
Hold
X:Irrelevant
H03
RB
D H01
RB
0
RB → QB
SB → QB
Set up time
Hold time
Release time
Release time
Removal time
Removal time
Min Pulse
Min Pulse
Min Pulse
← Prohibition
X:Irrelevant
Block Library
A13872EJ5V0BL
CB → Q
cells
x2
Logic Diagram for "Normal"
IN
Path
→ OUT
2 - 284
(LH)
(LL)
(LH)
(LL)
(LL)
(LH)
(LH)
(LL)
D
D
RB
SB
RB
SB
CB
RB
SB
(LH)
(LL)
(LL)
(LH)
D
D
RB
SB
RB
SB
CB
RB
SB
(LH)
(LL)
(LL)
(LH)
D
D
RB
SB
RB
SB
CB
RB
SB
(LH)
(LL)
(LH)
(LL)
D
D
RB
SB
RB
SB
CB
RB
SB
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.426
0.375
0.524
0.553
0.178
0.331
0.385
0.187
0.600
0.370
0.170
0.400
0.690
0.420
0.755
0.613
0.656
0.427
0.377
0.182
0.359
0.600
0.370
0.170
0.400
0.690
0.420
0.629
0.356
0.607
0.425
0.374
0.178
0.358
0.600
0.370
0.170
0.400
0.690
0.420
0.627
0.354
0.608
0.330
0.335
0.373
0.275
0.610
0.380
0.160
0.410
0.640
0.410
0.547
0.713
0.520
0.723
0.615
0.890
0.943
0.275
0.680
0.724
0.384
1.429
1.160
1.782
1.855
0.466
1.338
1.421
0.655
1.300
0.380
0.000
0.730
1.220
0.480
2.176
1.646
1.768
1.412
1.165
0.476
1.264
1.310
0.380
0.000
0.720
1.220
0.480
1.733
0.752
1.598
1.428
1.161
0.466
1.286
1.320
0.380
0.000
0.730
1.220
0.480
1.751
0.757
1.618
1.037
1.059
1.807
0.919
1.310
0.400
0.000
0.700
1.120
0.460
1.389
2.112
1.253
0.011
0.010
0.011
0.010
0.010
0.011
0.011
0.010
0.015
0.013
0.015
0.013
0.013
0.015
0.015
0.013
0.022
0.017
0.021
0.017
0.017
0.022
0.022
0.018
0.022
0.020
0.020
0.022
0.030
0.025
0.025
0.030
0.043
0.034
0.034
0.042
0.011
0.010
0.010
0.011
0.015
0.013
0.013
0.015
0.011
0.011
0.011
0.011
0.016
0.014
0.016
0.014
0.721
0.619
0.282
0.651
0.722
0.614
0.276
0.654
0.542
0.560
0.888
0.498
Block Library
A13872EJ5V0BL
Symbol
D
CB
RB
SB
Output
Fanin Symbol Fanout
1.0
1.0
2.3
2.2
Q
QB
34
32
D
CB
RB
SB
1.0
1.0
2.3
2.1
Q
16
0.022
0.017
0.017
0.022
D
CB
RB
SB
1.0
1.0
2.3
2.2
Q
34
0.023
0.020
0.023
0.020
D
CB
RB
SB
1.0
1.0
2.3
2.2
QB
32
2 - 285
Chapter 2 Function Block
Function
D-F/F with 2 to 1 Selector
Standard type
Block type
Normal
Drivability
Chapter 2 Function Block
Block
type
Low Gate type
Q output
QB output
Name
cells
Name
cells
Name
cells
F641S
10
F641SQ
9
F641SB
9
Normal
Name
Q output
cells
Name
cells
QB output
Name
F641S
C → Q
cells
C → QB
Low Power
x1
IN
Path
→ OUT
F641SQ
Set up time
Set up time
Set up time
Hold time
Hold time
Hold time
Min Pulse
C → Q
F641SB
Set up time
Set up time
Set up time
Hold time
Hold time
Hold time
Min Pulse
C → QB
x2
x4
Logic Diagram for "Normal"
D0 H01
D1 H02
C H03
A H04
Truth Table for "Normal"
N01
N02
Q
QB
D0
D1
A
Q
QB
0
X
C
0
0
1
1
X
0
1
0
X
0
1
0
1
X
1
1
1
X
X
0
Hold
X
X
1
Hold
0
X:Irrelevant
Logic Diagram for "Q output"
D0 H01
D1 H02
Set up time
Set up time
Set up time
Hold time
Hold time
Hold time
Min Pulse
Truth Table for "Q output"
N01
Q
C H03
A H04
D0
D1
A
Q
0
X
C
0
0
1
X
0
1
X
0
1
0
X
1
1
1
X
X
0
Hold
X
X
1
Hold
(HH)
(HL)
(HH)
(HL)
D0
D1
A
D0
D1
A
C
(HH)
(HL)
D0
D1
A
D0
D1
A
C
(HH)
(HL)
D0
D1
A
D0
D1
A
C
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.363
0.410
0.502
0.489
0.680
0.680
0.680
0.270
0.270
0.250
0.684
0.363
0.409
0.680
0.680
0.680
0.270
0.270
0.250
0.583
0.339
0.346
0.680
0.680
0.680
0.270
0.280
0.260
0.544
0.555
0.663
0.828
0.771
1.000
1.226
1.572
1.409
1.500
1.500
1.660
0.000
0.000
0.000
1.951
1.001
1.227
1.500
1.500
1.650
0.000
0.000
0.000
1.607
1.005
0.960
1.470
1.470
1.630
0.010
0.010
0.000
1.385
0.011
0.010
0.011
0.010
0.015
0.013
0.015
0.013
0.021
0.017
0.021
0.017
0.011
0.010
0.015
0.013
0.021
0.017
0.011
0.011
0.015
0.014
0.022
0.020
0.556
0.663
0.542
0.545
Symbol
D0
D1
C
A
Output
Fanin Symbol Fanout
1.0
1.0
1.0
1.0
Q
QB
35
35
D0
D1
C
A
1.0
1.0
1.0
1.0
Q
35
D0
D1
C
A
1.0
1.0
1.0
1.0
QB
34
X:Irrelevant
Logic Diagram for "QB output"
Truth Table for "QB output"
D0
D0 H01
D1 H02
C H03
A H04
N01
QB
D1
C
A
QB
0
X
0
1
1
X
0
0
X
0
1
1
X
1
1
0
X
X
0
Hold
X
X
1
Hold
X:Irrelevant
Block Library
A13872EJ5V0BL
2 - 286
Block Library
A13872EJ5V0BL
2 - 287
Chapter 2 Function Block
Function
D-F/F with R, 2 to 1 Selector
Standard type
Block type
Normal
Drivability
Chapter 2 Function Block
Block
type
Low Gate type
Q output
QB output
Name
cells
Name
cells
Name
cells
F642S
11
F642SQ
10
F642SB
10
Normal
Name
Q output
cells
Name
cells
QB output
Name
F642S
C → Q
cells
C → QB
Low Power
x1
IN
Path
→ OUT
F642SQ
R → Q
R → QB
Set up time
Set up time
Set up time
Hold time
Hold time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
C → Q
F642SB
R → Q
Set up time
Set up time
Set up time
Hold time
Hold time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
C → QB
x2
x4
Logic Diagram for "Normal"
D0 H01
D1 H02
Truth Table for "Normal"
N01
C H03
A H05
N02
Q
QB
H04
R
D0
D1
R
A
Q
QB
0
X
C
0
0
0
1
1
X
0
0
1
X
X
0
0
X
0
0
1
0
1
X
1
0
1
1
0
X
X
0
1
X
X
1
X
X
0
Hold
Hold
0
1
X:Irrelevant
Logic Diagram for "Q output"
D0 H01
D1 H02
Truth Table for "Q output"
N01
Q
C H03
A H05
H04
R
D0
D1
R
A
Q
0
X
C
0
0
0
1
X
0
0
1
X
X
0
0
Hold
X
0
0
1
0
X
1
0
1
1
X
X
0
1
Hold
X
X
1
X
0
R
A
QB
1
X
R → QB
Set up time
Set up time
Set up time
Hold time
Hold time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
X:Irrelevant
Logic Diagram for "QB output"
Truth Table for "QB output"
D0
D0 H01
D1 H02
C H03
A H05
N01
H04
R
QB
D1
C
0
X
0
0
1
X
0
0
0
X
X
0
0
Hold
X
0
0
1
1
X
1
0
1
0
X
X
0
1
Hold
X
X
1
X
1
X
(HH)
(HL)
(HH)
(HL)
(HL)
(HH)
D0
D1
A
D0
D1
A
R
R
C
R
(HH)
(HL)
(HL)
D0
D1
A
D0
D1
A
R
R
C
R
(HH)
(HL)
(HH)
D0
D1
A
D0
D1
A
R
R
C
R
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.377
0.408
0.498
0.580
0.361
0.180
0.730
0.730
0.730
0.280
0.280
0.260
0.410
0.400
0.795
0.582
0.372
0.401
0.337
0.740
0.740
0.740
0.270
0.280
0.260
0.410
0.400
0.577
0.533
0.329
0.358
0.262
0.750
0.740
0.740
0.280
0.290
0.270
0.420
0.390
0.564
0.500
0.574
0.659
0.824
0.928
0.604
0.329
1.034
1.222
1.571
1.711
1.129
0.573
2.140
2.130
2.290
0.000
0.010
0.000
1.240
0.270
2.107
1.596
1.029
1.214
1.050
2.150
2.140
2.300
0.000
0.000
0.000
1.250
0.270
1.585
1.495
0.987
1.034
0.817
2.020
2.000
2.160
0.000
0.000
0.000
1.110
0.240
1.426
1.298
0.011
0.010
0.011
0.010
0.010
0.011
0.015
0.013
0.015
0.013
0.013
0.015
0.022
0.017
0.021
0.019
0.017
0.022
0.011
0.010
0.010
0.015
0.013
0.013
0.022
0.017
0.017
0.011
0.011
0.011
0.015
0.015
0.015
0.022
0.022
0.022
0.570
0.653
0.564
0.528
0.572
0.434
Symbol
D0
D1
C
R
A
Output
Fanin Symbol Fanout
1.0
1.0
1.0
2.2
1.0
Q
QB
35
34
D0
D1
C
R
A
1.0
1.0
1.0
2.2
1.0
Q
35
D0
D1
C
R
A
1.0
1.0
1.0
2.2
1.0
QB
34
X:Irrelevant
Block Library
A13872EJ5V0BL
2 - 288
Block Library
A13872EJ5V0BL
2 - 289
Chapter 2 Function Block
Function
D-F/F with S, 2 to 1 Selector
Standard type
Block type
Normal
Drivability
Chapter 2 Function Block
Block
type
Low Gate type
Q output
QB output
Name
cells
Name
cells
Name
cells
F643S
11
F643SQ
10
F643SB
10
Normal
Name
Q output
cells
Name
cells
QB output
Name
F643S
C → QB
F643SQ
S → Q
S → QB
Set up time
Set up time
Set up time
Hold time
Hold time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
C → Q
F643SB
S → Q
Set up time
Set up time
Set up time
Hold time
Hold time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
C → QB
x2
x4
Logic Diagram for "Normal"
Truth Table for "Normal"
S
H04
D0 H01
D1 H02
N01
C H03
A H05
N02
Q
QB
D0
D1
S
A
Q
QB
0
X
C
0
0
0
1
1
X
0
0
1
X
X
0
0
X
0
0
1
0
1
X
1
0
1
1
0
X
X
0
1
X
X
1
X
X
0
Hold
Hold
1
0
X:Irrelevant
Logic Diagram for "Q output"
Truth Table for "Q output"
S
H04
D0 H01
D1 H02
N01
Q
C H03
A H05
D0
D1
S
A
Q
0
X
C
0
0
0
1
X
0
0
1
X
X
0
0
Hold
X
0
0
1
0
X
1
0
1
1
X
X
0
1
Hold
X
X
1
X
1
S
A
QB
1
X
S → QB
Set up time
Set up time
Set up time
Hold time
Hold time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
X:Irrelevant
Logic Diagram for "QB output"
Truth Table for "QB output"
S
H04
D0
D0 H01
D1 H02
C H03
A H05
C → Q
cells
Low Power
x1
IN
Path
→ OUT
N01
QB
D1
C
0
X
0
0
1
X
0
0
0
X
X
0
0
Hold
X
0
0
1
1
X
1
0
1
0
X
X
0
1
Hold
X
X
1
X
0
X
(HH)
(HL)
(HH)
(HL)
(HH)
(HL)
D0
D1
A
D0
D1
A
S
S
C
S
(HH)
(HL)
(HH)
D0
D1
A
D0
D1
A
S
S
C
S
(HH)
(HL)
(HL)
D0
D1
A
D0
D1
A
S
S
C
S
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.369
0.494
0.604
0.502
0.178
0.318
0.680
0.690
0.690
0.260
0.260
0.240
0.110
0.730
0.778
0.496
0.369
0.493
0.178
0.680
0.690
0.690
0.260
0.260
0.240
0.110
0.730
0.668
0.295
0.340
0.350
0.343
0.690
0.690
0.690
0.260
0.260
0.240
0.110
0.690
0.548
0.602
0.566
0.803
0.999
0.792
0.260
0.580
1.017
1.490
1.904
1.440
0.439
1.042
1.540
1.540
1.700
0.000
0.000
0.000
0.000
1.190
2.283
1.429
1.018
1.492
0.440
1.540
1.540
1.700
0.000
0.000
0.000
0.000
1.190
1.870
0.830
1.000
0.961
1.454
1.530
1.520
1.680
0.000
0.010
0.000
0.000
1.130
1.380
1.855
0.011
0.010
0.011
0.010
0.011
0.010
0.015
0.013
0.015
0.013
0.015
0.013
0.021
0.019
0.021
0.017
0.022
0.018
0.011
0.010
0.011
0.015
0.013
0.015
0.021
0.019
0.022
0.011
0.011
0.011
0.015
0.014
0.014
0.022
0.020
0.019
0.566
0.803
0.260
0.542
0.548
0.757
Symbol
D0
D1
C
S
A
Output
Fanin Symbol Fanout
1.0
1.0
1.0
2.2
1.0
Q
QB
35
35
D0
D1
C
S
A
1.0
1.0
1.0
2.2
1.0
Q
35
D0
D1
C
S
A
1.0
1.0
1.0
2.2
1.0
QB
34
X:Irrelevant
Block Library
A13872EJ5V0BL
2 - 290
Block Library
A13872EJ5V0BL
2 - 291
Chapter 2 Function Block
Function
D-F/F with R, S, 2 to 1 Selector
Standard type
Block type
Normal
Drivability
Chapter 2 Function Block
Q output
Block
type
Low Gate type
QB output
Normal
Name
cells
Name
cells
Name
cells
F644S
12
F644SQ
11
F644SB
11
Name
Q output
cells
Name
cells
QB output
Name
F644S
C → Q
cells
C → QB
Low Power
x1
IN
Path
→ OUT
F644SQ
R → Q
R → QB
S → Q
S → QB
Set up time
Set up time
Set up time
Hold time
Hold time
Hold time
Release time
Release time
Removal time
Removal time
Min Pulse
Min Pulse
Min Pulse
C → Q
F644SB
R → Q
S → Q
Set up time
Set up time
Set up time
Hold time
Hold time
Hold time
Release time
Release time
Removal time
Removal time
Min Pulse
Min Pulse
Min Pulse
C → QB
x2
x4
Logic Diagram for "Normal"
Truth Table for "Normal"
S
H05
D0 H01
D1 H02
N01 Q
C H03
A H06
N02 QB
H04
R
N01 Q
C H03
A H06
H04
R
C
S
A
Q
QB
0
0
0
0
1
1
X
0
0
0
1
X
X
0
0
0
X
0
0
0
1
0
X
1
0
0
1
1
X
X
0
0
1
X
X
X
0
1
X
1
0
X
X
X
1
0
X
0
1
X
X
X
1
1
X
1
1
0
Hold
1
0
Hold
← Prohibition
D0
D1
R
S
A
Q
0
X
C
0
0
0
0
1
X
0
0
0
1
X
X
0
0
0
Hold
X
0
0
0
1
0
X
1
0
0
1
1
X
X
0
0
1
Hold
X
X
X
0
1
X
1
X
X
X
1
0
X
0
X
X
X
1
1
X
1
← Prohibition
X:Irrelevant
Logic Diagram for "QB output"
R → QB
S → QB
Set up time
Set up time
Set up time
Hold time
Hold time
Hold time
Release time
Release time
Removal time
Removal time
Min Pulse
Min Pulse
Min Pulse
Truth Table for "QB output"
S
H05
D0 H01
D1 H02
N01 QB
H04
R
R
X
Truth Table for "Q output"
S
H05
C H03
A H06
D1
0
X:Irrelevant
Logic Diagram for "Q output"
D0 H01
D1 H02
D0
D0
D1
R
S
A
QB
0
X
C
0
0
0
1
1
X
0
0
0
0
X
X
0
0
0
Hold
X
0
0
0
1
1
X
1
0
0
1
0
X
X
0
0
1
Hold
X
X
X
0
1
X
0
X
X
X
1
0
X
1
X
X
X
1
1
X
1
← Prohibition
X:Irrelevant
Block Library
A13872EJ5V0BL
2 - 292
(HH)
(HL)
(HH)
(HL)
(HL)
(HH)
(HH)
(HL)
D0
D1
A
D0
D1
A
R
S
R
S
C
R
S
(HH)
(HL)
(HL)
(HH)
D0
D1
A
D0
D1
A
R
S
R
S
C
R
S
(HH)
(HL)
(HH)
(HL)
D0
D1
A
D0
D1
A
R
S
R
S
C
R
S
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.379
0.478
0.574
0.588
0.415
0.185
0.173
0.380
0.730
0.730
0.720
0.270
0.270
0.260
0.380
0.110
0.430
0.750
0.791
0.690
0.622
0.379
0.479
0.404
0.173
0.730
0.730
0.720
0.270
0.270
0.260
0.380
0.110
0.430
0.750
0.645
0.606
0.284
0.330
0.363
0.264
0.449
0.730
0.740
0.730
0.280
0.280
0.260
0.400
0.110
0.420
0.690
0.562
0.492
0.721
0.581
0.781
0.962
0.942
0.720
0.337
0.254
0.782
1.047
1.458
1.854
1.735
1.361
0.584
0.429
1.443
2.120
2.130
2.270
0.000
0.000
0.000
1.210
0.000
0.320
1.210
2.225
1.845
1.817
1.048
1.464
1.260
0.430
2.130
2.130
2.280
0.000
0.000
0.000
1.220
0.000
0.320
1.210
1.836
1.702
0.811
0.984
1.048
0.801
1.850
2.010
2.020
2.170
0.000
0.000
0.000
1.110
0.000
0.290
1.140
1.439
1.277
2.241
0.011
0.010
0.011
0.010
0.010
0.011
0.011
0.010
0.015
0.013
0.015
0.013
0.013
0.015
0.015
0.014
0.022
0.019
0.021
0.019
0.018
0.022
0.022
0.021
0.011
0.010
0.010
0.011
0.015
0.013
0.013
0.015
0.022
0.019
0.019
0.022
0.011
0.011
0.011
0.011
0.015
0.015
0.015
0.015
0.022
0.022
0.022
0.022
0.581
0.783
0.667
0.254
0.530
0.579
0.427
0.949
Block Library
A13872EJ5V0BL
Symbol
D0
D1
C
R
S
A
Output
Fanin Symbol Fanout
1.0
1.0
1.0
2.1
2.3
1.0
Q
QB
35
34
D0
D1
C
R
S
A
1.0
1.0
1.0
2.1
2.3
1.0
Q
35
D0
D1
C
R
S
A
1.0
1.0
1.0
2.1
2.3
1.0
QB
33
2 - 293
Chapter 2 Function Block
Function
D-F/F with RB, 2 to 1 Selector
Standard type
Block type
Normal
Drivability
Chapter 2 Function Block
Block
type
Low Gate type
Q output
QB output
Name
cells
Name
cells
Name
cells
F615S
11
F615SQ
10
F615SB
10
Normal
Name
Q output
cells
Name
cells
QB output
Name
F615S
C → Q
cells
C → QB
Low Power
x1
IN
Path
→ OUT
F615SQ
RB → Q
RB → QB
Set up time
Set up time
Set up time
Hold time
Hold time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
C → Q
F615SB
RB → Q
Set up time
Set up time
Set up time
Hold time
Hold time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
C → QB
x2
x4
Logic Diagram for "Normal"
D0 H01
D1 H02
Truth Table for "Normal"
N01
C H03
A H05
N02
Q
QB
H04
RB
D0
D1
RB
A
Q
QB
0
X
C
1
0
0
1
1
X
1
0
1
X
X
1
0
X
0
1
1
0
1
X
1
1
1
1
0
X
X
1
1
X
X
0
X
X
0
Hold
Hold
0
1
X:Irrelevant
Logic Diagram for "Q output"
D0 H01
D1 H02
Truth Table for "Q output"
N01
Q
C H03
A H05
H04
RB
D0
D1
RB
A
Q
0
X
C
1
0
0
1
X
1
0
1
X
X
1
0
Hold
X
0
1
1
0
X
1
1
1
1
X
X
1
1
Hold
X
X
0
X
0
RB
A
QB
1
X
RB → QB
Set up time
Set up time
Set up time
Hold time
Hold time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
X:Irrelevant
Logic Diagram for "QB output"
Truth Table for "QB output"
D0
D0 H01
D1 H02
C H03
A H05
N01
H04
RB
QB
D1
C
0
X
1
0
1
X
1
0
0
X
X
1
0
Hold
X
0
1
1
1
X
1
1
1
0
X
X
1
1
Hold
X
X
0
X
1
X
(HH)
(HL)
(HH)
(HL)
(LL)
(LH)
D0
D1
A
D0
D1
A
RB
RB
C
RB
(HH)
(HL)
(LL)
D0
D1
A
D0
D1
A
RB
RB
C
RB
(HH)
(HL)
(LH)
D0
D1
A
D0
D1
A
RB
RB
C
RB
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.423
0.422
0.521
0.556
0.199
0.305
0.700
0.700
0.700
0.270
0.270
0.250
0.190
0.670
0.747
0.547
0.423
0.422
0.199
0.700
0.700
0.700
0.260
0.270
0.250
0.190
0.670
0.614
0.384
0.351
0.356
0.327
0.710
0.710
0.700
0.270
0.270
0.250
0.170
0.630
0.548
0.626
0.673
0.685
0.856
0.902
0.311
0.567
1.278
1.274
1.620
1.723
0.535
1.028
1.560
1.570
1.720
0.000
0.000
0.000
0.000
1.010
2.104
1.337
1.282
1.276
0.537
1.570
1.570
1.720
0.000
0.000
0.000
0.000
1.010
1.664
0.837
1.051
1.010
1.443
1.550
1.550
1.700
0.000
0.000
0.000
0.000
0.960
1.426
1.743
0.012
0.010
0.012
0.010
0.010
0.012
0.016
0.013
0.016
0.013
0.013
0.016
0.023
0.017
0.022
0.017
0.017
0.022
0.012
0.010
0.010
0.016
0.013
0.013
0.023
0.017
0.017
0.012
0.011
0.012
0.016
0.014
0.016
0.023
0.020
0.023
0.674
0.684
0.312
0.564
0.567
0.748
Symbol
D0
D1
C
RB
A
Output
Fanin Symbol Fanout
1.0
1.0
1.0
2.2
1.0
Q
QB
31
31
D0
D1
C
RB
A
1.0
1.0
1.0
2.3
1.0
Q
31
D0
D1
C
RB
A
1.0
1.0
1.0
2.3
1.0
QB
31
X:Irrelevant
Block Library
A13872EJ5V0BL
2 - 294
Block Library
A13872EJ5V0BL
2 - 295
Chapter 2 Function Block
Function
D-F/F with SB, 2 to 1 Selector
Standard type
Block type
Normal
Drivability
Chapter 2 Function Block
Block
type
Low Gate type
Q output
QB output
Name
cells
Name
cells
Name
cells
F616S
11
F616SQ
10
F616SB
10
Normal
Name
Q output
cells
Name
cells
QB output
Name
F616S
C → QB
F616SQ
SB → Q
SB → QB
Set up time
Set up time
Set up time
Hold time
Hold time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
C → Q
F616SB
SB → Q
Set up time
Set up time
Set up time
Hold time
Hold time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
C → QB
x2
x4
Logic Diagram for "Normal"
Truth Table for "Normal"
SB
H04
D0 H01
D1 H02
N01
C H03
A H05
N02
Q
QB
D0
D1
SB
A
Q
QB
0
X
C
1
0
0
1
1
X
1
0
1
X
X
1
0
X
0
1
1
0
1
X
1
1
1
1
0
X
X
1
1
X
X
0
X
X
0
Hold
Hold
1
0
X:Irrelevant
Logic Diagram for "Q output"
Truth Table for "Q output"
SB
H04
D0 H01
D1 H02
N01
Q
C H03
A H05
D0
D1
SB
A
Q
0
X
C
1
0
0
1
X
1
0
1
X
X
1
0
Hold
X
0
1
1
0
X
1
1
1
1
X
X
1
1
Hold
X
X
0
X
1
SB
A
QB
1
X
SB → QB
Set up time
Set up time
Set up time
Hold time
Hold time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
X:Irrelevant
Logic Diagram for "QB output"
Truth Table for "QB output"
SB
H04
D0
D0 H01
D1 H02
C H03
A H05
C → Q
cells
Low Power
x1
IN
Path
→ OUT
N01
QB
D1
C
0
X
1
0
1
X
1
0
0
X
X
1
0
Hold
X
0
1
1
1
X
1
1
1
0
X
X
1
1
Hold
X
X
0
X
0
X
(HH)
(HL)
(HH)
(HL)
(LH)
(LL)
D0
D1
A
D0
D1
A
SB
SB
C
SB
(HH)
(HL)
(LH)
D0
D1
A
D0
D1
A
SB
SB
C
SB
(HH)
(HL)
(LL)
D0
D1
A
D0
D1
A
SB
SB
C
SB
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.365
0.431
0.582
0.493
0.335
0.189
0.720
0.720
0.740
0.240
0.240
0.230
0.440
0.370
0.755
0.577
0.366
0.429
0.316
0.720
0.720
0.730
0.240
0.240
0.230
0.440
0.370
0.603
0.535
0.376
0.350
0.282
0.730
0.730
0.750
0.250
0.250
0.230
0.450
0.350
0.549
0.521
0.560
0.699
0.978
0.779
0.620
0.385
1.005
1.310
1.936
1.416
1.172
0.658
1.740
1.740
1.860
0.000
0.000
0.000
0.550
0.380
2.313
1.506
1.007
1.309
1.051
1.740
1.730
1.860
0.000
0.000
0.000
0.550
0.380
1.688
1.374
1.137
0.976
0.929
1.750
1.750
1.880
0.000
0.000
0.000
0.570
0.340
1.517
1.267
0.011
0.010
0.011
0.010
0.011
0.010
0.015
0.013
0.015
0.013
0.015
0.013
0.021
0.017
0.021
0.017
0.021
0.018
0.011
0.010
0.011
0.015
0.013
0.015
0.021
0.017
0.021
0.011
0.011
0.010
0.016
0.014
0.014
0.023
0.020
0.019
0.561
0.695
0.559
0.604
0.553
0.501
Symbol
D0
D1
C
SB
A
Output
Fanin Symbol Fanout
1.0
1.0
1.0
2.2
1.0
Q
QB
35
34
D0
D1
C
SB
A
1.0
1.0
1.0
2.2
1.0
Q
35
D0
D1
C
SB
A
1.0
1.0
1.0
2.2
1.0
QB
32
X:Irrelevant
Block Library
A13872EJ5V0BL
2 - 296
Block Library
A13872EJ5V0BL
2 - 297
Chapter 2 Function Block
Function
D-F/F with RB, SB, 2 to 1 Selector
Standard type
Block type
Normal
Drivability
Chapter 2 Function Block
Q output
Block
type
Low Gate type
QB output
Normal
Name
cells
Name
cells
Name
cells
F647S
12
F647SQ
11
F647SB
11
Name
Q output
cells
Name
cells
QB output
Name
F647S
C → Q
cells
C → QB
Low Power
x1
IN
Path
→ OUT
F647SQ
RB → Q
RB → QB
SB → Q
SB → QB
Set up time
Set up time
Set up time
Hold time
Hold time
Hold time
Release time
Release time
Removal time
Removal time
Min Pulse
Min Pulse
Min Pulse
C → Q
F647SB
RB → Q
SB → Q
Set up time
Set up time
Set up time
Hold time
Hold time
Hold time
Release time
Release time
Removal time
Removal time
Min Pulse
Min Pulse
Min Pulse
C → QB
x2
x4
Logic Diagram for "Normal"
Truth Table for "Normal"
SB
H05
D0 H01
D1 H02
N01 Q
C H03
A H06
N02 QB
H04
RB
N01 Q
C H03
A H06
H04
RB
C
SB
A
Q
QB
1
1
0
0
1
1
X
1
1
0
1
X
X
1
1
0
X
0
1
1
1
0
X
1
1
1
1
1
X
X
1
1
1
X
X
X
0
1
X
0
1
X
X
X
1
0
X
1
0
X
X
X
0
0
X
0
0
0
Hold
1
0
Hold
← Prohibition
D0
D1
RB
SB
A
Q
0
X
C
1
1
0
0
1
X
1
1
0
1
X
X
1
1
0
Hold
X
0
1
1
1
0
X
1
1
1
1
1
X
X
1
1
1
Hold
X
X
X
0
1
X
0
X
X
X
1
0
X
1
X
X
X
0
0
X
0
← Prohibition
X:Irrelevant
Logic Diagram for "QB output"
RB → QB
SB → QB
Set up time
Set up time
Set up time
Hold time
Hold time
Hold time
Release time
Release time
Removal time
Removal time
Min Pulse
Min Pulse
Min Pulse
Truth Table for "QB output"
SB
H05
D0 H01
D1 H02
N01 QB
H04
RB
RB
X
Truth Table for "Q output"
SB
H05
C H03
A H06
D1
0
X:Irrelevant
Logic Diagram for "Q output"
D0 H01
D1 H02
D0
D0
D1
RB
SB
A
QB
0
X
C
1
1
0
1
1
X
1
1
0
0
X
X
1
1
0
Hold
X
0
1
1
1
1
X
1
1
1
1
0
X
X
1
1
1
Hold
X
X
X
0
1
X
1
X
X
X
1
0
X
0
X
X
X
0
0
X
0
← Prohibition
X:Irrelevant
Block Library
A13872EJ5V0BL
2 - 298
(HH)
(HL)
(HH)
(HL)
(LL)
(LH)
(LH)
(LL)
D0
D1
A
D0
D1
A
RB
SB
RB
SB
C
RB
SB
(HH)
(HL)
(LL)
(LH)
D0
D1
A
D0
D1
A
RB
SB
RB
SB
C
RB
SB
(HH)
(HL)
(LH)
(LL)
D0
D1
A
D0
D1
A
RB
SB
RB
SB
C
RB
SB
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.415
0.434
0.584
0.544
0.178
0.332
0.386
0.187
0.710
0.710
0.730
0.250
0.260
0.240
0.170
0.420
0.700
0.390
0.758
0.614
0.657
0.414
0.432
0.178
0.358
0.710
0.710
0.730
0.260
0.260
0.240
0.170
0.420
0.710
0.390
0.608
0.354
0.608
0.382
0.351
0.374
0.275
0.720
0.720
0.740
0.250
0.260
0.240
0.140
0.430
0.660
0.380
0.558
0.714
0.520
0.655
0.701
0.976
0.877
0.275
0.681
0.725
0.385
1.239
1.314
1.934
1.666
0.466
1.340
1.422
0.656
1.720
1.720
1.850
0.000
0.000
0.000
0.000
0.530
1.100
0.440
2.315
1.649
1.769
1.243
1.313
0.466
1.286
1.720
1.720
1.850
0.000
0.000
0.000
0.000
0.520
1.100
0.440
1.695
0.757
1.618
1.152
0.965
1.808
0.921
1.750
1.750
1.880
0.000
0.000
0.000
0.000
0.560
1.020
0.400
1.533
2.114
1.254
0.011
0.010
0.011
0.010
0.010
0.011
0.011
0.010
0.015
0.013
0.015
0.013
0.013
0.015
0.015
0.013
0.022
0.017
0.021
0.017
0.017
0.022
0.022
0.018
0.011
0.010
0.010
0.011
0.015
0.013
0.013
0.015
0.022
0.017
0.017
0.022
0.011
0.011
0.011
0.011
0.016
0.014
0.016
0.014
0.023
0.020
0.023
0.020
0.656
0.697
0.276
0.655
0.613
0.551
0.888
0.499
Block Library
A13872EJ5V0BL
Symbol
D0
D1
C
RB
SB
A
Output
Fanin Symbol Fanout
1.0
1.0
1.0
2.3
2.2
1.0
Q
QB
34
32
D0
D1
C
RB
SB
A
1.0
1.0
1.0
2.3
2.2
1.0
Q
34
D0
D1
C
RB
SB
A
1.0
1.0
1.0
2.3
2.2
1.0
QB
32
2 - 299
Chapter 2 Function Block
Function
D-F/F (CB) with 2 to 1 Selector
Standard type
Block type
Normal
Drivability
Chapter 2 Function Block
Block
type
Low Gate type
Q output
QB output
Name
cells
Name
cells
Name
cells
F661S
10
F661SQ
9
F661SB
9
Normal
Name
Q output
cells
Name
cells
QB output
Name
F661S
CB → Q
cells
CB → QB
Low Power
x1
IN
Path
→ OUT
F661SQ
Set up time
Set up time
Set up time
Hold time
Hold time
Hold time
Min Pulse
CB → Q
F661SB
Set up time
Set up time
Set up time
Hold time
Hold time
Hold time
Min Pulse
CB → QB
x2
x4
Logic Diagram for "Normal"
D0 H01
D1 H02
CB H03
A H04
Truth Table for "Normal"
N01
N02
Q
QB
D0
D1
A
Q
QB
0
X
CB
0
0
1
1
1
X
0
X
X
0
X
0
1
0
X
1
1
1
X
X
1
0
Hold
1
0
Hold
X:Irrelevant
Logic Diagram for "Q output"
D0 H01
D1 H02
Set up time
Set up time
Set up time
Hold time
Hold time
Hold time
Min Pulse
Truth Table for "Q output"
N01
Q
CB H03
A H04
D0
D1
A
Q
0
X
CB
0
0
1
X
0
1
X
X
0
Hold
X
0
1
0
X
1
1
1
X
X
1
Hold
(LH)
(LL)
(LH)
(LL)
D0
D1
A
D0
D1
A
CB
(LH)
(LL)
D0
D1
A
D0
D1
A
CB
(LH)
(LL)
D0
D1
A
D0
D1
A
CB
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.387
0.360
0.453
0.512
0.670
0.670
0.700
0.270
0.270
0.290
0.720
0.387
0.359
0.670
0.670
0.700
0.270
0.270
0.290
0.595
0.301
0.346
0.680
0.680
0.700
0.280
0.280
0.290
0.563
0.641
0.586
0.752
0.857
1.217
1.095
1.444
1.627
1.450
1.450
1.580
0.060
0.060
0.000
1.954
1.217
1.097
1.450
1.450
1.590
0.050
0.050
0.000
1.543
0.921
1.087
1.450
1.440
1.580
0.060
0.060
0.000
1.421
0.011
0.010
0.011
0.010
0.015
0.013
0.015
0.013
0.021
0.017
0.021
0.017
0.011
0.010
0.015
0.013
0.021
0.017
0.011
0.011
0.015
0.014
0.022
0.020
0.641
0.587
0.489
0.575
Symbol
D0
D1
CB
A
Output
Fanin Symbol Fanout
1.0
1.0
1.0
1.0
Q
QB
35
35
D0
D1
CB
A
1.0
1.0
1.0
1.0
Q
35
D0
D1
CB
A
1.0
1.0
1.0
1.0
QB
34
X:Irrelevant
Logic Diagram for "QB output"
Truth Table for "QB output"
D0
D0 H01
D1 H02
CB H03
A H04
N01
QB
D1
CB
A
QB
1
0
X
0
1
X
0
0
X
X
0
Hold
X
0
1
1
X
1
1
0
X
X
1
Hold
X:Irrelevant
Block Library
A13872EJ5V0BL
2 - 300
Block Library
A13872EJ5V0BL
2 - 301
Chapter 2 Function Block
Function
D-F/F (CB) with RB, 2 to 1 Selector
Standard type
Block type
Normal
Drivability
Chapter 2 Function Block
Block
type
Low Gate type
Q output
QB output
Name
cells
Name
cells
Name
cells
F665S
11
F665SQ
10
F665SB
10
Normal
Name
Q output
cells
Name
cells
QB output
Name
F665S
CB → Q
cells
CB → QB
Low Power
x1
IN
Path
→ OUT
F665SQ
RB → Q
RB → QB
Set up time
Set up time
Set up time
Hold time
Hold time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
CB → Q
F665SB
RB → Q
Set up time
Set up time
Set up time
Hold time
Hold time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
CB → QB
x2
x4
Logic Diagram for "Normal"
D0 H01
D1 H02
Truth Table for "Normal"
N01
CB H03
A H05
N02
Q
QB
H04
RB
D0
D1
RB
A
Q
QB
0
X
CB
1
0
0
1
1
X
1
0
1
X
X
1
0
X
0
1
1
0
1
X
1
1
1
1
0
X
X
1
1
X
X
0
X
X
0
Hold
Hold
0
1
X:Irrelevant
Logic Diagram for "Q output"
D0 H01
D1 H02
Truth Table for "Q output"
N01
Q
CB H03
A H05
H04
RB
D0
D1
RB
A
Q
0
X
CB
1
0
0
1
X
1
0
1
X
X
1
0
Hold
X
0
1
1
0
X
1
1
1
1
X
X
1
1
Hold
X
X
0
X
0
RB
A
QB
1
X
RB → QB
Set up time
Set up time
Set up time
Hold time
Hold time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
X:Irrelevant
Logic Diagram for "QB output"
Truth Table for "QB output"
D0
D0 H01
D1 H02
CB H03
A H05
N01
H04
RB
QB
D1
CB
0
X
1
0
1
X
1
0
0
X
X
1
0
Hold
X
0
1
1
1
X
1
1
1
0
X
X
1
1
Hold
X
X
0
X
1
X
(LH)
(LL)
(LH)
(LL)
(LL)
(LH)
D0
D1
A
D0
D1
A
RB
RB
CB
RB
(LH)
(LL)
(LL)
D0
D1
A
D0
D1
A
RB
RB
CB
RB
(LH)
(LL)
(LH)
D0
D1
A
D0
D1
A
RB
RB
CB
RB
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.447
0.375
0.475
0.582
0.199
0.304
0.710
0.700
0.710
0.250
0.250
0.280
0.190
0.650
0.784
0.546
0.446
0.375
0.199
0.710
0.700
0.710
0.250
0.250
0.280
0.190
0.650
0.650
0.383
0.319
0.359
0.329
0.720
0.710
0.710
0.260
0.260
0.280
0.190
0.610
0.573
0.635
0.755
0.614
0.787
0.985
0.310
0.566
1.491
1.151
1.501
1.939
0.533
1.027
1.500
1.490
1.620
0.020
0.030
0.000
0.000
1.110
2.260
1.336
1.493
1.155
0.535
1.500
1.490
1.620
0.020
0.030
0.000
0.000
1.110
1.815
0.835
0.978
1.143
1.458
1.490
1.490
1.610
0.030
0.040
0.000
0.000
1.040
1.473
1.759
0.012
0.010
0.012
0.010
0.010
0.012
0.016
0.013
0.016
0.013
0.013
0.016
0.023
0.017
0.022
0.017
0.017
0.022
0.012
0.010
0.010
0.016
0.013
0.013
0.023
0.017
0.017
0.012
0.011
0.012
0.016
0.014
0.016
0.023
0.020
0.023
0.756
0.613
0.312
0.519
0.601
0.757
Symbol
D0
D1
CB
RB
A
Output
Fanin Symbol Fanout
1.0
1.0
1.0
2.2
1.0
Q
QB
31
31
D0
D1
CB
RB
A
1.0
1.0
1.0
2.3
1.0
Q
31
D0
D1
CB
RB
A
1.0
1.0
1.0
2.3
1.0
QB
31
X:Irrelevant
Block Library
A13872EJ5V0BL
2 - 302
Block Library
A13872EJ5V0BL
2 - 303
Chapter 2 Function Block
Function
D-F/F (CB) with SB, 2 to 1 Selector
Standard type
Block type
Normal
Drivability
Chapter 2 Function Block
Block
type
Low Gate type
Q output
QB output
Name
cells
Name
cells
Name
cells
F666S
11
F666SQ
10
F666SB
10
Normal
Name
Q output
cells
Name
cells
QB output
Name
F666S
CB → QB
F666SQ
SB → Q
SB → QB
Set up time
Set up time
Set up time
Hold time
Hold time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
CB → Q
F666SB
SB → Q
Set up time
Set up time
Set up time
Hold time
Hold time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
CB → QB
x2
x4
Logic Diagram for "Normal"
Truth Table for "Normal"
SB
H04
D0 H01
D1 H02
N01
CB H03
A H05
N02
Q
QB
D0
D1
SB
A
Q
QB
0
X
CB
1
0
0
1
1
X
1
0
1
X
X
1
0
X
0
1
1
0
1
X
1
1
1
1
0
X
X
1
1
X
X
0
X
X
0
Hold
Hold
1
0
X:Irrelevant
Logic Diagram for "Q output"
Truth Table for "Q output"
SB
H04
D0 H01
D1 H02
N01
Q
CB H03
A H05
D0
D1
SB
A
Q
0
X
CB
1
0
0
1
X
1
0
1
X
X
1
0
Hold
X
0
1
1
0
X
1
1
1
1
X
X
1
1
Hold
X
X
0
X
1
SB
A
QB
1
X
SB → QB
Set up time
Set up time
Set up time
Hold time
Hold time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
X:Irrelevant
Logic Diagram for "QB output"
Truth Table for "QB output"
SB
H04
D0
D0 H01
D1 H02
CB H03
A H05
CB → Q
cells
Low Power
x1
IN
Path
→ OUT
N01
QB
D1
CB
0
X
1
0
1
X
1
0
0
X
X
1
0
Hold
X
0
1
1
1
X
1
1
1
0
X
X
1
1
Hold
X
X
0
X
0
X
(LH)
(LL)
(LH)
(LL)
(LH)
(LL)
D0
D1
A
D0
D1
A
SB
SB
CB
SB
(LH)
(LL)
(LH)
D0
D1
A
D0
D1
A
SB
SB
CB
SB
(LH)
(LL)
(LL)
D0
D1
A
D0
D1
A
SB
SB
CB
SB
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.385
0.377
0.529
0.511
0.330
0.189
0.720
0.720
0.750
0.290
0.290
0.300
0.410
0.410
0.735
0.576
0.384
0.376
0.314
0.720
0.720
0.750
0.290
0.290
0.300
0.410
0.410
0.589
0.527
0.335
0.343
0.281
0.730
0.730
0.750
0.290
0.290
0.300
0.420
0.390
0.559
0.514
0.636
0.615
0.895
0.853
0.618
0.383
1.206
1.160
1.790
1.618
1.169
0.656
1.820
1.810
1.950
0.080
0.080
0.000
0.720
0.460
2.125
1.502
1.205
1.162
1.042
1.820
1.820
1.940
0.080
0.080
0.000
0.720
0.460
1.530
1.364
1.041
1.081
0.921
1.790
1.790
1.920
0.080
0.080
0.000
0.680
0.430
1.414
1.257
0.011
0.010
0.011
0.010
0.011
0.010
0.015
0.013
0.015
0.013
0.015
0.013
0.021
0.017
0.021
0.017
0.021
0.018
0.011
0.010
0.011
0.015
0.013
0.015
0.021
0.017
0.021
0.011
0.011
0.010
0.016
0.014
0.014
0.023
0.020
0.019
0.635
0.614
0.553
0.545
0.572
0.496
Symbol
D0
D1
CB
SB
A
Output
Fanin Symbol Fanout
1.0
1.0
1.0
2.2
1.0
Q
QB
35
34
D0
D1
CB
SB
A
1.0
1.0
1.0
2.2
1.0
Q
35
D0
D1
CB
SB
A
1.0
1.0
1.0
2.2
1.0
QB
32
X:Irrelevant
Block Library
A13872EJ5V0BL
2 - 304
Block Library
A13872EJ5V0BL
2 - 305
Chapter 2 Function Block
Function
D-F/F (CB) with RB, SB, 2 to 1 Selector
Standard type
Block type
Normal
Drivability
Chapter 2 Function Block
Q output
Block
type
Low Gate type
QB output
Normal
Name
cells
Name
cells
Name
cells
F667S
12
F667SQ
11
F667SB
11
Name
Q output
cells
Name
cells
QB output
Name
F667S
CB → Q
cells
CB → QB
Low Power
x1
IN
Path
→ OUT
F667SQ
RB → Q
RB → QB
SB → Q
SB → QB
Set up time
Set up time
Set up time
Hold time
Hold time
Hold time
Release time
Release time
Removal time
Removal time
Min Pulse
Min Pulse
Min Pulse
CB → Q
F667SB
RB → Q
SB → Q
Set up time
Set up time
Set up time
Hold time
Hold time
Hold time
Release time
Release time
Removal time
Removal time
Min Pulse
Min Pulse
Min Pulse
CB → QB
x2
x4
Logic Diagram for "Normal"
Truth Table for "Normal"
SB
H05
D0 H01
D1 H02
N01 Q
CB H03
A H06
N02 QB
H04
RB
N01 Q
CB H03
A H06
H04
RB
CB
SB
A
Q
QB
1
1
0
0
1
1
X
1
1
0
1
X
X
1
1
0
X
0
1
1
1
0
X
1
1
1
1
1
X
X
1
1
1
X
X
X
0
1
X
0
1
X
X
X
1
0
X
1
0
X
X
X
0
0
X
0
0
0
Hold
1
0
Hold
← Prohibition
D0
D1
RB
SB
A
Q
0
X
CB
1
1
0
0
1
X
1
1
0
1
X
X
1
1
0
Hold
X
0
1
1
1
0
X
1
1
1
1
1
X
X
1
1
1
Hold
X
X
X
0
1
X
0
X
X
X
1
0
X
1
X
X
X
0
0
X
0
← Prohibition
X:Irrelevant
Logic Diagram for "QB output"
RB → QB
SB → QB
Set up time
Set up time
Set up time
Hold time
Hold time
Hold time
Release time
Release time
Removal time
Removal time
Min Pulse
Min Pulse
Min Pulse
Truth Table for "QB output"
SB
H05
D0 H01
D1 H02
N01 QB
H04
RB
RB
X
Truth Table for "Q output"
SB
H05
CB H03
A H06
D1
0
X:Irrelevant
Logic Diagram for "Q output"
D0 H01
D1 H02
D0
D0
D1
RB
SB
A
QB
0
X
CB
1
1
0
1
1
X
1
1
0
0
X
X
1
1
0
Hold
X
0
1
1
1
1
X
1
1
1
1
0
X
X
1
1
1
Hold
X
X
X
0
1
X
1
X
X
X
1
0
X
0
X
X
X
0
0
X
0
← Prohibition
X:Irrelevant
Block Library
A13872EJ5V0BL
2 - 306
(LH)
(LL)
(LH)
(LL)
(LL)
(LH)
(LH)
(LL)
D0
D1
A
D0
D1
A
RB
SB
RB
SB
CB
RB
SB
(LH)
(LL)
(LL)
(LH)
D0
D1
A
D0
D1
A
RB
SB
RB
SB
CB
RB
SB
(LH)
(LL)
(LH)
(LL)
D0
D1
A
D0
D1
A
RB
SB
RB
SB
CB
RB
SB
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.437
0.382
0.531
0.564
0.179
0.331
0.385
0.187
0.720
0.720
0.750
0.280
0.280
0.290
0.170
0.390
0.680
0.430
0.769
0.614
0.656
0.435
0.381
0.178
0.358
0.720
0.720
0.750
0.280
0.280
0.290
0.170
0.390
0.690
0.430
0.641
0.354
0.608
0.340
0.345
0.374
0.274
0.730
0.720
0.750
0.290
0.290
0.300
0.160
0.410
0.640
0.420
0.561
0.713
0.520
0.736
0.622
0.898
0.956
0.275
0.680
0.724
0.384
1.446
1.171
1.793
1.872
0.466
1.338
1.422
0.656
1.830
1.830
1.960
0.070
0.070
0.000
0.000
0.720
1.220
0.490
2.196
1.646
1.768
1.445
1.172
0.466
1.286
1.830
1.830
1.970
0.070
0.070
0.000
0.000
0.720
1.220
0.490
1.771
0.757
1.617
1.051
1.077
1.807
0.919
1.820
1.820
1.950
0.080
0.080
0.000
0.000
0.690
1.120
0.470
1.411
2.112
1.253
0.011
0.010
0.011
0.010
0.010
0.011
0.011
0.010
0.015
0.013
0.015
0.013
0.013
0.015
0.015
0.013
0.022
0.017
0.021
0.017
0.017
0.022
0.022
0.018
0.011
0.010
0.010
0.011
0.015
0.013
0.013
0.015
0.022
0.017
0.017
0.022
0.011
0.011
0.011
0.011
0.016
0.014
0.016
0.014
0.023
0.020
0.023
0.020
0.734
0.621
0.276
0.655
0.552
0.572
0.887
0.499
Block Library
A13872EJ5V0BL
Symbol
D0
D1
CB
RB
SB
A
Output
Fanin Symbol Fanout
1.0
1.0
1.0
2.3
2.2
1.0
Q
QB
34
32
D0
D1
CB
RB
SB
A
1.0
1.0
1.0
2.3
2.2
1.0
Q
34
D0
D1
CB
RB
SB
A
1.0
1.0
1.0
2.3
2.2
1.0
QB
32
2 - 307
Chapter 2 Function Block
Function
D-F/F with Hold
Standard type
Block type
Normal
Drivability
Chapter 2 Function Block
Q output
Block
type
Low Gate type
QB output
Normal
Name
cells
Name
cells
Name
cells
F641H
10
F641HQ
9
F641HB
9
Name
cells
Q output
Name
cells
QB output
Name
F641H
D
H
D
H
C
F641HQ
Set up time
Set up time
Hold time
Hold time
Min Pulse
C → Q
D
H
D
H
C
F641HB
Set up time
Set up time
Hold time
Hold time
Min Pulse
C → QB
Set up time
Set up time
Hold time
Hold time
Min Pulse
D
H
D
H
C
x4
Logic Diagram for "Normal"
H01
Truth Table for "Normal"
N01
Q
C H02
H
H03
N02
QB
D
C
H
Q
QB
0
0
0
1
1
1
0
X
1
Hold
0
X
X
Hold
X:Irrelevant
Logic Diagram for "Q output"
D
H01
(HH)
(HL)
(HH)
(HL)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.362
0.409
0.528
0.521
0.680
0.670
0.270
0.250
0.714
0.361
0.409
0.680
0.670
0.270
0.250
0.580
0.338
0.345
0.680
0.670
0.270
0.250
0.541
0.554
0.661
0.866
0.821
0.998
1.224
1.639
1.492
1.500
1.590
0.000
0.000
2.015
0.998
1.223
1.500
1.600
0.000
0.000
1.600
1.002
0.958
1.470
1.560
0.010
0.000
1.382
0.011
0.010
0.011
0.010
0.015
0.013
0.015
0.013
0.021
0.017
0.021
0.018
0.011
0.010
0.015
0.013
0.021
0.017
0.011
0.011
0.015
0.014
0.022
0.020
0.554
0.660
0.540
0.543
Symbol
D
C
H
Output
Fanin Symbol Fanout
1.0
1.0
1.0
Q
QB
35
35
D
C
H
1.0
1.0
1.0
Q
35
D
C
H
1.0
1.0
1.0
QB
34
Truth Table for "Q output"
N01
Q
C H02
H
(HH)
(HL)
(HH)
(HL)
C → QB
x2
D
C → Q
cells
Low Power
x1
IN
Path
→ OUT
H03
D
H
Q
0
C
0
0
1
0
1
X
1
Hold
X
X
Hold
X:Irrelevant
Logic Diagram for "QB output"
D
Truth Table for "QB output"
D
H01
C H02
H
H03
N01
QB
C
H
QB
1
0
0
1
0
0
X
1
Hold
X
X
Hold
X:Irrelevant
Block Library
A13872EJ5V0BL
2 - 308
Block Library
A13872EJ5V0BL
2 - 309
Chapter 2 Function Block
Function
D-F/F with RB, Hold
Standard type
Block type
Normal
Drivability
Chapter 2 Function Block
Block
type
Low Gate type
Q output
QB output
Name
cells
Name
cells
Name
cells
F615H
11
F615HQ
10
F615HB
10
Normal
Name
Q output
cells
Name
cells
QB output
Name
F615H
C → QB
F615HQ
RB → Q
RB → QB
Set up time
Set up time
Hold time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
C → Q
F615HB
RB → Q
Set up time
Set up time
Hold time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
C → QB
x2
x4
Logic Diagram for "Normal"
D
H01
Truth Table for "Normal"
N01
Q
C H02
H
H04
N02
QB
D
RB
H
Q
QB
0
C
1
0
0
1
1
1
0
1
X
1
1
1
X
0
X
X
X
H03
RB
H01
N01
Q
H04
D
C
H
Q
0
1
0
0
1
1
0
1
X
1
1
Hold
1
X
Hold
0
X
0
X
H03
RB
D
C H02
N01
QB
C
RB
H
QB
1
0
1
0
1
1
0
0
X
1
1
Hold
1
X
Hold
0
X
1
X
X
H03
RB
(HH)
(HL)
(HH)
(HL)
(LL)
(LH)
D
H
D
H
RB
RB
C
RB
(HH)
(HL)
(LL)
D
H
D
H
RB
RB
C
RB
(HH)
(HL)
(LH)
D
H
D
H
RB
RB
C
RB
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.432
0.436
0.562
0.602
0.199
0.333
0.690
0.680
0.290
0.270
0.170
0.680
0.802
0.576
0.432
0.435
0.199
0.690
0.680
0.290
0.270
0.170
0.680
0.633
0.384
0.366
0.371
0.350
0.690
0.680
0.290
0.260
0.160
0.640
0.572
0.629
0.682
0.702
0.913
0.966
0.311
0.607
1.289
1.297
1.713
1.829
0.534
1.097
1.540
1.630
0.010
0.000
0.000
1.030
2.224
1.407
1.291
1.298
0.535
1.540
1.630
0.010
0.000
0.000
1.030
1.685
0.834
1.077
1.022
1.450
1.540
1.630
0.020
0.000
0.000
0.980
1.462
1.748
0.012
0.010
0.012
0.010
0.010
0.012
0.016
0.013
0.016
0.013
0.013
0.016
0.023
0.017
0.022
0.018
0.017
0.022
0.012
0.010
0.010
0.016
0.013
0.013
0.023
0.017
0.017
0.012
0.011
0.012
0.016
0.014
0.016
0.023
0.020
0.023
0.682
0.701
0.312
0.583
0.579
0.752
Symbol
D
C
RB
H
Output
Fanin Symbol Fanout
1.0
1.0
2.3
1.0
Q
QB
31
31
D
C
RB
H
1.0
1.0
2.3
1.0
Q
31
D
C
RB
H
1.0
1.0
2.3
1.0
QB
31
Truth Table for "QB output"
H01
H04
X
RB → QB
Set up time
Set up time
Hold time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
X:Irrelevant
Logic Diagram for "QB output"
H
1
RB
X
D
Hold
0
Truth Table for "Q output"
C H02
H
X
0
Hold
X:Irrelevant
Logic Diagram for "Q output"
D
C → Q
cells
Low Power
x1
IN
Path
→ OUT
X
X:Irrelevant
Block Library
A13872EJ5V0BL
2 - 310
Block Library
A13872EJ5V0BL
2 - 311
Chapter 2 Function Block
Function
D-F/F with SB, Hold
Standard type
Block type
Normal
Drivability
Chapter 2 Function Block
Block
type
Low Gate type
Q output
QB output
Name
cells
Name
cells
Name
cells
F616H
11
F616HQ
10
F616HB
10
Normal
Name
Q output
cells
Name
cells
QB output
Name
F616H
C → QB
F616HQ
SB → Q
SB → QB
Set up time
Set up time
Hold time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
C → Q
F616HB
SB → Q
Set up time
Set up time
Hold time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
C → QB
x2
x4
Logic Diagram for "Normal"
Truth Table for "Normal"
SB
H03
D
H01
D
N01
Q
C H02
H
H04
N02
QB
SB
H
Q
QB
0
C
1
0
0
1
1
1
0
1
X
1
0
X
X
1
1
X
X
0
X
0
Hold
Hold
1
0
X:Irrelevant
Logic Diagram for "Q output"
Truth Table for "Q output"
SB
H03
D
H01
D
N01
Q
C H02
H
C
SB
H
Q
0
1
0
0
1
1
0
1
X
1
0
Hold
X
X
1
1
Hold
X
X
0
X
1
SB → QB
Set up time
Set up time
Hold time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
H04
X:Irrelevant
Logic Diagram for "QB output"
D
H01
C H02
H
H04
(HH)
(HL)
(HH)
(HL)
(LH)
(LL)
D
H
D
H
SB
SB
C
SB
(HH)
(HL)
(LH)
D
H
D
H
SB
SB
C
SB
(HH)
(HL)
(LL)
D
H
D
H
SB
SB
C
SB
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.365
0.431
0.624
0.530
0.334
0.223
0.720
0.740
0.240
0.230
0.440
0.370
0.796
0.629
0.366
0.430
0.336
0.720
0.730
0.240
0.230
0.440
0.370
0.604
0.551
0.378
0.350
0.301
0.730
0.750
0.250
0.230
0.450
0.350
0.552
0.537
0.559
0.698
1.042
0.834
0.675
0.436
1.004
1.309
2.055
1.507
1.273
0.747
1.740
1.860
0.000
0.000
0.560
0.380
2.435
1.614
1.007
1.307
1.090
1.740
1.860
0.000
0.000
0.560
0.380
1.689
1.420
1.143
0.977
0.970
1.750
1.880
0.000
0.000
0.570
0.340
1.522
1.310
0.011
0.010
0.011
0.010
0.011
0.010
0.015
0.013
0.015
0.013
0.015
0.013
0.021
0.017
0.022
0.018
0.021
0.019
0.011
0.010
0.011
0.015
0.013
0.015
0.021
0.017
0.021
0.011
0.011
0.011
0.016
0.014
0.014
0.023
0.020
0.019
0.561
0.697
0.583
0.607
0.553
0.523
Symbol
D
C
SB
H
Output
Fanin Symbol Fanout
1.0
1.0
2.2
1.0
Q
QB
35
33
D
C
SB
H
1.0
1.0
2.2
1.0
Q
35
D
C
SB
H
1.0
1.0
2.2
1.0
QB
32
Truth Table for "QB output"
SB
H03
D
C → Q
cells
Low Power
x1
IN
Path
→ OUT
N01
QB
C
SB
H
QB
1
0
1
0
1
1
0
0
X
1
0
Hold
X
X
1
1
Hold
X
X
0
X
0
X:Irrelevant
Block Library
A13872EJ5V0BL
2 - 312
Block Library
A13872EJ5V0BL
2 - 313
Chapter 2 Function Block
Function
D-F/F with RB, SB, Hold
Standard type
Block type
Normal
Drivability
Chapter 2 Function Block
Block
type
Low Gate type
Q output
QB output
Name
cells
Name
cells
Name
cells
F647H
12
F647HQ
11
F647HB
11
Normal
Name
Q output
cells
Name
cells
QB output
Name
F647H
C → Q
cells
C → QB
Low Power
x1
IN
Path
→ OUT
F647HQ
RB → Q
RB → QB
SB → Q
SB → QB
Set up time
Set up time
Hold time
Hold time
Release time
Release time
Removal time
Removal time
Min Pulse
Min Pulse
Min Pulse
C → Q
F647HB
RB → Q
SB → Q
Set up time
Set up time
Hold time
Hold time
Release time
Release time
Removal time
Removal time
Min Pulse
Min Pulse
Min Pulse
C → QB
x2
x4
Logic Diagram for "Normal"
Truth Table for "Normal"
SB
H04
D H01
D
N01 Q
C H02
H H05
N02 QB
H03
RB
H
Q
QB
1
0
0
1
1
1
1
0
1
X
1
1
0
0
Hold
X
X
1
1
1
X
X
0
1
X
0
1
X
X
1
0
X
1
0
X
X
0
0
X
0
0
D
N01 Q
C H02
H H05
H03
RB
Hold
← Prohibition
RB
SB
H
Q
0
C
1
1
0
0
1
1
1
0
1
X
1
1
0
Hold
X
X
1
1
1
Hold
X
X
0
1
X
0
X
X
1
0
X
1
X
X
0
0
X
0
← Prohibition
RB → QB
SB → QB
Set up time
Set up time
Hold time
Hold time
Release time
Release time
Removal time
Removal time
Min Pulse
Min Pulse
Min Pulse
X:Irrelevant
Logic Diagram for "QB output"
Truth Table for "QB output"
SB
H04
D
D H01
C H02
N01 QB
H03
RB
SB
1
Truth Table for "Q output"
SB
H04
H H05
C
X:Irrelevant
Logic Diagram for "Q output"
D H01
RB
0
C
RB
SB
H
QB
1
0
1
1
0
1
1
1
0
0
X
1
1
0
Hold
X
X
1
1
1
Hold
X
X
0
1
X
1
X
X
1
0
X
0
X
X
0
0
X
0
(HH)
(HL)
(HH)
(HL)
(LL)
(LH)
(LH)
(LL)
D
H
D
H
RB
SB
RB
SB
C
RB
SB
(HH)
(HL)
(LL)
(LH)
D
H
D
H
RB
SB
RB
SB
C
RB
SB
(HH)
(HL)
(LH)
(LL)
D
H
D
H
RB
SB
RB
SB
C
RB
SB
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.416
0.435
0.627
0.584
0.179
0.376
0.387
0.223
0.710
0.730
0.250
0.240
0.170
0.420
0.700
0.390
0.801
0.660
0.717
0.414
0.433
0.178
0.386
0.710
0.730
0.250
0.240
0.170
0.420
0.700
0.390
0.607
0.353
0.627
0.383
0.350
0.416
0.302
0.730
0.740
0.250
0.240
0.140
0.430
0.660
0.380
0.558
0.713
0.536
0.657
0.702
1.044
0.940
0.275
0.749
0.793
0.440
1.240
1.315
2.059
1.769
0.466
1.465
1.545
0.748
1.720
1.850
0.000
0.000
0.000
0.530
1.100
0.440
2.440
1.775
1.902
1.239
1.311
0.466
1.331
1.720
1.850
0.000
0.000
0.000
0.530
1.100
0.440
1.693
0.756
1.672
1.152
0.964
1.812
0.954
1.760
1.890
0.000
0.000
0.000
0.560
1.020
0.400
1.533
2.113
1.293
0.011
0.010
0.011
0.010
0.010
0.011
0.011
0.010
0.015
0.013
0.015
0.013
0.013
0.016
0.015
0.013
0.022
0.017
0.022
0.018
0.017
0.023
0.022
0.019
0.011
0.010
0.010
0.011
0.015
0.013
0.013
0.015
0.022
0.017
0.017
0.022
0.011
0.011
0.011
0.011
0.016
0.014
0.016
0.014
0.023
0.020
0.023
0.020
0.655
0.700
0.275
0.683
0.613
0.550
0.892
0.516
Symbol
D
C
RB
SB
H
Output
Fanin Symbol Fanout
1.0
1.0
2.4
2.1
1.0
Q
QB
34
31
D
C
RB
SB
H
1.0
1.0
2.3
2.2
1.0
Q
34
D
C
RB
SB
H
1.0
1.0
2.3
2.2
1.0
QB
31
← Prohibition
X:Irrelevant
Block Library
A13872EJ5V0BL
2 - 314
Block Library
A13872EJ5V0BL
2 - 315
Chapter 2 Function Block
Function
D-F/F (CB) with 2 to 1 Selector(2 CTRL), RB
Standard type
Block type
Normal
Drivability
Chapter 2 Function Block
Q output
Name
cells
F673
11
Name
Low Gate type
QB output
cells
Block
type
Name
Normal
cells
Name
Q output
cells
Name
cells
QB output
Name
CB → QB
RB → Q
RB → QB
Set up time
Set up time
Set up time
Set up time
Hold time
Hold time
Hold time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
x2
x4
Logic Diagram for "Normal"
D0
D1
S0
S1
CB
CB → Q
cells
Low Power
x1
F673
IN
Path
→ OUT
H01
H02
H05
H06
H03
Truth Table for "Normal"
N01
N02
H04
RB
Q
QB
D0
D1
S0
S1
RB
Q
QB
0
X
1
0
CB
1
0
1
1
X
1
0
1
1
0
X
0
0
1
1
0
1
X
1
0
1
1
1
0
X
X
0
0
1
0
1
X
X
1
1
1
X
X
X
X
X
X
X
X
X
X
1
X
0
(LH)
(LL)
(LH)
(LL)
(LL)
(LH)
D0
D1
S0
S1
D0
D1
S0
S1
RB
RB
CB
RB
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.464
0.383
0.453
0.571
0.207
0.280
0.670
0.760
0.690
0.690
0.280
0.270
0.350
0.270
0.180
0.660
0.776
0.484
0.780
0.625
0.749
0.957
0.323
0.447
1.542
1.166
1.423
1.885
0.549
0.806
1.340
1.690
1.260
1.590
0.120
0.000
0.220
0.000
0.000
1.120
2.210
1.134
0.011
0.010
0.011
0.010
0.010
0.011
0.016
0.013
0.015
0.012
0.013
0.015
0.022
0.018
0.021
0.017
0.018
0.021
Symbol
D0
D1
CB
RB
S0
S1
Output
Fanin Symbol Fanout
1.0
1.0
1.0
2.2
1.0
1.0
Q
QB
Hold
0
1
X:Irrelevant
Logic Diagram for "Q output"
Truth Table for "Q output"
Logic Diagram for "QB output"
Truth Table for "QB output"
Block Library
A13872EJ5V0BL
2 - 316
Block Library
A13872EJ5V0BL
2 - 317
33
35
Chapter 2 Function Block
Function
D-F/F (CB) with Hold, 2 to 1 Selector(2 CTRL), RB
Standard type
Block type
Normal
Drivability
Chapter 2 Function Block
Low Gate type
Q output
Name
cells
F674
12
Name
QB output
cells
Block
type
Name
Normal
cells
Name
Q output
cells
Name
cells
QB output
Name
CB → QB
RB → Q
RB → QB
Set up time
Set up time
Set up time
Set up time
Set up time
Hold time
Hold time
Hold time
Hold time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
x2
x4
Logic Diagram for "Normal"
D0
D1
S0
S1
H
CB
CB → Q
cells
Low Power
x1
F674
IN
Path
→ OUT
H01
H02
H05
H06
H07
H03
Truth Table for "Normal"
N01
Q
D0
D1
S0
S1
RB
H
Q
0
X
1
0
1
0
0
1
X
1
0
1
0
1
0
X
X
1
0
1
1
X
X
X
N02
H04
RB
QB
CB
QB
1
0
0
1
1
0
X
1
0
1
1
0
1
0
X
X
0
1
1
1
X
X
X
X
0
0
1
0
0
X
X
0
0
1
1
X
X
1
1
1
X
X
X
X
X
1
X
X
X
X
X
0
X
X
0
1
1
Hold
X
X
(LH)
(LL)
(LH)
(LL)
(LL)
(LH)
D0
D1
S0
S1
H
D0
D1
S0
S1
H
RB
RB
CB
RB
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.466
0.384
0.496
0.619
0.202
0.316
0.830
0.840
0.870
0.880
0.750
0.260
0.200
0.330
0.280
0.140
0.190
0.650
0.827
0.515
0.785
0.626
0.808
1.032
0.316
0.498
1.548
1.168
1.521
2.010
0.539
0.891
1.780
2.090
1.830
2.140
2.080
0.000
0.000
0.070
0.000
0.000
0.000
1.110
2.335
1.218
0.011
0.010
0.011
0.010
0.010
0.011
0.015
0.013
0.015
0.013
0.013
0.015
0.022
0.018
0.021
0.017
0.018
0.021
Symbol
D0
D1
CB
RB
S0
S1
H
Output
Fanin Symbol Fanout
1.0
1.0
1.0
2.1
1.0
1.0
1.0
Q
QB
Hold
0
1
X:Irrelevant
Logic Diagram for "Q output"
Truth Table for "Q output"
Logic Diagram for "QB output"
Truth Table for "QB output"
Block Library
A13872EJ5V0BL
2 - 318
Block Library
A13872EJ5V0BL
2 - 319
33
35
Chapter 2 Function Block
Chapter 2 Function Block
[MEMO]
[MEMO]
Block Library
A13872EJ5V0BL
2 - 320
Block Library
A13872EJ5V0BL
2 - 321
Chapter 2 Function Block
Chapter 2 Function Block
[MEMO]
2.12 T-F/F, JK-F/F
Block Library
A13872EJ5V0BL
2 - 322
Block Library
A13872EJ5V0BL
2 - 323
Chapter 2 Function Block
Function
T-F/F with R, S
Standard type
Block type
Normal
Drivability
Q output
QB output
Name
cells
Name
cells
F744
9
F744NQ
8
Block
type
Low Gate type
Name
Normal
cells
Name
Low Power
x1
Chapter 2 Function Block
cells
Q output
QB output
Name
cells
L744
7
Name
F744
L744
R → Q
R → QB
S → Q
S → QB
Release time
Release time
Removal time
Removal time
Min Pulse
Min Pulse
Min Pulse
T → Q
F744NQ
R → Q
S → Q
Release time
Release time
Removal time
Removal time
Min Pulse
Min Pulse
Min Pulse
T → Q
Truth Table for "Normal"
T
R
S
0
0
N01 Q
T H01
Q
QB
Invert
0
0
X
1
0
0
1
X
0
1
1
0
Hold
X
1
1
1
1
N02 QB
← Prohibition
X:Irrelevant
H02
R
Logic Diagram for "Q output"
Truth Table for "Q output"
S
H03
T
R
S
Q
0
0
Invert
0
0
Hold
X
1
0
0
X
0
1
1
X
1
1
1
N01 Q
T H01
(HH)
(HL)
(HH)
(HL)
(HL)
(HH)
(HH)
(HL)
T → QB
x4
S
H03
T → Q
cells
x2
Logic Diagram for "Normal"
IN
Path
→ OUT
R → Q
S → Q
Release time
Release time
Removal time
Removal time
Min Pulse
Min Pulse
Min Pulse
← Prohibition
X:Irrelevant
R
S
R
S
T
R
S
(HH)
(HL)
(HL)
(HH)
R
S
R
S
T
R
S
(HH)
(HL)
(HL)
(HH)
R
S
R
S
T
R
S
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.379
0.477
0.608
0.639
0.416
0.213
0.170
0.428
0.380
0.110
0.440
0.740
0.839
0.844
0.751
0.342
0.330
0.140
0.283
0.110
0.380
0.740
0.440
0.530
0.228
0.609
0.379
0.477
0.412
0.170
0.380
0.110
0.440
0.740
0.641
0.744
0.278
0.582
0.780
1.020
1.036
0.830
0.442
0.251
1.026
1.050
1.457
1.977
1.903
1.574
0.782
0.426
1.892
1.170
0.000
0.330
1.200
2.348
2.135
2.254
1.037
0.861
0.233
1.024
0.000
1.150
1.200
0.330
1.409
0.594
1.557
1.052
1.459
1.438
0.426
1.170
0.000
0.330
1.200
1.831
1.968
0.804
0.011
0.010
0.011
0.011
0.010
0.011
0.011
0.011
0.015
0.013
0.015
0.014
0.013
0.015
0.015
0.016
0.021
0.019
0.021
0.020
0.018
0.022
0.022
0.023
0.038
0.021
0.014
0.038
0.053
0.027
0.024
0.054
0.078
0.038
0.033
0.079
0.011
0.010
0.010
0.011
0.015
0.013
0.013
0.015
0.021
0.019
0.018
0.022
0.556
0.493
0.156
0.540
0.584
0.780
0.757
0.251
Symbol
T
R
S
Output
Fanin Symbol Fanout
1.0
2.1
2.3
Q
QB
35
33
T
R
S
1.0
2.3
2.1
Q
7
T
R
S
1.0
2.1
2.3
Q
35
H02
R
Logic Diagram for "QB output"
Truth Table for "QB output"
Block Library
A13872EJ5V0BL
2 - 324
Block Library
A13872EJ5V0BL
2 - 325
Chapter 2 Function Block
Function
T-F/F with RB
Standard type
Block type
Normal
Drivability
Chapter 2 Function Block
Low Gate type
Q output
QB output
Name
cells
Name
cells
F745
8
F745NQ
7
Block
type
Name
Normal
cells
Name
cells
Q output
Name
cells
QB output
Name
F745
T → Q
cells
T → QB
Low Power
x1
IN
Path
→ OUT
x2
x4
Logic Diagram for "Normal"
Truth Table for "Normal"
N01
T H01
N02
Q
QB
T
X
RB
Q
1
Invert
1
Hold
0
F745NQ
QB
0
RB → Q
RB → QB
Release time
Removal time
Min Pulse
Min Pulse
T → Q
RB → Q
Release time
Removal time
Min Pulse
Min Pulse
1
(HH)
(HL)
(HH)
(HL)
(LL)
(LH)
RB
RB
T
RB
(HH)
(HL)
(LL)
RB
RB
T
RB
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.406
0.404
0.532
0.572
0.183
0.316
0.190
0.660
0.761
0.605
0.405
0.403
0.182
0.190
0.660
0.594
0.364
0.642
0.654
0.878
0.931
0.284
0.651
1.223
1.215
1.677
1.775
0.479
1.189
0.000
1.010
2.160
1.503
1.223
1.214
0.478
0.000
1.010
1.606
0.773
0.011
0.010
0.011
0.010
0.010
0.011
0.015
0.013
0.015
0.013
0.013
0.015
0.022
0.017
0.021
0.018
0.017
0.022
0.011
0.010
0.010
0.015
0.013
0.013
0.022
0.017
0.017
0.643
0.653
0.284
Symbol
T
RB
T
RB
Output
Fanin Symbol Fanout
1.0
2.2
Q
QB
34
33
1.0
2.2
Q
34
X:Irrelevant
H02
RB
Logic Diagram for "Q output"
Truth Table for "Q output"
N01
Q
T
X
RB
Q
1
Invert
1
Hold
0
0
T H01
X:Irrelevant
H02
RB
Logic Diagram for "QB output"
Truth Table for "QB output"
Block Library
A13872EJ5V0BL
2 - 326
Block Library
A13872EJ5V0BL
2 - 327
Chapter 2 Function Block
Function
T-F/F with RB, SB
Standard type
Block type
Normal
Drivability
Chapter 2 Function Block
Low Gate type
Q output
QB output
Name
cells
Name
cells
F747
9
F747NQ
8
Name
cells
Normal
Name
Q output
cells
Low Power
x1
Block
type
QB output
Name
cells
L747
7
Name
F747
T → QB
L747
RB → Q
RB → QB
SB → Q
SB → QB
Release time
Release time
Removal time
Removal time
Min Pulse
Min Pulse
Min Pulse
T → Q
F747NQ
RB → Q
SB → Q
Release time
Release time
Removal time
Removal time
Min Pulse
Min Pulse
Min Pulse
T → Q
x4
Truth Table for "Normal"
SB
H03
T
N01 Q
T H01
RB
SB
1
1
Q
QB
Invert
1
1
X
0
1
0
1
X
1
0
1
0
X
0
0
0
0
Hold
← Prohibition
N02 QB
X:Irrelevant
H02
RB
Logic Diagram for "Q output"
Truth Table for "Q output"
SB
H03
T
RB
SB
Q
1
1
Invert
1
1
Hold
X
0
1
0
X
1
0
1
X
0
0
0
N01 Q
T → Q
cells
x2
Logic Diagram for "Normal"
IN
Path
→ OUT
RB → Q
SB → Q
Release time
Release time
Removal time
Removal time
Min Pulse
Min Pulse
Min Pulse
← Prohibition
T H01
X:Irrelevant
(HH)
(HL)
(HH)
(HL)
(LL)
(LH)
(LH)
(LL)
RB
SB
RB
SB
T
RB
SB
(HH)
(HL)
(LL)
(LH)
RB
SB
RB
SB
T
RB
SB
(HH)
(HL)
(LL)
(LH)
RB
SB
RB
SB
T
RB
SB
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.412
0.424
0.614
0.574
0.176
0.369
0.374
0.217
0.170
0.410
0.690
0.400
0.780
0.720
0.770
0.339
0.334
0.298
0.117
0.410
0.170
0.400
0.690
0.517
0.611
0.234
0.412
0.424
0.176
0.375
0.170
0.410
0.690
0.400
0.595
0.351
0.688
0.651
0.689
1.040
0.934
0.273
0.863
0.876
0.516
1.232
1.298
2.089
1.769
0.463
1.723
1.712
0.897
0.000
0.480
1.080
0.460
2.466
2.033
2.079
1.023
0.944
1.207
0.200
0.470
0.000
0.460
1.080
1.400
1.565
0.450
1.237
1.298
0.463
1.504
0.000
0.480
1.080
0.460
1.675
0.752
1.866
0.011
0.010
0.011
0.010
0.010
0.011
0.011
0.010
0.015
0.013
0.015
0.013
0.013
0.016
0.015
0.014
0.022
0.017
0.022
0.018
0.017
0.023
0.022
0.020
0.022
0.030
0.030
0.014
0.030
0.041
0.042
0.029
0.044
0.063
0.065
0.042
0.011
0.010
0.010
0.011
0.015
0.013
0.013
0.015
0.022
0.017
0.017
0.022
0.546
0.515
0.630
0.126
0.653
0.689
0.273
0.769
Symbol
T
RB
SB
Output
Fanin Symbol Fanout
1.0
2.3
2.1
Q
QB
34
30
T
RB
SB
1.0
2.1
2.3
Q
11
T
RB
SB
1.0
2.3
2.1
Q
34
H02
RB
Logic Diagram for "QB output"
Truth Table for "QB output"
Block Library
A13872EJ5V0BL
2 - 328
Block Library
A13872EJ5V0BL
2 - 329
Chapter 2 Function Block
Function
T-F/F with Data-Hold R, S
Standard type
Block type
Normal
Drivability
Chapter 2 Function Block
Low Gate type
Q output
Name
cells
F791
12
Name
Block
type
QB output
cells
Name
cells
Normal
Name
Q output
cells
Name
cells
QB output
Name
T → Q
cells
T → QB
Low Power
x1
F791
IN
Path
→ OUT
R → Q
R → QB
S → Q
S → QB
Set up time
Hold time
Release time
Release time
Removal time
Removal time
Min Pulse
Min Pulse
Min Pulse
x2
x4
Logic Diagram for "Normal"
Truth Table for "Normal"
S
H04
T H01
T
N01 Q
TE H02
N02 QB
H03
R
TE
R
S
1
0
0
Q
Invert
QB
Hold
1
0
0
X
0
0
0
X
X
1
0
0
1
X
X
0
1
1
0
X
X
1
1
1
1
Hold
(HH)
(HL)
(HH)
(HL)
(HL)
(HH)
(HH)
(HL)
TE
TE
R
S
R
S
T
R
S
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.429
0.563
0.665
0.651
0.503
0.189
0.219
0.439
0.770
0.310
0.390
0.110
0.430
0.750
0.853
0.777
0.739
0.656
0.915
1.109
1.036
0.860
0.340
0.314
0.856
1.180
1.691
2.116
1.899
1.607
0.590
0.532
1.569
2.310
0.000
1.240
0.000
0.320
1.210
2.485
2.086
2.022
0.011
0.011
0.011
0.010
0.011
0.011
0.011
0.010
0.015
0.014
0.015
0.014
0.014
0.015
0.015
0.014
0.022
0.020
0.021
0.019
0.020
0.022
0.022
0.021
Symbol
T
TE
R
S
Output
Fanin Symbol Fanout
1.0
1.7
2.1
2.2
Q
QB
← Prohibition
X:Irrelevant
Logic Diagram for "Q output"
Truth Table for "Q output"
Logic Diagram for "QB output"
Truth Table for "QB output"
Block Library
A13872EJ5V0BL
2 - 330
Block Library
A13872EJ5V0BL
2 - 331
34
34
Chapter 2 Function Block
Function
T-F/F (TB) with RB
Standard type
Block type
Normal
Drivability
Chapter 2 Function Block
Low Gate type
Q output
QB output
Name
cells
Name
cells
F765
8
F765NQ
7
Block
type
Name
Normal
cells
Name
cells
Q output
Name
cells
QB output
Name
F765
TB → Q
cells
TB → QB
Low Power
x1
IN
Path
→ OUT
x2
x4
Logic Diagram for "Normal"
Truth Table for "Normal"
N01
TB H01
N02
Q
QB
T
X
RB
Q
1
Invert
1
Hold
0
F765NQ
QB
0
RB → Q
RB → QB
Release time
Removal time
Min Pulse
Min Pulse
TB → Q
RB → Q
Release time
Removal time
Min Pulse
Min Pulse
1
(LH)
(LL)
(LH)
(LL)
(LL)
(LH)
RB
RB
TB
RB
(LH)
(LL)
(LL)
RB
RB
TB
RB
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.428
0.357
0.486
0.596
0.183
0.317
0.180
0.650
0.794
0.605
0.428
0.356
0.183
0.180
0.650
0.627
0.364
0.724
0.582
0.807
1.014
0.285
0.651
1.433
1.089
1.559
1.989
0.479
1.188
0.000
1.110
2.308
1.502
1.432
1.091
0.478
0.000
1.110
1.752
0.773
0.011
0.010
0.011
0.010
0.010
0.011
0.015
0.013
0.015
0.013
0.013
0.015
0.022
0.017
0.021
0.018
0.017
0.022
0.011
0.010
0.010
0.015
0.013
0.013
0.022
0.017
0.017
0.723
0.582
0.284
Symbol
TB
RB
TB
RB
Output
Fanin Symbol Fanout
1.0
2.2
Q
QB
34
33
1.0
2.2
Q
34
X:Irrelevant
H02
RB
Logic Diagram for "Q output"
Truth Table for "Q output"
N01
Q
T
X
TB H01
RB
Q
1
Invert
1
Hold
0
0
X:Irrelevant
H02
RB
Logic Diagram for "QB output"
Truth Table for "QB output"
Block Library
A13872EJ5V0BL
2 - 332
Block Library
A13872EJ5V0BL
2 - 333
Chapter 2 Function Block
Function
T-F/F (TB) with RB, SB
Standard type
Block type
Normal
Drivability
Chapter 2 Function Block
Low Gate type
Q output
QB output
Name
cells
Name
cells
F767
9
F767NQ
8
Name
cells
Normal
Name
Q output
cells
Low Power
x1
Block
type
QB output
Name
cells
L767
7
Name
F767
TB → QB
L767
RB → Q
RB → QB
SB → Q
SB → QB
Release time
Release time
Removal time
Removal time
Min Pulse
Min Pulse
Min Pulse
TB → Q
F767NQ
RB → Q
SB → Q
Release time
Release time
Removal time
Removal time
Min Pulse
Min Pulse
Min Pulse
TB → Q
x4
Truth Table for "Normal"
SB
H03
TB
N01 Q
TB H01
N02 QB
RB
SB
1
1
Q
QB
Invert
1
1
X
0
1
0
1
X
1
0
1
0
X
0
0
0
0
Hold
← Prohibition
X:Irrelevant
H02
RB
Logic Diagram for "Q output"
Truth Table for "Q output"
SB
H03
TB
RB
SB
Q
1
1
Invert
1
1
Hold
X
0
1
0
X
1
0
1
X
0
0
0
N01 Q
TB H01
TB → Q
cells
x2
Logic Diagram for "Normal"
IN
Path
→ OUT
RB → Q
SB → Q
Release time
Release time
Removal time
Removal time
Min Pulse
Min Pulse
Min Pulse
← Prohibition
X:Irrelevant
(LH)
(LL)
(LH)
(LL)
(LL)
(LH)
(LH)
(LL)
RB
SB
RB
SB
TB
RB
SB
(LH)
(LL)
(LL)
(LH)
RB
SB
RB
SB
TB
RB
SB
(LH)
(LL)
(LL)
(LH)
RB
SB
RB
SB
TB
RB
SB
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.426
0.376
0.567
0.587
0.176
0.369
0.374
0.217
0.180
0.390
0.670
0.430
0.787
0.720
0.770
0.291
0.348
0.298
0.117
0.390
0.170
0.430
0.660
0.547
0.611
0.234
0.426
0.376
0.176
0.375
0.180
0.390
0.660
0.430
0.626
0.351
0.688
0.723
0.614
0.967
1.005
0.273
0.863
0.876
0.517
1.425
1.162
1.962
1.965
0.462
1.723
1.712
0.897
0.000
0.650
1.180
0.500
2.296
2.033
2.079
0.893
1.130
1.207
0.200
0.640
0.000
0.500
1.180
1.453
1.566
0.450
1.425
1.165
0.463
1.505
0.000
0.650
1.180
0.500
1.747
0.752
1.866
0.011
0.010
0.011
0.010
0.010
0.011
0.011
0.010
0.015
0.013
0.015
0.013
0.013
0.016
0.015
0.014
0.022
0.017
0.022
0.018
0.017
0.023
0.022
0.020
0.022
0.030
0.030
0.014
0.030
0.041
0.042
0.029
0.044
0.063
0.065
0.042
0.011
0.010
0.010
0.011
0.015
0.013
0.013
0.015
0.022
0.017
0.017
0.022
0.473
0.585
0.630
0.126
0.723
0.615
0.273
0.769
Symbol
TB
RB
SB
Output
Fanin Symbol Fanout
1.0
2.3
2.1
Q
QB
34
30
TB
RB
SB
1.0
2.1
2.3
Q
11
TB
RB
SB
1.0
2.3
2.1
Q
34
H02
RB
Logic Diagram for "QB output"
Truth Table for "QB output"
Block Library
A13872EJ5V0BL
2 - 334
Block Library
A13872EJ5V0BL
2 - 335
Chapter 2 Function Block
Function
T-F/F (TB) with Data-Hold RB, SB
Standard type
Block type
Normal
Drivability
Chapter 2 Function Block
Low Gate type
Q output
Name
cells
F792
12
Name
Block
type
QB output
cells
Name
Normal
cells
Name
Q output
cells
Name
cells
QB output
Name
TB → Q
cells
TB → QB
Low Power
x1
F792
IN
Path
→ OUT
RB → Q
RB → QB
SB → Q
SB → QB
Set up time
Hold time
Release time
Release time
Removal time
Removal time
Min Pulse
Min Pulse
Min Pulse
x2
x4
Logic Diagram for "Normal"
Truth Table for "Normal"
SB
H04
TB H01
TB
N01 Q
TEB H02
N02 QB
H03
RB
TEB
RB
SB
0
1
1
Q
Invert
QB
Hold
0
1
1
X
1
1
1
X
X
0
1
0
1
X
X
1
0
1
0
X
X
0
0
0
0
Hold
(LH)
(LL)
(LH)
(LL)
(LL)
(LH)
(LH)
(LL)
TEB
TEB
RB
SB
RB
SB
TB
RB
SB
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.492
0.432
0.599
0.626
0.230
0.399
0.449
0.193
0.850
0.350
0.180
0.400
0.670
0.430
0.824
0.716
0.739
0.826
0.702
1.006
1.057
0.356
0.788
0.845
0.391
1.629
1.309
1.984
2.075
0.603
1.524
1.639
0.664
1.850
0.190
0.000
0.710
1.190
0.490
2.395
1.870
1.985
0.011
0.010
0.011
0.010
0.010
0.011
0.011
0.010
0.015
0.013
0.015
0.013
0.013
0.015
0.015
0.013
0.022
0.018
0.021
0.017
0.018
0.022
0.022
0.019
Symbol
TB
TEB
RB
SB
Output
Fanin Symbol Fanout
1.0
1.7
2.3
2.1
Q
QB
← Prohibition
X:Irrelevant
Logic Diagram for "Q output"
Truth Table for "Q output"
Logic Diagram for "QB output"
Truth Table for "QB output"
Block Library
A13872EJ5V0BL
2 - 336
Block Library
A13872EJ5V0BL
2 - 337
33
32
Chapter 2 Function Block
Function
JK-F/F
Standard type
Block type
Normal
Drivability
Chapter 2 Function Block
Q output
Block
type
Low Gate type
QB output
Normal
Name
cells
Name
cells
Name
cells
F771
10
F771NQ
9
F771NB
9
Name
cells
Q output
Name
cells
QB output
Name
F771
C → Q
(HH)
(HL)
(HH)
(HL)
cells
C → QB
Low Power
x1
IN
Path
→ OUT
J
K
J
K
C
F771NQ
Set up time
Set up time
Hold time
Hold time
Min Pulse
C → Q
J
K
J
K
C
F771NB
Set up time
Set up time
Hold time
Hold time
Min Pulse
C → QB
Set up time
Set up time
Hold time
Hold time
Min Pulse
J
K
J
K
C
x2
x4
Logic Diagram for "Normal"
J H01
Truth Table for "Normal"
N01
Q
C H03
K H02
N02
QB
J
K
C
Q
QB
0
0
0
1
0
1
0
1
1
1
Invert
X
X
Hold
Hold
1
0
X:Irrelevant
Logic Diagram for "Q output"
J H01
(HH)
(HL)
(HH)
(HL)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.357
0.398
0.534
0.534
0.680
0.660
0.200
0.250
0.719
0.326
0.332
0.690
0.660
0.180
0.200
0.518
0.326
0.332
0.660
0.660
0.200
0.250
0.518
0.550
0.647
0.876
0.845
0.991
1.202
1.663
1.535
1.360
1.480
0.000
0.000
2.032
0.980
0.944
1.470
1.300
0.000
0.000
1.352
0.980
0.944
1.300
1.470
0.000
0.000
1.352
0.011
0.010
0.011
0.010
0.015
0.013
0.015
0.013
0.021
0.017
0.021
0.018
0.011
0.011
0.015
0.014
0.022
0.020
0.011
0.011
0.015
0.014
0.022
0.020
0.525
0.530
0.525
0.530
Symbol
J
K
C
Output
Fanin Symbol Fanout
1.0
1.0
1.0
Q
QB
35
34
J
K
C
1.0
1.0
1.0
Q
33
J
K
C
1.0
1.0
1.0
QB
33
Truth Table for "Q output"
N01
Q
C H03
K H02
J
K
0
0
C
Hold
Q
0
1
0
1
0
1
1
1
Invert
X
X
Hold
X:Irrelevant
Logic Diagram for "QB output"
Truth Table for "QB output"
J
J H01
C H03
K H02
N01
QB
K
C
QB
0
0
Hold
0
1
1
1
0
0
1
1
Invert
X
X
Hold
X:Irrelevant
Block Library
A13872EJ5V0BL
2 - 338
Block Library
A13872EJ5V0BL
2 - 339
Chapter 2 Function Block
Function
JK-F/F, High Speed
Standard type
Block type
Normal
Drivability
Chapter 2 Function Block
Q output
Name
cells
F7D1
10
Name
Low Gate type
QB output
cells
Block
type
Name
Normal
cells
Name
cells
Q output
Name
cells
QB output
Name
C → Q
(HH)
(HL)
(HH)
(HL)
cells
C → QB
Low Power
x1
F7D1
IN
Path
→ OUT
Set up time
Set up time
Hold time
Hold time
Min Pulse
x2
x4
Logic Diagram for "Normal"
J H01
Truth Table for "Normal"
N01
Q
C H03
K H02
N02
QB
J
K
0
0
C
Q
0
1
0
1
0
1
1
1
Invert
X
X
Hold
J
K
J
K
C
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.333
0.340
0.433
0.458
0.690
0.660
0.180
0.200
0.621
0.534
0.541
0.711
0.743
0.993
0.963
1.321
1.396
1.470
1.290
0.000
0.000
1.766
0.011
0.011
0.011
0.010
0.015
0.014
0.015
0.013
0.022
0.020
0.021
0.017
Symbol
J
K
C
Output
Fanin Symbol Fanout
1.0
1.0
1.0
Q
QB
QB
Hold
1
0
X:Irrelevant
Logic Diagram for "Q output"
Truth Table for "Q output"
Logic Diagram for "QB output"
Truth Table for "QB output"
Block Library
A13872EJ5V0BL
2 - 340
Block Library
A13872EJ5V0BL
2 - 341
34
35
Chapter 2 Function Block
Function
JK-F/F with R, S
Standard type
Block type
Normal
Drivability
Chapter 2 Function Block
Q output
Block
type
Low Gate type
QB output
Normal
Name
cells
Name
cells
Name
cells
F774
12
F774NQ
11
F774NB
11
Name
Q output
cells
Name
cells
QB output
Name
F774
C → Q
(HH)
(HL)
(HH)
(HL)
(HL)
(HH)
(HH)
(HL)
cells
C → QB
Low Power
x1
IN
Path
→ OUT
F774NQ
R → Q
R → QB
S → Q
S → QB
Set up time
Set up time
Hold time
Hold time
Release time
Release time
Removal time
Removal time
Min Pulse
Min Pulse
Min Pulse
C → Q
F774NB
R → Q
S → Q
Set up time
Set up time
Hold time
Hold time
Release time
Release time
Removal time
Removal time
Min Pulse
Min Pulse
Min Pulse
C → QB
x2
x4
Logic Diagram for "Normal"
Truth Table for "Normal"
S
H05
J H01
N01 Q
C H03
K H02
N02 QB
H04
R
N01 Q
C H03
K H02
H04
R
C
S
0
0
Q
QB
0
1
0
0
0
1
0
0
0
1
1
1
0
0
X
X
0
0
X
X
X
1
0
0
1
X
X
X
0
1
1
0
X
X
X
1
1
1
1
Hold
1
0
Invert
Hold
J
K
R
S
Q
0
0
C
0
0
Hold
0
1
0
0
0
1
0
0
0
1
1
1
0
0
Invert
X
X
0
0
Hold
X
X
X
1
0
0
X
X
X
0
1
1
X
X
X
1
1
1
← Prohibition
R → QB
S → QB
Set up time
Set up time
Hold time
Hold time
Release time
Release time
Removal time
Removal time
Min Pulse
Min Pulse
Min Pulse
Truth Table for "QB output"
S
H05
J H01
C H03
N01 QB
J
K
R
S
QB
0
0
C
0
0
Hold
0
1
0
0
1
1
0
0
0
0
1
1
0
0
Invert
X
X
0
0
Hold
X
X
X
1
0
1
X
X
X
0
1
0
X
X
X
1
1
1
(HH)
(HL)
(HL)
(HH)
← Prohibition
X:Irrelevant
Logic Diagram for "QB output"
H04
R
R
0
Truth Table for "Q output"
S
H05
K H02
K
X:Irrelevant
Logic Diagram for "Q output"
J H01
J
0
J
K
J
K
R
S
R
S
C
R
S
J
K
J
K
R
S
R
S
C
R
S
(HH)
(HL)
(HH)
(HL)
J
K
J
K
R
S
R
S
C
R
S
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.374
0.475
0.620
0.662
0.417
0.227
0.170
0.457
0.660
0.660
0.160
0.230
0.380
0.110
0.430
0.760
0.861
0.779
0.689
0.374
0.473
0.414
0.170
0.660
0.660
0.160
0.230
0.380
0.110
0.430
0.760
0.637
0.687
0.277
0.328
0.359
0.276
0.534
0.650
0.660
0.160
0.240
0.400
0.100
0.420
0.700
0.554
0.557
0.710
0.575
0.777
1.030
1.059
0.776
0.393
0.251
0.904
1.040
1.451
1.975
1.944
1.463
0.683
0.426
1.664
1.970
1.600
0.000
0.000
1.210
0.000
0.320
1.220
2.344
1.990
2.031
1.041
1.451
1.338
0.426
1.970
1.600
0.000
0.000
1.210
0.000
0.320
1.220
1.821
1.826
0.804
0.981
1.038
0.866
1.851
1.860
1.580
0.000
0.000
1.110
0.000
0.290
1.150
1.428
1.376
2.228
0.011
0.010
0.011
0.011
0.010
0.011
0.011
0.011
0.015
0.013
0.015
0.014
0.013
0.015
0.015
0.015
0.021
0.019
0.021
0.020
0.018
0.022
0.022
0.022
0.011
0.010
0.010
0.011
0.015
0.013
0.013
0.015
0.021
0.019
0.018
0.022
0.011
0.011
0.011
0.012
0.015
0.015
0.015
0.016
0.022
0.022
0.022
0.023
0.576
0.777
0.712
0.251
0.527
0.573
0.466
0.944
Symbol
J
K
C
R
S
Output
Fanin Symbol Fanout
1.0
1.0
1.0
2.1
2.2
Q
QB
34
34
J
K
C
R
S
1.0
1.0
1.0
2.1
2.2
Q
35
J
K
C
R
S
1.0
1.0
1.0
2.1
2.2
QB
33
← Prohibition
X:Irrelevant
Block Library
A13872EJ5V0BL
2 - 342
Block Library
A13872EJ5V0BL
2 - 343
Chapter 2 Function Block
Function
JK-F/F with RB
Standard type
Block type
Normal
Drivability
Chapter 2 Function Block
Block
type
Low Gate type
Q output
QB output
Name
cells
Name
cells
Name
cells
F775
11
F775NQ
10
F775NB
10
Normal
Name
Q output
cells
Name
cells
QB output
Name
F775
C → Q
cells
C → QB
Low Power
x1
IN
Path
→ OUT
F775NQ
RB → Q
RB → QB
Set up time
Set up time
Hold time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
C → Q
F775NB
RB → Q
Set up time
Set up time
Hold time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
C → QB
x2
x4
Logic Diagram for "Normal"
J H01
Truth Table for "Normal"
N01
Q
C H03
K H02
N02
QB
H04
RB
J
K
0
0
C
RB
1
Q
QB
0
1
1
0
1
1
0
1
1
0
Hold
1
1
1
Invert
X
X
1
Hold
X
X
X
0
0
1
X:Irrelevant
Logic Diagram for "Q output"
J H01
Truth Table for "Q output"
N01
Q
C H03
K H02
H04
RB
J
K
0
C
RB
Q
0
1
Hold
0
1
1
0
1
0
1
1
1
1
1
Invert
X
X
1
Hold
X
X
0
0
X
RB → QB
Set up time
Set up time
Hold time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
(HH)
(HL)
(HH)
(HL)
(LL)
(LH)
J
K
J
K
RB
RB
C
RB
(HH)
(HL)
(LL)
J
K
J
K
RB
RB
C
RB
(HH)
(HL)
(LH)
J
K
J
K
RB
RB
C
RB
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.401
0.403
0.544
0.587
0.185
0.334
0.660
0.660
0.180
0.240
0.190
0.670
0.774
0.574
0.401
0.402
0.185
0.660
0.650
0.180
0.240
0.190
0.670
0.589
0.365
0.330
0.334
0.348
0.650
0.660
0.180
0.240
0.180
0.620
0.525
0.602
0.636
0.652
0.888
0.945
0.285
0.598
1.214
1.209
1.678
1.798
0.479
1.083
1.390
1.540
0.000
0.000
0.000
1.010
2.181
1.397
1.216
1.209
0.480
1.390
1.540
0.000
0.000
0.000
1.010
1.598
0.775
0.987
0.928
1.374
1.360
1.530
0.000
0.000
0.000
0.960
1.362
1.674
0.011
0.010
0.011
0.010
0.010
0.011
0.015
0.013
0.015
0.013
0.013
0.015
0.022
0.017
0.021
0.018
0.017
0.022
0.011
0.010
0.010
0.015
0.013
0.013
0.022
0.017
0.017
0.011
0.011
0.011
0.015
0.014
0.015
0.022
0.020
0.022
0.637
0.652
0.285
0.529
0.526
0.711
Symbol
J
K
C
RB
Output
Fanin Symbol Fanout
1.0
1.0
1.0
2.2
Q
QB
34
34
J
K
C
RB
1.0
1.0
1.0
2.2
Q
34
J
K
C
RB
1.0
1.0
1.0
2.2
QB
33
X:Irrelevant
Logic Diagram for "QB output"
Truth Table for "QB output"
J
J H01
C H03
K H02
N01
H04
RB
QB
K
C
RB
QB
0
0
1
Hold
0
1
1
1
1
0
1
0
1
1
1
Invert
X
X
1
Hold
X
X
0
1
X
X:Irrelevant
Block Library
A13872EJ5V0BL
2 - 344
Block Library
A13872EJ5V0BL
2 - 345
Chapter 2 Function Block
Function
JK-F/F with SB
Standard type
Block type
Normal
Drivability
Chapter 2 Function Block
Block
type
Low Gate type
Q output
QB output
Name
cells
Name
cells
Name
cells
F776
11
F776NQ
10
F776NB
10
Normal
Name
Q output
cells
Name
cells
QB output
Name
F776
C → Q
cells
C → QB
Low Power
x1
IN
Path
→ OUT
F776NQ
SB → Q
SB → QB
Set up time
Set up time
Hold time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
C → Q
F776NB
SB → Q
Set up time
Set up time
Hold time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
C → QB
x2
x4
Logic Diagram for "Normal"
Truth Table for "Normal"
SB
H04
J H01
N01
Q
C H03
K H02
N02
QB
J
K
0
0
C
SB
1
Q
QB
0
1
1
0
1
1
0
1
1
0
Hold
1
1
1
Invert
X
X
1
Hold
X
X
X
0
1
0
X:Irrelevant
Logic Diagram for "Q output"
Truth Table for "Q output"
SB
H04
J H01
N01
Q
C H03
K H02
J
K
0
C
SB
Q
0
1
Hold
0
1
1
0
1
0
1
1
1
1
1
Invert
X
X
1
Hold
X
X
0
1
X
SB → QB
Set up time
Set up time
Hold time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
(HH)
(HL)
(HH)
(HL)
(LH)
(LL)
J
K
J
K
SB
SB
C
SB
(HH)
(HL)
(LH)
J
K
J
K
SB
SB
C
SB
(HH)
(HL)
(LL)
J
K
J
K
SB
SB
C
SB
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.375
0.439
0.634
0.539
0.341
0.233
0.730
0.720
0.200
0.260
0.430
0.370
0.798
0.655
0.375
0.438
0.344
0.730
0.720
0.200
0.260
0.430
0.370
0.603
0.584
0.385
0.357
0.316
0.700
0.730
0.200
0.260
0.450
0.360
0.551
0.565
0.579
0.715
1.060
0.850
0.711
0.457
1.044
1.351
2.100
1.537
1.342
0.785
1.340
1.580
0.000
0.000
0.540
0.390
2.474
1.686
1.045
1.349
1.166
1.350
1.580
0.000
0.000
0.540
0.390
1.723
1.503
1.181
1.026
1.078
1.310
1.600
0.000
0.000
0.560
0.350
1.556
1.424
0.011
0.010
0.011
0.010
0.011
0.010
0.015
0.013
0.015
0.013
0.015
0.013
0.021
0.017
0.022
0.018
0.021
0.019
0.011
0.010
0.011
0.015
0.013
0.015
0.021
0.017
0.021
0.011
0.011
0.010
0.015
0.014
0.013
0.023
0.019
0.019
0.580
0.714
0.623
0.623
0.572
0.574
Symbol
J
K
C
SB
Output
Fanin Symbol Fanout
1.0
1.0
1.0
2.1
Q
QB
34
33
J
K
C
SB
1.0
1.0
1.0
2.1
Q
34
J
K
C
SB
1.0
1.0
1.0
2.1
QB
31
X:Irrelevant
Logic Diagram for "QB output"
Truth Table for "QB output"
SB
H04
J
J H01
C H03
K H02
N01
QB
K
C
SB
QB
0
0
1
Hold
0
1
1
1
1
0
1
0
1
1
1
Invert
X
X
1
Hold
X
X
0
0
X
X:Irrelevant
Block Library
A13872EJ5V0BL
2 - 346
Block Library
A13872EJ5V0BL
2 - 347
Chapter 2 Function Block
Function
JK-F/F with RB, SB
Standard type
Block type
Normal
Drivability
Chapter 2 Function Block
Q output
Block
type
Low Gate type
QB output
Name
cells
Name
cells
Name
cells
F777
12
F777NQ
11
F777NB
11
Normal
Name
Q output
cells
Name
cells
QB output
Name
F777
C → Q
cells
C → QB
Low Power
x1
IN
Path
→ OUT
F777NQ
RB → Q
RB → QB
SB → Q
SB → QB
Set up time
Set up time
Hold time
Hold time
Release time
Release time
Removal time
Removal time
Min Pulse
Min Pulse
Min Pulse
C → Q
F777NB
RB → Q
SB → Q
Set up time
Set up time
Hold time
Hold time
Release time
Release time
Removal time
Removal time
Min Pulse
Min Pulse
Min Pulse
C → QB
x2
x4
Logic Diagram for "Normal"
Truth Table for "Normal"
SB
H05
J H01
N01 Q
C H03
K H02
N02 QB
H04
RB
N01 Q
C H03
K H02
H04
RB
C
SB
1
1
Q
QB
0
1
1
1
0
1
0
1
1
1
1
1
1
1
X
X
1
1
X
X
X
0
1
0
1
X
X
X
1
0
1
0
X
X
X
0
0
0
0
Hold
1
0
Invert
Hold
← Prohibition
J
K
RB
SB
Q
0
0
C
1
1
Hold
0
1
1
1
0
1
0
1
1
1
1
1
1
1
Invert
X
X
1
1
Hold
X
X
X
0
1
0
X
X
X
1
0
1
X
X
X
0
0
0
← Prohibition
RB → QB
SB → QB
Set up time
Set up time
Hold time
Hold time
Release time
Release time
Removal time
Removal time
Min Pulse
Min Pulse
Min Pulse
X:Irrelevant
Logic Diagram for "QB output"
Truth Table for "QB output"
SB
H05
J H01
C H03
N01 QB
H04
RB
RB
0
Truth Table for "Q output"
SB
H05
K H02
K
X:Irrelevant
Logic Diagram for "Q output"
J H01
J
0
J
K
RB
SB
QB
0
0
C
1
1
Hold
0
1
1
1
1
1
0
1
1
0
1
1
1
1
Invert
X
X
1
1
Hold
X
X
X
0
1
1
X
X
X
1
0
0
X
X
X
0
0
0
(HH)
(HL)
(HH)
(HL)
(LL)
(LH)
(LH)
(LL)
J
K
J
K
RB
SB
RB
SB
C
RB
SB
(HH)
(HL)
(LL)
(LH)
J
K
J
K
RB
SB
RB
SB
C
RB
SB
(HH)
(HL)
(LH)
(LL)
J
K
J
K
RB
SB
RB
SB
C
RB
SB
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.406
0.422
0.631
0.587
0.177
0.391
0.378
0.235
0.720
0.710
0.190
0.250
0.180
0.420
0.690
0.390
0.795
0.672
0.732
0.406
0.421
0.177
0.379
0.710
0.710
0.190
0.250
0.180
0.420
0.690
0.390
0.587
0.351
0.655
0.367
0.336
0.432
0.293
0.690
0.720
0.190
0.260
0.160
0.430
0.640
0.380
0.533
0.695
0.553
0.644
0.686
1.057
0.946
0.273
0.772
0.809
0.458
1.223
1.291
2.095
1.794
0.463
1.521
1.571
0.782
1.380
1.560
0.000
0.000
0.000
0.520
1.080
0.440
2.469
1.830
1.932
1.224
1.289
0.463
1.374
1.380
1.560
0.000
0.000
0.000
0.520
1.080
0.440
1.665
0.752
1.723
1.125
0.943
1.774
0.991
1.330
1.590
0.000
0.000
0.000
0.550
1.010
0.400
1.500
2.075
1.336
0.011
0.010
0.011
0.010
0.010
0.011
0.011
0.010
0.015
0.013
0.015
0.013
0.013
0.016
0.015
0.013
0.022
0.017
0.022
0.018
0.017
0.023
0.022
0.019
0.011
0.010
0.010
0.011
0.015
0.013
0.013
0.015
0.022
0.017
0.017
0.022
0.011
0.011
0.011
0.011
0.016
0.014
0.016
0.014
0.023
0.020
0.023
0.020
0.644
0.685
0.273
0.708
0.593
0.533
0.869
0.536
Symbol
J
K
C
RB
SB
Output
Fanin Symbol Fanout
1.0
1.0
1.0
2.3
2.1
Q
QB
34
31
J
K
C
RB
SB
1.0
1.0
1.0
2.3
2.1
Q
34
J
K
C
RB
SB
1.0
1.0
1.0
2.3
2.1
QB
31
← Prohibition
X:Irrelevant
Block Library
A13872EJ5V0BL
2 - 348
Block Library
A13872EJ5V0BL
2 - 349
Chapter 2 Function Block
Function
JK-F/F (CB)
Standard type
Block type
Normal
Drivability
Chapter 2 Function Block
Block
type
Low Gate type
Q output
QB output
Name
cells
Name
cells
Name
cells
F781
10
F781NQ
9
F781NB
9
Normal
Name
cells
Q output
Name
cells
QB output
Name
F781
CB → Q
cells
CB → QB
Low Power
x1
IN
Path
→ OUT
F781NQ
Set up time
Set up time
Hold time
Hold time
Min Pulse
CB → Q
F781NB
Set up time
Set up time
Hold time
Hold time
Min Pulse
CB → QB
x2
x4
Logic Diagram for "Normal"
J H01
Truth Table for "Normal"
N01
Q
CB H03
K H02
N02
QB
J
K
CB
Q
QB
0
0
0
1
0
1
0
1
1
1
Invert
X
X
Hold
Hold
1
0
Set up time
Set up time
Hold time
Hold time
Min Pulse
X:Irrelevant
Logic Diagram for "Q output"
J H01
(LH)
(LL)
(LH)
(LL)
J
K
J
K
CB
(LH)
(LL)
J
K
J
K
CB
(LH)
(LL)
J
K
J
K
CB
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.372
0.351
0.489
0.549
0.700
0.710
0.200
0.370
0.748
0.290
0.330
0.720
0.690
0.310
0.190
0.538
0.290
0.330
0.690
0.710
0.190
0.370
0.538
0.622
0.574
0.807
0.916
1.190
1.076
1.543
1.737
1.290
1.380
0.000
0.100
2.056
0.897
1.057
1.470
1.280
0.000
0.000
1.384
0.897
1.057
1.280
1.380
0.000
0.110
1.384
0.011
0.010
0.011
0.010
0.015
0.013
0.015
0.013
0.021
0.017
0.021
0.018
0.011
0.011
0.015
0.014
0.022
0.020
0.011
0.011
0.015
0.014
0.022
0.020
0.473
0.553
0.473
0.553
Symbol
J
K
CB
Output
Fanin Symbol Fanout
1.0
1.0
1.0
Q
QB
35
34
J
K
CB
1.0
1.0
1.0
Q
34
J
K
CB
1.0
1.0
1.0
QB
34
Truth Table for "Q output"
N01
Q
CB H03
K H02
J
K
0
0
CB
Hold
Q
0
1
0
1
0
1
1
1
Invert
X
X
Hold
X:Irrelevant
Logic Diagram for "QB output"
Truth Table for "QB output"
J
J H01
CB H03
K H02
N01
QB
K
CB
QB
0
0
Hold
0
1
1
1
0
0
1
1
Invert
X
X
Hold
X:Irrelevant
Block Library
A13872EJ5V0BL
2 - 350
Block Library
A13872EJ5V0BL
2 - 351
Chapter 2 Function Block
Function
JK-F/F (CB), High Speed
Standard type
Block type
Normal
Drivability
Chapter 2 Function Block
Low Gate type
Q output
Name
cells
F7E1
10
Name
Block
type
QB output
cells
Name
cells
Normal
Name
cells
Q output
Name
cells
QB output
Name
CB → Q
cells
CB → QB
Low Power
x1
F7E1
IN
Path
→ OUT
Set up time
Set up time
Hold time
Hold time
Min Pulse
x2
x4
Logic Diagram for "Normal"
J H01
Truth Table for "Normal"
N01
Q
CB H03
K H02
N02
QB
J
K
0
0
CB
Q
0
1
0
1
0
1
1
1
Invert
X
X
Hold
(LH)
(LL)
(LH)
(LL)
J
K
J
K
CB
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.298
0.337
0.431
0.423
0.730
0.690
0.310
0.190
0.642
0.484
0.561
0.732
0.693
0.913
1.067
1.428
1.315
1.470
1.270
0.000
0.000
1.754
0.011
0.011
0.011
0.010
0.015
0.014
0.015
0.013
0.022
0.020
0.021
0.017
Symbol
J
K
CB
Output
Fanin Symbol Fanout
1.0
1.0
1.0
Q
QB
QB
Hold
1
0
X:Irrelevant
Logic Diagram for "Q output"
Truth Table for "Q output"
Logic Diagram for "QB output"
Truth Table for "QB output"
Block Library
A13872EJ5V0BL
2 - 352
Block Library
A13872EJ5V0BL
2 - 353
34
35
Chapter 2 Function Block
Function
JK-F/F (CB) with RB, SB
Standard type
Block type
Normal
Drivability
Chapter 2 Function Block
Q output
Block
type
Low Gate type
QB output
Name
cells
Name
cells
Name
cells
F787
12
F787NQ
11
F787NB
11
Normal
Name
Q output
cells
Name
cells
QB output
Name
F787
CB → Q
cells
CB → QB
Low Power
x1
IN
Path
→ OUT
F787NQ
RB → Q
RB → QB
SB → Q
SB → QB
Set up time
Set up time
Hold time
Hold time
Release time
Release time
Removal time
Removal time
Min Pulse
Min Pulse
Min Pulse
CB → Q
F787NB
RB → Q
SB → Q
Set up time
Set up time
Hold time
Hold time
Release time
Release time
Removal time
Removal time
Min Pulse
Min Pulse
Min Pulse
CB → QB
x2
x4
Logic Diagram for "Normal"
Truth Table for "Normal"
SB
H05
J H01
N01 Q
CB H03
K H02
N02 QB
H04
RB
N01 Q
CB H03
K H02
H04
RB
CB
SB
1
1
Q
QB
0
1
1
1
0
1
0
1
1
1
1
1
1
1
X
X
1
1
X
X
X
0
1
0
1
X
X
X
1
0
1
0
X
X
X
0
0
0
0
Hold
1
0
Invert
Hold
← Prohibition
J
K
RB
SB
Q
0
0
CB
1
1
Hold
0
1
1
1
0
1
0
1
1
1
1
1
1
1
Invert
X
X
1
1
Hold
X
X
X
0
1
0
X
X
X
1
0
1
X
X
X
0
0
0
← Prohibition
RB → QB
SB → QB
Set up time
Set up time
Hold time
Hold time
Release time
Release time
Removal time
Removal time
Min Pulse
Min Pulse
Min Pulse
X:Irrelevant
Logic Diagram for "QB output"
Truth Table for "QB output"
SB
H05
J H01
CB H03
N01 QB
H04
RB
RB
0
Truth Table for "Q output"
SB
H05
K H02
K
X:Irrelevant
Logic Diagram for "Q output"
J H01
J
0
J
K
RB
SB
QB
0
0
CB
1
1
Hold
0
1
1
1
1
1
0
1
1
0
1
1
1
1
Invert
X
X
1
1
Hold
X
X
X
0
1
1
X
X
X
1
0
0
X
X
X
0
0
0
(LH)
(LL)
(LH)
(LL)
(LL)
(LH)
(LH)
(LL)
J
K
J
K
RB
SB
RB
SB
CB
RB
SB
(LH)
(LL)
(LL)
(LH)
J
K
J
K
RB
SB
RB
SB
CB
RB
SB
(LH)
(LL)
(LH)
(LL)
J
K
J
K
RB
SB
RB
SB
CB
RB
SB
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.421
0.373
0.584
0.600
0.177
0.391
0.377
0.235
0.750
0.740
0.200
0.370
0.180
0.390
0.670
0.430
0.798
0.672
0.732
0.420
0.372
0.177
0.379
0.750
0.740
0.200
0.370
0.180
0.390
0.670
0.430
0.620
0.351
0.655
0.326
0.331
0.432
0.293
0.730
0.740
0.190
0.370
0.170
0.410
0.630
0.420
0.539
0.695
0.553
0.716
0.609
0.983
1.016
0.273
0.772
0.808
0.458
1.419
1.150
1.962
1.986
0.463
1.520
1.570
0.783
1.460
1.680
0.000
0.110
0.000
0.700
1.180
0.490
2.307
1.830
1.932
1.417
1.151
0.463
1.374
1.460
1.680
0.000
0.110
0.000
0.700
1.190
0.490
1.737
0.752
1.724
1.022
1.051
1.774
0.992
1.440
1.680
0.000
0.120
0.000
0.680
1.090
0.470
1.380
2.074
1.336
0.011
0.010
0.011
0.010
0.010
0.011
0.011
0.010
0.015
0.013
0.015
0.013
0.013
0.016
0.015
0.013
0.022
0.017
0.022
0.018
0.017
0.023
0.022
0.019
0.011
0.010
0.010
0.011
0.015
0.013
0.013
0.015
0.022
0.017
0.017
0.022
0.011
0.011
0.011
0.011
0.016
0.014
0.016
0.014
0.023
0.020
0.023
0.020
0.716
0.609
0.273
0.709
0.532
0.553
0.869
0.536
Symbol
J
K
CB
RB
SB
Output
Fanin Symbol Fanout
1.0
1.0
1.0
2.3
2.1
Q
QB
34
31
J
K
CB
RB
SB
1.0
1.0
1.0
2.3
2.1
Q
34
J
K
CB
RB
SB
1.0
1.0
1.0
2.3
2.1
QB
31
← Prohibition
X:Irrelevant
Block Library
A13872EJ5V0BL
2 - 354
Block Library
A13872EJ5V0BL
2 - 355
Chapter 3
Scan Path Block
3-1
Block Library
A13872EJ5V0BL
Chapter 3 Scan Path Block
Chapter 3 Scan Path Block
[MEMO]
3.1
Standard Type
Block Library
A13872EJ5V0BL
3-2
Block Library
A13872EJ5V0BL
3-3
Chapter 3 Scan Path Block
Function
Chapter 3 Scan Path Block
Scan D-F/F with R, S, 2 to 1 Selector
Block
type
Standard type
Block type
Normal
Drivability
Name
cells
x1
S000
12
Q output
Name
cells
Name
cells
QB output
Name
cells
Name
cells
S000
Name
SCK → QB
x4
x8
Logic Diagram for "Normal"
Truth Table for "Normal"
S
H04
H01
H02
H03
H06
N01
Q
SIN
SCK
SMC
S
R
D
Q
QB
X
X
X
1
0
X
1
0
X
X
X
0
1
X
0
1
0
0
0
X
A
AB
X
1
0
0
B
B
X
X
0
0
X
X
1
1
X
A
N02
QB
X
H05
R
SCK → Q
cells
x2
SIN
SCK
SMC
D
IN
Path
→ OUT
X
BB
Hold
1
1
← Prohibition
X:Irrelevant
Logic Diagram for "Q output"
Truth Table for "Q output"
Logic Diagram for "QB output"
Truth Table for "QB output"
Block Library
A13872EJ5V0BL
3-4
S → Q
S → QB
R → Q
R → QB
Set up time
Set up time
Set up time
Hold time
Hold time
Hold time
Release time
Release time
Removal time
Removal time
Min Pulse
Min Pulse
Min Pulse
(HH)
(HL)
(HH)
(HL)
(HH)
(HL)
(HL)
(HH)
SIN
SMC
D
SIN
SMC
D
S
R
S
R
SCK
S
R
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.375
0.476
0.570
0.581
0.172
0.378
0.418
0.183
0.740
0.730
0.740
0.260
0.250
0.260
0.110
0.380
0.760
0.430
0.783
0.613
0.679
0.577
0.780
0.956
0.936
0.253
0.780
0.717
0.334
1.042
1.456
1.848
1.726
0.429
1.439
1.357
0.581
2.150
2.300
2.160
0.000
0.000
0.000
0.000
1.230
1.220
0.320
2.217
1.811
1.841
0.011
0.010
0.011
0.010
0.011
0.010
0.010
0.011
0.015
0.013
0.015
0.013
0.015
0.014
0.013
0.015
0.021
0.019
0.021
0.019
0.022
0.021
0.018
0.022
Block Library
A13872EJ5V0BL
Symbol
SIN
SCK
SMC
S
R
D
Output
Fanin Symbol Fanout
1.0
1.0
1.0
2.2
2.2
1.0
Q
QB
3-5
35
34
Chapter 3 Scan Path Block
Function
Chapter 3 Scan Path Block
Scan D-F/F with 2 to 1 Selector
Block
type
Standard type
Block type
Normal
Drivability
Name
cells
x1
S002
10
Q output
Name
cells
Name
cells
QB output
Name
cells
Name
cells
Name
S002
SCK → QB
Set up time
Set up time
Set up time
Hold time
Hold time
Hold time
Min Pulse
x4
x8
Logic Diagram for "Normal"
H01
H02
H03
H04
SCK → Q
cells
x2
SIN
SCK
SMC
D
IN
Path
→ OUT
Truth Table for "Normal"
N01
N02
SIN
Q
QB
SMC
D
Q
QB
X
SCK
1
B
B
BB
A
0
X
A
X
X
X
(HH)
(HL)
(HH)
(HL)
SIN
SMC
D
SIN
SMC
D
SCK
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.356
0.399
0.491
0.482
0.690
0.690
0.700
0.250
0.240
0.250
0.668
0.550
0.648
0.812
0.765
0.992
1.205
1.551
1.400
1.520
1.660
1.530
0.000
0.000
0.000
1.920
0.011
0.010
0.011
0.010
0.015
0.013
0.015
0.013
0.021
0.017
0.021
0.017
Symbol
SIN
SCK
SMC
D
Output
Fanin Symbol Fanout
1.0
1.0
1.0
1.0
Q
QB
AB
Hold
X:Irrelevant
Logic Diagram for "Q output"
Truth Table for "Q output"
Logic Diagram for "QB output"
Truth Table for "QB output"
Block Library
A13872EJ5V0BL
3-6
Block Library
A13872EJ5V0BL
3-7
35
35
Chapter 3 Scan Path Block
Function
Chapter 3 Scan Path Block
Scan D-F/F with 2 to 1 Selector, High Speed
Block
type
Standard type
Block type
Normal
Drivability
Name
cells
x1
S003
11
Q output
Name
cells
Name
cells
QB output
Name
cells
Name
cells
Name
S003
SCK → QB
Set up time
Set up time
Set up time
Hold time
Hold time
Hold time
Min Pulse
x4
x8
Logic Diagram for "Normal"
H01
H02
H03
H04
SCK → Q
cells
x2
SIN
SCK
SMC
D
IN
Path
→ OUT
Truth Table for "Normal"
N01
N02
SIN
Q
QB
SMC
D
Q
QB
X
SCK
1
B
B
BB
A
0
X
A
X
X
X
(HH)
(HL)
(HH)
(HL)
SIN
SMC
D
SIN
SMC
D
SCK
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.325
0.334
0.428
0.451
0.720
0.740
0.710
0.190
0.200
0.200
0.615
0.525
0.532
0.702
0.735
0.980
0.946
1.304
1.385
1.590
1.730
1.570
0.000
0.000
0.000
1.754
0.011
0.011
0.011
0.010
0.015
0.014
0.015
0.013
0.022
0.020
0.021
0.017
Symbol
SIN
SCK
SMC
D
Output
Fanin Symbol Fanout
1.0
1.0
1.0
1.0
Q
QB
AB
Hold
X:Irrelevant
Logic Diagram for "Q output"
Truth Table for "Q output"
Logic Diagram for "QB output"
Truth Table for "QB output"
Block Library
A13872EJ5V0BL
3-8
Block Library
A13872EJ5V0BL
3-9
34
35
Chapter 3 Scan Path Block
Function
Chapter 3 Scan Path Block
Scan D-F/F with R, S, Hold, 2 to 1 Selector
Block
type
Standard type
Block type
Normal
Drivability
Name
cells
x1
S050
16
Q output
Name
cells
Name
cells
QB output
Name
cells
Name
cells
S050
Name
SCK → QB
x4
x8
Logic Diagram for "Normal"
Truth Table for "Normal"
S
H06
H01
H02
H03
H04
H07
SCK → Q
cells
x2
SIN
SCK
SMC
SDH
D
IN
Path
→ OUT
SIN
N01 Q
N02 QB
SMC
SDH
S
R
D
X
SCK
X
1
0
0
X
Q
A
0
0
0
0
X
A
X
1
0
0
0
B
B
X
X
X
0
0
X
QB
Hold
AB
BB
Hold
X
X
X
X
0
1
X
0
1
X
X
X
X
1
0
X
1
0
X
X
X
X
1
1
X
1
1
← Prohibition
X:Irrelevant
H05
R
Logic Diagram for "Q output"
Truth Table for "Q output"
Logic Diagram for "QB output"
Truth Table for "QB output"
Block Library
A13872EJ5V0BL
3 - 10
R → Q
R → QB
S → Q
S → QB
Set up time
Set up time
Set up time
Set up time
Hold time
Hold time
Hold time
Hold time
Release time
Release time
Removal time
Removal time
Min Pulse
Min Pulse
Min Pulse
(HH)
(HL)
(HH)
(HL)
(HL)
(HH)
(HH)
(HL)
SIN
SMC
SDH
D
SIN
SMC
SDH
D
R
S
R
S
SCK
R
S
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.413
0.542
0.636
0.623
0.484
0.183
0.207
0.416
0.900
0.910
0.760
0.900
0.070
0.050
0.180
0.080
0.390
0.110
0.430
0.760
0.824
0.745
0.702
0.632
0.880
1.063
0.996
0.820
0.334
0.297
0.826
1.135
1.626
2.036
1.834
1.531
0.581
0.499
1.517
2.800
2.960
2.420
2.800
0.000
0.000
0.000
0.000
1.240
0.000
0.320
1.220
2.404
2.009
1.947
0.011
0.011
0.011
0.010
0.011
0.011
0.011
0.010
0.015
0.014
0.015
0.013
0.014
0.015
0.015
0.014
0.022
0.020
0.021
0.019
0.020
0.022
0.022
0.021
Block Library
A13872EJ5V0BL
Symbol
SIN
SCK
SMC
SDH
R
S
D
Output
Fanin Symbol Fanout
1.0
1.0
1.0
1.0
2.2
2.4
1.0
Q
QB
3 - 11
34
34
Chapter 3 Scan Path Block
Function
Chapter 3 Scan Path Block
Scan D-F/F with Hold, 2 to 1 Selector
Block
type
Standard type
Block type
Normal
Drivability
Name
cells
x1
S052
14
Q output
Name
cells
Name
cells
QB output
Name
cells
Name
cells
Name
S052
SCK → QB
Set up time
Set up time
Set up time
Set up time
Hold time
Hold time
Hold time
Hold time
Min Pulse
x4
x8
Logic Diagram for "Normal"
H01
H02
H03
H04
H05
SCK → Q
cells
x2
SIN
SCK
SMC
SDH
D
IN
Path
→ OUT
Truth Table for "Normal"
N01
N02
Q
QB
SIN
SMC
SDH
D
X
SCK
X
1
X
Q
A
0
0
X
A
X
1
0
B
B
X
X
X
X
QB
Hold
(HH)
(HL)
(HH)
(HL)
SIN
SMC
SDH
D
SIN
SMC
SDH
D
SCK
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.390
0.438
0.531
0.516
0.880
0.880
0.730
0.870
0.070
0.040
0.180
0.070
0.702
0.598
0.709
0.877
0.815
1.074
1.306
1.664
1.489
2.180
2.330
1.790
2.170
0.000
0.000
0.000
0.000
2.033
0.011
0.010
0.011
0.010
0.015
0.013
0.015
0.013
0.022
0.018
0.021
0.017
Symbol
SIN
SCK
SMC
SDH
D
Output
Fanin Symbol Fanout
1.0
1.0
1.0
1.0
1.0
Q
QB
AB
BB
Hold
X:Irrelevant
Logic Diagram for "Q output"
Truth Table for "Q output"
Logic Diagram for "QB output"
Truth Table for "QB output"
Block Library
A13872EJ5V0BL
3 - 12
Block Library
A13872EJ5V0BL
3 - 13
35
35
Chapter 3 Scan Path Block
Function
Chapter 3 Scan Path Block
Scan JK-F/F with R, S, D-F/F Function
Block
type
Standard type
Block type
Normal
Drivability
Name
cells
x1
S100
14
Q output
Name
cells
Name
cells
QB output
Name
cells
Name
cells
S100
Name
SCK → QB
x4
x8
Logic Diagram for "Normal"
Truth Table for "Normal"
S
H04
H01
H02
H03
H06
H07
SCK → Q
cells
x2
SIN
SCK
SMC
J
K
IN
Path
→ OUT
N01 Q
SIN
SCK
SMC
S
R
J
K
Qn
QBn
Qn+1
X
X
X
1
0
X
X
X
X
1
X
X
X
0
1
X
X
X
X
0
1
A
0
0
0
X
X
X
X
A
AB
X
1
0
0
B
X
0
1
B
BB
CB
X
X
X
X
1
0
0
X
C
1
0
X
0
0
X
X
X
X
X
1
1
X
X
X
X
QBn+1
0
C
Hold
1
1
← Prohibition
X:Irrelevant
N02 QB
H05
R
Logic Diagram for "Q output"
Truth Table for "Q output"
Logic Diagram for "QB output"
Truth Table for "QB output"
Block Library
A13872EJ5V0BL
3 - 14
S → Q
S → QB
R → Q
R → QB
Set up time
Set up time
Set up time
Set up time
Hold time
Hold time
Hold time
Hold time
Release time
Release time
Removal time
Removal time
Min Pulse
Min Pulse
Min Pulse
(HH)
(HL)
(HH)
(HL)
(HH)
(HL)
(HL)
(HH)
SIN
SMC
J
K
SIN
SMC
J
K
S
R
S
R
SCK
S
R
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.375
0.478
0.636
0.686
0.172
0.482
0.423
0.239
0.730
0.790
0.780
0.790
0.270
0.250
0.040
0.040
0.110
0.380
0.750
0.430
0.886
0.715
0.806
0.576
0.780
1.051
1.094
0.253
0.938
0.797
0.407
1.041
1.457
2.006
1.993
0.429
1.712
1.492
0.703
2.140
2.550
2.540
2.160
0.000
0.000
0.000
0.000
0.000
1.220
1.210
0.320
2.387
2.078
2.027
0.011
0.010
0.011
0.011
0.011
0.011
0.010
0.011
0.015
0.013
0.015
0.014
0.015
0.015
0.013
0.015
0.021
0.019
0.021
0.021
0.022
0.022
0.018
0.022
Block Library
A13872EJ5V0BL
Symbol
SIN
SCK
SMC
S
R
J
K
Output
Fanin Symbol Fanout
1.0
1.0
1.0
2.2
2.2
1.0
1.0
Q
QB
3 - 15
34
33
Chapter 3 Scan Path Block
Function
Chapter 3 Scan Path Block
Scan JK-F/F with D-F/F Function
Block
type
Standard type
Block type
Normal
Drivability
Name
cells
x1
S102
12
Q output
Name
cells
Name
cells
QB output
Name
cells
Name
cells
Name
S102
SCK → QB
Set up time
Set up time
Set up time
Set up time
Hold time
Hold time
Hold time
Hold time
Min Pulse
x4
x8
Logic Diagram for "Normal"
H01
H02
H03
H04
H05
SCK → Q
cells
x2
SIN
SCK
SMC
J
K
IN
Path
→ OUT
Truth Table for "Normal"
N01
N02
Q
QB
SIN
SMC
J
K
Qn
QBn
Qn+1
QBn+1
A
SCK
0
X
X
X
X
A
AB
X
1
B
X
0
1
B
BB
X
1
X
C
1
0
CB
X
X
X
X
X
X
(HH)
(HL)
(HH)
(HL)
SIN
SMC
J
K
SIN
SMC
J
K
SCK
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.358
0.401
0.540
0.539
0.700
0.740
0.810
0.810
0.250
0.240
0.060
0.050
0.724
0.550
0.650
0.883
0.851
0.992
1.207
1.673
1.544
1.530
1.930
1.920
2.020
0.000
0.000
0.000
0.000
2.042
0.011
0.010
0.011
0.010
0.015
0.013
0.015
0.013
0.021
0.017
0.021
0.018
Symbol
SIN
SCK
SMC
J
K
Output
Fanin Symbol Fanout
1.0
1.0
1.0
1.0
1.0
Q
QB
C
Hold
X:Irrelevant
Logic Diagram for "Q output"
Truth Table for "Q output"
Logic Diagram for "QB output"
Truth Table for "QB output"
Block Library
A13872EJ5V0BL
3 - 16
Block Library
A13872EJ5V0BL
3 - 17
35
34
Chapter 3 Scan Path Block
Function
Chapter 3 Scan Path Block
Scan JK-F/F with R, S, Hold, D-F/F Function
Block
type
Standard type
Block type
Normal
Drivability
Name
cells
x1
S150
18
Q output
Name
cells
Name
cells
QB output
Name
cells
Name
cells
S150
Name
SCK → QB
x4
x8
Logic Diagram for "Normal"
Truth Table for "Normal"
S
H06
H01
H02
H03
H04
H07
H08
SCK → Q
cells
x2
SIN
SCK
SMC
SDH
J
K
IN
Path
→ OUT
SIN
N01 Q
SMC
SDH
S
R
J
K
Qn
QBn
X
X
1
0
0
X
X
X
X
A
SCK
0
0
0
0
X
X
X
X
Qn+1
X
1
0
0
0
B
X
0
1
B
X
1
0
0
0
X
C
1
0
CB
X
X
X
0
0
X
X
X
X
QBn+1
Hold
A
AB
BB
C
Hold
X
X
X
X
0
1
X
X
X
X
0
1
X
X
X
X
1
0
X
X
X
X
1
0
X
X
X
X
1
1
X
X
X
X
1
1
← Prohibition
X:Irrelevant
N02 QB
H05
R
Logic Diagram for "Q output"
Truth Table for "Q output"
Logic Diagram for "QB output"
Truth Table for "QB output"
Block Library
A13872EJ5V0BL
3 - 18
R → Q
R → QB
S → Q
S → QB
Set up time
Set up time
Set up time
Set up time
Set up time
Hold time
Hold time
Hold time
Hold time
Hold time
Release time
Release time
Removal time
Removal time
Min Pulse
Min Pulse
Min Pulse
(HH)
(HL)
(HH)
(HL)
(HL)
(HH)
(HH)
(HL)
SIN
SMC
SDH
J
K
SIN
SMC
SDH
J
K
R
S
R
S
SCK
R
S
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.376
0.480
0.662
0.732
0.425
0.259
0.172
0.527
0.900
0.930
0.710
0.940
0.980
0.070
0.040
0.240
0.000
0.000
0.380
0.110
0.430
0.740
0.931
0.854
0.759
0.577
0.783
1.090
1.165
0.832
0.438
0.253
1.009
1.041
1.459
2.075
2.119
1.556
0.757
0.429
1.842
2.810
3.060
2.230
3.030
2.630
0.000
0.000
0.000
0.000
0.000
1.230
0.000
0.320
1.210
2.516
2.108
2.208
0.011
0.010
0.011
0.011
0.010
0.011
0.011
0.011
0.015
0.013
0.015
0.015
0.013
0.015
0.015
0.016
0.021
0.019
0.021
0.021
0.019
0.022
0.022
0.023
Block Library
A13872EJ5V0BL
Symbol
SIN
SCK
SMC
SDH
R
S
J
K
Output
Fanin Symbol Fanout
1.0
1.0
1.0
1.0
2.2
2.3
1.0
1.0
Q
QB
3 - 19
35
33
Chapter 3 Scan Path Block
Function
Chapter 3 Scan Path Block
Scan JK-F/F with Hold, D-F/F Function
Block
type
Standard type
Block type
Normal
Drivability
Name
cells
x1
S152
16
Q output
Name
cells
Name
cells
QB output
Name
cells
Name
cells
Name
S152
SCK → QB
Set up time
Set up time
Set up time
Set up time
Set up time
Hold time
Hold time
Hold time
Hold time
Hold time
Min Pulse
x4
x8
Logic Diagram for "Normal"
H01
H02
H03
H04
H05
H06
SCK → Q
cells
x2
SIN
SCK
SMC
SDH
J
K
IN
Path
→ OUT
Truth Table for "Normal"
N01
N02
Q
QB
SIN
SMC
SDH
J
K
Qn
QBn
X
SCK
X
1
X
X
X
X
Qn+1
QBn+1
A
0
0
X
X
X
X
A
AB
X
1
0
B
X
0
1
B
BB
X
1
0
X
C
1
0
CB
X
X
X
X
X
X
X
Hold
C
Hold
(HH)
(HL)
(HH)
(HL)
SIN
SMC
SDH
J
K
SIN
SMC
SDH
J
K
SCK
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.357
0.402
0.566
0.571
0.870
0.900
0.680
0.950
0.990
0.060
0.030
0.230
0.000
0.000
0.758
0.550
0.652
0.922
0.899
0.991
1.210
1.740
1.624
2.190
2.430
1.610
2.410
2.560
0.000
0.000
0.000
0.000
0.000
2.109
0.011
0.010
0.011
0.010
0.015
0.013
0.015
0.013
0.021
0.017
0.021
0.019
Symbol
SIN
SCK
SMC
SDH
J
K
Output
Fanin Symbol Fanout
1.0
1.0
1.0
1.0
1.0
1.0
Q
QB
X:Irrelevant
Logic Diagram for "Q output"
Truth Table for "Q output"
Logic Diagram for "QB output"
Truth Table for "QB output"
Block Library
A13872EJ5V0BL
3 - 20
Block Library
A13872EJ5V0BL
3 - 21
35
34
Chapter 3 Scan Path Block
Function
Chapter 3 Scan Path Block
Scan D-Latch with R, D-F/F Function
Block
type
Standard type
Block type
Normal
Drivability
Name
cells
x1
S201
13
Q output
Name
cells
Name
cells
QB output
Name
cells
Name
cells
S201
Name
SCK → Q
cells
SCK → QB
x2
R → Q
R → QB
D → Q
x4
x8
Logic Diagram for "Normal"
SIN
SCK
SMC
D
G
IN
Path
→ OUT
H01
H02
H03
H05
H06
Truth Table for "Normal"
N01
N02
H04
R
Q
QB
D → QB
SIN
SCK
SMC
R
D
G
Q
QB
X
X
X
1
X
X
0
1
A
0
0
X
X
A
X
0
0
X
X
X
X
1
0
B
1
X
X
1
0
X
0
X
1
Down
0
1
1
G → Q
G → QB
AB
Hold
B
BB
Latch
X
X
← Prohibition
X:Irrelevant
Logic Diagram for "Q output"
Truth Table for "Q output"
Logic Diagram for "QB output"
Truth Table for "QB output"
Block Library
A13872EJ5V0BL
3 - 22
Set up time
Set up time
Set up time
Hold time
Hold time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
Min Pulse
(HH)
(HL)
(HH)
(HL)
(HL)
(HH)
(HH)
(LL)
(HL)
(LH)
(HH)
(HL)
(HH)
(HL)
SIN
SMC
D
SIN
SMC
D
R
R
SCK
R
G
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.726
0.619
0.490
0.619
0.366
0.177
0.631
0.533
0.522
0.403
0.720
0.616
0.486
0.612
0.540
0.950
0.640
0.440
0.000
0.200
0.350
0.550
0.995
0.485
0.981
1.200
0.988
0.767
1.006
0.578
0.259
1.035
0.924
0.841
0.702
1.194
0.986
0.765
1.001
2.338
1.848
1.432
1.926
1.038
0.437
2.028
1.827
1.615
1.404
2.334
1.851
1.435
1.922
2.080
1.860
1.210
0.460
0.000
0.000
0.690
0.730
2.805
1.420
2.796
0.011
0.010
0.011
0.010
0.010
0.011
0.011
0.010
0.010
0.011
0.011
0.010
0.011
0.010
0.015
0.013
0.015
0.013
0.013
0.015
0.015
0.013
0.013
0.015
0.015
0.013
0.015
0.013
0.021
0.017
0.021
0.019
0.018
0.021
0.021
0.017
0.019
0.021
0.021
0.017
0.021
0.019
Block Library
A13872EJ5V0BL
Symbol
SIN
SCK
SMC
R
D
G
Output
Fanin Symbol Fanout
1.0
1.0
1.0
2.1
1.0
1.0
Q
QB
3 - 23
35
34
Chapter 3 Scan Path Block
Function
Chapter 3 Scan Path Block
Scan D-Latch with D-F/F Function
Block
type
Standard type
Block type
Normal
Drivability
Name
cells
x1
S202
12
Q output
Name
cells
Name
cells
Name
QB output
cells
Name
cells
S202
Name
IN
Path
→ OUT
SCK → Q
cells
SCK → QB
x2
D → Q
x4
D → QB
x8
Logic Diagram for "Normal"
SIN
SCK
SMC
D
G
H01
H02
H03
H04
H05
Truth Table for "Normal"
N01
N02
Q
QB
SIN
SCK
G → Q
SMC
D
G
Q
A
0
X
X
A
X
0
X
X
X
X
1
B
1
X
X
1
X
0
X
1
Down
1
1
G → QB
QB
AB
Hold
B
BB
Latch
X
X
← Prohibition
X:Irrelevant
Logic Diagram for "Q output"
Truth Table for "Q output"
Logic Diagram for "QB output"
Truth Table for "QB output"
Block Library
A13872EJ5V0BL
3 - 24
Set up time
Set up time
Set up time
Hold time
Hold time
Hold time
Min Pulse
Min Pulse
(HH)
(HL)
(HH)
(HL)
(HH)
(LL)
(HL)
(LH)
(HH)
(HL)
(HH)
(HL)
SIN
SMC
D
SIN
SMC
D
SCK
G
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.625
0.607
0.484
0.535
0.522
0.530
0.430
0.405
0.618
0.610
0.487
0.527
0.470
0.960
0.620
0.460
0.000
0.270
0.912
0.912
1.029
0.964
0.752
0.866
0.857
0.921
0.692
0.705
1.023
0.968
0.755
0.860
2.007
1.810
1.405
1.663
1.678
1.822
1.331
1.410
2.002
1.821
1.415
1.658
2.050
1.860
1.220
0.480
0.000
0.090
2.474
2.466
0.011
0.010
0.011
0.010
0.011
0.010
0.010
0.011
0.011
0.010
0.011
0.010
0.015
0.013
0.015
0.013
0.015
0.013
0.013
0.015
0.015
0.013
0.015
0.013
0.021
0.017
0.021
0.017
0.021
0.017
0.017
0.021
0.021
0.017
0.021
0.017
Block Library
A13872EJ5V0BL
Symbol
SIN
SCK
SMC
D
G
Output
Fanin Symbol Fanout
1.0
1.0
1.0
1.0
1.0
Q
QB
3 - 25
35
34
Chapter 3 Scan Path Block
Function
Chapter 3 Scan Path Block
Scan D-Latch with D-F/F Function, High Speed
Block
type
Standard type
Block type
Normal
Drivability
Name
cells
x1
S204
12
Q output
Name
cells
Name
cells
Name
QB output
cells
Name
cells
S204
Name
IN
Path
→ OUT
SCK → Q
cells
SCK → QB
x2
D → Q
x4
D → QB
x8
Logic Diagram for "Normal"
SIN
SCK
SMC
D
G
H01
H02
H03
H04
H05
Truth Table for "Normal"
N01
N02
Q
QB
SIN
SCK
G → Q
SMC
D
G
Q
A
0
X
X
A
X
0
X
X
X
X
1
B
1
X
X
1
X
0
X
1
Down
1
1
G → QB
QB
AB
Hold
B
BB
Latch
X
X
← Prohibition
X:Irrelevant
Logic Diagram for "Q output"
Truth Table for "Q output"
Logic Diagram for "QB output"
Truth Table for "QB output"
Block Library
A13872EJ5V0BL
3 - 26
Set up time
Set up time
Set up time
Hold time
Hold time
Hold time
Min Pulse
Min Pulse
(HH)
(HL)
(HH)
(HL)
(HH)
(LL)
(HL)
(LH)
(HH)
(HL)
(HH)
(HL)
SIN
SMC
D
SIN
SMC
D
SCK
G
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.477
0.464
0.562
0.611
0.371
0.378
0.506
0.480
0.470
0.466
0.565
0.604
0.470
0.970
0.670
0.460
0.000
0.280
0.882
0.869
0.767
0.757
0.942
0.991
0.595
0.652
0.821
0.848
0.762
0.762
0.948
0.985
1.485
1.423
1.828
1.924
1.163
1.304
1.608
1.742
1.480
1.438
1.846
1.919
1.890
2.100
1.480
0.490
0.000
0.030
2.392
2.382
0.011
0.012
0.011
0.010
0.011
0.012
0.010
0.011
0.011
0.012
0.011
0.010
0.016
0.015
0.015
0.012
0.016
0.016
0.012
0.015
0.016
0.015
0.015
0.012
0.023
0.022
0.020
0.017
0.023
0.023
0.017
0.020
0.023
0.022
0.020
0.017
Block Library
A13872EJ5V0BL
Symbol
SIN
SCK
SMC
D
G
Output
Fanin Symbol Fanout
1.0
1.0
1.0
1.0
1.0
Q
QB
3 - 27
31
34
Chapter 3 Scan Path Block
Function
Chapter 3 Scan Path Block
Scan D-Latch with R, Special Function, R
Block
type
Standard type
Block type
Normal
Drivability
Name
cells
x1
S301
8
Q output
Name
cells
Name
cells
QB output
Name
cells
Name
cells
Name
S301
IN
Path
→ OUT
AMC → Q
cells
AMC → QB
x2
x4
R → Q
x8
Logic Diagram for "Normal"
AMC H01
D
Truth Table for "Normal"
N01
Q
H03
GB H04
N02
H02
R
QB
R → QB
AMC
R
D
GB
Q
QB
1
0
0
0
0
1
1
0
1
0
1
0
D → Q
D → QB
GB → Q
1
0
X
1
X
1
X
X
0
Latch
1
0
0
0
0
0
1
0
0
0
1
0
1
0
0
1
0
0
1
0
0
1
1
1
0
GB → QB
Set up time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
X:Irrelevant
Logic Diagram for "Q output"
Truth Table for "Q output"
Logic Diagram for "QB output"
Truth Table for "QB output"
Block Library
A13872EJ5V0BL
3 - 28
(HH)
(LH)
(LL)
(HL)
(LH)
(LL)
(HL)
(LH)
(HH)
(LL)
(HH)
(LL)
(HL)
(LH)
(HH)
(LH)
(LL)
(HL)
(LH)
(LL)
D
D
R
R
R
GB
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.555
0.553
0.579
0.445
0.447
0.442
0.307
0.349
0.176
0.239
0.573
0.414
0.462
0.283
0.598
0.561
0.443
0.488
0.313
0.451
0.710
0.340
0.440
0.370
0.622
0.799
0.937
0.944
0.967
0.740
0.742
0.747
0.479
0.590
0.257
0.394
0.945
0.709
0.748
0.487
1.018
0.937
1.057
0.821
0.830
0.740
1.857
1.884
1.765
1.440
1.339
1.466
0.860
1.199
0.436
0.785
1.872
1.364
1.456
0.943
2.091
1.797
1.961
1.674
1.533
1.380
1.390
0.100
0.580
0.240
1.417
2.360
0.011
0.011
0.010
0.010
0.011
0.010
0.010
0.011
0.011
0.010
0.011
0.010
0.010
0.011
0.011
0.011
0.010
0.010
0.011
0.010
0.015
0.015
0.013
0.013
0.015
0.013
0.013
0.015
0.015
0.013
0.015
0.013
0.013
0.015
0.015
0.015
0.013
0.013
0.015
0.013
0.021
0.021
0.017
0.019
0.021
0.019
0.017
0.021
0.022
0.019
0.021
0.017
0.019
0.021
0.021
0.021
0.017
0.019
0.021
0.019
Block Library
A13872EJ5V0BL
Symbol
AMC
R
D
GB
Output
Fanin Symbol Fanout
1.8
1.0
1.0
2.0
Q
QB
3 - 29
35
34
Chapter 3 Scan Path Block
Function
Chapter 3 Scan Path Block
Scan D-Latch with Special Function
Block
type
Standard type
Block type
Normal
Drivability
Name
cells
x1
S302
7
Q output
Name
cells
Name
cells
QB output
Name
cells
Name
cells
Name
S302
IN
Path
→ OUT
AMC → Q
cells
AMC → QB
x2
x4
D → Q
x8
Logic Diagram for "Normal"
AMC H01
D
Truth Table for "Normal"
N01
Q
H02
GB H03
N02
QB
D → QB
AMC
D
GB
Q
QB
1
0
0
0
1
1
1
0
1
1
X
1
0
0
0
0
1
0
0
1
0
1
0
1
0
0
1
0
1
1
1
0
GB → Q
GB → QB
0
Latch
Set up time
Hold time
Min Pulse
(HH)
(LH)
(LL)
(HL)
(LH)
(LL)
(HH)
(LL)
(HL)
(LH)
(HH)
(LH)
(LL)
(HL)
(LH)
(LL)
D
D
GB
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.456
0.455
0.587
0.360
0.456
0.359
0.474
0.410
0.378
0.283
0.496
0.464
0.438
0.400
0.311
0.369
0.650
0.340
0.832
0.767
0.774
0.972
0.597
0.750
0.604
0.776
0.702
0.606
0.483
0.845
0.769
1.063
0.675
0.839
0.600
1.527
1.553
1.766
1.174
1.346
1.197
1.540
1.351
1.187
0.934
1.753
1.472
1.966
1.398
1.542
1.116
1.150
0.090
2.238
0.011
0.011
0.010
0.010
0.011
0.010
0.011
0.010
0.010
0.011
0.011
0.011
0.010
0.010
0.011
0.010
0.015
0.015
0.013
0.013
0.015
0.013
0.015
0.013
0.013
0.015
0.015
0.015
0.013
0.013
0.015
0.013
0.021
0.021
0.017
0.017
0.021
0.017
0.021
0.017
0.017
0.021
0.021
0.021
0.017
0.017
0.021
0.017
Symbol
AMC
D
GB
Output
Fanin Symbol Fanout
1.8
1.0
2.0
Q
QB
X:Irrelevant
Logic Diagram for "Q output"
Truth Table for "Q output"
Logic Diagram for "QB output"
Truth Table for "QB output"
Block Library
A13872EJ5V0BL
3 - 30
Block Library
A13872EJ5V0BL
3 - 31
35
34
Chapter 3 Scan Path Block
Function
Chapter 3 Scan Path Block
Scan D-Latch with Special Function, High Speed
Block
type
Standard type
Block type
Normal
Drivability
Name
cells
x1
S303
7
Q output
Name
cells
Name
cells
QB output
Name
cells
Name
cells
Name
S303
IN
Path
→ OUT
AMC → Q
cells
AMC → QB
x2
x4
D → Q
x8
Logic Diagram for "Normal"
AMC H01
D
Truth Table for "Normal"
N01
Q
H02
GB H03
N02
QB
D → QB
AMC
D
GB
Q
QB
1
0
0
0
1
1
1
0
1
1
X
1
0
0
0
0
1
0
0
1
0
1
0
1
0
0
1
0
1
1
1
0
GB → Q
GB → QB
0
Latch
Set up time
Hold time
Min Pulse
(HH)
(LH)
(LL)
(HL)
(LH)
(LL)
(HH)
(LL)
(HL)
(LH)
(HH)
(LH)
(LL)
(HL)
(LH)
(LL)
D
D
GB
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.306
0.309
0.453
0.437
0.559
0.441
0.324
0.253
0.456
0.347
0.347
0.317
0.295
0.481
0.366
0.449
0.720
0.320
0.809
0.507
0.522
0.732
0.727
0.928
0.744
0.513
0.426
0.735
0.597
0.586
0.514
0.799
0.811
1.020
0.734
1.018
1.058
1.290
1.452
1.720
1.497
1.028
0.814
1.463
1.178
1.252
0.971
1.473
1.697
1.921
1.404
1.380
0.080
2.198
0.011
0.011
0.012
0.010
0.011
0.010
0.011
0.011
0.010
0.011
0.011
0.011
0.011
0.010
0.011
0.010
0.016
0.016
0.016
0.012
0.015
0.012
0.016
0.014
0.012
0.015
0.016
0.016
0.015
0.012
0.015
0.012
0.023
0.023
0.023
0.017
0.020
0.017
0.023
0.020
0.017
0.021
0.023
0.023
0.022
0.017
0.021
0.017
Symbol
AMC
D
GB
Output
Fanin Symbol Fanout
1.8
1.0
2.0
Q
QB
X:Irrelevant
Logic Diagram for "Q output"
Truth Table for "Q output"
Logic Diagram for "QB output"
Truth Table for "QB output"
Block Library
A13872EJ5V0BL
3 - 32
Block Library
A13872EJ5V0BL
3 - 33
31
34
Chapter 3 Scan Path Block
Chapter 3 Scan Path Block
[MEMO]
[MEMO]
Block Library
A13872EJ5V0BL
3 - 34
Block Library
A13872EJ5V0BL
3 - 35
Chapter 3 Scan Path Block
Chapter 3 Scan Path Block
[MEMO]
3.2
NEC Scan
Block Library
A13872EJ5V0BL
3 - 36
Block Library
A13872EJ5V0BL
3 - 37
Chapter 3 Scan Path Block
Function
Chapter 3 Scan Path Block
NEC Scan D-Latch
Block
type
Standard type
Block type
Normal
Drivability
Name
cells
x1
SE601
13
Q output
Name
cells
Name
cells
Name
QB output
cells
Name
cells
Name
SE601
IN
Path
→ OUT
D → Q
(HH)
(LL)
(HL)
(LH)
(HH)
(HL)
(HH)
(HL)
cells
D → QB
x2
G → Q
x4
G → QB
x8
Logic Diagram for "Normal"
D
H01
G H02
Truth Table for "Normal"
N01
N02
Q
QB
D
G
Q
QB
0
1
0
1
1
1
1
X
0
Set up time
Hold time
Min Pulse
D
D
G
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.589
0.575
0.460
0.420
0.466
0.488
0.334
0.342
0.930
0.010
0.848
0.972
0.962
0.747
0.705
0.770
0.793
0.539
0.555
1.872
1.860
1.410
1.369
1.492
1.525
1.038
1.052
1.930
0.000
2.151
0.011
0.010
0.011
0.011
0.011
0.010
0.011
0.011
0.015
0.013
0.014
0.015
0.015
0.013
0.015
0.014
0.021
0.017
0.020
0.022
0.021
0.017
0.022
0.020
Symbol
D
G
Output
Fanin Symbol Fanout
1.0
2.0
Q
QB
0
Latch
X:Irrelevant
Logic Diagram for "Q output"
Truth Table for "Q output"
Logic Diagram for "QB output"
Truth Table for "QB output"
Block Library
A13872EJ5V0BL
3 - 38
Block Library
A13872EJ5V0BL
3 - 39
34
34
Chapter 3 Scan Path Block
Function
Chapter 3 Scan Path Block
NEC Scan D-Latch with R
Block
type
Standard type
Block type
Normal
Drivability
Name
cells
x1
SE602
14
Q output
Name
cells
Name
cells
QB output
Name
cells
Name
cells
Name
SE602
IN
Path
→ OUT
D → Q
(HH)
(LL)
(HL)
(LH)
(HH)
(HL)
(HH)
(HL)
(HL)
(LH)
(HH)
(LL)
cells
D → QB
x2
G → Q
x4
G → QB
x8
Logic Diagram for "Normal"
D
H01
Truth Table for "Normal"
N01
G H02
N02
H03
R
Q
QB
R → Q
D
G
R
Q
QB
1
1
0
1
0
0
1
0
0
1
X
0
0
X
X
1
R → QB
Set up time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
Latch
0
1
D
D
R
R
G
R
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.725
0.571
0.590
0.416
0.485
0.485
0.332
0.359
0.413
0.553
0.266
0.419
1.080
0.020
0.890
0.000
0.862
0.865
1.215
0.959
0.972
0.702
0.808
0.790
0.536
0.581
0.690
0.965
0.446
0.723
2.371
1.860
1.846
1.370
1.595
1.520
1.034
1.113
1.304
1.965
0.831
1.441
2.490
0.000
1.980
0.000
2.197
2.225
0.011
0.010
0.012
0.011
0.011
0.010
0.011
0.012
0.010
0.011
0.011
0.012
0.015
0.013
0.016
0.015
0.015
0.013
0.015
0.015
0.013
0.015
0.015
0.016
0.020
0.017
0.023
0.022
0.021
0.017
0.022
0.022
0.017
0.020
0.022
0.023
Symbol
D
G
R
Output
Fanin Symbol Fanout
1.0
1.9
2.5
Q
QB
X:Irrelevant
Logic Diagram for "Q output"
Truth Table for "Q output"
Logic Diagram for "QB output"
Truth Table for "QB output"
Block Library
A13872EJ5V0BL
3 - 40
Block Library
A13872EJ5V0BL
3 - 41
34
34
Chapter 3 Scan Path Block
Function
Chapter 3 Scan Path Block
NEC Scan D-Latch with RB
Block
type
Standard type
Block type
Normal
Drivability
Name
cells
x1
SE603
14
Q output
Name
cells
Name
cells
QB output
Name
cells
Name
cells
Name
SE603
IN
Path
→ OUT
D → Q
cells
D → QB
x2
G → Q
x4
G → QB
x8
Logic Diagram for "Normal"
D
H01
Truth Table for "Normal"
N01
G H02
N02
H03
RB
Q
QB
RB → Q
D
G
RB
Q
QB
1
1
1
1
0
0
1
1
0
1
X
0
1
X
X
0
RB → QB
Set up time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
Latch
0
1
(HH)
(LL)
(HL)
(LH)
(HH)
(HL)
(HH)
(HL)
(HH)
(LL)
(HL)
(LH)
D
D
RB
RB
G
RB
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.572
0.512
0.717
0.619
0.451
0.429
0.535
0.596
0.221
0.203
0.366
0.311
0.930
0.050
0.520
0.310
0.958
0.613
0.953
0.858
1.201
1.044
0.727
0.698
0.883
0.975
0.345
0.315
0.592
0.584
1.871
1.650
2.347
2.033
1.430
1.330
1.710
1.905
0.689
0.536
1.163
1.064
1.920
0.000
0.580
0.290
2.443
1.451
0.011
0.010
0.011
0.011
0.011
0.010
0.011
0.011
0.011
0.010
0.011
0.011
0.015
0.013
0.013
0.015
0.015
0.013
0.015
0.013
0.015
0.013
0.013
0.015
0.022
0.018
0.018
0.021
0.022
0.018
0.021
0.018
0.022
0.018
0.018
0.021
Symbol
D
G
RB
Output
Fanin Symbol Fanout
1.0
1.9
2.5
Q
QB
X:Irrelevant
Logic Diagram for "Q output"
Truth Table for "Q output"
Logic Diagram for "QB output"
Truth Table for "QB output"
Block Library
A13872EJ5V0BL
3 - 42
Block Library
A13872EJ5V0BL
3 - 43
33
35
Chapter 3 Scan Path Block
Function
Chapter 3 Scan Path Block
NEC Scan D-Latch(GB)
Block
type
Standard type
Block type
Normal
Drivability
Name
cells
x1
SE604
13
Q output
Name
cells
Name
cells
Name
QB output
cells
Name
cells
Name
SE604
IN
Path
→ OUT
D → Q
cells
D → QB
x2
GB → Q
x4
GB → QB
x8
Logic Diagram for "Normal"
D
H01
GB H02
Truth Table for "Normal"
N01
N02
Q
QB
D
GB
Q
QB
1
0
1
0
0
0
0
X
1
Set up time
Hold time
Min Pulse
(HH)
(LL)
(HL)
(LH)
(LH)
(LL)
(LH)
(LL)
D
D
GB
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.587
0.576
0.459
0.421
0.497
0.496
0.342
0.371
0.870
0.000
0.902
0.968
0.965
0.745
0.708
0.838
0.811
0.556
0.619
1.865
1.867
1.404
1.376
1.623
1.561
1.071
1.183
1.780
0.000
2.122
0.011
0.010
0.011
0.011
0.011
0.010
0.011
0.011
0.015
0.013
0.014
0.015
0.015
0.013
0.015
0.014
0.021
0.017
0.020
0.022
0.021
0.017
0.022
0.020
Symbol
D
GB
Output
Fanin Symbol Fanout
1.0
2.0
Q
QB
1
Latch
X:Irrelevant
Logic Diagram for "Q output"
Truth Table for "Q output"
Logic Diagram for "QB output"
Truth Table for "QB output"
Block Library
A13872EJ5V0BL
3 - 44
Block Library
A13872EJ5V0BL
3 - 45
34
33
Chapter 3 Scan Path Block
Function
Chapter 3 Scan Path Block
NEC Scan D-Latch(GB) with RB
Block
type
Standard type
Block type
Normal
Drivability
Name
cells
x1
SE605
14
Q output
Name
cells
Name
cells
QB output
Name
cells
Name
cells
Name
SE605
IN
Path
→ OUT
D → Q
cells
D → QB
x2
GB → Q
x4
GB → QB
x8
Logic Diagram for "Normal"
D
H01
Truth Table for "Normal"
N01
GB H02
N02
H03
RB
Q
QB
RB → Q
D
GB
RB
Q
QB
1
0
1
1
0
0
0
1
0
1
X
1
1
X
X
0
RB → QB
Set up time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
Latch
0
1
(HH)
(LL)
(HL)
(LH)
(LH)
(LL)
(LH)
(LL)
(HH)
(LL)
(HL)
(LH)
D
D
RB
RB
GB
RB
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.571
0.512
0.716
0.619
0.487
0.431
0.536
0.632
0.221
0.203
0.366
0.311
0.850
0.010
0.480
0.340
0.999
0.613
0.952
0.859
1.199
1.045
0.816
0.702
0.886
1.062
0.345
0.315
0.592
0.584
1.869
1.654
2.346
2.035
1.624
1.328
1.710
2.099
0.689
0.536
1.164
1.064
1.780
0.000
0.480
0.370
2.517
1.451
0.011
0.010
0.011
0.011
0.011
0.010
0.011
0.011
0.011
0.010
0.011
0.011
0.015
0.013
0.013
0.015
0.015
0.013
0.015
0.013
0.015
0.013
0.013
0.015
0.022
0.018
0.018
0.021
0.022
0.018
0.021
0.018
0.022
0.018
0.018
0.021
Symbol
D
GB
RB
Output
Fanin Symbol Fanout
1.0
2.0
2.5
Q
QB
X:Irrelevant
Logic Diagram for "Q output"
Truth Table for "Q output"
Logic Diagram for "QB output"
Truth Table for "QB output"
Block Library
A13872EJ5V0BL
3 - 46
Block Library
A13872EJ5V0BL
3 - 47
33
33
Chapter 3 Scan Path Block
Function
Chapter 3 Scan Path Block
NEC Scan D-F/F
Block
type
Standard type
Block type
Normal
Drivability
Name
cells
x1
SE611
11
Q output
Name
cells
Name
cells
Name
QB output
cells
Name
cells
Name
SE611
Set up time
Hold time
Min Pulse
x8
Logic Diagram for "Normal"
C H02
(HH)
(HL)
(HH)
(HL)
C → QB
x4
H01
C → Q
cells
x2
D
IN
Path
→ OUT
D
D
C
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.382
0.411
0.522
0.531
0.620
0.280
0.924
0.600
0.666
0.860
0.852
1.120
1.272
1.671
1.596
1.200
0.210
2.263
0.011
0.010
0.011
0.010
0.015
0.013
0.015
0.013
0.021
0.017
0.021
0.018
Symbol
D
C
Output
Fanin Symbol Fanout
1.0
2.4
Q
QB
Truth Table for "Normal"
N01
N02
Q
QB
D
Q
QB
0
C
0
1
1
1
X
0
Hold
X:Irrelevant
Logic Diagram for "Q output"
Truth Table for "Q output"
Logic Diagram for "QB output"
Truth Table for "QB output"
Block Library
A13872EJ5V0BL
3 - 48
Block Library
A13872EJ5V0BL
3 - 49
35
35
Chapter 3 Scan Path Block
Function
Chapter 3 Scan Path Block
NEC Scan D-F/F with R, S
Block
type
Standard type
Block type
Normal
Drivability
Name
cells
x1
SE614
13
Q output
Name
cells
Name
cells
QB output
Name
cells
Name
cells
Name
SE614
R → Q
R → QB
S → Q
S → QB
Set up time
Hold time
Release time
Release time
Removal time
Removal time
Min Pulse
Min Pulse
Min Pulse
x8
Logic Diagram for "Normal"
Truth Table for "Normal"
S
H04
D
N01 Q
N02 QB
H03
R
(HH)
(HL)
(HH)
(HL)
(HL)
(HH)
(HH)
(HL)
C → QB
x4
C H02
C → Q
cells
x2
D H01
IN
Path
→ OUT
R
S
Q
QB
0
C
0
0
0
1
1
0
0
1
X
0
0
0
Hold
X
X
0
1
1
0
X
X
1
0
0
1
X
X
1
1
1
1
D
D
R
S
R
S
C
R
S
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.387
0.483
0.602
0.634
0.424
0.203
0.173
0.418
0.670
0.300
0.470
0.200
0.350
0.630
1.041
0.726
0.706
0.616
0.792
1.008
1.039
0.751
0.361
0.254
0.844
1.158
1.512
1.972
1.960
1.420
0.629
0.429
1.558
1.790
0.230
1.280
0.130
0.110
0.980
2.653
1.923
2.098
0.011
0.010
0.011
0.011
0.010
0.011
0.011
0.011
0.015
0.013
0.015
0.014
0.013
0.015
0.015
0.015
0.021
0.019
0.021
0.019
0.018
0.022
0.022
0.021
Symbol
D
C
R
S
Output
Fanin Symbol Fanout
1.0
2.5
2.2
2.4
Q
QB
← Prohibition
X:Irrelevant
Logic Diagram for "Q output"
Truth Table for "Q output"
Logic Diagram for "QB output"
Truth Table for "QB output"
Block Library
A13872EJ5V0BL
3 - 50
Block Library
A13872EJ5V0BL
3 - 51
35
34
Chapter 3 Scan Path Block
Function
Chapter 3 Scan Path Block
NEC Scan D-F/F with RB
Block
type
Standard type
Block type
Normal
Drivability
Name
cells
x1
SE615
12
Q output
Name
cells
Name
cells
QB output
Name
cells
Name
cells
Name
SE615
C → QB
RB → Q
RB → QB
Set up time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
x4
x8
Logic Diagram for "Normal"
H01
Truth Table for "Normal"
N01
C H02
N02
Q
QB
D
RB
Q
QB
0
1
0
1
1
1
1
X
1
X
H03
RB
C → Q
cells
x2
D
IN
Path
→ OUT
C
X
0
(HH)
(HL)
(HH)
(HL)
(LL)
(LH)
D
D
RB
RB
C
RB
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.439
0.419
0.534
0.591
0.181
0.300
0.630
0.300
0.320
0.510
0.977
0.562
0.705
0.677
0.875
0.966
0.281
0.565
1.369
1.288
1.694
1.874
0.474
1.025
1.360
0.230
0.350
0.710
2.498
1.401
0.011
0.010
0.011
0.010
0.010
0.011
0.015
0.013
0.015
0.013
0.013
0.015
0.022
0.017
0.021
0.017
0.017
0.021
Symbol
D
C
RB
Output
Fanin Symbol Fanout
1.0
2.5
2.6
Q
QB
0
Hold
0
1
X:Irrelevant
Logic Diagram for "Q output"
Truth Table for "Q output"
Logic Diagram for "QB output"
Truth Table for "QB output"
Block Library
A13872EJ5V0BL
3 - 52
Block Library
A13872EJ5V0BL
3 - 53
34
34
Chapter 3 Scan Path Block
Function
Chapter 3 Scan Path Block
NEC Scan D-F/F with SB
Block
type
Standard type
Block type
Normal
Drivability
Name
cells
x1
SE616
12
Q output
Name
cells
Name
cells
QB output
Name
cells
Name
cells
Name
SE616
C → QB
SB → Q
SB → QB
Set up time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
x4
x8
Logic Diagram for "Normal"
Truth Table for "Normal"
SB
H03
H01
D
N01
Q
SB
Q
QB
0
1
0
1
1
1
1
X
1
X
C H02
C → Q
cells
x2
D
IN
Path
→ OUT
N02
QB
C
X
0
(HH)
(HL)
(HH)
(HL)
(LH)
(LL)
D
D
SB
SB
C
SB
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.385
0.430
0.607
0.533
0.341
0.207
0.640
0.250
0.470
0.340
0.964
0.611
0.604
0.702
1.023
0.855
0.661
0.415
1.126
1.354
2.062
1.599
1.254
0.713
1.390
0.180
0.720
0.290
2.672
1.590
0.011
0.011
0.011
0.010
0.011
0.010
0.015
0.013
0.015
0.013
0.015
0.013
0.022
0.018
0.022
0.017
0.022
0.018
Symbol
D
C
SB
Output
Fanin Symbol Fanout
1.0
2.5
2.3
Q
QB
0
Hold
1
0
X:Irrelevant
Logic Diagram for "Q output"
Truth Table for "Q output"
Logic Diagram for "QB output"
Truth Table for "QB output"
Block Library
A13872EJ5V0BL
3 - 54
Block Library
A13872EJ5V0BL
3 - 55
34
33
Chapter 3 Scan Path Block
Function
Chapter 3 Scan Path Block
NEC Scan D-F/F with RB, SB
Block
type
Standard type
Block type
Normal
Drivability
Name
cells
x1
SE617
13
Q output
Name
cells
Name
cells
QB output
Name
cells
Name
cells
Name
SE617
C → QB
RB → Q
RB → QB
SB → Q
SB → QB
Set up time
Hold time
Release time
Release time
Removal time
Removal time
Min Pulse
Min Pulse
Min Pulse
x4
x8
Logic Diagram for "Normal"
Truth Table for "Normal"
SB
H04
D
N01 Q
C H02
N02 QB
H03
RB
C → Q
cells
x2
D H01
IN
Path
→ OUT
RB
SB
Q
QB
0
C
1
1
0
1
1
1
1
1
X
1
1
0
Hold
X
X
0
1
0
1
X
X
1
0
1
0
X
X
0
0
0
0
(HH)
(HL)
(HH)
(HL)
(LL)
(LH)
(LH)
(LL)
D
D
RB
SB
RB
SB
C
RB
SB
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.424
0.423
0.599
0.576
0.176
0.356
0.382
0.210
0.630
0.260
0.280
0.450
0.560
0.360
0.957
0.660
0.691
0.686
0.693
1.011
0.946
0.274
0.721
0.766
0.417
1.340
1.337
2.044
1.840
0.463
1.421
1.506
0.717
1.350
0.180
0.290
0.680
0.840
0.330
2.651
1.824
1.857
0.011
0.010
0.011
0.010
0.010
0.011
0.011
0.010
0.015
0.013
0.015
0.013
0.013
0.015
0.015
0.013
0.022
0.017
0.022
0.017
0.017
0.022
0.022
0.019
Symbol
D
C
RB
SB
Output
Fanin Symbol Fanout
1.0
2.5
2.4
2.2
Q
QB
← Prohibition
X:Irrelevant
Logic Diagram for "Q output"
Truth Table for "Q output"
Logic Diagram for "QB output"
Truth Table for "QB output"
Block Library
A13872EJ5V0BL
3 - 56
Block Library
A13872EJ5V0BL
3 - 57
34
32
Chapter 3 Scan Path Block
Function
Chapter 3 Scan Path Block
NEC Scan D-F/F (CB)
Block
type
Standard type
Block type
Normal
Drivability
Name
cells
x1
SE631
11
Q output
Name
cells
Name
cells
Name
QB output
cells
Name
cells
Name
SE631
CB → QB
Set up time
Hold time
Min Pulse
x4
x8
Logic Diagram for "Normal"
H01
CB H02
CB → Q
cells
x2
D
IN
Path
→ OUT
(LH)
(LL)
(LH)
(LL)
D
D
CB
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.412
0.405
0.516
0.561
0.610
0.270
0.958
0.681
0.659
0.854
0.933
1.304
1.254
1.655
1.780
1.150
0.250
2.297
0.011
0.010
0.011
0.010
0.015
0.013
0.015
0.013
0.021
0.017
0.021
0.018
Symbol
D
CB
Output
Fanin Symbol Fanout
1.0
2.3
Q
QB
Truth Table for "Normal"
N01
N02
Q
QB
D
Q
QB
0
0
1
1
1
X
CB
0
Hold
X:Irrelevant
Logic Diagram for "Q output"
Truth Table for "Q output"
Logic Diagram for "QB output"
Truth Table for "QB output"
Block Library
A13872EJ5V0BL
3 - 58
Block Library
A13872EJ5V0BL
3 - 59
35
35
Chapter 3 Scan Path Block
Function
Chapter 3 Scan Path Block
NEC Scan D-F/F (CB) with RB, SB
Block
type
Standard type
Block type
Normal
Drivability
Name
cells
x1
SE637
13
Q output
Name
cells
Name
cells
QB output
Name
cells
Name
cells
Name
SE637
CB → QB
RB → Q
RB → QB
SB → Q
SB → QB
Set up time
Hold time
Release time
Release time
Removal time
Removal time
Min Pulse
Min Pulse
Min Pulse
x4
x8
Logic Diagram for "Normal"
Truth Table for "Normal"
SB
H04
D
N01 Q
CB H02
N02 QB
H03
RB
CB → Q
cells
x2
D H01
IN
Path
→ OUT
RB
SB
Q
QB
0
CB
1
1
0
1
1
1
1
1
X
1
1
0
Hold
X
X
0
1
0
1
X
X
1
0
1
0
X
X
0
0
0
0
(LH)
(LL)
(LH)
(LL)
(LL)
(LH)
(LH)
(LL)
D
D
RB
SB
RB
SB
CB
RB
SB
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.453
0.418
0.593
0.604
0.176
0.356
0.381
0.210
0.650
0.290
0.280
0.450
0.550
0.370
0.994
0.660
0.692
0.762
0.684
1.002
1.021
0.274
0.720
0.766
0.417
1.513
1.313
2.023
2.011
0.463
1.419
1.506
0.717
1.440
0.260
0.240
0.760
0.920
0.330
2.534
1.823
1.858
0.011
0.010
0.011
0.010
0.010
0.011
0.011
0.010
0.015
0.013
0.015
0.013
0.013
0.015
0.015
0.013
0.022
0.017
0.022
0.017
0.017
0.022
0.022
0.019
Symbol
D
CB
RB
SB
Output
Fanin Symbol Fanout
1.0
2.5
2.4
2.2
Q
QB
← Prohibition
X:Irrelevant
Logic Diagram for "Q output"
Truth Table for "Q output"
Logic Diagram for "QB output"
Truth Table for "QB output"
Block Library
A13872EJ5V0BL
3 - 60
Block Library
A13872EJ5V0BL
3 - 61
34
32
Chapter 3 Scan Path Block
Chapter 3 Scan Path Block
[MEMO]
[MEMO]
Block Library
A13872EJ5V0BL
3 - 62
Block Library
A13872EJ5V0BL
3 - 63
Chapter 3 Scan Path Block
Chapter 3 Scan Path Block
[MEMO]
3.3
Scan Controller
Block Library
A13872EJ5V0BL
3 - 64
Block Library
A13872EJ5V0BL
3 - 65
Chapter 3 Scan Path Block
Chapter 3 Scan Path Block
Clock Distributor
Function
Block
type
Standard type
Block type
Normal
High speed
Drivability
Name
cells
x1
SCD1
8
Name
SCD1
IN
Path
→ OUT
CL → Y
cells
CL → Z
(HH)
(LL)
(HH)
(LL)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.215
0.224
0.214
0.223
0.327
0.365
0.326
0.364
0.590
0.684
0.589
0.683
0.011
0.010
0.011
0.010
0.015
0.013
0.015
0.013
0.022
0.019
0.022
0.019
Symbol
CL
Output
Fanin Symbol Fanout
2.1
Y
Z
x2
x4
x8
Logic Diagram
N01
Y
N02
Z
CL H01
Truth Table
CL
Y
Z
1
1
1
0
0
0
Y:Must be connected to the clock of Negative edge
triggered F/F or the gate of Low enable Latch
Z:Must be connected to the clock of Positice edge
triggered F/F or the gate of High enable Latch
Block Library
A13872EJ5V0BL
3 - 66
Block Library
A13872EJ5V0BL
3 - 67
34
34
Chapter 3 Scan Path Block
Chapter 3 Scan Path Block
Clock Distributor with Test (Positive Clock)
Function
Block
type
Standard type
Block type
Normal
High speed
Drivability
Name
cells
x1
SCDC
2
Name
SCDC
cells
IN
Path
→ OUT
CL → Y
(HH)
(LL)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.133
0.208
0.204
0.320
0.345
0.579
0.011
0.010
0.015
0.013
0.021
0.018
Symbol
CL
Output
Fanin Symbol Fanout
1.0
Y
x2
x4
x8
Logic Diagram
CL H01
N01
Y
Truth Table
CL
Y
1
1
0
0
Block Library
A13872EJ5V0BL
3 - 68
Block Library
A13872EJ5V0BL
3 - 69
35
Chapter 3 Scan Path Block
Chapter 3 Scan Path Block
Clock Distributor with Test (Negative Clock)
Function
Block
type
Standard type
Block type
Normal
High speed
Drivability
Name
cells
x1
SCDD
2
Name
SCDD
cells
IN
Path
→ OUT
CL → Y
(HH)
(LL)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.184
0.132
0.274
0.213
0.499
0.380
0.011
0.010
0.015
0.012
0.022
0.017
Symbol
CL
Output
Fanin Symbol Fanout
1.0
Y
x2
x4
x8
Logic Diagram
CL H01
N01
Y
Truth Table
CL
Y
1
1
0
0
Block Library
A13872EJ5V0BL
3 - 70
Block Library
A13872EJ5V0BL
3 - 71
34
Chapter 3 Scan Path Block
Chapter 3 Scan Path Block
I/F Control (AMC) with EN
Function
Block
type
Standard type
Block type
Normal
High speed
Drivability
Name
cells
x1
SFEH
3
Name
SFEH
cells
IN
Path
→ OUT
D → EN
(HH)
(LL)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.184
0.133
0.274
0.212
0.498
0.380
0.011
0.010
0.015
0.012
0.022
0.017
Symbol
D
Output
Fanin Symbol Fanout
1.0
EN
x2
x4
x8
Logic Diagram
D
H01
N01
EN
Truth Table
D
EN
1
1
0
0
Block Library
A13872EJ5V0BL
3 - 72
Block Library
A13872EJ5V0BL
3 - 73
34
Chapter 3 Scan Path Block
Chapter 3 Scan Path Block
I/F Control (AMC) with ENB
Function
Block
type
Standard type
Block type
Normal
High speed
Drivability
Name
cells
x1
SFEL
2
Name
SFEL
cells
IN
Path
→ OUT
D → ENB
(HH)
(LL)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.133
0.208
0.204
0.320
0.345
0.579
0.011
0.010
0.015
0.013
0.021
0.018
Symbol
D
Output
Fanin Symbol Fanout
1.0
ENB
x2
x4
x8
Logic Diagram
D
H01
N01
ENB
Truth Table
D
ENB
1
1
0
0
Block Library
A13872EJ5V0BL
3 - 74
Block Library
A13872EJ5V0BL
3 - 75
35
Chapter 3 Scan Path Block
Chapter 3 Scan Path Block
I/F Control (SMC) with EN
Function
Block
type
Standard type
Block type
Normal
High speed
Drivability
Name
cells
x1
SOEH
3
Name
SOEH
cells
IN
Path
→ OUT
D → EN
(HH)
(LL)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.184
0.133
0.274
0.212
0.498
0.380
0.011
0.010
0.015
0.012
0.022
0.017
Symbol
D
Output
Fanin Symbol Fanout
1.0
EN
x2
x4
x8
Logic Diagram
D
H01
N01
EN
Truth Table
D
EN
1
1
0
0
Block Library
A13872EJ5V0BL
3 - 76
Block Library
A13872EJ5V0BL
3 - 77
34
Chapter 3 Scan Path Block
Chapter 3 Scan Path Block
I/F Control (SMC) with ENB
Function
Block
type
Standard type
Block type
Normal
High speed
Drivability
Name
cells
x1
SOEL
2
Name
SOEL
cells
IN
Path
→ OUT
D → ENB
(HH)
(LL)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.133
0.208
0.204
0.320
0.345
0.579
0.011
0.010
0.015
0.013
0.021
0.018
Symbol
D
Output
Fanin Symbol Fanout
1.0
ENB
x2
x4
x8
Logic Diagram
D
H01
N01
ENB
Truth Table
D
ENB
1
1
0
0
Block Library
A13872EJ5V0BL
3 - 78
Block Library
A13872EJ5V0BL
3 - 79
35
Chapter 3 Scan Path Block
Chapter 3 Scan Path Block
Mega Macro Skip
Function
Block
type
Standard type
Block type
Normal
High speed
Drivability
Name
cells
x1
SMS1
4
Name
SMS1
cells
IN
Path
→ OUT
A → Y
(HH)
(LL)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.229
0.234
0.347
0.389
0.633
0.733
0.011
0.010
0.015
0.013
0.022
0.019
Symbol
A
B
Output
Fanin Symbol Fanout
1.0
1.0
Y
x2
x4
x8
Logic Diagram
A
H01
N01
Y
B H02
Truth Table
A
Y
1
1
0
0
Note:H02 is a pin of scan
Block Library
A13872EJ5V0BL
3 - 80
Block Library
A13872EJ5V0BL
3 - 81
34
Chapter 3 Scan Path Block
Chapter 3 Scan Path Block
Set/Reset Control
Function
Block
type
Standard type
Block type
Normal
High speed
Drivability
Name
cells
x1
SRH1
2
Name
SRH1
cells
IN
Path
→ OUT
SET → S
(HH)
(LL)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.184
0.132
0.274
0.213
0.499
0.380
0.011
0.010
0.015
0.012
0.022
0.017
Symbol
SET
Output
Fanin Symbol Fanout
1.0
S
x2
x4
x8
Logic Diagram
SET H01
N01
S
Truth Table
SET
S
1
1
0
0
Block Library
A13872EJ5V0BL
3 - 82
Block Library
A13872EJ5V0BL
3 - 83
34
Chapter 3 Scan Path Block
Chapter 3 Scan Path Block
Set-B/Reset-B Control
Function
Block
type
Standard type
Block type
Normal
High speed
Drivability
Name
cells
x1
SRL1
2
Name
SRL1
cells
IN
Path
→ OUT
SETB → S
(HH)
(LL)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.133
0.208
0.204
0.320
0.345
0.579
0.011
0.010
0.015
0.013
0.021
0.018
Symbol
SETB
Output
Fanin Symbol Fanout
1.0
S
x2
x4
x8
Logic Diagram
SETB H01
N01
S
Truth Table
SETB
S
1
1
0
0
Block Library
A13872EJ5V0BL
3 - 84
Block Library
A13872EJ5V0BL
3 - 85
35
Chapter 3 Scan Path Block
Chapter 3 Scan Path Block
Loop Cut
Function
Block
type
Standard type
Block type
Normal
High speed
Drivability
Name
cells
x1
SRPD
12
Name
SRPD
cells
IN
Path
→ OUT
RIN → ROUT
(HH)
(LL)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.312
0.329
0.471
0.545
0.864
1.011
0.011
0.011
0.015
0.014
0.022
0.020
Symbol
RIN
Output
Fanin Symbol Fanout
1.0
ROUT
x2
x4
x8
Logic Diagram
RIN H01
N01
ROUT
Truth Table
RIN
ROUT
1
1
0
0
Block Library
A13872EJ5V0BL
3 - 86
Block Library
A13872EJ5V0BL
3 - 87
33
Chapter 3 Scan Path Block
Chapter 3 Scan Path Block
Clock Generator
Function
Block
type
Standard type
Block type
Normal
High speed
Drivability
Name
cells
x1
SCKG
16
Name
IN
Path
→ OUT
Switching speed
t LD0 (ns)
MIN.
TYP.
MAX.
Input
t1
MIN.
TYP.
SCKG
MAX.
Symbol
CL
Output
Fanin Symbol Fanout
2.1
SC
cells
x2
x4
x8
Logic Diagram
CL H01
N01
SC
Truth Table
CL
SC
1
1
0
0
Block Library
A13872EJ5V0BL
3 - 88
Block Library
A13872EJ5V0BL
3 - 89
34
Chapter 3 Scan Path Block
Chapter 3 Scan Path Block
Common Input
Function
Block
type
Standard type
Block type
Normal
High speed
Drivability
Name
cells
x1
SCI1
2
Name
SCI1
cells
IN
Path
→ OUT
A → Y
(HH)
(LL)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.143
0.143
0.208
0.219
0.343
0.385
0.011
0.010
0.015
0.012
0.021
0.017
Symbol
A
Output
Fanin Symbol Fanout
1.0
Y
x2
x4
x8
Logic Diagram
A
H01
N01
Y
Truth Table
A
Y
1
1
0
0
Block Library
A13872EJ5V0BL
3 - 90
Block Library
A13872EJ5V0BL
3 - 91
35
Chapter 3 Scan Path Block
Chapter 3 Scan Path Block
Common Output
Function
Block
type
Standard type
Block type
Normal
High speed
Drivability
Name
cells
x1
SCO1
4
Name
SCO1
cells
IN
Path
→ OUT
A → Y
(HH)
(LL)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.228
0.234
0.346
0.388
0.633
0.732
0.011
0.010
0.015
0.013
0.022
0.019
Symbol
A
Output
Fanin Symbol Fanout
1.0
Y
x2
x4
x8
Logic Diagram
A
H01
N01
Y
Truth Table
A
Y
1
1
0
0
Block Library
A13872EJ5V0BL
3 - 92
Block Library
A13872EJ5V0BL
3 - 93
34
Chapter 3 Scan Path Block
Chapter 3 Scan Path Block
GND
Function
Block
type
Standard type
Block type
Normal
High speed
Drivability
Name
cells
x1
SGND
2
Name
IN
Path
→ OUT
Switching speed
t LD0 (ns)
MIN.
TYP.
MAX.
Input
t1
MIN.
TYP.
MAX.
Symbol
Output
Fanin Symbol Fanout
Y
SGND
cells
x2
x4
x8
Logic Diagram
N01
Y
Truth Table
Y
0
Block Library
A13872EJ5V0BL
3 - 94
Block Library
A13872EJ5V0BL
3 - 95
35
Chapter 4
Boundary Scan Block
4-1
Block Library
A13872EJ5V0BL
Chapter 4 Boundary Scan Block
Chapter 4 Boundary Scan Block
[MEMO]
4.1
TAP Macro
Block Library
A13872EJ5V0BL
4-2
Block Library
A13872EJ5V0BL
4-3
Chapter 4 Boundary Scan Block
Chapter 4 Boundary Scan Block
BScan TAP Macro
Function
Block
type
Standard type
Block type
-
-
Drivability
Name
cells
-
SBCJ
262
Name
IN
Path
→ OUT
Switching speed
t LD0 (ns)
MIN.
TYP.
MAX.
Input
t1
MIN.
TYP.
MAX.
Symbol
Output
Fanin Symbol Fanout
SBCJ
cells
Logic Diagram
SIN
TDI
TMS
TCK
TRB
H01
H02
H03
H04
H05
N01
N02
N03
N04
N05
N06
N07
N08
SOUT
TDO
SFDR
CLKDR
UPDDR
EN
MODE1
MODE2
Equivalent Circuit
SBD1
SOUT
SBS3
F111
SIN
SBM5
TDI
SBM6
F565
TDO
MODE1
MODE2
TMS
TCK
SFDR
CLKDR
UPDDR
EN
SBCK
TRB
Block Library
A13872EJ5V0BL
4-4
Block Library
A13872EJ5V0BL
4-5
Chapter 4 Boundary Scan Block
Chapter 4 Boundary Scan Block
BScan TAP Macro with NEC Scan
Function
Block
type
Standard type
Block type
-
-
Drivability
Name
cells
-
SBCL
315
Name
IN
Path
→ OUT
Switching speed
t LD0 (ns)
MIN.
TYP.
MAX.
Input
t1
MIN.
TYP.
MAX.
Symbol
Output
Fanin Symbol Fanout
SBCL
cells
Logic Diagram
BS_SOT
TDI
TMS
TCK
TRB
SC_SOT
H01
H02
H03
H04
H05
H06
N01
N02
N03
N04
N05
N06
N07
N08
N09
N10
N11
N12
N13
N14
N15
BS_SIN
TDO
SFDR
CLKDR
UPPDR
EN
MODE1
MODE2
AMC
SC_SIN
SMC
SMC2
SC1
SC2
MODE1S
Equivalent Circuit
F111
L565
BS_SOT
SC_SOT
SC_SIN
AMC
F111
SBD1
BS_SIN
F565
SBS3
TDO
SBM5
TDI
TMS
TCK
SFDR
SBCK
EN F212
L212
TRB
AMC
F091
MODE1
MODE2
AMC
AMC
MODE1S
SBMC
UPPDR
UPPDR
CLKDR
SMC2
L302
F202
SC1
L312
L312
L302
L101
L303
F302
SC2
F767
SMC2
AMC
F203
UPPDR
F747
SMC
F312
SMC2
SMC2
Block Library
L202
A13872EJ5V0BL
4-6
Block Library
A13872EJ5V0BL
4-7
Chapter 4 Boundary Scan Block
Chapter 4 Boundary Scan Block
[MEMO]
[MEMO]
Block Library
A13872EJ5V0BL
4-8
Block Library
A13872EJ5V0BL
4-9
Chapter 4 Boundary Scan Block
Chapter 4 Boundary Scan Block
[MEMO]
4.2
Level Generator
Block Library
A13872EJ5V0BL
4 - 10
Block Library
A13872EJ5V0BL
4 - 11
Chapter 4 Boundary Scan Block
Chapter 4 Boundary Scan Block
BScan Level Generator (CLANP)
Function
Block
type
Standard type
Block type
-
-
Drivability
Name
cells
-
SBZ1
1
Name
IN
Path
→ OUT
Switching speed
t LD0 (ns)
MIN.
TYP.
MAX.
Input
t1
MIN.
TYP.
MAX.
Symbol
Output
Fanin Symbol Fanout
L
SBZ1
152
cells
Logic Diagram
N01
L
Truth Table
L
0
Block Library
A13872EJ5V0BL
4 - 12
Block Library
A13872EJ5V0BL
4 - 13
Chapter 4 Boundary Scan Block
Chapter 4 Boundary Scan Block
[MEMO]
[MEMO]
Block Library
A13872EJ5V0BL
4 - 14
Block Library
A13872EJ5V0BL
4 - 15
Chapter 4 Boundary Scan Block
Chapter 4 Boundary Scan Block
[MEMO]
4.3
Data Register
Block Library
A13872EJ5V0BL
4 - 16
Block Library
A13872EJ5V0BL
4 - 17
Chapter 4 Boundary Scan Block
Chapter 4 Boundary Scan Block
BScan Data Register for Input
Function
Block
type
Standard type
Block type
-
-
Drivability
Name
cells
-
SVRNI2
12
Name
IN
Path
→ OUT
Switching speed
t LD0 (ns)
MIN.
TYP.
MAX.
Input
t1
MIN.
TYP.
MAX.
Symbol
Output
Fanin Symbol Fanout
SVRNI2
cells
Logic Diagram
SIN
PIN
SFDR
CLKDR
H01
H02
H03
H04
N01 SOUT
Equivalent Circuit
SBD1
SBR1
PIN
SIN
SFDR
SOUT
CLKDR
Block Library
A13872EJ5V0BL
4 - 18
Block Library
A13872EJ5V0BL
4 - 19
Chapter 4 Boundary Scan Block
Chapter 4 Boundary Scan Block
BScan Data Register for Output
Function
Block
type
Standard type
Block type
-
-
Drivability
Name
cells
-
SVRN22
24
Name
IN
Path
→ OUT
Switching speed
t LD0 (ns)
MIN.
TYP.
MAX.
Input
t1
MIN.
TYP.
MAX.
Symbol
Output
Fanin Symbol Fanout
SVRN22
cells
Logic Diagram
SIN
PIN
SFDR
CLKDR
UPDDR
MODE1
H01
H02
H03
H04
H05
H06
N01 SOUT
N02 POUT
Equivalent Circuit
SOUT
SBD1
SBR1
PIN
SIN
SFDR
SVSNA2
F601NQ
POUT
CLKDR
UPDDR
MODE1
Block Library
A13872EJ5V0BL
4 - 20
Block Library
A13872EJ5V0BL
4 - 21
Chapter 4 Boundary Scan Block
Chapter 4 Boundary Scan Block
BScan Data Register for 3-state
Function
Block
type
Standard type
Block type
-
-
Drivability
Name
cells
-
SVRN32
50
Name
IN
Path
→ OUT
Switching speed
t LD0 (ns)
MIN.
TYP.
MAX.
Input
t1
MIN.
TYP.
MAX.
Symbol
Output
Fanin Symbol Fanout
SVRN32
cells
Logic Diagram
SIN
PIN
ENIN
SFDR
CLKDR
UPDDR
MODE1
MODE2
H01
H02
H03
H04
H05
H06
H07
H08
N01 SOUT
N02 POUT
N03 ENOUT
Equivalent Circuit
SOUT
PIN
ENIN
SIN
SFDR
CLKDR
UPDDR
MODE1
MODE2
SBD1
SBR1
SVSNA2
F601NQ
SBD1
SBR1
F601NQ
Block Library
A13872EJ5V0BL
POUT
SVSNC2
ENOUT
4 - 22
Block Library
A13872EJ5V0BL
4 - 23
Chapter 4 Boundary Scan Block
Chapter 4 Boundary Scan Block
BScan Data Register for Bid
Function
Block
type
Standard type
Block type
-
-
Drivability
Name
cells
-
SVRNB2
57
Name
IN
Path
→ OUT
Switching speed
t LD0 (ns)
MIN.
TYP.
MAX.
Input
t1
MIN.
TYP.
MAX.
Symbol
Output
Fanin Symbol Fanout
SVRNB2
cells
Logic Diagram
SIN
PIN
ENIN
ININ
SFDR
CLKDR
UPDDR
MODE1
MODE2
H01
H02
H03
H04
H05
H06
H07
H08
H09
N01 SOUT
N02 POUT
N03 ENOUT
Equivalent Circuit
PIN
ININ
SOUT
SBD1
SBD1
SBR1
L101 L312
F601NQ
SVSNB2
POUT
ENIN
SBD1
SBR1
F601NQ
SIN
SFDR
CLKDR
UPDDR
MODE1
MODE2
Block Library
A13872EJ5V0BL
SVSNE2
ENOUT
4 - 24
Block Library
A13872EJ5V0BL
4 - 25
Chapter 4 Boundary Scan Block
Chapter 4 Boundary Scan Block
[MEMO]
[MEMO]
Block Library
A13872EJ5V0BL
4 - 26
Block Library
A13872EJ5V0BL
4 - 27
Chapter 4 Boundary Scan Block
Chapter 4 Boundary Scan Block
[MEMO]
4.4
D-latch, Selector, Shift Register
Block Library
A13872EJ5V0BL
4 - 28
Block Library
A13872EJ5V0BL
4 - 29
Chapter 4 Boundary Scan Block
Chapter 4 Boundary Scan Block
BScan D-Latch with SB Q Out, Low Power
Function
Block
type
Standard type
Block type
-
-
Drivability
Name
cells
-
L606
5
Name
L606
IN
Path
→ OUT
D → Q
cells
C → Q
-
SB → Q
Logic Diagram
Set up time
Hold time
Release time
Removal time
Min Pulse
Min Pulse
SB
H03
D
H01
N01
(HH)
(LL)
(HH)
(HL)
(HL)
(LH)
D
D
SB
SB
C
SB
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.193
0.240
0.304
0.394
0.289
0.205
0.460
0.370
0.430
0.380
0.527
0.433
0.314
0.409
0.480
0.658
0.468
0.331
0.581
0.834
0.870
1.256
0.852
0.603
0.610
0.400
0.540
0.340
1.581
1.135
0.022
0.020
0.022
0.020
0.020
0.022
0.030
0.026
0.030
0.026
0.026
0.030
0.042
0.036
0.042
0.036
0.036
0.043
Symbol
D
C
SB
Output
Fanin Symbol Fanout
3.9
1.0
1.0
Q
Q
C H02
Truth Table
D
C
SB
Q
1
0
1
1
0
0
1
0
X
1
1
Latch
X
X
0
1
X:Irrelevant
Block Library
A13872EJ5V0BL
4 - 30
Block Library
A13872EJ5V0BL
4 - 31
16
Chapter 4 Boundary Scan Block
Chapter 4 Boundary Scan Block
BScan Selector
Function
Block
type
Standard type
Block type
-
-
Drivability
Name
cells
-
SBD1
4
Name
SBD1
IN
Path
→ OUT
A → Y
cells
B → Y
-
MODE1 → Y
Logic Diagram
A
(HH)
(LL)
(HH)
(LL)
(HH)
(HL)
(LH)
(LL)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.218
0.232
0.222
0.237
0.258
0.267
0.231
0.271
0.335
0.384
0.340
0.390
0.420
0.416
0.374
0.454
0.606
0.724
0.614
0.733
0.784
0.734
0.700
0.863
0.021
0.020
0.021
0.020
0.021
0.020
0.021
0.020
0.029
0.025
0.029
0.025
0.029
0.025
0.029
0.025
0.042
0.034
0.042
0.034
0.042
0.034
0.042
0.034
Symbol
A
B
MODE1
Output
Fanin Symbol Fanout
1.0
1.0
1.0
Y
H01
N01
Y
B H02
MODE1 H03
Truth Table
A
B
MODE1
Y
A
X
0
A
X
B
1
B
X : Irrelevant
Block Library
A13872EJ5V0BL
4 - 32
Block Library
A13872EJ5V0BL
4 - 33
16
Chapter 4 Boundary Scan Block
Chapter 4 Boundary Scan Block
BScan Shift Register
Function
Block
type
Standard type
Block type
-
-
Drivability
Name
cells
-
SBR1
8
Name
SBR1
C → Q
(LH)
(LL)
(HH)
(HL)
cells
C → U
-
Set up time
Hold time
Min Pulse
Logic Diagram
D
IN
Path
→ OUT
H01
N01
Q
C H02
N02
U
D
D
C
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.345
0.317
0.503
0.494
0.270
0.650
0.672
0.586
0.521
0.824
0.785
1.126
0.993
1.549
1.440
0.160
1.200
1.900
0.020
0.019
0.022
0.020
0.028
0.023
0.030
0.025
0.038
0.031
0.042
0.035
Symbol
D
C
Output
Fanin Symbol Fanout
3.8
1.0
Q
U
Truth Table
D
Q
U
A
C
A
Hold
B
Hold
B
X : Irrelevant
Block Library
A13872EJ5V0BL
4 - 34
Block Library
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4 - 35
15
13
Chapter 4 Boundary Scan Block
Chapter 4 Boundary Scan Block
BScan Data Selector for Output
Function
Block
type
Standard type
Block type
-
-
Drivability
Name
cells
-
SVSNA2
7
Name
SVSNA2
IN
Path
→ OUT
PIN → POUT
cells
BSCAN → POUT
-
MODE1 → POUT
Logic Diagram
(HH)
(LL)
(HH)
(LL)
(HH)
(HL)
(LH)
(LL)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.169
0.170
0.290
0.296
0.318
0.318
0.260
0.276
0.270
0.286
0.438
0.487
0.513
0.519
0.414
0.459
0.496
0.558
0.802
0.926
0.962
0.972
0.768
0.876
0.006
0.005
0.006
0.006
0.006
0.006
0.006
0.005
0.008
0.007
0.008
0.007
0.008
0.007
0.008
0.007
0.011
0.009
0.011
0.010
0.011
0.010
0.011
0.009
Symbol
PIN
BSCAN
MODE1
Output
Fanin Symbol Fanout
4.1
1.0
1.0
POUT
PIN H01
BSCON POUT
BSCAN H02
MODE1 H03
Truth Table
PIN
BSCAN
MODE1
POUT
A
X
0
A
X
B
1
B
X : Irrelevant
Block Library
A13872EJ5V0BL
4 - 36
Block Library
A13872EJ5V0BL
4 - 37
65
Chapter 4 Boundary Scan Block
Chapter 4 Boundary Scan Block
BScan Data Selector for Bid
Function
Block
type
Standard type
Block type
-
-
Drivability
Name
cells
-
SVSNB2
7
Name
SVSNB2
IN
Path
→ OUT
PIN → POUT
cells
PIN → Z1
-
BSCAN → POUT
Logic Diagram
BSCAN → Z1
MODE1 → POUT
PIN H01
BSCON POUT
MODE1 → Z1
BSCAN H02
N02
Z1
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(HL)
(LH)
(LL)
(HH)
(HL)
(LH)
(LL)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.185
0.184
0.205
0.226
0.311
0.320
0.332
0.374
0.339
0.339
0.276
0.290
0.361
0.398
0.295
0.332
0.294
0.310
0.334
0.392
0.473
0.527
0.522
0.637
0.546
0.556
0.439
0.483
0.597
0.671
0.479
0.565
0.540
0.606
0.631
0.782
0.870
1.005
0.992
1.242
1.028
1.051
0.816
0.922
1.150
1.294
0.906
1.098
0.006
0.005
0.021
0.020
0.006
0.006
0.021
0.020
0.006
0.006
0.006
0.005
0.022
0.020
0.021
0.020
0.008
0.007
0.029
0.025
0.008
0.007
0.030
0.025
0.008
0.007
0.008
0.007
0.030
0.025
0.029
0.025
0.011
0.009
0.042
0.033
0.011
0.011
0.042
0.034
0.011
0.011
0.011
0.009
0.042
0.034
0.042
0.033
Symbol
PIN
BSCAN
MODE1
Output
Fanin Symbol Fanout
4.1
1.0
1.0
POUT
Z1
MODE1 H03
Truth Table
PIN
BSCAN
MODE1
POUT
Z1
A
X
0
A
A
X
B
1
B
B
X : Irrelevant
Block Library
A13872EJ5V0BL
4 - 38
Block Library
A13872EJ5V0BL
4 - 39
64
15
Chapter 4 Boundary Scan Block
Chapter 4 Boundary Scan Block
BScan Data Enable Selector for 3-state
Function
Block
type
Standard type
Block type
-
-
Drivability
Name
cells
-
SVSNC2
9
Name
SVSNC2
cells
Logic Diagram
ENIN H01
IN
Path
→ OUT
ENIN → ENOUT (HH)
(LL)
BSCAN → ENOUT (HH)
(LL)
MODE1 → ENOUT (HH)
(HL)
(LH)
(LL)
MODE2 → ENOUT (HL)
(LH)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.201
0.188
0.325
0.309
0.353
0.334
0.291
0.294
0.083
0.081
0.329
0.322
0.499
0.518
0.574
0.553
0.472
0.495
0.120
0.122
0.625
0.634
0.934
0.999
1.094
1.050
0.896
0.950
0.180
0.235
0.009
0.005
0.009
0.006
0.009
0.006
0.009
0.005
0.005
0.009
0.013
0.007
0.013
0.008
0.013
0.008
0.013
0.007
0.006
0.013
0.020
0.010
0.020
0.011
0.020
0.011
0.019
0.010
0.008
0.020
Symbol
ENIN
BSCAN
MODE1
MODE2
Output
Fanin Symbol Fanout
4.1
1.0
1.0
4.2
ENOUT
BSCON ENOUT
BSCAN H02
MODE1 H03
MODE2 H04
Truth Table
ENIN
BSCAN
MODE1
MODE2
ENOUT
A
X
0
0
A
X
B
1
0
B
X
X
X
1
0
X : Irrelevant
Block Library
A13872EJ5V0BL
4 - 40
Block Library
A13872EJ5V0BL
4 - 41
33
Chapter 4 Boundary Scan Block
Chapter 4 Boundary Scan Block
BScan Data Enable Selector for Bid
Function
Block
type
Standard type
Block type
-
-
Drivability
Name
cells
-
SVSNE2
9
Name
SVSNE2
cells
Logic Diagram
ENIN H01
BSCON ENOUT
BSCAN H02
N02
Z2
MODE1 H03
IN
Path
→ OUT
ENIN → ENOUT (HH)
(LL)
(HH)
ENIN → Z2
(LL)
BSCAN → ENOUT (HH)
(LL)
(HH)
BSCAN → Z2
(LL)
MODE1 → ENOUT (HH)
(HL)
(LH)
(LL)
(HH)
MODE1 → Z2
(HL)
(LH)
(LL)
(HL)
MODE2 → ENOUT
(LH)
Switching speed
t LD0 (ns)
Input
t1
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.217
0.201
0.198
0.206
0.349
0.333
0.322
0.341
0.376
0.354
0.308
0.308
0.350
0.365
0.288
0.313
0.083
0.081
0.353
0.345
0.326
0.380
0.537
0.557
0.510
0.616
0.610
0.589
0.498
0.518
0.584
0.649
0.471
0.553
0.120
0.122
0.671
0.685
0.603
0.738
1.010
1.080
0.948
1.174
1.167
1.129
0.946
1.000
1.105
1.224
0.878
1.054
0.180
0.234
0.009
0.006
0.021
0.020
0.009
0.006
0.022
0.020
0.009
0.006
0.009
0.006
0.022
0.020
0.021
0.020
0.005
0.009
0.013
0.007
0.030
0.025
0.013
0.008
0.030
0.026
0.013
0.008
0.013
0.007
0.030
0.026
0.030
0.025
0.006
0.013
0.019
0.010
0.042
0.034
0.019
0.012
0.043
0.037
0.019
0.012
0.019
0.010
0.043
0.037
0.042
0.034
0.008
0.020
Symbol
ENIN
BSCAN
MODE1
MODE2
Output
Fanin Symbol Fanout
4.1
1.0
1.0
4.2
ENOUT
Z2
MODE2 H04
Truth Table
ENIN
BSCAN
MODE1
MODE2
ENOUT
Z2
A
X
0
0
A
A
X
B
1
0
B
B
A
X
0
1
0
A
X
B
1
1
0
B
X : Irrelevant
Block Library
A13872EJ5V0BL
4 - 42
Block Library
A13872EJ5V0BL
4 - 43
32
15
Chapter 4 Boundary Scan Block
Chapter 4 Boundary Scan Block
[MEMO]
[MEMO]
Block Library
A13872EJ5V0BL
4 - 44
Block Library
A13872EJ5V0BL
4 - 45
Chapter 4 Boundary Scan Block
Chapter 4 Boundary Scan Block
[MEMO]
4.5
Soft Macro
Block Library
A13872EJ5V0BL
4 - 46
Block Library
A13872EJ5V0BL
4 - 47
Chapter 4 Boundary Scan Block
Chapter 4 Boundary Scan Block
BScan TAP Controller
Function
Block
type
Standard type
Block type
-
-
Drivability
Name
cells
-
SBCK
392
Name
IN
Path
→ OUT
Switching speed
t LD0 (ns)
MIN.
TYP.
MAX.
Input
t1
MIN.
TYP.
MAX.
Symbol
Output
Fanin Symbol Fanout
SBCK
cells
Logic Diagram
TMS H01
N01
N02
N03
N04
N05
N06
N07
N08
N09
TCK H02
TRB H03
SFIR
CLKIR
UPDIR
SFDR
CLKDR
UPDDR
SEL
EN
RB
Equivalent Circuit
TMS
F101
L303
F111
L302
F111
L304
TRB
L304
F615
RB
L302
F111
L303
SEL
F616
L303
L302
L302
L303
F615
EN
F306
F616
L303
F615
L303
F616
L304
SFIR
F304
F304
L302
L302
CLKIR
F616
L303
F315
UPDIR
L302
F615
F101
L302
L302
L304
F101
F111
F132
L304
SFDR
TCK
L303
F132
F132
F132
F304
F304
CLKDR
F315
UPDDR
Block Library
A13872EJ5V0BL
4 - 48
Block Library
A13872EJ5V0BL
4 - 49
Chapter 4 Boundary Scan Block
Chapter 4 Boundary Scan Block
BScan Instruction Register (Internal Circuit)
Function
Block
type
Standard type
Block type
-
-
Drivability
Name
cells
-
SBM4
46
Name
IN
Path
→ OUT
Switching speed
t LD0 (ns)
MIN.
TYP.
MAX.
Input
t1
MIN.
TYP.
MAX.
Symbol
Output
Fanin Symbol Fanout
SBM4
cells
Logic Diagram
SIN
SFIR
CLKIR
UPDIR
CLAMP
RB
H01
H02
H03
H04
H05
H06
N01 SOUT
N02 IR
Equivalent Circuit
SOUT
SBD1
RB
SBR1
L606
CLAMP
SIN
IR
SFIR
CLRIR
UPDIR
Block Library
A13872EJ5V0BL
4 - 50
Block Library
A13872EJ5V0BL
4 - 51
Chapter 4 Boundary Scan Block
Chapter 4 Boundary Scan Block
BScan Instruction Register
Function
Block
type
Standard type
Block type
-
-
Drivability
Name
cells
-
SBM5
140
Name
IN
Path
→ OUT
Switching speed
t LD0 (ns)
MIN.
TYP.
MAX.
Input
t1
MIN.
TYP.
MAX.
Symbol
Output
Fanin Symbol Fanout
SBM5
cells
Logic Diagram
SIN
SFIR
CLKIR
UPDIR
RB
H01
H02
H03
H04
H05
N01
N02
N03
N04
SOUT
IR1
IR2
IR3
Equivalent Circuit
IR3
IR2
IR1
SOUT
SIN
SBM4
SBM4
SFIR
CLKIR
UPDIR
RB
SBM4
F091
Block Library
A13872EJ5V0BL
4 - 52
Block Library
A13872EJ5V0BL
4 - 53
Chapter 4 Boundary Scan Block
Chapter 4 Boundary Scan Block
BScan Instruction Decoder
Function
Block
type
Standard type
Block type
-
-
Drivability
Name
cells
-
SBM6
24
Name
IN
Path
→ OUT
Switching speed
t LD0 (ns)
MIN.
TYP.
MAX.
Input
t1
MIN.
TYP.
MAX.
Symbol
Output
Fanin Symbol Fanout
SBM6
cells
Logic Diagram
BIT1 H01
BIT2 H02
BIT3 H03
N01 MODE1
N02 MODE2
N03 SELECT
Equivalent Circuit
L101
L303
L101
BIT3
MODE1
L101
L302
BIT2
SELECT
L101
BIT1
L303
L313
MODE2
Block Library
A13872EJ5V0BL
4 - 54
Block Library
A13872EJ5V0BL
4 - 55
Chapter 4 Boundary Scan Block
Chapter 4 Boundary Scan Block
BScan Instruction Decoder with NEC Scan
Function
Block
type
Standard type
Block type
-
-
Drivability
Name
cells
-
SBMC
37
Name
IN
Path
→ OUT
Switching speed
t LD0 (ns)
MIN.
TYP.
MAX.
Input
t1
MIN.
TYP.
MAX.
Symbol
Output
Fanin Symbol Fanout
SBMC
cells
Logic Diagram
BIT1 H01
BIT2 H02
BIT3 H03
N01
N02
N03
N04
N05
MODE1
MODE2
SELECT
AMC
MODE1S
Equivalent Circuit
L101
L101
BIT3
MODE1
L303
L302
L101
MODE1S
BIT2
L101
BIT1
SELECT
L303
L303
L303
L302
MODE2
L303
F101
AMC
Block Library
A13872EJ5V0BL
4 - 56
Block Library
A13872EJ5V0BL
4 - 57
Chapter 4 Boundary Scan Block
Chapter 4 Boundary Scan Block
BScan Bypass Register
Function
Block
type
Standard type
Block type
-
-
Drivability
Name
cells
-
SBS3
26
Name
IN
Path
→ OUT
Switching speed
t LD0 (ns)
MIN.
TYP.
MAX.
Input
t1
MIN.
TYP.
MAX.
Symbol
Output
Fanin Symbol Fanout
SBS3
cells
Logic Diagram
SIN H01
SFDR H02
CLKDR H03
N01 SOUT
Equivalent Circuit
L312
SBR1
SIN
SOUT
SFDR
CLKDR
Block Library
A13872EJ5V0BL
4 - 58
Block Library
A13872EJ5V0BL
4 - 59
Index
Block
Function
Cells (I/O)
Page
B001
I/O Buffer 12mA
20 (1)
1-28
B002
I/O Buffer 12mA
20 (1)
1-72
B003
I/O Buffer 9mA
10 (1)
1-28
B004
I/O Buffer 9mA
10 (1)
1-72
B005
I/O Buffer 18mA
20 (1)
1-28
B006
I/O Buffer 18mA
20 (1)
1-72
B007
3-State Buffer 12mA
17 (1)
1-16
B008
3-State Buffer 9mA
7 (1)
1-16
B009
3-State Buffer 18mA
17 (1)
1-16
B00C
I/O Buffer 6mA
10 (1)
1-28
B00D
I/O Buffer 6mA
10 (1)
1-72
B00E
3-State Buffer 6mA
7 (1)
1-16
B00F
I/O Buffer 24mA
20 (1)
1-28
B00G
I/O Buffer 24mA
20 (1)
1-72
B00H
3-State Buffer 24mA
17 (1)
1-16
B00T
3-State Buffer 3mA
7 (1)
1-16
B00U
I/O Buffer 3mA
10 (1)
1-28
B00V
I/O Buffer 3mA
10 (1)
1-72
B0D1
I/O Buffer 12mA 50kΩ Pull-down
20 (1)
1-28
B0D2
I/O Buffer 12mA 50kΩ Pull-down
20 (1)
1-72
B0D3
I/O Buffer 9mA 50kΩ Pull-down
10 (1)
1-28
B0D4
I/O Buffer 9mA 50kΩ Pull-down
10 (1)
1-72
B0D5
I/O Buffer 18mA 50kΩ Pull-down
20 (1)
1-28
B0D6
I/O Buffer 18mA 50kΩ Pull-down
20 (1)
1-72
B0D7
3-State Buffer 12mA 50kΩ Pull-down
17 (1)
1-16
B0D8
3-State Buffer 9mA 50kΩ Pull-down
7 (1)
1-16
B0D9
3-State Buffer 18mA 50kΩ Pull-down
17 (1)
1-16
B0DC
I/O Buffer 6mA 50kΩ Pull-down
10 (1)
1-28
B0DD
I/O Buffer 6mA 50kΩ Pull-down
10 (1)
1-72
B0DE
3-State Buffer 6mA 50kΩ Pull-down
7 (1)
1-16
B0DF
I/O Buffer 24mA 50kΩ Pull-down
20 (1)
1-28
B0DG
I/O Buffer 24mA 50kΩ Pull-down
20 (1)
1-72
B0DH
3-State Buffer 24mA 50kΩ Pull-down
17 (1)
1-16
B0DT
3-State Buffer 3mA 50kΩ Pull-down
7 (1)
1-16
B0DU
I/O Buffer 3mA 50kΩ Pull-down
10 (1)
1-28
B0DV
I/O Buffer 3mA 50kΩ Pull-down
10 (1)
1-72
B0U1
I/O Buffer 12mA 50kΩ Pull-up
20 (1)
1-28
B0U2
I/O Buffer 12mA 50kΩ Pull-up
20 (1)
1-72
B0U3
I/O Buffer 9mA 50kΩ Pull-up
10 (1)
1-28
B0U4
I/O Buffer 9mA 50kΩ Pull-up
10 (1)
1-72
B0U5
I/O Buffer 18mA 50kΩ Pull-up
20 (1)
1-28
Index-1
Block Library A13872EJ5V0BL
Block
Function
Cells (I/O)
Page
B0U6
I/O Buffer 18mA 50kΩ Pull-up
20 (1)
1-72
B0U7
3-State Buffer 12mA 50kΩ Pull-up
17 (1)
1-16
B0U8
3-State Buffer 9mA 50kΩ Pull-up
7 (1)
1-16
B0U9
3-State Buffer 18mA 50kΩ Pull-up
17 (1)
1-16
B0UC
I/O Buffer 6mA 50kΩ Pull-up
10 (1)
1-28
B0UD
I/O Buffer 6mA 50kΩ Pull-up
10 (1)
1-72
B0UE
3-State Buffer 6mA 50kΩ Pull-up
7 (1)
1-16
B0UF
I/O Buffer 24mA 50kΩ Pull-up
20 (1)
1-28
B0UG
I/O Buffer 24mA 50kΩ Pull-up
20 (1)
1-72
B0UH
3-State Buffer 24mA 50kΩ Pull-up
17 (1)
1-16
B0UT
3-State Buffer 3mA 50kΩ Pull-up
7 (1)
1-16
B0UU
I/O Buffer 3mA 50kΩ Pull-up
10 (1)
1-28
B0UV
I/O Buffer 3mA 50kΩ Pull-up
10 (1)
1-72
B0W1
I/O Buffer 12mA 5kΩ Pull-up
20 (1)
1-28
B0W2
I/O Buffer 12mA 5kΩ Pull-up
20 (1)
1-72
B0W3
I/O Buffer 9mA 5kΩ Pull-up
10 (1)
1-28
B0W4
I/O Buffer 9mA 5kΩ Pull-up
10 (1)
1-72
B0W5
I/O Buffer 18mA 5kΩ Pull-up
20 (1)
1-28
B0W6
I/O Buffer 18mA 5kΩ Pull-up
20 (1)
1-72
B0W7
3-State Buffer 12mA 5kΩ Pull-up
17 (1)
1-16
B0W8
3-State Buffer 9mA 5kΩ Pull-up
7 (1)
1-16
B0W9
3-State Buffer 18mA 5kΩ Pull-up
17 (1)
1-16
B0WC
I/O Buffer 6mA 5kΩ Pull-up
10 (1)
1-28
B0WD
I/O Buffer 6mA 5kΩ Pull-up
10 (1)
1-72
B0WE
3-State Buffer 6mA 5kΩ Pull-up
7 (1)
1-16
B0WF
I/O Buffer 24mA 5kΩ Pull-up
20 (1)
1-28
B0WG
I/O Buffer 24mA 5kΩ Pull-up
20 (1)
1-72
B0WH
3-State Buffer 24mA 5kΩ Pull-up
17 (1)
1-16
B0WT
3-State Buffer 3mA 5kΩ Pull-up
7 (1)
1-16
B0WU
I/O Buffer 3mA 5kΩ Pull-up
10 (1)
1-28
B0WV
I/O Buffer 3mA 5kΩ Pull-up
10 (1)
1-72
BE01
Low-noise I/O Buffer 12mA
10 (1)
1-34
BE02
Low-noise I/O Buffer 12mA
10 (1)
1-78
BE03
Low-noise I/O Buffer 9mA
10 (1)
1-34
BE04
Low-noise I/O Buffer 9mA
10 (1)
1-78
BE05
Low-noise I/O Buffer 18mA
10 (1)
1-34
BE06
Low-noise I/O Buffer 18mA
10 (1)
1-78
BE07
Low-noise 3-State Buffer 12mA
7 (1)
1-20
BE08
Low-noise 3-State Buffer 9mA
7 (1)
1-20
BE09
Low-noise 3-State Buffer 18mA
7 (1)
1-20
BE0C
Low-noise I/O Buffer 6mA
10 (1)
1-34
BE0D
Low-noise I/O Buffer 6mA
10 (1)
1-78
BE0E
Low-noise 3-State Buffer 6mA
7 (1)
1-20
Block Library A13872EJ5V0BL
Index-2
Block
Function
Cells (I/O)
Page
BE0F
Low-noise I/O Buffer 24mA
10 (1)
1-34
BE0G
Low-noise I/O Buffer 24mA
10 (1)
1-78
BE0H
Low-noise 3-State Buffer 24mA
7 (1)
1-20
BE0T
Low-noise 3-State Buffer 3mA
7 (1)
1-20
BE0U
Low-noise I/O Buffer 3mA
10 (1)
1-34
BE0V
Low-noise I/O Buffer 3mA
10 (1)
1-78
BED1
Low-noise I/O Buffer 12mA 50kΩ Pull-down
10 (1)
1-34
BED2
Low-noise I/O Buffer 12mA 50kΩ Pull-down
10 (1)
1-78
BED3
Low-noise I/O Buffer 9mA 50kΩ Pull-down
10 (1)
1-34
BED4
Low-noise I/O Buffer 9mA 50kΩ Pull-down
10 (1)
1-78
BED5
Low-noise I/O Buffer 18mA 50kΩ Pull-down
10 (1)
1-34
BED6
Low-noise I/O Buffer 18mA 50kΩ Pull-down
10 (1)
1-78
BED7
Low-noise 3-State Buffer 12mA 50kΩ Pull-down
7 (1)
1-20
BED8
Low-noise 3-State Buffer 9mA 50kΩ Pull-down
7 (1)
1-20
BED9
Low-noise 3-State Buffer 18mA 50kΩ Pull-down
7 (1)
1-20
BEDC
Low-noise I/O Buffer 6mA 50kΩ Pull-down
10 (1)
1-34
BEDD
Low-noise I/O Buffer 6mA 50kΩ Pull-down
10 (1)
1-78
BEDE
Low-noise 3-State Buffer 6mA 50kΩ Pull-down
7 (1)
1-20
BEDF
Low-noise I/O Buffer 24mA 50kΩ Pull-down
10 (1)
1-34
BEDG
Low-noise I/O Buffer 24mA 50kΩ Pull-down
10 (1)
1-78
BEDH
Low-noise 3-State Buffer 24mA 50kΩ Pull-down
7 (1)
1-20
BEDT
Low-noise 3-State Buffer 3mA 50kΩ Pull-down
7 (1)
1-20
BEDU
Low-noise I/O Buffer 3mA 50kΩ Pull-down
10 (1)
1-34
BEDV
Low-noise I/O Buffer 3mA 50kΩ Pull-down
10 (1)
1-78
BEU1
Low-noise I/O Buffer 12mA 50kΩ Pull-up
10 (1)
1-34
BEU2
Low-noise I/O Buffer 12mA 50kΩ Pull-up
10 (1)
1-78
BEU3
Low-noise I/O Buffer 9mA 50kΩ Pull-up
10 (1)
1-34
BEU4
Low-noise I/O Buffer 9mA 50kΩ Pull-up
10 (1)
1-78
BEU5
Low-noise I/O Buffer 18mA 50kΩ Pull-up
10 (1)
1-34
BEU6
Low-noise I/O Buffer 18mA 50kΩ Pull-up
10 (1)
1-78
BEU7
Low-noise 3-State Buffer 12mA 50kΩ Pull-up
7 (1)
1-20
BEU8
Low-noise 3-State Buffer 9mA 50kΩ Pull-up
7 (1)
1-20
BEU9
Low-noise 3-State Buffer 18mA 50kΩ Pull-up
7 (1)
1-20
BEUC
Low-noise I/O Buffer 6mA 50kΩ Pull-up
10 (1)
1-34
BEUD
Low-noise I/O Buffer 6mA 50kΩ Pull-up
10 (1)
1-78
BEUE
Low-noise 3-State Buffer 6mA 50kΩ Pull-up
7 (1)
1-20
BEUF
Low-noise I/O Buffer 24mA 50kΩ Pull-up
10 (1)
1-34
BEUG
Low-noise I/O Buffer 24mA 50kΩ Pull-up
10 (1)
1-78
BEUH
Low-noise 3-State Buffer 24mA 50kΩ Pull-up
7 (1)
1-20
BEUT
Low-noise 3-State Buffer 3mA 50kΩ Pull-up
7 (1)
1-20
BEUU
Low-noise I/O Buffer 3mA 50kΩ Pull-up
10 (1)
1-34
BEUV
Low-noise I/O Buffer 3mA 50kΩ Pull-up
10 (1)
1-78
BEW1
Low-noise I/O Buffer 12mA 5kΩ Pull-up
10 (1)
1-34
Index-3
Block Library A13872EJ5V0BL
Block
Function
Cells (I/O)
Page
BEW2
Low-noise I/O Buffer 12mA 5kΩ Pull-up
10 (1)
1-78
BEW3
Low-noise I/O Buffer 9mA 5kΩ Pull-up
10 (1)
1-34
BEW4
Low-noise I/O Buffer 9mA 5kΩ Pull-up
10 (1)
1-78
BEW5
Low-noise I/O Buffer 18mA 5kΩ Pull-up
10 (1)
1-34
BEW6
Low-noise I/O Buffer 18mA 5kΩ Pull-up
10 (1)
1-78
BEW7
Low-noise 3-State Buffer 12mA 5kΩ Pull-up
7 (1)
1-20
BEW8
Low-noise 3-State Buffer 9mA 5kΩ Pull-up
7 (1)
1-20
BEW9
Low-noise 3-State Buffer 18mA 5kΩ Pull-up
7 (1)
1-20
BEWC
Low-noise I/O Buffer 6mA 5kΩ Pull-up
10 (1)
1-34
BEWD
Low-noise I/O Buffer 6mA 5kΩ Pull-up
10 (1)
1-78
BEWE
Low-noise 3-State Buffer 6mA 5kΩ Pull-up
7 (1)
1-20
BEWF
Low-noise I/O Buffer 24mA 5kΩ Pull-up
10 (1)
1-34
BEWG
Low-noise I/O Buffer 24mA 5kΩ Pull-up
10 (1)
1-78
BEWH
Low-noise 3-State Buffer 24mA 5kΩ Pull-up
7 (1)
1-20
BEWT
Low-noise 3-State Buffer 3mA 5kΩ Pull-up
7 (1)
1-20
BEWU
Low-noise I/O Buffer 3mA 5kΩ Pull-up
10 (1)
1-34
BEWV
Low-noise I/O Buffer 3mA 5kΩ Pull-up
10 (1)
1-78
BFD1W
Low-noise Schmitt I/O Buffer 12mA 50kΩ Pull-down
13 (1)
1-46
BFD2W
Low-noise Schmitt I/O Buffer 12mA 50kΩ Pull-down
13 (1)
1-90
BFD3W
Low-noise Schmitt I/O Buffer 9mA 50kΩ Pull-down
13 (1)
1-46
BFD4W
Low-noise Schmitt I/O Buffer 9mA 50kΩ Pull-down
13 (1)
1-90
BFD5W
Low-noise Schmitt I/O Buffer 18mA 50kΩ Pull-down
13 (1)
1-46
BFD6W
Low-noise Schmitt I/O Buffer 18mA 50kΩ Pull-down
13 (1)
1-90
BFDCW
Low-noise Schmitt I/O Buffer 6mA 50kΩ Pull-down
13 (1)
1-46
BFDDW
Low-noise Schmitt I/O Buffer 6mA 50kΩ Pull-down
13 (1)
1-90
BFDFW
Low-noise Schmitt I/O Buffer 24mA 50kΩ Pull-down
13 (1)
1-46
BFDGW
Low-noise Schmitt I/O Buffer 24mA 50kΩ Pull-down
13 (1)
1-90
BFDUW
Low-noise Schmitt I/O Buffer 3mA 50kΩ Pull-down
13 (1)
1-46
BFDVW
Low-noise Schmitt I/O Buffer 3mA 50kΩ Pull-down
13 (1)
1-90
BFI1W
Low-noise Schmitt I/O Buffer 12mA
13 (1)
1-46
BFI2W
Low-noise Schmitt I/O Buffer 12mA
13 (1)
1-90
BFI3W
Low-noise Schmitt I/O Buffer 9mA
13 (1)
1-46
BFI4W
Low-noise Schmitt I/O Buffer 9mA
13 (1)
1-90
BFI5W
Low-noise Schmitt I/O Buffer 18mA
13 (1)
1-46
BFI6W
Low-noise Schmitt I/O Buffer 18mA
13 (1)
1-90
BFICW
Low-noise Schmitt I/O Buffer 6mA
13 (1)
1-46
BFIDW
Low-noise Schmitt I/O Buffer 6mA
13 (1)
1-90
BFIFW
Low-noise Schmitt I/O Buffer 24mA
13 (1)
1-46
BFIGW
Low-noise Schmitt I/O Buffer 24mA
13 (1)
1-90
BFIUW
Low-noise Schmitt I/O Buffer 3mA
13 (1)
1-46
BFIVW
Low-noise Schmitt I/O Buffer 3mA
13 (1)
1-90
BFU1W
Low-noise Schmitt I/O Buffer 12mA 50kΩ Pull-up
13 (1)
1-46
BFU2W
Low-noise Schmitt I/O Buffer 12mA 50kΩ Pull-up
13 (1)
1-90
Block Library A13872EJ5V0BL
Index-4
Block
Function
Cells (I/O)
Page
BFU3W
Low-noise Schmitt I/O Buffer 9mA 50kΩ Pull-up
13 (1)
1-46
BFU4W
Low-noise Schmitt I/O Buffer 9mA 50kΩ Pull-up
13 (1)
1-90
BFU5W
Low-noise Schmitt I/O Buffer 18mA 50kΩ Pull-up
13 (1)
1-46
BFU6W
Low-noise Schmitt I/O Buffer 18mA 50kΩ Pull-up
13 (1)
1-90
BFUCW
Low-noise Schmitt I/O Buffer 6mA 50kΩ Pull-up
13 (1)
1-46
BFUDW
Low-noise Schmitt I/O Buffer 6mA 50kΩ Pull-up
13 (1)
1-90
BFUFW
Low-noise Schmitt I/O Buffer 24mA 50kΩ Pull-up
13 (1)
1-46
BFUGW
Low-noise Schmitt I/O Buffer 24mA 50kΩ Pull-up
13 (1)
1-90
BFUUW
Low-noise Schmitt I/O Buffer 3mA 50kΩ Pull-up
13 (1)
1-46
BFUVW
Low-noise Schmitt I/O Buffer 3mA 50kΩ Pull-up
13 (1)
1-90
BFW1W
Low-noise Schmitt I/O Buffer 12mA 5kΩ Pull-up
13 (1)
1-46
BFW2W
Low-noise Schmitt I/O Buffer 12mA 5kΩ Pull-up
13 (1)
1-90
BFW3W
Low-noise Schmitt I/O Buffer 9mA 5kΩ Pull-up
13 (1)
1-46
BFW4W
Low-noise Schmitt I/O Buffer 9mA 5kΩ Pull-up
13 (1)
1-90
BFW5W
Low-noise Schmitt I/O Buffer 18mA 5kΩ Pull-up
13 (1)
1-46
BFW6W
Low-noise Schmitt I/O Buffer 18mA 5kΩ Pull-up
13 (1)
1-90
BFWCW
Low-noise Schmitt I/O Buffer 6mA 5kΩ Pull-up
13 (1)
1-46
BFWDW
Low-noise Schmitt I/O Buffer 6mA 5kΩ Pull-up
13 (1)
1-90
BFWFW
Low-noise Schmitt I/O Buffer 24mA 5kΩ Pull-up
13 (1)
1-46
BFWGW
Low-noise Schmitt I/O Buffer 24mA 5kΩ Pull-up
13 (1)
1-90
BFWUW
Low-noise Schmitt I/O Buffer 3mA 5kΩ Pull-up
13 (1)
1-46
BFWVW
Low-noise Schmitt I/O Buffer 3mA 5kΩ Pull-up
13 (1)
1-90
BN21
I/O Buffer with EN(AND) 12mA
23 (1)
1-52
BN22
I/O Buffer with EN(AND) 12mA
24 (1)
1-96
BN23
I/O Buffer with EN(AND) 9mA
13 (1)
1-52
BN24
I/O Buffer with EN(AND) 9mA
14 (1)
1-96
BN25
I/O Buffer with EN(AND) 18mA
23 (1)
1-52
BN26
I/O Buffer with EN(AND) 18mA
24 (1)
1-96
BN2C
I/O Buffer with EN(AND) 6mA
13 (1)
1-52
BN2D
I/O Buffer with EN(AND) 6mA
14 (1)
1-96
BN2F
I/O Buffer with EN(AND) 24mA
23 (1)
1-52
BN2G
I/O Buffer with EN(AND) 24mA
24 (1)
1-96
BN2U
I/O Buffer with EN(AND) 3mA
13 (1)
1-52
BN2V
I/O Buffer with EN(AND) 3mA
14 (1)
1-96
BN31
I/O Buffer with EN(OR) 12mA
21 (1)
1-56
BN32
I/O Buffer with EN(OR) 12mA
21 (1)
1-100
BN33
I/O Buffer with EN(OR) 9mA
11 (1)
1-56
BN34
I/O Buffer with EN(OR) 9mA
11 (1)
1-100
BN35
I/O Buffer with EN(OR) 18mA
21 (1)
1-56
BN36
I/O Buffer with EN(OR) 18mA
21 (1)
1-100
BN3C
I/O Buffer with EN(OR) 6mA
11 (1)
1-56
BN3D
I/O Buffer with EN(OR) 6mA
11 (1)
1-100
BN3F
I/O Buffer with EN(OR) 24mA
21 (1)
1-56
Index-5
Block Library A13872EJ5V0BL
Block
Function
Cells (I/O)
Page
BN3G
I/O Buffer with EN(OR) 24mA
21 (1)
1-100
BN3U
I/O Buffer with EN(OR) 3mA
11 (1)
1-56
BN3V
I/O Buffer with EN(OR) 3mA
11 (1)
1-100
BN41
I/O Buffer with EN(AND) 12mA 50kΩ Pull-down
23 (1)
1-52
BN42
I/O Buffer with EN(AND) 12mA 50kΩ Pull-down
24 (1)
1-96
BN43
I/O Buffer with EN(AND) 9mA 50kΩ Pull-down
13 (1)
1-52
BN44
I/O Buffer with EN(AND) 9mA 50kΩ Pull-down
14 (1)
1-96
BN45
I/O Buffer with EN(AND) 18mA 50kΩ Pull-down
23 (1)
1-52
BN46
I/O Buffer with EN(AND) 18mA 50kΩ Pull-down
24 (1)
1-96
BN4C
I/O Buffer with EN(AND) 6mA 50kΩ Pull-down
13 (1)
1-52
BN4D
I/O Buffer with EN(AND) 6mA 50kΩ Pull-down
14 (1)
1-96
BN4F
I/O Buffer with EN(AND) 24mA 50kΩ Pull-down
23 (1)
1-52
BN4G
I/O Buffer with EN(AND) 24mA 50kΩ Pull-down
24 (1)
1-96
BN4U
I/O Buffer with EN(AND) 3mA 50kΩ Pull-down
13 (1)
1-52
BN4V
I/O Buffer with EN(AND) 3mA 50kΩ Pull-down
14 (1)
1-96
BN51
I/O Buffer with EN(OR) 12mA 50kΩ Pull-down
21 (1)
1-56
BN52
I/O Buffer with EN(OR) 12mA 50kΩ Pull-down
21 (1)
1-100
BN53
I/O Buffer with EN(OR) 9mA 50kΩ Pull-down
11 (1)
1-56
BN54
I/O Buffer with EN(OR) 9mA 50kΩ Pull-down
11 (1)
1-100
BN55
I/O Buffer with EN(OR) 18mA 50kΩ Pull-down
21 (1)
1-56
BN56
I/O Buffer with EN(OR) 18mA 50kΩ Pull-down
21 (1)
1-100
BN5C
I/O Buffer with EN(OR) 6mA 50kΩ Pull-down
11 (1)
1-56
BN5D
I/O Buffer with EN(OR) 6mA 50kΩ Pull-down
11 (1)
1-100
BN5F
I/O Buffer with EN(OR) 24mA 50kΩ Pull-down
21 (1)
1-56
BN5G
I/O Buffer with EN(OR) 24mA 50kΩ Pull-down
21 (1)
1-100
BN5U
I/O Buffer with EN(OR) 3mA 50kΩ Pull-down
11 (1)
1-56
BN5V
I/O Buffer with EN(OR) 3mA 50kΩ Pull-down
11 (1)
1-100
BSD1W
Schmitt I/O Buffer 12mA 50kΩ Pull-down
23 (1)
1-40
BSD2W
Schmitt I/O Buffer 12mA 50kΩ Pull-down
23 (1)
1-84
BSD3W
Schmitt I/O Buffer 9mA 50kΩ Pull-down
13 (1)
1-40
BSD4W
Schmitt I/O Buffer 9mA 50kΩ Pull-down
13 (1)
1-84
BSD5W
Schmitt I/O Buffer 18mA 50kΩ Pull-down
23 (1)
1-40
BSD6W
Schmitt I/O Buffer 18mA 50kΩ Pull-down
23 (1)
1-84
BSDCW
Schmitt I/O Buffer 6mA 50kΩ Pull-down
13 (1)
1-40
BSDDW
Schmitt I/O Buffer 6mA 50kΩ Pull-down
13 (1)
1-84
BSDFW
Schmitt I/O Buffer 24mA 50kΩ Pull-down
23 (1)
1-40
BSDGW
Schmitt I/O Buffer 24mA 50kΩ Pull-down
23 (1)
1-84
BSDUW
Schmitt I/O Buffer 3mA 50kΩ Pull-down
13 (1)
1-40
BSDVW
Schmitt I/O Buffer 3mA 50kΩ Pull-down
13 (1)
1-84
BSI1W
Schmitt I/O Buffer 12mA
23 (1)
1-40
BSI2W
Schmitt I/O Buffer 12mA
23 (1)
1-84
BSI3W
Schmitt I/O Buffer 9mA
13 (1)
1-40
BSI4W
Schmitt I/O Buffer 9mA
13 (1)
1-84
Block Library A13872EJ5V0BL
Index-6
Block
Function
Cells (I/O)
Page
BSI5W
Schmitt I/O Buffer 18mA
23 (1)
1-40
BSI6W
Schmitt I/O Buffer 18mA
23 (1)
1-84
BSICW
Schmitt I/O Buffer 6mA
13 (1)
1-40
BSIDW
Schmitt I/O Buffer 6mA
13 (1)
1-84
BSIFW
Schmitt I/O Buffer 24mA
23 (1)
1-40
BSIGW
Schmitt I/O Buffer 24mA
23 (1)
1-84
BSIUW
Schmitt I/O Buffer 3mA
13 (1)
1-40
BSIVW
Schmitt I/O Buffer 3mA
13 (1)
1-84
BSU1W
Schmitt I/O Buffer 12mA 50kΩ Pull-up
23 (1)
1-40
BSU2W
Schmitt I/O Buffer 12mA 50kΩ Pull-up
23 (1)
1-84
BSU3W
Schmitt I/O Buffer 9mA 50kΩ Pull-up
13 (1)
1-40
BSU4W
Schmitt I/O Buffer 9mA 50kΩ Pull-up
13 (1)
1-84
BSU5W
Schmitt I/O Buffer 18mA 50kΩ Pull-up
23 (1)
1-40
BSU6W
Schmitt I/O Buffer 18mA 50kΩ Pull-up
23 (1)
1-84
BSUCW
Schmitt I/O Buffer 6mA 50kΩ Pull-up
13 (1)
1-40
BSUDW
Schmitt I/O Buffer 6mA 50kΩ Pull-up
13 (1)
1-84
BSUFW
Schmitt I/O Buffer 24mA 50kΩ Pull-up
23 (1)
1-40
BSUGW
Schmitt I/O Buffer 24mA 50kΩ Pull-up
23 (1)
1-84
BSUUW
Schmitt I/O Buffer 3mA 50kΩ Pull-up
13 (1)
1-40
BSUVW
Schmitt I/O Buffer 3mA 50kΩ Pull-up
13 (1)
1-84
BSW1W
Schmitt I/O Buffer 12mA 5kΩ Pull-up
23 (1)
1-40
BSW2W
Schmitt I/O Buffer 12mA 5kΩ Pull-up
23 (1)
1-84
BSW3W
Schmitt I/O Buffer 9mA 5kΩ Pull-up
13 (1)
1-40
BSW4W
Schmitt I/O Buffer 9mA 5kΩ Pull-up
13 (1)
1-84
BSW5W
Schmitt I/O Buffer 18mA 5kΩ Pull-up
23 (1)
1-40
BSW6W
Schmitt I/O Buffer 18mA 5kΩ Pull-up
23 (1)
1-84
BSWCW
Schmitt I/O Buffer 6mA 5kΩ Pull-up
13 (1)
1-40
BSWDW
Schmitt I/O Buffer 6mA 5kΩ Pull-up
13 (1)
1-84
BSWFW
Schmitt I/O Buffer 24mA 5kΩ Pull-up
23 (1)
1-40
BSWGW
Schmitt I/O Buffer 24mA 5kΩ Pull-up
23 (1)
1-84
BSWUW
Schmitt I/O Buffer 3mA 5kΩ Pull-up
13 (1)
1-40
BSWVW
Schmitt I/O Buffer 3mA 5kΩ Pull-up
13 (1)
1-84
EXO1
N-ch open drain Buffer with failsafe 9mA
4 (1)
1-26
EXO5
N-ch open drain Buffer with failsafe 18mA
4 (1)
1-26
EXO9
N-ch open drain Buffer with failsafe 12mA
4 (1)
1-26
EXOD
N-ch open drain Buffer with failsafe 24mA
4 (1)
1-26
EXT1
N-ch open drain Buffer 9mA
4 (1)
1-24
EXT3
N-ch open drain Buffer 9mA 50kΩ Pull-up
4 (1)
1-24
EXT5
N-ch open drain Buffer 18mA
4 (1)
1-24
EXT7
N-ch open drain Buffer 18mA 50kΩ Pull-up
4 (1)
1-24
EXT9
N-ch open drain Buffer 12mA
4 (1)
1-24
EXTB
N-ch open drain Buffer 12mA 50kΩ Pull-up
4 (1)
1-24
EXTD
N-ch open drain Buffer 24mA
4 (1)
1-24
Index-7
Block Library A13872EJ5V0BL
Block
Function
Cells (I/O)
Page
EXTF
N-ch open drain Buffer 24mA 50kΩ Pull-up
4 (1)
1-24
EXW3
N-ch open drain Buffer 9mA 5kΩ Pull-up
4 (1)
1-24
EXW7
N-ch open drain Buffer 18mA 5kΩ Pull-up
4 (1)
1-24
EXWB
N-ch open drain Buffer 12mA 5kΩ Pull-up
4 (1)
1-24
EXWF
N-ch open drain Buffer 24mA 5kΩ Pull-up
4 (1)
1-24
F091
H, L Level Generator
1 (-)
2-4
F101
Inverter Single Out
1 (-)
2-10
F102
Inverter Single Out, x2-drive
2 (-)
2-10
F111
Buffer Single Out
2 (-)
2-12
F112
Buffer Single Out, x2-drive
3 (-)
2-12
F131
Delay Gate
6 (-)
2-16
F132
Delay Gate
10 (-)
2-16
F143
Inverter Single Out, x3-drive
3 (-)
2-10
F144
Inverter Single Out, x4-drive
4 (-)
2-10
F145
Inverter Single Out, x5-drive
5 (-)
2-10
F146
Inverter Single Out, x6-drive
6 (-)
2-10
F148
Inverter Single Out, x8-drive
12 (-)
2-10
F153
Buffer Single Out, x3-drive
4 (-)
2-12
F154
Buffer Single Out, x4-drive
5 (-)
2-12
F158
Buffer Single Out, x8-drive
11 (-)
2-12
F202
2-Input NOR
2 (-)
2-22
F203
3-Input NOR
3 (-)
2-24
F204
4-Input NOR
4 (-)
2-26
F205
5-Input NOR
5 (-)
2-28
F206
6-Input NOR
5 (-)
2-30
F208
8-Input NOR
7 (-)
2-32
F212
2-Input OR
2 (-)
2-34
F213
3-Input OR
3 (-)
2-36
F214
4-Input OR
3 (-)
2-38
F215
5-Input OR
5 (-)
2-40
F216
6-Input OR
5 (-)
2-42
F218
8-Input OR
8 (-)
2-44
F222
2-Input NOR x2-drive
4 (-)
2-22
F223
3-Input NOR x2-drive
6 (-)
2-24
F225
5-Input NOR x2-drive
6 (-)
2-28
F226
6-Input NOR x2-drive
6 (-)
2-30
F228
8-Input NOR x2-drive
8 (-)
2-32
F232
2-Input OR x2-drive
3 (-)
2-34
F233
3-Input OR x2-drive
4 (-)
2-36
F234
4-Input OR x2-drive
4 (-)
2-38
F235
5-Input OR x2-drive
7 (-)
2-40
F236
6-Input OR x2-drive
7 (-)
2-42
F238
8-Input OR x2-drive
9 (-)
2-44
Block Library A13872EJ5V0BL
Index-8
Block
Function
Cells (I/O)
Page
F252
2-Input OR x4-drive
6 (-)
2-34
F282
2-Input NOR x4-drive
6 (-)
2-22
F302
2-Input NAND
2 (-)
2-50
F303
3-Input NAND
3 (-)
2-52
F304
4-Input NAND
4 (-)
2-54
F305
5-Input NAND
5 (-)
2-56
F306
6-Input NAND
5 (-)
2-58
F308
8-Input NAND
6 (-)
2-60
F312
2-Input AND
2 (-)
2-62
F313
3-Input AND
3 (-)
2-64
F314
4-Input AND
3 (-)
2-66
F315
5-Input AND
5 (-)
2-68
F316
6-Input AND
5 (-)
2-70
F318
8-Input AND
6 (-)
2-72
F322
2-Input NAND x2-drive
4 (-)
2-50
F323
3-Input NAND x2-drive
6 (-)
2-52
F324
4-Input NAND x2-drive
8 (-)
2-54
F325
5-Input NAND x2-drive
6 (-)
2-56
F326
6-Input NAND x2-drive
6 (-)
2-58
F328
8-Input NAND x2-drive
7 (-)
2-60
F332
2-Input AND x2-drive
3 (-)
2-62
F333
3-Input AND x2-drive
4 (-)
2-64
F334
4-Input AND x2-drive
4 (-)
2-66
F335
5-Input AND x2-drive
7 (-)
2-68
F336
6-Input AND x2-drive
7 (-)
2-70
F338
8-Input AND x2-drive
8 (-)
2-72
F352
2-Input AND x4-drive
6 (-)
2-62
F382
2-Input NAND x4-drive
6 (-)
2-50
F421
1-2-Input AND-NOR
3 (-)
2-78
F422
1-1-2-Input AND-NOR
4 (-)
2-80
F423
1-3-Input AND-NOR
4 (-)
2-82
F424
2-2-Input AND-NOR
4 (-)
2-84
F425
2-2-2-Input AND-NOR
6 (-)
2-86
F427
2-3-Input AND-NOR
5 (-)
2-88
F428
1-2-2-Input AND-NOR
5 (-)
2-90
F429
2-2-2-2-Input AND-NOR
6 (-)
2-92
F430
1-4-Input OR-NAND
5 (-)
2-124
F431
1-2-Input OR-NAND
3 (-)
2-126
F432
1-1-2-Input OR-NAND
4 (-)
2-128
F433
1-3-Input OR-NAND
4 (-)
2-130
F434
2-2-Input OR-NAND
4 (-)
2-132
F435
2-3-Input OR-NAND
5 (-)
2-134
F436
3-3-Input OR-NAND
6 (-)
2-136
Index-9
Block Library A13872EJ5V0BL
Block
Function
Cells (I/O)
Page
F437
1-2-2-Input OR-NAND
5 (-)
2-138
F438
2-2-2-Input OR-NAND
6 (-)
2-140
F439
1-5-Input OR-NAND
6 (-)
2-142
F440
1-4-Input AND-NOR
5 (-)
2-94
F441
1-5-Input AND-NOR
7 (-)
2-96
F444
4-4-4-Input AND-NOR
8 (-)
2-98
F446
1-1-1-2-Input AND-NOR
5 (-)
2-100
F447
1-1-1-3-Input AND-NOR
5 (-)
2-102
F448
1-1-2-2-Input AND-NOR
5 (-)
2-104
F449
3-3-3-3-Input AND-NOR
8 (-)
2-106
F450
2-4-Input OR-NAND
6 (-)
2-144
F451
4-4-Input OR-NAND
8 (-)
2-146
F452
1-1-3-Input OR-NAND
5 (-)
2-148
F453
1-1-4-Input OR-NAND
6 (-)
2-150
F457
4-4-4-Input OR-NAND
10 (-)
2-152
F458
1-1-1-2-Input OR-NAND
5 (-)
2-154
F459
1-1-1-3-Input OR-NAND
5 (-)
2-156
F460
3-3-3-Input AND-NOR
7 (-)
2-108
F462
1-2-3-Input AND-NOR
6 (-)
2-110
F463
1-1-3-Input AND-NOR
5 (-)
2-112
F464
1-1-4-Input AND-NOR
5 (-)
2-114
F465
1-1-1-1-2-Input AND-NOR
5 (-)
2-116
F466
4-4-4-4-Input AND-NOR
10 (-)
2-118
F490
1-1-1-1-2-Input OR-NAND
5 (-)
2-158
F491
1-2-3-Input OR-NAND
5 (-)
2-160
F493
3-3-3-Input OR-NAND
7 (-)
2-162
F495
1-1-2-2-Input OR-NAND
6 (-)
2-164
F496
3-3-3-3-Input OR-NAND
8 (-)
2-166
F498
4-4-4-4-Input OR-NAND
14 (-)
2-168
F511
2-Input Exclusive OR
4 (-)
2-174
F512
2-Input Exclusive NOR
4 (-)
2-178
F516
3-Input Exclusive OR
7 (-)
2-176
F517
3-Input Exclusive NOR
7 (-)
2-180
F521
1-Bit Full Adder
9 (-)
2-186
F523
4-Bit Full Adder
32 (-)
2-188
F526
4-Bit Look Ahead Carry Generator
34 (-)
2-192
F527
4-Bit Carry Look Ahead Adder
69 (-)
2-194
F531
3-State Buffer with EN
5 (-)
2-198
F532
3-State Buffer with ENB
5 (-)
2-198
F533
3-State Buffer with EN, x2-drive
7 (-)
2-198
F534
3-State Buffer with ENB, x2-drive
7 (-)
2-198
F53F
3-State Buffer with EN, x4-drive
11 (-)
2-198
F53G
3-State Buffer with ENB, x4-drive
11 (-)
2-198
Block Library A13872EJ5V0BL
Index-10
Block
Function
Cells (I/O)
Page
F541
3-State Buffer Inverter with EN
6 (-)
2-198
F542
3-State Buffer Inverter with ENB
6 (-)
2-198
F543
3-State Buffer Inverter with EN, x2-drive
8 (-)
2-198
F544
3-State Buffer Inverter with ENB, x2-drive
8 (-)
2-198
F54F
3-State Buffer Inverter with EN, x4-drive
12 (-)
2-198
F54G
3-State Buffer Inverter with ENB, x4-drive
12 (-)
2-198
F560
2 to 4 Decoder Positive Out
10 (-)
2-202
F561
2 to 4 Decoder Negative Out
10 (-)
2-202
F563
8 to 1 Multiplexer (Positive Out)
18 (-)
2-210
F564
4 to 1 Multiplexer (Positive Out)
8 (-)
2-208
F565
2 to 1 Multiplexer (Positive Out)
4 (-)
2-206
F569
8 to 1 Multiplexer (Positive Out) with ENB
18 (-)
2-210
F570
4 to 1 Multiplexer (Positive Out) with ENB
10 (-)
2-208
F571
2 to 1 Multiplexer (Positive Out) with ENB
6 (-)
2-206
F572
Quad 2 to 1 Multiplexer (Negative Out) with ENB
17 (-)
2-214
F581
8-Bit Odd Parity Generator
19 (-)
2-218
F582
8-Bit Even Parity Generator
19 (-)
2-220
F595
RS-Latch
5 (-)
2-226
F596
RS-F/F with R, S
11 (-)
2-228
F601
D-Latch
6 (-)
2-234
F601NB
D-Latch QB Out
5 (-)
2-234
F601NQ
D-Latch Q Out
5 (-)
2-234
F602
D-Latch with R
6 (-)
2-238
F602NB
D-Latch with R QB Out
5 (-)
2-238
F602NQ
D-Latch with R Q Out
6 (-)
2-238
F603
D-Latch with RB
7 (-)
2-242
F603NB
D-Latch with RB QB Out
6 (-)
2-242
F603NQ
D-Latch with RB Q Out
5 (-)
2-242
F604
D-Latch (GB)
6 (-)
2-252
F604NB
D-Latch (GB) QB Out
5 (-)
2-252
F604NQ
D-Latch (GB) Q Out
5 (-)
2-252
F605
D-Latch (GB) with RB
7 (-)
2-256
F605NB
D-Latch (GB) with RB QB Out
6 (-)
2-256
F605NQ
D-Latch (GB) with RB Q Out
5 (-)
2-256
F60J
D-Latch with RB, SB
7 (-)
2-248
F60JNB
D-Latch with RB, SB QB Out
6 (-)
2-248
F60JNQ
D-Latch with RB, SB Q Out
6 (-)
2-248
F60K
D-Latch with SB
7 (-)
2-246
F60KNB
D-Latch with SB QB Out
5 (-)
2-246
F60KNQ
D-Latch with SB Q Out
6 (-)
2-246
F615
D-F/F with RB
9 (-)
2-272
F615H
D-F/F with RB, Hold
11 (-)
2-310
F615HB
D-F/F with RB, Hold QB Out
10 (-)
2-310
Index-11
Block Library A13872EJ5V0BL
Block
Function
Cells (I/O)
Page
F615HQ
D-F/F with RB, Hold Q Out
10 (-)
2-310
F615NB
D-F/F with RB QB Out
8 (-)
2-272
F615NQ
D-F/F with RB Q Out
8 (-)
2-272
F615S
D-F/F with RB, 2 to 1 Selector
11 (-)
2-294
F615SB
D-F/F with RB, 2 to 1 Selector QB Out
10 (-)
2-294
F615SQ
D-F/F with RB, 2 to 1 Selector Q Out
10 (-)
2-294
F616
D-F/F with SB
9 (-)
2-274
F616H
D-F/F with SB, Hold
11 (-)
2-312
F616HB
D-F/F with SB, Hold QB Out
10 (-)
2-312
F616HQ
D-F/F with SB, Hold Q Out
10 (-)
2-312
F616NB
D-F/F with SB QB Out
8 (-)
2-274
F616NQ
D-F/F with SB Q Out
8 (-)
2-274
F616S
D-F/F with SB, 2 to 1 Selector
11 (-)
2-296
F616SB
D-F/F with SB, 2 to 1 Selector QB Out
10 (-)
2-296
F616SQ
D-F/F with SB, 2 to 1 Selector Q Out
10 (-)
2-296
F641
D-F/F
8 (-)
2-264
F641H
D-F/F with Hold
10 (-)
2-308
F641HB
D-F/F with Hold QB Out
9 (-)
2-308
F641HQ
D-F/F with Hold Q Out
9 (-)
2-308
F641NB
D-F/F QB Out
7 (-)
2-264
F641NQ
D-F/F Q Out
7 (-)
2-264
F641S
D-F/F with 2 to 1 Selector
10 (-)
2-286
F641SB
D-F/F with 2 to 1 Selector QB Out
9 (-)
2-286
F641SQ
D-F/F with 2 to 1 Selector Q Out
9 (-)
2-286
F642
D-F/F with R
9 (-)
2-266
F642NB
D-F/F with R QB Out
8 (-)
2-266
F642NQ
D-F/F with R Q Out
8 (-)
2-266
F642S
D-F/F with R, 2 to 1 Selector
11 (-)
2-288
F642SB
D-F/F with R, 2 to 1 Selector QB Out
10 (-)
2-288
F642SQ
D-F/F with R, 2 to 1 Selector Q Out
10 (-)
2-288
F643
D-F/F with S
9 (-)
2-268
F643NB
D-F/F with S QB Out
8 (-)
2-268
F643NQ
D-F/F with S Q Out
8 (-)
2-268
F643S
D-F/F with S, 2 to 1 Selector
11 (-)
2-290
F643SB
D-F/F with S, 2 to 1 Selector QB Out
10 (-)
2-290
F643SQ
D-F/F with S, 2 to 1 Selector Q Out
10 (-)
2-290
F644
D-F/F with R, S
10 (-)
2-270
F644NB
D-F/F with R, S QB Out
9 (-)
2-270
F644NQ
D-F/F with R, S Q Out
9 (-)
2-270
F644S
D-F/F with R, S, 2 to 1 Selector
12 (-)
2-292
F644SB
D-F/F with R, S, 2 to 1 Selector QB Out
11 (-)
2-292
F644SQ
D-F/F with R, S, 2 to 1 Selector Q Out
11 (-)
2-292
F647
D-F/F with RB, SB
10 (-)
2-276
Block Library A13872EJ5V0BL
Index-12
Block
Function
Cells (I/O)
Page
F647H
D-F/F with RB, SB, Hold
12 (-)
2-314
F647HB
D-F/F with RB, SB, Hold QB Out
11 (-)
2-314
F647HQ
D-F/F with RB, SB, Hold Q Out
11 (-)
2-314
F647NB
D-F/F with RB, SB QB Out
9 (-)
2-276
F647NQ
D-F/F with RB, SB Q Out
9 (-)
2-276
F647S
D-F/F with RB, SB, 2 to 1 Selector
12 (-)
2-298
F647SB
D-F/F with RB, SB, 2 to 1 Selector QB Out
11 (-)
2-298
F647SQ
D-F/F with RB, SB, 2 to 1 Selector Q Out
11 (-)
2-298
F661
D-F/F (CB)
8 (-)
2-278
F661NB
D-F/F (CB) QB Out
7 (-)
2-278
F661NQ
D-F/F (CB) Q Out
7 (-)
2-278
F661S
D-F/F (CB) with 2 to 1 Selector
10 (-)
2-300
F661SB
D-F/F (CB) with 2 to 1 Selector QB Out
9 (-)
2-300
F661SQ
D-F/F (CB) with 2 to 1 Selector Q Out
9 (-)
2-300
F665
D-F/F (CB) with RB
9 (-)
2-280
F665NB
D-F/F (CB) with RB QB Out
8 (-)
2-280
F665NQ
D-F/F (CB) with RB Q Out
8 (-)
2-280
F665S
D-F/F (CB) with RB, 2 to 1 Selector
11 (-)
2-302
F665SB
D-F/F (CB) with RB, 2 to 1 Selector QB Out
10 (-)
2-302
F665SQ
D-F/F (CB) with RB, 2 to 1 Selector Q Out
10 (-)
2-302
F666
D-F/F (CB) with SB
9 (-)
2-282
F666NB
D-F/F (CB) with SB QB Out
8 (-)
2-282
F666NQ
D-F/F (CB) with SB Q Out
8 (-)
2-282
F666S
D-F/F (CB) with SB, 2 to 1 Selector
11 (-)
2-304
F666SB
D-F/F (CB) with SB, 2 to 1 Selector QB Out
10 (-)
2-304
F666SQ
D-F/F (CB) with SB, 2 to 1 Selector Q Out
10 (-)
2-304
F667
D-F/F (CB) with RB, SB
10 (-)
2-284
F667NB
D-F/F (CB) with RB, SB QB Out
9 (-)
2-284
F667NQ
D-F/F (CB) with RB, SB Q Out
9 (-)
2-284
F667S
D-F/F (CB) with RB, SB, 2 to 1 Selector
12 (-)
2-306
F667SB
D-F/F (CB) with RB, SB, 2 to 1 Selector QB Out
11 (-)
2-306
F667SQ
D-F/F (CB) with RB, SB, 2 to 1 Selector Q Out
11 (-)
2-306
F673
D-F/F (CB) with 2 to 1 Selector(2 CTRL), RB
11 (-)
2-316
F674
D-F/F (CB) with Hold, 2 to 1 Selector(2 CTRL), RB
12 (-)
2-318
F6R1
D-Latch, High Speed
6 (-)
2-236
F6R2
D-Latch with R, High Speed
7 (-)
2-240
F6R5
D-Latch with RB, High Speed
6 (-)
2-244
F6R8
D-Latch (GB), High Speed
6 (-)
2-254
F6R9
D-Latch (GB) with RB, High Speed
6 (-)
2-258
F744
T-F/F with R, S
9 (-)
2-324
F744NQ
T-F/F with R, S Q Out
8 (-)
2-324
F745
T-F/F with RB
8 (-)
2-326
F745NQ
T-F/F with RB Q Out
7 (-)
2-326
Index-13
Block Library A13872EJ5V0BL
Block
Function
Cells (I/O)
Page
F747
T-F/F with RB, SB
9 (-)
2-328
F747NQ
T-F/F with RB, SB Q Out
8 (-)
2-328
F765
T-F/F (TB) with RB
8 (-)
2-332
F765NQ
T-F/F (TB) with RB Q Out
7 (-)
2-332
F767
T-F/F (TB) with RB, SB
9 (-)
2-334
F767NQ
T-F/F (TB) with RB, SB Q Out
8 (-)
2-334
F771
JK-F/F
10 (-)
2-338
F771NB
JK-F/F QB Out
9 (-)
2-338
F771NQ
JK-F/F Q Out
9 (-)
2-338
F774
JK-F/F with R, S
12 (-)
2-342
F774NB
JK-F/F with R, S QB Out
11 (-)
2-342
F774NQ
JK-F/F with R, S Q Out
11 (-)
2-342
F775
JK-F/F with RB
11 (-)
2-344
F775NB
JK-F/F with RB QB Out
10 (-)
2-344
F775NQ
JK-F/F with RB Q Out
10 (-)
2-344
F776
JK-F/F with SB
11 (-)
2-346
F776NB
JK-F/F with SB QB Out
10 (-)
2-346
F776NQ
JK-F/F with SB Q Out
10 (-)
2-346
F777
JK-F/F with RB, SB
12 (-)
2-348
F777NB
JK-F/F with RB, SB QB Out
11 (-)
2-348
F777NQ
JK-F/F with RB, SB Q Out
11 (-)
2-348
F781
JK-F/F (CB)
10 (-)
2-350
F781NB
JK-F/F (CB) QB Out
9 (-)
2-350
F781NQ
JK-F/F (CB) Q Out
9 (-)
2-350
F787
JK-F/F (CB) with RB, SB
12 (-)
2-354
F787NB
JK-F/F (CB) with RB, SB QB Out
11 (-)
2-354
F787NQ
JK-F/F (CB) with RB, SB Q Out
11 (-)
2-354
F791
T-F/F with Data-Hold R, S
12 (-)
2-330
F792
T-F/F (TB) with Data-Hold RB, SB
12 (-)
2-336
F7D1
JK-F/F, High Speed
10 (-)
2-340
F7E1
JK-F/F (CB), High Speed
10 (-)
2-352
FC42
CTS Driver (Inverter Type) Single type
132 (-)
2-14
FC44
CTS Driver (Inverter Type) Double type
340 (-)
2-14
FC82
CTS Driver (Inverter Type) Single type, x2-drive
396 (-)
2-14
FC84
CTS Driver (Inverter Type) Double type, x2-drive
1020 (-)
2-14
FDA1
Input Buffer with failsafe 50kΩ Pull-down
3 (1)
1-6
FDA2
Input Buffer with failsafe 50kΩ Pull-down
3 (1)
1-66
FDE1W
Input Buffer with failsafe Schmitt 50kΩ Pull-down
6 (1)
1-6
FDE2W
Input Buffer with failsafe Schmitt 50kΩ Pull-down
6 (1)
1-66
FDS1W
Input Buffer Schmitt 50kΩ Pull-down
6 (1)
1-4
FDS2W
Input Buffer Schmitt 50kΩ Pull-down
6 (1)
1-64
FE01
Low-noise Output Buffer 9mA
5 (1)
1-14
FE02
Low-noise Output Buffer 12mA
5 (1)
1-14
Block Library A13872EJ5V0BL
Index-14
Block
Function
Cells (I/O)
Page
FE03
Low-noise Output Buffer 18mA
5 (1)
1-14
FE04
Low-noise Output Buffer 6mA
5 (1)
1-14
FE06
Low-noise Output Buffer 24mA
5 (1)
1-14
FE09
Low-noise Output Buffer 3mA
5 (1)
1-14
FI01
Input Buffer
3 (1)
1-4
FI02
Input Buffer
3 (1)
1-64
FIA1
Input Buffer with failsafe
3 (1)
1-6
FIA2
Input Buffer with failsafe
3 (1)
1-66
FID1
Input Buffer 50kΩ Pull-down
3 (1)
1-4
FID2
Input Buffer 50kΩ Pull-down
3 (1)
1-64
FIE1W
Input Buffer with failsafe Schmitt
6 (1)
1-6
FIE2W
Input Buffer with failsafe Schmitt
6 (1)
1-66
FIS1W
Input Buffer Schmitt
6 (1)
1-4
FIS2W
Input Buffer Schmitt
6 (1)
1-64
FIU1
Input Buffer 50kΩ Pull-up
3 (1)
1-4
FIU2
Input Buffer 50kΩ Pull-up
3 (1)
1-64
FIW1
Input Buffer 5kΩ Pull-up
3 (1)
1-4
FIW2
Input Buffer 5kΩ Pull-up
3 (1)
1-64
FN11
Input Buffer with EN(AND)
6 (1)
1-8
FN12
Input Buffer with EN(AND)
7 (1)
1-68
FN13
Input Buffer with EN(OR)
4 (1)
1-10
FN14
Input Buffer with EN(OR)
4 (1)
1-70
FN21
Input Buffer with EN(AND) 50kΩ Pull-down
6 (1)
1-8
FN22
Input Buffer with EN(AND) 50kΩ Pull-down
7 (1)
1-68
FN23
Input Buffer with EN(OR) 50kΩ Pull-down
4 (1)
1-10
FN24
Input Buffer with EN(OR) 50kΩ Pull-down
4 (1)
1-70
FO01
Output Buffer 9mA
4 (1)
1-12
FO02
Output Buffer 12mA
12 (1)
1-12
FO03
Output Buffer 18mA
12 (1)
1-12
FO04
Output Buffer 6mA
4 (1)
1-12
FO06
Output Buffer 24mA
12 (1)
1-12
FO09
Output Buffer 3mA
4 (1)
1-12
FUS1W
Input Buffer Schmitt 50kΩ Pull-up
6 (1)
1-4
FUS2W
Input Buffer Schmitt 50kΩ Pull-up
6 (1)
1-64
FWS1W
Input Buffer Schmitt 5kΩ Pull-up
6 (1)
1-4
FWS2W
Input Buffer Schmitt 5kΩ Pull-up
6 (1)
1-64
L101
Inverter Single Out, Low Power
1 (-)
2-10
L111
Buffer Single Out, Low Power
1 (-)
2-12
L202
2-Input NOR Low Power
1 (-)
2-22
L203
3-Input NOR Low Power
2 (-)
2-24
L204
4-Input NOR Low Power
2 (-)
2-26
L205
5-Input NOR Low Power
4 (-)
2-28
L208
8-Input NOR Low Power
7 (-)
2-32
Index-15
Block Library A13872EJ5V0BL
Block
Function
Cells (I/O)
Page
L212
2-Input OR Low Power
2 (-)
2-34
L213
3-Input OR Low Power
2 (-)
2-36
L214
4-Input OR Low Power
3 (-)
2-38
L215
5-Input OR Low Power
4 (-)
2-40
L216
6-Input OR Low Power
4 (-)
2-42
L218
8-Input OR Low Power
6 (-)
2-44
L302
2-Input NAND Low Power
1 (-)
2-50
L303
3-Input NAND Low Power
2 (-)
2-52
L304
4-Input NAND Low Power
2 (-)
2-54
L312
2-Input AND Low Power
2 (-)
2-62
L313
3-Input AND Low Power
2 (-)
2-64
L314
4-Input AND Low Power
3 (-)
2-66
L315
5-Input AND Low Power
4 (-)
2-68
L316
6-Input AND Low Power
4 (-)
2-70
L318
8-Input AND Low Power
5 (-)
2-72
L421
1-2-Input AND-NOR Low Power
2 (-)
2-78
L422
1-1-2-Input AND-NOR Low Power
2 (-)
2-80
L423
1-3-Input AND-NOR Low Power
2 (-)
2-82
L424
2-2-Input AND-NOR Low Power
2 (-)
2-84
L425
2-2-2-Input AND-NOR Low Power
3 (-)
2-86
L427
2-3-Input AND-NOR Low Power
3 (-)
2-88
L428
1-2-2-Input AND-NOR Low Power
3 (-)
2-90
L429
2-2-2-2-Input AND-NOR Low Power
6 (-)
2-92
L430
1-4-Input OR-NAND Low Power
4 (-)
2-124
L431
1-2-Input OR-NAND Low Power
2 (-)
2-126
L432
1-1-2-Input OR-NAND Low Power
2 (-)
2-128
L433
1-3-Input OR-NAND Low Power
2 (-)
2-130
L434
2-2-Input OR-NAND Low Power
2 (-)
2-132
L436
3-3-Input OR-NAND Low Power
3 (-)
2-136
L439
1-5-Input OR-NAND Low Power
5 (-)
2-142
L440
1-4-Input AND-NOR Low Power
3 (-)
2-94
L441
1-5-Input AND-NOR Low Power
5 (-)
2-96
L444
4-4-4-Input AND-NOR Low Power
8 (-)
2-98
L446
1-1-1-2-Input AND-NOR Low Power
4 (-)
2-100
L447
1-1-1-3-Input AND-NOR Low Power
5 (-)
2-102
L448
1-1-2-2-Input AND-NOR Low Power
5 (-)
2-104
L450
2-4-Input OR-NAND Low Power
5 (-)
2-144
L451
4-4-Input OR-NAND Low Power
7 (-)
2-146
L452
1-1-3-Input OR-NAND Low Power
4 (-)
2-148
L453
1-1-4-Input OR-NAND Low Power
5 (-)
2-150
L458
1-1-1-2-Input OR-NAND Low Power
3 (-)
2-154
L459
1-1-1-3-Input OR-NAND Low Power
5 (-)
2-156
L460
3-3-3-Input AND-NOR Low Power
6 (-)
2-108
Block Library A13872EJ5V0BL
Index-16
Block
Function
Cells (I/O)
Page
L463
1-1-3-Input AND-NOR Low Power
3 (-)
2-112
L464
1-1-4-Input AND-NOR Low Power
5 (-)
2-114
L491
1-2-3-Input OR-NAND Low Power
5 (-)
2-160
L493
3-3-3-Input OR-NAND Low Power
6 (-)
2-162
L511
2-Input Exclusive OR Low Power
3 (-)
2-174
L512
2-Input Exclusive NOR Low Power
3 (-)
2-178
L516
3-Input Exclusive OR Low Power
6 (-)
2-176
L517
3-Input Exclusive NOR Low Power
7 (-)
2-180
L531
3-State Buffer with EN, Low Power
4 (-)
2-198
L532
3-State Buffer with ENB, Low Power
4 (-)
2-198
L560
2 to 4 Decoder Positive Out, Low Power
6 (-)
2-202
L561
2 to 4 Decoder Negative Out, Low Power
6 (-)
2-202
L565
2 to 1 Multiplexer (Positive Out) Low Power
3 (-)
2-206
L571
2 to 1 Multiplexer (Positive Out) with ENB, Low Power
4 (-)
2-206
L572
Quad 2 to 1 Multiplexer (Negative Out) with ENB, Low Power
15 (-)
2-214
L601
D-Latch Q Out, Low Power
4 (-)
2-234
L602
D-Latch with R Q Out, Low Power
5 (-)
2-238
L603
D-Latch with RB Q Out, Low Power
5 (-)
2-242
L604
D-Latch (GB) Q Out, Low Power
4 (-)
2-252
L605
D-Latch (GB) with RB Q Out, Low Power
5 (-)
2-256
L606
BScan D-Latch with SB Q Out, Low Power
5 (-)
4-30
L641
D-F/F Q Out, Low Power
6 (-)
2-264
L644
D-F/F with R, S Q Out, Low Power
8 (-)
2-270
L645
D-F/F with RB Q Out, Low Power
7 (-)
2-272
L647
D-F/F with RB, SB Q Out, Low Power
8 (-)
2-276
L661
D-F/F (CB) Q Out, Low Power
6 (-)
2-278
L667
D-F/F (CB) with RB, SB Q Out, Low Power
8 (-)
2-284
L744
T-F/F with R, S Q Out, Low Power
7 (-)
2-324
L747
T-F/F with RB, SB Q Out, Low Power
7 (-)
2-328
L767
T-F/F (TB) with RB, SB Q Out, Low Power
7 (-)
2-334
OSI1
Oscillator Input Buffer
0 (1)
1-108
OSI2
Oscillator Input Buffer for Enable
0 (1)
1-110
OSI4
Oscillator Input Buffer for OSO9
0 (1)
1-112
OSO1
Oscillator Output Buffer (Internal Feedback Resistor)
0 (1)
1-114
OSO7
Oscillator Output Buffer (for Enable Type)
0 (1)
1-116
OSO9
Oscillator Output Buffer (External Feedback Resistor)
0 (1)
1-118
S000
Scan D-F/F with R, S, 2 to 1 Selector
12 (-)
3-4
S002
Scan D-F/F with 2 to 1 Selector
10 (-)
3-6
S003
Scan D-F/F with 2 to 1 Selector, High Speed
11 (-)
3-8
S050
Scan D-F/F with R, S, Hold, 2 to 1 Selector
16 (-)
3-10
S052
Scan D-F/F with Hold, 2 to 1 Selector
14 (-)
3-12
S100
Scan JK-F/F with R, S, D-F/F Function
14 (-)
3-14
S102
Scan JK-F/F with D-F/F Function
12 (-)
3-16
Index-17
Block Library A13872EJ5V0BL
Block
Function
Cells (I/O)
Page
S150
Scan JK-F/F with R, S, Hold, D-F/F Function
18 (-)
3-18
S152
Scan JK-F/F with Hold, D-F/F Function
16 (-)
3-20
S201
Scan D-Latch with R, D-F/F Function
13 (-)
3-22
S202
Scan D-Latch with D-F/F Function
12 (-)
3-24
S204
Scan D-Latch with D-F/F Function, High Speed
12 (-)
3-26
S301
Scan D-Latch with R, Special Function, R
8 (-)
3-28
S302
Scan D-Latch with Special Function
7 (-)
3-30
S303
Scan D-Latch with Special Function, High Speed
7 (-)
3-32
SBCJ
BScan TAP Macro
262 (-)
4-4
SBCK
BScan TAP Controller
392 (-)
4-48
SBCL
BScan TAP Macro with NEC Scan
315 (-)
4-6
SBD1
BScan Selector
4 (-)
4-32
SBM4
BScan Instruction Register (Internal Circuit)
46 (-)
4-50
SBM5
BScan Instruction Register
140 (-)
4-52
SBM6
BScan Instruction Decoder
24 (-)
4-54
SBMC
BScan Instruction Decoder with NEC Scan
37 (-)
4-56
SBR1
BScan Shift Register
8 (-)
4-34
SBS3
BScan Bypass Register
26 (-)
4-58
SBZ1
BScan Level Generator (CLANP)
1 (-)
4-12
SCD1
Clock Distributor
8 (-)
3-66
SCDC
Clock Distributor with Test (Positive Clock)
2 (-)
3-68
SCDD
Clock Distributor with Test (Negative Clock)
2 (-)
3-70
SCI1
Common Input
2 (-)
3-90
SCKG
Clock Generator
16 (-)
3-88
SCO1
Common Output
4 (-)
3-92
SE601
NEC Scan D-Latch
13 (-)
3-38
SE602
NEC Scan D-Latch with R
14 (-)
3-40
SE603
NEC Scan D-Latch with RB
14 (-)
3-42
SE604
NEC Scan D-Latch(GB)
13 (-)
3-44
SE605
NEC Scan D-Latch(GB) with RB
14 (-)
3-46
SE611
NEC Scan D-F/F
11 (-)
3-48
SE614
NEC Scan D-F/F with R, S
13 (-)
3-50
SE615
NEC Scan D-F/F with RB
12 (-)
3-52
SE616
NEC Scan D-F/F with SB
12 (-)
3-54
SE617
NEC Scan D-F/F with RB, SB
13 (-)
3-56
SE631
NEC Scan D-F/F (CB)
11 (-)
3-58
SE637
NEC Scan D-F/F (CB) with RB, SB
13 (-)
3-60
SFEH
I/F Control (AMC) with EN
3 (-)
3-72
SFEL
I/F Control (AMC) with ENB
2 (-)
3-74
SGND
GND
2 (-)
3-94
SMS1
Mega Macro Skip
4 (-)
3-80
SOEH
I/F Control (SMC) with EN
3 (-)
3-76
SOEL
I/F Control (SMC) with ENB
2 (-)
3-78
Block Library A13872EJ5V0BL
Index-18
Block
Function
Cells (I/O)
Page
SRH1
Set/Reset Control
2 (-)
3-82
SRL1
Set-B/Reset-B Control
2 (-)
3-84
SRPD
Loop Cut
12 (-)
3-86
SVRN22
BScan Data Register for Output
24 (-)
4-20
SVRN32
BScan Data Register for 3-state
50 (-)
4-22
SVRNB2
BScan Data Register for Bid
57 (-)
4-24
SVRNI2
BScan Data Register for Input
12 (-)
4-18
SVSNA2
BScan Data Selector for Output
7 (-)
4-36
SVSNB2
BScan Data Selector for Bid
7 (-)
4-38
SVSNC2
BScan Data Enable Selector for 3-state
9 (-)
4-40
SVSNE2
BScan Data Enable Selector for Bid
9 (-)
4-42
Index-19
Block Library A13872EJ5V0BL
Facsimile Message
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CS 01.11