ETC UPD65703

New ASIC Solution Platform
ISSP Series
(ISSP1-STD Family)
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FEATURES (1/2)
Introduced by NEC Electronics, an ISSP represents a new class of ASIC devices based
on a cost effective, high-function and easy to design ASIC architecture. ISSP devices are
easily customizable using upper metal layers to meet individual design requirements. An
ISSP is ideal for mid-volume designers engaged in complex designs with high system
clock speeds. However, the platforms are generally very easy to design, consume much
lower power than a comparable FPGA based solution and offer up to an order of
magnitude lower NRE than cell-based designs. NEC Electronics offers a breadth of ASIC
solutions using Cell-Based and Gate Array products. An ISSP complements these
approaches by serving the growing number of mid-volume applications which cannot bear
the development costs associated with leading-edge cell-based designs but which require
higher complexity than a Gate Array or FPGA solution.
ASIC Roadmap
CB-130
CB-12
CB-11
CBIC
CB-10VX
ISSP
Performance
CB-9VX
CB-8
System LSI
G/A
SoCLite
SoCLite+
ISSP1
System LSI
&
High Performance
SoC G/A
EA-9HD
CMOS-9HD
ISSP2
ce
rforman
High pe
CMOS-10HD
CMOS-N5
0.5 µ m
: Planning
0.35 µ m
0.25 µ m
0.18 µ m
0.13 µ m
0.10 µ m
Process technology
Advantages of ISSP
(1) System LSI with low overall development cost (engineering resources/mask NRE)
(2) New “Built-in” features (DFT, clocks, signal integrity) drastically provide “easy to design” .
(3) Includes many other benefits associated with Gate Array, Cell-Based and even FPGA
(4) Ability to leverage Cell-Based IP – allows quick migration to Cell-Based designs
(5) Small/Middle production volume capabilities with very quick turn around time
2
Pamphlet A16092EJ2V0PF
FEATURES (2/2)
Design turn around time (RTL to Prototypes)
Design Time Advantage
RTL design
ISSP
DFT
Verification
Design cycle times for complex ASICs
Manufacturing
are on the rise due to the need to insert FPGA
and verify DFT(Design For Test) and
to address deep sub-micron design
GateArray
issues such as signal integrity (SI).
Even in the FPGA world, it is not
CBIC
unusual to spend weeks to converge
on timing especially for higher utilized
0
4
8
12
16
20
24
large gate-count designs exceeding
Turn around time (week)
100 MHz clock speeds.
Users designing with ISSPs do not have to worry about a DFT impact to their design
cycle because an ISSP comes pre-configured with all testing technologies like SCAN,
BSCAN etc. The clock domains are also built into the ISSP, which results in additional
design time savings due to predictable timing and lower clock skew. The use of a high
performance process technology also enables the designer to achieve high clock speeds.
The Low Risk Advantage
The rising development and mask NRE costs of deep sub-micron ASICs make it more
difficult for mid-volume designers to target multiple re-spins of their prototypes. For early
stage products, there is also an additional risk involved in predicting the production
volumes necessary to amortize these development costs.
By providing a high performance solution, an easy design flow and an NRE typically
associated with Gate Arrays, an ISSP allows quick re-spins of prototypes and enables
products to reach mid-volume production at very reasonable costs. If the volumes
increase, ISSP users can migrate to NEC Electronics’s Cell Based products which are
built on the same process technology and based on same IP and design flow.
Total volume vs Total cost
Most cost effective device zone
FPGA
CBIC
CBIC Zone
10K-100K
Total volume
Total cost
ISSP
ISSP Zone
100-1K
FPGA Zone
100-1K
Total volume
10K-100K
Life cycle
Total cost = Engineering cost + Mask NRE + Total volume x Unit cost
Pamphlet A16092EJ2V0PF
3
PRODUCT OUTLINE (ISSP1-STD Family)
NEC Electronics’s first generation of ISSP platforms known as the ISSP1-STD family includes
embedded high density SRAM, Analog PLLs (APLL), and Delay-Locked Loops (DLL). ISSP1-STD
family is based on NEC Electronics’s production-proven UX4 CMOS process technology with 5
metal layer (aluminum) technology. It features advanced 0.13 µ m (drawn) transistors, which
enables up to 300 MHz system clock speeds and a 1.5 V core voltage, which results in low-power
dissipation.
This product applies a complex multi gates architecture to the user-defined logic area. The lower
3 metal layers are predefined for the interconnection related to the embedded IP cores, the built-in
testing (DFT) circuits, clock domains and power lines. The upper 2 metal layers are used for
customization of the users design.
The ISSP1-STD is a versatile platform and is targeted to support several major applications such
as high performance broadband communication and networking equipments, computer
peripherals, instrumentation and digital consumer products.
In the future NEC Electronics is planning to introduce ISSP platforms with embedded processor
cores and high speed interface macros.
Chip Structure of ISSP1-STD Family
Embedded APLL
Embedded DLL
APLL
APLL
DLL
Embedded clock
Complex Multi Gates
DLL
eRAM
eRAM
eRAM
eRAM
eRAM
Embedded SRAM
eRAM
CLK
Test circuit
BSCAN
Multi-SCAN
BIST
TESTBUS
eRAM
eRAM
eRAM
eRAM
eRAM
eRAM
DLL
DLL
APLL
APLL
Planned ISSP1-STD Family Master Offering
Master
4
Usable gates
Embedded SRAM size
(bit)
Embedded SRAM block
(16 K bit)
µPD65701
227 K
16
µPD65702
530 K
48
µPD65703
1,109 K
64
262,144
li
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P
r
a
n
mi
y
Package (TBGA)
352
420
786,432
352
500
696
1,048,576
500
576
696
Pamphlet A16092EJ2V0PF
Specification for ISSP1-STD Family
Process
0.13 µ m (drawn) Si gate CMOS, 5 metal layers
Maximum usable gates
1 M gates (Usable)
Packages Note
352 / 420 / 500 / 576 / 696 TBGA
Supply voltage
Internal : 1.5V
Interface : 2.5V / 3.3V, other high speed interfaces
Power dissipation
0.014 µ W/MHz/gate (@Operating ratio: 0.3)
Maximum frequency
300 MHz
Interface
3.3V / 2.5V LVTTL
3.3V PCI, PCI-X
LVDS, HSTL, SSTL, PECL, others
Embedded cores
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a
in
SRAM : 1/2 port compile type synchronous (Max: 1M bit)
APLL : High / Middle speed type
DLL : for High speed DRAM interface
Soft cores
SRAM : Distributed compiled type synchronous SRAM
UART, EthernetTM MAC, Memory interface, others
Embedded clocks
Main clock : 2
Local clock : 8
Embedded testing
SCAN, BSCAN, BIST, TESTBUS
Note The number of usable signal pins depend on each package.
Pamphlet A16092EJ2V0PF
5
MEMO
6
Pamphlet A16092EJ2V0PF
Ethernet is a trademark of XEROX Corporation USA.
These commodities, technology or software, must be exported in accordance
with the export administration regulations of the exporting country.
Diversion contrary to the law of that country is prohibited.
• The information in this document is current as of November, 2002. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data
sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not
all products and/or types are available in every country. Please check with NEC Electronics sales
representative for availability and additional information.
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others.
• Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
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or third parties arising from the use of these circuits, software and information.
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redundancy, fire-containment and anti-failure features.
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The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
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(Note)
(1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
(2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
M8E 02. 11
Pamphlet A16092EJ2V0PF
7
For further information, please contact:
NEC Electronics Corporation
1753, Shimonumabe, Nakahara-ku,
Kawasaki, Kanagawa 211-8668, Japan
Tel: 044-435-5111
http://www.necel.com/
[North & South America]
[Europe]
[Asia & Oceania]
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800-366-9782
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800-729-9288
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40472 Düsseldorf, Germany
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G02.11
Document No. A16092EJ2V0PF00 (2nd edition)
Date Published November 2002 NS CP(K)
C
2002
Printed in Japan