DATA SHEET MOS INTEGRATED CIRCUIT µPD98408 6-PORT 25M ATM PHY LSI The µPD98408 is an ATM physical layer LSI IC that complies with ATM25 (25.6 Mbps) and which supports TC sublayer and PMD sublayer functions. Interfacing with the ATM layer and AAL layer LSI is implemented at UTOPIA Level 2. FEATURES • Provides a 25.6-Mbps ATM PHY (PMD & TC) function for six circuits • Conforms to the ATM Forum PHY interface specifications (af-phy-0040.000 November 1995). • UTOPIA Level 2 V1.0 (af-phy-0039.000 June 1995: max. 8 bits/40 MHz) interface • Three-cell built-in transmit/receive FIFOs for each circuit • PMD sublayer functions: (a) Built-in clock recovery. (b) Built-in equalizer. • TC sublayer functions: (a) NRZI encoder/decoder. (b) Command byte insertion/detection. (c) 4B/5B encoder/decoder. (d) Cell scrambler/descrambler. (e) HEC generation/verification. • CPU interface: Intel or Motorola can be selected. • Supports STP and UTP (Categories 3, 4, 5). • Loopback function: Loopback in the PMD and ATM layers. • Operation And Maintenance (OAM) functions: Input failure detection, HEC error detection and 4B/5B code error detection. • Test function: Supports JTAG. • Power supply voltage: 3.3 V ± 5 %. ORDERING INFORMATION Part Number Package µPD98408GD-LML 208-pin plastic QFP (fine pitch) (28 × 28 mm) Remark This document indicates active low pins in the format of "xxx_B" (_B after the pin name). The information in this document is subject to change without notice. Document No. S12313EJ2V1DS00 (2nd edition) Date Published April 1998 J CP(K) Printed in Japan © 1997 µPD98408 SYSTEM CONFIGURATION EXAMPLE (APPLICATION) ATM switching hub µ PD98408 … … #5 NIC UTOPIA Level 2 #0 UTOPIA Level 2 NIC µPD98408 Backbone network 25-Mbps ATM interface using UTP (Category 3) CPU 2 UTOPIA Level 2 UTOPIA Level 2 ATM-SW NIC SONET-IF BLOCK DIAGRAM JTAG interface µ PD98408 TEST interface Receive data Receive FIFO UTOPIA interface Magnetic module Equalizer UTP/STP (cat.3/4/5) Receiver PMD loopback 1 Clock/data recovery NRZI decoder 4B/5B decoder (command byte detection) Descrambler HEC verification PMD loopback 2 ATM layer UTOPIA Level 2 loopback NRZI encoder Transmitter Idle/unassigned cell detector 4B/5B encoder (command byte insertion) Scrambler Transmit data HEC generation Transmit FIFO PMD TC CPU interface CPU bus 3 µPD98408 Transmit clock (32 MHz) µPD98408 PIN LAYOUT RDIP0 RDIN0 TDOP0 TDON0 RxSOC RxENB_B RxADDR0 - RxADDR4 TxDATA0 - TxDATA7 TxSOC TxADDR0 - TxADDR4 5 TxCLAV µ PD98408 (NEASCOT - T20TM) DATA0 - DATA7 ADDR0 - ADDR5 SEL_B ... ... 8 TxENB_B RW_B/WR_B DS_B/RD_B DTACK_B/RDY_B INT_B TCLOCK RESET_B SIN/TDATA5 SOUT BUSMODE Timing marker 4 ATM layer interface TxCLK JCK/TCLK1 JMS/TCLK2 JRST_B/TCLK3 IC/RCLK5 IC/TDATA0 IC/RDATA4 IC/RDATA5 IC/TDATA1 IC/TDATA2 IC/TDATA3 IC/TDATA4 PMDONLY 5 RxCLAV JDI/TCLK0 JDO/RDATA0 Interface for external TC 8 RxCLK RDIP5 RDIN5 TDOP5 TDON5 IC/TCLK4 IC/TCLK5 RECCLK/RDATA1 IC/RDATA3 IC/RDADA2 IC/RCLK0 DGND RxDATA0 - RxDATA7 ... UTP/STP interface AGND AGND AGND AGND AGND AGND AGND ... ... DVDD ... ... AVDD AVDD AVDD Power supply AVDD AVDD AVDD 3.3 V Transmit clock (32 MHz) Reset 8 6 CPU interface µPD98408 PIN CONFIGURATION (TOP VIEW) 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 AGND TDOP5 TDON5 AGND AVDD AVDD AGND RDIP4 RDIN4 AVDD AGND TDOP4 TDON4 AGND AVDD AVDD AGND RDIP3 RDIN3 AVDD AGND TDOP3 TDON3 AGND AVDD AVDD AGND RDIP2 RDIN2 AVDD AGND TDOP2 TDON2 AGND AVDD AVDD AGND RDIP1 RDIN1 AVDD AGND TDOP1 TDON1 AGND AVDD AVDD AGND RDIP0 RDIN0 AVDD AGND AVDD 208-pin plastic QFP (fine pitch) (28 × 28 mm) AVDD TDOP0 TDON0 AGND AGND AVDD AGND AVDD AGND AVDD AGND IC IC DVDD DGND BUSMODE DS_B/RD_B RW_B/WR_B SEL_B DTACK_B/RDY_B INT_B DGND ADDR0 ADDR1 ADDR2 DGND DVDD ADDR3 ADDR4 ADDR5 DGND DATA0 DATA1 DGND DATA2 DATA3 DVDD DATA4 DATA5 DGND DATA6 DATA7 DGND CG TxENB_B TxCLAV DVDD TxSOC TxADDR0 TxADDR1 DGND DGND 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 DVDD SOUT RESET_B DGND TCLOCK DGND RxDATA7 RxDATA6 DVDD RxDATA5 RxDATA4 DGND RxDATA3 RxDATA2 DGND RxDATA1 RxDATA0 DVDD RxCLK DGND RxADDR4 RxADDR3 DGNG RxADDR2 RxADDR1 DVDD DGND RxADDR0 RxSOC DGND RxCLAV RxENB_B IC DVDD TxDATA7 TxDATA6 DGND TxDATA5 TxDATA4 DGND TxDATA3 TxDATA2 DVDD TxDATA1 TxDATA0 DGND TxCLK DGND TxADDR4 TxADDR3 TxADDR2 DVDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 µPD98408GD-LML AVDD RDIN5 RDIP5 AGND IC IC AGND AVDD AGND AVDD AGND AVDD AGND IC IC DVDD DGND PMDONLY IC/RCLK0 IC/RCLK1 IC/RCLK2 DGND IC/RCLK3 IC/RCLK4 IC/RCLK5 DGND DVDD JDI/TCLK0 JCK/TCLK1 JMS/TCLK2 DGND JRST_B/TCLK3 IC/TCLK4 IC/TCLK5 DVDD JDO/RDATA0 RECCLK/RDATA1 IC/RDATA2 DGND IC/RDATA3 IC/RDATA4 IC/RDATA5 DGND IC/TDATA0 IC/TDATA1 IC/TDATA2 DVDD IC/TDATA3 IC/DATA4 SIN/TDATA5 DGND DGND 5 µPD98408 PIN NAMES ADDR0-ADDR5 : Address RxADDR0-RxADDR4: Receive address AGND : Analog ground RxCLAV : Receive cell available AVDD : Analog supply voltage RxCLK : Receive data clock BUSMODE : Bus mode RxDATA0RxDATA7 : Receive data CG : Connect GND RxENB_B : Receive enable DATA0-DATA7 : Data RxSOC : Receive start address of ATM cell DGND : Digital ground SEL_B : Selector DS_B/RD_B : Data strove/read SIN/TDATA5 : Signal in/transmit data DTACK_B/RDY_B : Data acknowledge/ready SOUT : Signal out DVDD : Digital supply voltage TCLOCK : Transmit clock IC : Internal connect TDON0-TDON5 : Transmit data output negative IC/RCLK0-IC/RCLK5 : Internal connect/receive clock TDOP0-TDOP5 : Transmit data output positive IC/RDATA2-IC/RDATA5: Internal connect/receive data TxADDR0TxADDR4 : Transmit address IC/TCLK4, IC/TCLK5 TxCLAV : Transmit cell available IC/TDATA0-IC/TDATA4 : Internal connect/transmit data TxCLK : Transmit data clock INT_B : Interrupt TxDATA0-TxDATA7 : Transmit data JCK/TCLK1 : JTAG test clock/transmit clock TxENB_B : Transmit enable JDI/TCLK0 : JTAG test data input/transmit clock TxSOC : Transmit start address of ATM cell JDO/RDATA0 : JTAG test data output/recieve data JMS/TCLK2 : JTAG test mode select/transmit clock JRST_B/TCLK3 : JTAG test reset/transmit clock PMDONLY : PMD only RDIN0-RDIN5 : Receive data input negative RDIP0-RDIP5 : Receive data input positive RECCLK/RDATA1 : Recovery clock/receive data RESET_B : Reset RW_B/WR_B : Read write/write 6 : Internal connect/transmit clock µPD98408 CONTENTS 1. PIN FUNCTIONS ................................................................................................................................ 8 1.1 Power Supply .............................................................................................................................. 8 1.2 UTP/STP Interface ...................................................................................................................... 9 1.3 UTOPIA Interface ...................................................................................................................... 10 1.4 CPU Interface ............................................................................................................................ 11 1.5 Other Pins.................................................................................................................................. 12 1.6 Handling Unused Pins ............................................................................................................... 15 1.7 Pin States at Reset.................................................................................................................... 16 2. ELECTRICAL CHARACTERISTICS ................................................................................................ 17 3. PACKAGE DRAWING...................................................................................................................... 29 4. RECOMMENDED SOLDERING CONDITIONS ............................................................................... 30 7 µPD98408 1. PIN FUNCTIONS 1.1 Power Supply Pin Name Pin No. I/O Active Level Function AVDD 1, 8, 10, 12, 147, 149, 151, 156, 157,159, 163, 164, 169,173, 174, 179, 183,184, 189, 193, 194,199, 203, 204 − − +3.3-V power supply pins for analog circuits. DVDD 16, 27, 35, 47, 53, 61, 70, 78, 86, 95, 104, 110, 120, 130, 143 − − +3.3-V power supply pins for digital circuits. AGND 4, 7, 9, 11, 13, 146, 148, 150, 152,153, 158, 162, 165,168, 172, 175, 178,182, 185, 188, 192,195, 198, 202, 205, 208 − − Analog circuit grounding pins. DGND 17, 22, 26, 31, 39, 43, 51, 52, 56, 58, 64, 67, 72, 75, 79, 82, 89, 92, 98, 100, 105, 106, 114, 117, 123, 126, 131, 135, 142 − Digital circuit grounding pins. Caution On the PC board layout, AGND and DGND should be connected to the same, wide plane. On the PC board layout, AVDD and DVDD should be connected to the same, wide plane. For details, refer to the User's Manual (S11409E). 8 µPD98408 1.2 UTP/STP Interface Pin Name RDIP0 Pin No. I/O Active Level 161 I − Receive data inputs from circuit #0 (analog balanced signal Function RDIN0 160 I − inputs). TDOP0 155 O − Transmit data outputs to circuit #0 (analog balanced signal TDON0 154 O − outputs). RDIP1 171 I − Receive data inputs from circuit #1 (analog balanced signal RDIN1 170 I − inputs). TDOP1 167 O − Transmit data outputs to circuit #1 (analog balanced signal TDON1 166 O − outputs). RDIP2 181 I − Receive data inputs from circuit #2 (analog balanced signal RDIN2 180 I − inputs). TDOP2 177 O − Transmit data outputs to circuit #2 (analog balanced signal outputs). TDON2 176 O − RDIP3 191 I − Receive data inputs from circuit #3 (analog balanced signal RDIN3 190 I − inputs). TDOP3 187 O − Transmit data outputs to circuit #3 (analog balanced signal TDON3 186 O − outputs). RDIP4 201 I − Receive data inputs from circuit #4 (analog balanced signal RDIN4 200 I − inputs). TDOP4 197 O − Transmit data outputs to circuit #4 (analog balanced signal TDON4 196 O − outputs). RDIP5 3 I − Receive data inputs from circuit #5 (analog balanced signal RDIN5 2 I − inputs). TDOP5 207 O − Transmit data outputs to circuit #5 (analog balanced signal TDON5 206 O − outputs). 9 µPD98408 1.3 UTOPIA Interface Pin Name Active Level Pin No. I/O 69, 68, 66, 65, 63, 62, 60, 59 O Tristate − 8-bit data bus used for receive data output to the ATM layer device. Data is output in sync with the positive-going edge of RxCLK. RxCLK 71 I − Input pin of the clock for receive data transfer to the ATM layer device. RxSOC 81 O Tristate H Receive cell start address signal output, which outputs the signal for informing the ATM layer device of the start byte position of the receive cell. The start byte position is that position where RxSOC = 1. RxENB_B 84 I L RxDATA0-RxDATA7 and RxSOC output enable signal input. When 0 is input, outputs RxDATA0-RxDATA7 and RxSOC are enabled. RxADDR0RxADDR4 80, 77, 76, 74, 73 I − Input pins for the signal indicating the address of the µPD98408. 83 O Tristate H Cell receive available signal output. Becomes 1 when the µPD98408 has an output cell. 97, 96, 94, 93, 91, 90, 88, 87 I − 8-bit data bus used for transmit data input to the ATM layer device. Data is input in sync with the positive-going edge of TxCLK. TxCLK 99 I − Input pin of the clock for the transmit data transfer to the ATM layer device TxSOC 109 I H Transmit cell start address signal input, which inputs the signal indicating the start byte position of the transmit cell input from the ATM layer device. The start byte position is that position where TxSOC = 1. TxENB_B 112 I L Transmit enable signal input, which inputs a signal indicating that the ATM layer device is outputting valid transmit data at TxDATA0-TxDATA7. 0 for enable and 1 for disable. TxADDR0TxADDR4 108, 107, 103, 102, 101 I − Input pins of the signal indicating the address of the µPD98408 which transmits data 111 O Tristate H Cell transmit available signal output. Goes to 1 when the µPD98408 is ready to receive a cell. RxDATA0RxDATA7 RxCLAV TxDATA0TxDATA7 TxCLAV 10 Function µPD98408 1.4 CPU Interface Pin Name BUSMODE Pin No. I/O Active Level 141 I − Function Selects the CPU interface operation mode. 0: <DS_B, RW_B, DTACK_B> style (Motorola compatible) 1: <RD_B, WR_B, RDY_B> style (Intel compatible) DATA0DATA7 125, 124, 122, 121, 119, 118, 116, 115 I/O − Used to transfer data between the CPU and an internal register (8-bit). The MSB is DATA7. ADDR0ADDR5 134, 133, 132, 129, 128, 127 I − Used to set the address of an internal register (6-bit). SEL_ B 138 I L DS_B/RD_B 140 I L/L Register access enable signal. 0 for enable. • When BUSMODE = 0, becomes the data strobe signal (DS_B) of the Motorola-compatible interface. In read cycle: DS_B = 0 for read data enable. In write cycle: DS_B = 0 for write data strobe. • When BUSMODE = 1, becomes the read instruction signal of the Intel-compatible interface. RD_B = 0 for read instruction. RW_B/WR_B 139 I L/L • When BUSMODE = 0, becomes the read/write control signal (RW_B) of the Motorola-compatible interface. 0: Write cycle 1: Read cycle • When BUSMODE = 1, becomes the write instruction signal of the Intel-compatible interface. WR_B = 0 for write instruction. DTACK_B/ RDY_B 137 O L/L • When BUSMODE = 0, becomes the data acknowledge signal (DTACK_B) of the Motorola-compatible interface. This signal indicates the completion of data transmission over the data bus. DTACK_B is set to 0 upon the completion of data transmission. • When BUSMODE = 1, becomes the ready signal (RDY_B) of the Intel-compatible interface. This signal indicates the completion of data transmission over the data bus. RDY_B is set to 0 upon the completion of data transmission. INT_B 136 O L Notifies the CPU of the occurrence of an interrupt factor. 11 µPD98408 1.5 Other Pins (1/3) Pin Name JDI/TCLK0 Pin No. I/O Active Level 28 I −/− Function Two pin functions can be selected according to the level of the PMDONLY pin. • When PMDONLY = 0 (JDI): JTAG test data input pin. • When PMDONLY = 1 (TCLK0): Input pin for transmit clock for the PMD transmitter (Circuit 0). JDO/ RDATA0 36 O −/− Two pin functions can be selected according to the level of the PMDONLY pin. • When PMDONLY = 0 (JDO): JTAG test data output pin. • When PMDONLY = 1 (RDATA0): Output pin for data received from the PMD receiver (Circuit 0). JCK/TCLK1 29 I −/− Two pin functions can be selected according to the level of the PMDONLY pin. • When PMDONLY = 0 (JCK): JTAG test clock input pin. • When PMDONLY = 1 (TCLK1): Input pin for transmit clock for the PMD transmitter (Circuit 1). JMS/TCLK2 30 I −/− Two pin functions can be selected according to the level of the PMDONLY pin. • When PMDONLY = 0 (JMS): JTAG test mode input pin. • When PMDONLY = 1 (TCLK2): Input pin for transmit clock for the PMD transmitter (Circuit 2). JRST_B/ TCLK3 32 I L/− Two pin functions can be selected according to the level of the PMDONLY pin. • When PMDONLY = 0 (JRST_B): JTAG test reset signal input pin. • When PMDONLY = 1 (TCLK3): Input pin for transmit clock for the PMD transmitter (Circuit 3). IC/TCLK4 33 I (with pulldown resistor) −/− Two pin functions can be selected according to the level of the PMDONLY pin. • When PMDONLY = 0 (IC): No signal should be connected to this pin. • When PMDONLY = 1 (TCLK4): Input pin for transmit clock for the PMD transmitter (Circuit 4). IC/TCLK5 34 I (with pulldown resistor) −/− Two pin functions can be selected according to the level of the PMDONLY pin. • When PMDONLY = 0 (IC): No signal should be connected to this pin. • When PMDONLY = 1 (TCLK5): Input pin for transmit clock for the PMD transmitter (Circuit 5). 12 µPD98408 (2/3) Pin Name RECCLK/ RDATA1 Pin No. I/O Active Level 37 O −/− Function Two pin functions can be selected according to the level of the PMDONLY pin. • When PMDONLY = 0 (RECCLK): Output pin for the recovery clock on the receive data. The recovery clock of circuit 0 is output. • When PMDONLY = 1 (RDATA1): Output pin for data received from the PMD receiver (Circuit 1). IC/RDATA3 40 O −/− Two pin functions can be selected according to the level of the PMDONLY pin. • When PMDONLY = 0 (IC): No signal should be connected to this pin. • When PMDONLY = 1 (RDATA3): Output pin for data received from the PMD receiver (Circuit 3). IC/RDATA2 38 O −/− Two pin functions can be selected according to the level of the PMDONLY pin. • When PMDONLY = 0 (IC): No signal should be connected to this pin. • When PMDONLY = 1 (RDATA2): Output pin for data received from the PMD receiver (Circuit 2). IC/ RCLK0RCLK5 19, 20, 21, 23, 24, 25 O/I (with pulldown resistor) −/− Two pin functions can be selected according to the level of the PMDONLY pin. • When PMDONLY = 0 (IC): • When PMDONLY = 1 (RCLK0-RCLK5): No signal should be connected to these pins. Output pins for the clock received from the PMD receiver (Circuits 0 to 5). IC/TDATA0 44 I (with pulldown resistor) −/− Two pin functions can be selected according to the level of the PMDONLY pin. • When PMDONLY = 0 (IC): • When PMDONLY = 1 (TDATA0): No signal should be connected to this pin. Input pin for transmit data for the PMD transmitter (Circuit 0). IC/RDATA4 41 O −/− Two pin functions can be selected according to the level of the PMDONLY pin. • When PMDONLY = 0 (IC): • When PMDONLY = 1 (RDATA4): No signal should be connected to this pin. Output pin for the data received from the PMD receiver (Circuit 4). 13 µPD98408 (3/3) Pin Name IC/RDATA5 Pin No. I/O Active Level 42 O −/− Function Two pin functions can be selected according to the level of the PMDONLY pin. • When PMDONLY = 0 (IC): No signal should be connected to this pin. • When PMDONLY = 1 (RDATA5): Output pin for the data received from the PMD receiver (Circuit 5). IC/TDATA1 45 I (with pulldown resistor) −/− Two pin functions can be selected according to the level of the PMDONLY pin. • When PMDONLY = 0 (IC): No signal should be connected to this pin. • When PMDONLY = 1 (TDATA1): Input pin for transmit data for the PMD transmitter (Circuit 1). IC/TDATA2 46 I (with pulldown resistor) −/− Two pin functions can be selected according to the level of the PMDONLY pin. • When PMDONLY = 0 (IC): No signal should be connected to this pin. • When PMDONLY = 1 (TDATA2): Input pin for transmit data for the PMD transmitter (Circuit 2). IC/TDATA3 48 I (with pulldown resistor) −/− Two pin functions can be selected according to the level of the PMDONLY pin. • When PMDONLY = 0 (IC): No signal should be connected to this pin. • When PMDONLY = 1 (TDATA3): Input pin for transmit data for the PMD transmitter (Circuit 3). IC/TDATA4 49 I (with pulldown resistor) −/− Two pin functions can be selected according to the level of the PMDONLY pin. • When PMDONLY = 0 (IC): No signal should be connected to this pin. • When PMDONLY = 1 (TDATA4): Input pin for transmit data for the PMD transmitter (Circuit 4). SIN/TDATA5 50 I (with pulldown resistor) H/− Two pin functions can be selected according to the level of the PMDONLY pin. • When PMDONLY = 0 (SIN): X_8 command transmit timing signal input pin. • When PMDONLY = 1 (TDATA5): Input pin for transmit data for the PMD transmitter (Circuit 5). SOUT 54 O H X_8 command receive timing signal output pin. PMDONLY 18 I (with pulldown resistor) − Specifies the mode of the µPD98408: whether it is operated as PMD + TC or as PMD only. I − Transmit clock (32 MHz) input pin 0: Operation as PMD + TC. 1: Operation as PMD only. TCLOCK 57 RESET_B 55 I L Input pin for the reset signal for the entire µPD98408. IC 5, 6, 14, 15, 85, 144, 145 − − No signal should be connected to these pins. CG 113 I − Should be connected to GND for normal use. 14 µPD98408 1.6 Handling Unused Pins Pin Name I/O Recommended Connection When Not in Use RDIP0-RDIP5 I Pull up with a resistor (1 kΩ). RDIN0-RDIN5 I Pull up with a resistor (1 kΩ). TDOP0-TDOP5 O Open. TDON0-TDON5 O Open. JDI/TCLK0 I Pull up with a resistor. JDO/RDATA0 O Open. JCK/TCLK1 I Pull up with a resistor. JMS/TCLK2 I Pull up with a resistor. JRST_B/TCLK3 I Pull up with a resistor. IC/TCLK4 I (with pull-down resistor) Open. IC/TCLK5 I (with pull-down resistor) Open. RECCLK/RDATA1 O Open. IC/RDATA3 O Open. IC/RDATA2 O Open. IC/RCLK0-IC/RCLK5 I/O (with pull-down resistor) Open. IC/TDATA0 I (with pull-down resistor) Open. IC/RDATA4 O Open. IC/RDATA5 O Open. IC/TDATA1 I (with pull-down resistor) Open. IC/TDATA2 I (with pull-down resistor) Open. IC/TDATA3 I (with pull-down resistor) Open. IC/TDATA4 I (with pull-down resistor) Open. SIN/TDATA5 I (with pull-down resistor) Open. SOUT O Open. PMDONLY I (with pull-down resistor) Open. 15 µPD98408 1.7 Pin States at Reset Pin Name I/O Pin States at Reset TDOP0-TDOP5 O Not defined TDON0-TDON5 O Not defined RxDATA0-RxDATA7 Tristate O Hi-Z RxSOC Tristate O Hi-Z RxCLAV Tristate O Hi-Z TxCLAV Tristate O Hi-Z DATA0-DATA7 I/O Hi-Z DTACK_B/RDY_B O High level INT_B O High level JDO/RDATA0 O Not defined RECCLK/RDATA1 O Not defined SOUT O Low level 16 µPD98408 2. ELECTRIC CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Parameter Rating Unit VDD -0.5 to +4.6 V Input voltage VI -0.5 to +6.6 V Output voltage VO -0.5 to +6.6 V Output current IO1 Note 1 10 mA IO2 Note 2 30 mA -65 to +150 °C Power supply voltage Storage temperature Symbol Conditions Tstg Caution Absolute maximum ratings are rated values beyond which physical damage will be caused to the product; if the rated value of any of the parameters in the above table is exceeded, even momentarily, the quality of the product may deteriorate. Always use the product within its rated values. Notes 1. Applies to pins JDO/RDATA0, RECCLK/RDATA1, IC/RDATA2, IC/RDATA3, IC/RDATA4, IC/RDATA5, SOUT, and IC/RCLK0-IC/RCLK5. 2. Applies to pins RxDATA0-RxDATA7, RxSOC, RxCLAV, TxCLAV, INT_B, DTACK_B/RDY_B, and DATA0-DATA7. RECOMMENDED OPERATING CONDITIONS Parameter Symbol Conditions MIN. TYP. MAX. Unit Power supply voltage VDD 3.135 3.3 3.465 V High-level input voltage VIH 2.0 − 5.5 V Low-level input voltage VIL 0 − 0.8 V Operating ambient temperature TA -40 − +85 °C 17 µPD98408 DC CHARACTERISTICS (TA = -40 to +85 °C, VDD = 3.3 V ± 5 %) Parameter Input leakage current High-level output current Symbol IL IOH1 Conditions VI = VDD or GND VOH = 2.4 V MIN. TYP. MAX. Unit − − 2 µA -3.0 − − mA -8.0 − − mA 3.0 − − mA 9.0 − − mA Note 1 IOH2 VOH = 2.4 V Note 2 Low-level output current IOL1 VOL = 0.4 V Note 1 IOL2 VOL = 0.4 V Note 2 VOH1 IOH = 0 mA Note 3 VDD - 0.4 − − V VOH2 IOH = 0 mA When Note 3 is not applied VDD - 0.2 − − V Low-level output voltage VOL IOL = 0 mA − − 0.1 V Supply current IDD In operation − 180 280 mA High-level output voltage Notes 1. Applies to pins JDO/RDATA0, RECCLK/RDATA1, IC/RDATA2, IC/RDATA3, IC/RDATA4, IC/RDATA5, SOUT, and IC/RCLK0-IC/RCLK5. 2. Applies to pins RxDATA0-RxDATA7, RxSOC, RxCLAV, TxCLAV, INT_B, DTACK_B/RDY_B, and DATA0-DATA7. 3. Applies to pins IC/RCLK0-IC/RCLK5 only when 1 is input to the PMDONLY pin (only PMD operates). 18 µPD98408 CAPACITANCE Parameter Symbol Conditions MIN. TYP. MAX. Unit Input capacitance CI Frequency = 1 MHz − 10 20 pF Output capacitance CO Frequency = 1 MHz − 10 20 pF I/O capacitance CIO Frequency = 1 MHz − 10 20 pF MIN. TYP. MAX. Unit AC Test I/O Waveform VDD 0.5VDD Test points 0V AC CHARACTERISTICS (TA = -40 to +85 °C, VDD = 3.3 V ± 5 %) TCLOCK Parameter Symbol Conditions TCLOCK frequency t1-1 − 32 − MHz TCLOCK duty t1-2 40 − 60 % TCLOCK frequency accuracy t1-3 − − 100 ppm TCLOCK rise time t1-4 Measurement of 10 to 90 % transition time − − 5 ns TCLOCK fall time t1-5 Measurement of 10 to 90 % transition time − − 5 ns TCLOCK Input t1-3 cycle TCLOCK t1-2 (min.) t1-2 (max.) t1-1 = 1/cycle TCLOCK t1-4 t1-5 19 µPD98408 CPU INTERFACE (1) Write operation (when BUSMODE = 1) Parameter MIN. TYP. MAX. Unit t2-1 10 − − ns t2-2 5 − − ns WR_B pulse width t2-3 50 − − ns DATA setup time t2-4 16 − − ns t2-5 4 − − ns t2-6 − − 10 ns t2-7 0 − − ns ADDR setup time Symbol Conditions (referred to WR_B↓) SEL_B setup time (referred to WR_B↓) (referred to WR_B↑) ADDR/DATA hold time (referred to WR_B↑) RDY_B disable time (referred to WR_B↑) SEL_B hold time (referred to WR_B↑) CPU Interface Write Operation (BUSMODE = 1) ADDR0 -ADDR5 t2-1 t2-5 SEL_B t2-4 DATA0 -DATA7 t2-2 t2-3 WR_B t2-7 RD_B t2-6 RDY_B 20 µPD98408 (2) Read operation (when BUSMODE = 1) Parameter MIN. TYP. MAX. Unit t2-10 10 − − ns t2-11 5 − − ns RD_B pulse width t2-12 50 − − ns DATA fixed time t2-13 − − 10 ns t2-14 4 − − ns t2-15 − − 10 ns t2-16 0 − − ns t2-17 0 − − ns ADDR setup time Symbol Conditions (referred to RD_B↓) SEL_B setup time (referred to RD_B↓) (referred to RDY_B↓) ADDR hold time (referred to RD_B↑) RDY_B disable time (referred to RD_B↑) SEL_B hold time (referred to RD_B↑) DATA invalid/tristate time (referred to RD_B↑) CPU Interface Read Operation (BUSMODE = 1) ADDR0 -ADDR5 t2-14 t2-10 SEL_B t2-17 t2-11 DATA0 -DATA7 t2-13 t2-12 RD_B t2-16 WR_B t2-15 RDY_B 21 µPD98408 (3) Write operation (when BUSMODE = 0) Parameter MIN. TYP. MAX. Unit t2-1 10 − − ns t2-2 5 − − ns DS_B pulse width t2-3 50 − − ns DATA setup time t2-4 15 − − ns t2-5 4 − − ns t2-6 − − 10 ns t2-7 0 − − ns ADDR setup time Symbol Conditions (referred to DS_B↓) SEL_B or RW_B setup time (referred to DS_B↓) (referred to DS_B↑) ADDR/DATA hold time (referred to DS_B↑) DTACK_B disable time (referred to DS_B↑) SEL_B or RW_B hold time (referred to DS_B↑) CPU Interface Write Operation (BUSMODE = 0) ADDR0 -ADDR5 t2-1 t2-5 SEL_B t2-4 DATA0 -DATA7 t2-2 t2-3 DS_B t2-7 RW_B t2-6 DTACK_B 22 µPD98408 (4) Read operation (when BUSMODE = 0) Parameter MIN. TYP. MAX. Unit t2-10 10 − − ns t2-11 5 − − ns DS_B pulse width t2-12 50 − − ns DATA fixed time t2-13 − − 10 ns t2-14 4 − − ns t2-15 − − 10 ns t2-16 0 − − ns t2-17 0 − − ns ADDR setup time Symbol Conditions (referred to DS_B↓) SEL_B or RW_B setup time (referred to DS_B↓) (referred to DTACK_B↓) ADDR hold time (referred to DS_B↑) DTACK_B disable time (referred to DS_B↑) SEL_B or RW_B hold time (referred to DS_B↑) DATA invalid/tristate time (referred to DS_B↑) CPU Interface Read Operation (BUSMODE = 0) ADDR0 -ADDR5 t2-14 t2-10 SEL_B t2-17 t2-11 DATA0 -DATA7 t2-13 t2-12 DS_B t2-16 RW_B t2-15 DTACK_B 23 µPD98408 UTOPIA INTERFACE (1) Transmission MIN. TYP. MAX. Unit TxCLK frequency Parameter Symbol t3-1 Conditions 0 − 40 MHz TxCLK duty cycle t3-2 40 − 60 % TxCLK jitter (peak to peak) t3-3 − − 5 % TxCLK rise time t3-4 Measurement of 10 to 90 % transition time − − 3 ns TxCLK fall time t3-5 Measurement of 10 to 90 % transition time − − 3 ns TxDATA[7:0], TxSOC, TxENB_B, or TxADDR[4:0] setup time t3-6 8 − − ns TxDATA[7:0], TxSOC, TxENB_B, or TxADDR[4:0] hold time t3-7 1 − − ns TxCLAV low-impedance delay time t3-8 8 − − ns TxCLAV high-impedance delay time (referred to TxCLK↑) t3-9 0 − − ns TxCLAV low-impedance delay time t3-10 1 − − ns t3-11 1 − − ns (referred to TxCLK↑) (referred to TxCLK↑) TxCLAV high-impedance delay time (referred to TxCLK↑) 24 µPD98408 (2) Reception Parameter Symbol Conditions MIN. TYP. MAX. Unit RxCLK frequency t3-12 0 − 40 MHz RxCLK duty cycle t3-13 40 − 60 % RxCLK jitter (peak to peak) t3-14 − − 5 % RxCLK rise time t3-15 Measurement of 10 to 90 % transition time − − 3 ns RxCLK fall time t3-16 Measurement of 10 to 90 % transition time − − 3 ns RxENB_B or RxADDR[4:0] t3-17 8 − − ns t3-18 1 − − ns t3-19 8 − − ns t3-20 0 − − ns t3-21 1 − − ns t3-22 1 − − ns setup time RxENB_B or RxADDR[4:0] hold time RxDATA[7:0], RxSOC, or RxCLAV low-impedance delay time (referred to RxCLK↑) RxDATA[7:0], RxSOC, or RxCLAV high-impedance delay time (referred to RxCLK↑) RxDATA[7:0], RxSOC, or RxCLAV low-impedance delay time (referred to RxCLK↑) RxDATA[7:0], RxSOC, or RxCLAV high-impedance delay time (referred to RxCLK↑) TxCLK or RxCLK Timing - 1 t3-3, t3-14 cycle TxCLK/RxCLK t3-2, t3-13 (min.) t3-2, t3-13 (max.) max. max. t3-1, t3-12 = 1/cycle 2.5 % 2.5 % TxCLK or RxCLK Timing - 2 TxCLK/RxCLK t3-4, t3-15 t3-5, t3-16 25 µPD98408 Input Signal Setup Timing TxCLK, RxCLK TxDATA[7:0], TxSOC, TxENB_B, TxADDR[4:0], RxENB_B, RxADDR[4:0] t3-6, t3-17 Input Signal Hold Timing TxCLK, RxCLK TxDATA[7:0], TxSOC, TxE NB_B, TxADDR[4:0], RxENB_B, RxADDR[4:0] t3-7, t3-18 Output Delay Time - 1 TxCLK, RxCLK TxCLAV, RxDATA[7:0], RxSOC, RxCLAV Hi-Z t3-8, t3-19 t3-10, t3-21 Output Delay Time - 2 TxCLK, RxCLK TxCLAV, RxDATA[7:0], RxSOC, RxCLAV Hi-Z t3-11, t3-22 26 t3-9, t3-20 µPD98408 PMDONLY MODE Parameter Symbol RxDATA delay time Conditions MIN. TYP. MAX. Unit t4-1 0.5 − 15.0 ns t4-2 8.0 − − ns t4-3 0.5 − − ns (referred to RxCLK↑) TxDATA setup time (referred to TxCLK↑) TxDATA hold time (referred to TxCLK↑) Reception Data Output Delay Time RxCLK0 -RxCLK5 RxDATA0 -RxDATA5 Hi-Z t4-1 Transmission Data Setup/Hold Time TxCLK0 -TxCLK5 TxDATA0 -TxDATA5 t4-2 t4-3 27 µPD98408 OTHERS Parameter Symbol Conditions MIN. TYP. MAX. Unit SIN pulse width t5-1 11 − − TCLOCK clock SOUT pulse width t5-2 − 15 − TCLOCK clock RESET_B pulse width t5-3 50 − − ns SIN and SOUT Timings TCLOCK 11 clocks SIN t5-1 11 clocks or more SOUT t5-2 15 clocks RESET_B Timing RESET_B t5-3 28 50 ns or more µPD98408 3. PACKAGE DRAWING 208 PIN PLASTIC QFP (FINE PITCH) (28x28) A B 156 157 105 104 detail of lead end S C D Q 208 1 R 53 52 F G H I J M P K N S NOTE 1. Each lead centerline is located within 0.12 mm of its true position (T.P.) at maximum material condition. S L M ITEM A MILLIMETERS 30.6±0.2 B 28.0±0.2 C 28.0±0.2 D 30.6±0.2 F 1.25 G 1.25 H 0.22 +0.05 −0.04 I 0.10 J K 0.5 (T.P.) 1.3±0.2 L 0.5±0.2 0.17 +0.03 −0.07 M N 0.10 P Q 3.2±0.1 0.4±0.1 R 5°±5° S 3.8 MAX. P208GD-50-LML, MML, SML-5 29 µPD98408 4. RECOMMENDED SOLDERING CONDITIONS The conditions listed below shall be met when soldering the µPD98408. For details of the recommended soldering conditions, refer to our document Semiconductor Device Mounting Technology Manual (C10535E). Please consult with our sales offices in case any other soldering process is used, or in case soldering is done under different conditions. Surface-Mount Type • µPD98408GD-LML: 208-pin plastic QFP (fine pitch) (28 × 28 mm) Soldering Process Infrared ray reflow Soldering Conditions Peak package's surface temperature: 235 °C Reflow time: 30 seconds or less (210 °C or more) Maximum allowable number of reflow processes: 2 Exposure limit: 7 days Note Symbol IR35-367-2 (36 hours of pre-baking is required at 125 °C afterward) <Caution> Non-heat-resistant trays, such as magazine and taping trays, cannot be baked before unpacking. Peak package's surface temperature: 215 °C Reflow time: 40 seconds or less (200 °C or more) Maximum allowable number of reflow processes: 2 VPS Exposure limit: 7 days Note VP15-367-2 (36 hours of pre-baking is required at 125 °C afterward) <Caution> Non-heat-resistant trays, such as magazine and taping trays, cannot be baked before unpacking. Partial heating method Note Terminal temperature: 300 °C or less Heat time: 3 seconds or less (for one side of a device) − Maximum number of days during which the product can be stored at a temperature of 25 °C and a relative humidity of 65 % or less after dry-pack package is opened. Caution 30 Do not apply two or more different soldering methods to one chip (except for partial heating method for terminal sections). µPD98408 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 31 µPD98408 NEASCOT-T20 is a trademark of NEC Corporation. The export of this product from Japan is prohibited without governmental license. To export or re-export this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC’s Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96. 5