USBDFxxW5 ® A.S.D. EMI FILTER AND LINE TERMINATION FOR USB DOWNSTREAM PORTS APPLICATIONS EMI Filter and line termination for USB downstream ports on: - Desktop computer - Notebooks - Workstations - USB Hubs FEATURES n Monolithic device with recommended line termination for USB downstream ports n Integrated Rt series termination and Ct bypassing capacitors. n Integrated ESD protection n Small package size DESCRIPTION The USB specification requires USB downstream ports to be terminated with pull-down resistors from the D+ and D- lines to ground. On the implementation of USB systems, the radiated and conducted EMI should be kept within the required levels as stated by the FCC regulations. In addition to the requirements of termination and EMC compatibility, the computing devices are required to be tested for ESD susceptibility. The USBDFxxW5 provides the recommended line termination while implementing a low pass filter to limit EMI levels and providing ESD protection which exceeds IEC 61000-4-2 level 4 standard. The device is packaged in a SOT323-5L which is the smallest available lead frame package (50% smaller than the standard SOT23). SOT323-5L FUNCTIONAL DIAGRAM Rt D+ Out D+ In Ct Rd Ct Rd Gnd D- In D- Out Rt BENEFITS n n n n n EMI / RFI noise suppression Required line termination for USB downstream ports ESD protection exceeding IEC61000-4-2 level 4 High flexibility in the design of high density boards Tailored to meet USB 1.1 standard Rt Rd Ct Code 01 33Ω 15kΩ 47pF Code 02 15Ω 15kΩ 47pF Tolerance ±10% ±10% ±20% TM: ASD and TRANSIL are a trademarks of STMicroelectronics. May 2000 Ed : 1C 1/9 USBDFxxW5 COMPLIES WITH THE FOLLOWING ESD STANDARDS: IEC-61000-4-2, level 4 ±15 kV (air discharge) ±8 kV (contact discharge) MIL STD 883C, Method 3015-6 Class 3 C = 100 pF R = 1500 Ω 3 positive strikes and 3 negative strikes (F = 1 Hz) ABSOLUTE MAXIMUM RATINGS (Tamb = 25°C) Symbol VPP Tj Parameter Value Unit ESD discharge IEC 61000-4-2, contact discharge ESD discharge - MIL STD 883 - Method 3015-6 ±15 ±25 kV kV Junction temperature 150 °C - 55 to +150 °C 260 °C 0 to 70 °C 100 mW Tstg Storage temperature range TL Lead solder temperature (10 second duration) Top Operating temperature Range Pr Power rating per resistor ELECTRICAL CHARACTERISTICS (Tamb = 25°C) Symbol Parameters VBR Diode breakdown voltage IR = 1mA VF Diode forward voltage drop IF = 50mA 2/9 Test conditions Min Typ 6 Max Unit V 0.9 V USBDFxxW5 APPLICATION INFORMATION Fig. A1: USB Standard requirements +Vbus 1.5k Rt Full-speed or Low-speed USB Transceiver D+ Ct Twisted pair shielded Rt Zo = 90ohms 5m max DHost or Hub port Ct 15k Rt D+ 15k Ct Full-speed USB Transceiver Ct Hub 0 or Full-speed function Ct Low-speed USB Transceiver Ct Hub 0 or Low-speed function Rt D- FULL SPEED CONNECTION +Vbus 1.5k D+ Rt Full-speed or Low-speed USB Transceiver D+ Ct Untwisted unshielded Rt 3m max DHost or Hub port Ct 15k Rt Rt D- 15k LOW SPEED CONNECTION APPLICATION EXAMPLE Downstream port D+ Upstream port CABLE D+ (1) D- (2) +Vbus USBDF xxW5 USBUF xxW6 D- Host/Hub USB port transceiver D- (1) D+ (2) Peripheral transceiver (1) for a low-speed port (2) for a full-speed port 3/9 USBDFxxW5 EMI FILTERING Current FCC regulations requires that class B computing devices meet specified maximum levels for both ratiated and conducted EMI. - Radiated EMI covers the frequency range from 30MHz to 1GHz. - Conducted EMI covers the 450kHz to 30MHz range. For the types of devices utilizing the USB the most difficult test to pass is usually the radiated EMI test. For this reason the USBDF device is aiming to minimize radiated EMI. The differential signal (D+ and D-) of the USB does not contribute significantly to radiated or conducted EMI because the magnetic field of the two conductors exactly cancels each other. The inside of the PC environment is very noisy and designers must minimise noise coupling from the different sources. D+ and D- must not be routed near high speed lines (clocks...). Induced common mode noise can be minimised by running pairs of USB signals parallel to each other and running grounded guard trace on each side of the signal pair from the USB controller to the USBDF device. If possible, locate the USBDF device physically near the USB connectors. Distance between the USB controller and the USB connector must be minimized. The 47pF (Ct) capacitors are used to bypass high frequency energy to ground and for edge control, and must be placed between the USB Controller and the series termination resistors (Rt). Both Ct and Rt should be placed as close to the USB Controller as practicable. The USBDFxxW5 ensure a filtering protection against ElectroMagnetic and RadioFrequency Interferences thanks to its low-pass filter structure. This filter is characterized by the following parameters : - cut-off frequency - Insertion loss - high frequency rejection Fig. A3 shows the attenuation curve for frequencies up to 3GHz. Fig. A2: Measurement configuration Fig. A3: USBDFxxW5 attenuation curve. Insertion loss (dB) 0 50 Ω TG OUT TEST BOARD RF IN -10 UD1 Vg 50 Ω -20 -30 1 10 100 F (MHz) 1000 3000 ESD PROTECTION In addition to the requirements of termination and EMC compatibility, computing devices are required to be tested for ESD susceptibility. This test is described in the IEC 61000-4-2 and is already in place in Europe. This test requires that a device tolerates ESD events and remain operational without user intervention. The USBDFxxW5 is particularly optimized to perform ESD protection. ESD protection is based on the use of device which clamps at : Vinput = VBR + Rd .IPP This protection function is splitted in 2 stages. As shown in figure A4, the ESD strikes are clamped by the first stage S1 and then its remaining overvoltage is applied to the second stage through the resistor R. Such a configuration makes the output voltage very low at the Vout level. 4/9 USBDFxxW5 Fig. A4: USBDFxxW5 ESD clamping behavior Rg S1 Rd VPP R Rd Vinput Rload Voutput VBR USBDFxxW5 ESD Surge S2 VBR Device to be protected To have a good approximation of the remaining voltages at both Vin and Vout stages, we give the typical dynamical resistance value Rd. By taking into account these following hypothesis : Rt>Rd, Rg>Rd and Rload>Rd, it gives these formulas: Rg .VBR + Rd .Vg Vinput = Rg Rt.VBR + Rd .Vinput Voutput = Rt The results of the calculation done for V PP=8kV, Rg=330Ω (IEC61000-4-2 standard), V BR=7V (typ.) and Rd = 1Ω (typ.) give: Vinput = 31.2 V Voutput = 7.95 V This confirms the very low remaining voltage across the device to be protected. It is also important to note that in this approximation the parasitic inductance effect was not taken into account. This could be few tenths of volts during few ns at the Vin side. This parasitic effect is not present at the Vout side due the low current involved after the resistance R. The measurements done here after show very clearly (Fig. A6) the high efficiency of the ESD protection : - no influence of the parasitic inductances on Vout stage - output clamping voltage very close to VBR (positive strike) and -VF (negative strike) Fig. A5: Measurement board ESD SURGE Vin UD1 16kV Air Discharge TEST BOARD Vout 5/9 USBDFxxW5 Fig. A6: Remaining voltage at both stages S1 (Vinput) and S2 (Voutput) during ESD surge. b.Negative surge a. Positive surge Please note that the USBDFxxW5 is not only acting for positive ESD surges but also for negative ones. For these kinds of disturbances it clamps close to ground voltage as shown in Fig. A6b. LATCH-UP PHENOMENA The early ageing and destruction of IC’s is often due to latch-up phenomena which is mainly induced by dV/dt. Thanks to its structure, the USBDFxxW5 provides a high immunity to latch-up phenomena by smoothing very fast edges. CROSSTALK BEHAVIOR Fig. A7: Crosstalk phenomena RG1 Line 1 VG1 RL1 RG2 VG2 Line 2 RL2 DRIVERS α1 VG1 + β12 VG2 α2 VG2 + β21 VG1 RECEIVERS The crosstalk phenomena is due to the coupling between 2 lines. The coupling factor ( β12 or β21 ) increases when the gap across lines decreases, this is the reason why we provide crosstalk measurements for monolithic device to guarantee negligeable crosstalk between the lines. In the example above the expected signal on load RL2 is α2VG2, in fact the real voltage at this point has got an extra value β21VG1. This part of the VG1 signal represents the effect of the crosstalk phenomenon of the line 1 on the line 2. This phenomenon has to be taken into account when the drivers impose fast digital data or high frequency analog signals in the disturbing line. The perturbed line will be more affected if it works with low voltage signal or high load impedance (few kΩ). 6/9 USBDFxxW5 Fig. A8: Analog Crosstalk measurements Fig. A9: Typical Analog Crosstalk results Analog crosstalk (dB) 0 -20 TEST BOARD 50 Ω TG OUT RF IN UD1 -40 50 Ω Vg -60 -80 -100 1 10 100 frequency (MHz) 1,000 Figure A8 gives the measurement circuit for the analog crosstalk application. In figure A9, the curve shows the effect of the D+ cell on the D- cell. In usual frequency range of analog signals (up to 100MHz) the effect on disturbed line is less than -46dB. Fig. A10: Digital crosstalk measurements configuration +5V Fig. A11: Digital crosstalk results +5V 74HC04 74HC04 Line 1 Square Pulse Generator 5KHz +5V VG1 USBDF xxW5 Line 2 b21 VG1 Figure A10 shows the measurement circuit used to quantify the crosstalk effect in a classical digital application. Figure A11 shows that in such a condition signal from 0 to 5V and rise time of few ns, the impact on the other line is less than 100mV peak to peak (Below the logic high voltage threshold).The measurements performed with falling edges give the same results. 7/9 USBDFxxW5 TRANSITION TIMES This low pass filter has been designed in order to meet the USB 1.1 standard requirements that implies the signal edges are maintained within the 4ns-20ns stipulated USB specification limits. Fig. A12: Typical rise and fall times: measurements configuration +5V +5V 74HC04 74HC04 D+ USBDF xxW5 +5V Square Pulse Generator D- Fig. A13: Typical rise and fall times a. Rise time 8/9 b. Fall time USBDFxxW5 PACKAGE MECHANICAL DATA. SOT323-5L DIMENSIONS A A2 REF. Millimeters Inches Min. Max. Min. Max. A 0.8 1.1 0.031 0.043 A1 0 0.1 0 0.004 A2 0.8 1 0.031 0.039 b 0.15 0.3 0.006 0.012 c 0.1 0.18 0.004 0.007 D 1.8 2.2 0.071 0.086 E 1.15 1.35 0.045 0.053 A1 D e e H E e Q1 c b RECOMMENDED FOOTPRINT (mm) 0.65 Typ. 0.025 Typ. H 1.8 2.4 0.071 0.094 Q1 0.1 0.4 0.004 0.016 MECHANICAL SPECIFICATIONS 0.3mm Lead plating Tin-lead Lead plating thickness 5µm min 25µm max Lead material Sn / Pb (70% to 90%Sn) Lead coplanarity 10µm max Body material Molded epoxy Flammability UL94V-0 1mm 2.9mm 1mm 0.35mm MARKING Type Order Code Weight Marking Package Base Qty USBDF01W5 USBDF01W5 5.4mg UD1 SOT323-5L 3000 USBDF02W5 USBDF02W5 UD2 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics © 2000 STMicroelectronics - Printed in Italy - All rights reserved. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 9/9