ETC VES1848

VES 1848
SINGLE CHIP
DAVIC / DVB-RC
CABLE MODEM
FEATURES
APPLICATIONS
• Fully compliant ETS300800 and DAVIC 1.2
• Out-Off Band demodulation scheme :
On chip 7-bit ADC.
DQPSK demodulator.
Roll-off factor = 0.3 .
Direct IF sampling.
Variable bit rate from 1 to 12 Mbit/s (SAW
@ 8MHz BW).
Automatic Gain Control PWM output.
Descrambler.
Frame synchronization.
Deinterleaver.
RS decoder (55,53) .
• In Band scheme :
Parallel or serial MPEG2 Transport Stream
inputs.
MAC PID filtering.
DAVIC ATM cells transmission supported.
• Up-Stream synchronization.
• Up-Stream modulation scheme :
Burst QPSK/16QAM modulator.
Roll-off factor = 0.25/0.3 .
Programmable preamble value.
Programmable burst length.
Direct IF synthesys from 5 to 46 MHz.
I and Q base band outputs provided.
Variable bit rate from 256kbit/s to 16Mbit/s.
Programmable RS encoder.
Scrambler.
On chip 10 bit DACs.
• External MAC functionality.
• Package 208 MQFP.
• CMOS technology (0.35µm, 3.3V).
•
•
•
Cable modem.
DVB interactive set-top box.
DAVIC ATM cable physical layer.
DESCRIPTION
Based on the DVB-RC cable and DAVIC
specifications, the VES 1848 allows interactive
communication through HFC network between settop boxes and headends.
For Down Stream (DS) channel the circuit
implements a differential QPSK demodulator (Out Of
Band application) and accepts MPEG2 Transport
Stream inputs from a DS QAM demodulator (In Band
application). This channel allows to synchronize the
Up Stream (US) channel and to provide data to the
MAC layer which remains external.
The US channel is highly programmable and built
around a digital burst QPSK or 16QAM modulator
with direct IF synthesys or I and Q base band
outputs. The modulator is fully DVB and MCNS
compliant thanks to its burst profile programmation
(burst length, preamble, RS encoder, scrambler, bit
rate …).
The VES 1848 is packaged in a 208 MQFP, and
operates over the commercial temperature 0-70°C.
comatlas S.A., 30 rue du Chêne Germain, BP 814, 35518 CESSON SEVIGNE Cedex, France
Phone : + 33 2 99 27 55 55 – Fax : +33 2 99 27 55 27, Internet : www.comatlas.fr / VES 1848 rev 1.2 / July 99
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SUMMARY
CAUTION
This document is preliminary and is subject to change. Contact a
comatlas representative to determine if this is the current information
on this device.
The information contained in this document has been carefully checked and is believed to be reliable. However,
comatlas makes no guarantee or warranty concerning the accuracy of said information and shall not be
responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon, it. comatlas
does not guarantee that the use of any information contained herein will not infringe upon the patent, trademark,
copyright, mask work right or other rights of third parties, and no patent or other license is implied hereby.
This document does not in any way extend comatlas warranty on any product beyond that set forth in its
standard terms and conditions of sale. comatlas reserves the right to make changes in the products or
specifications, or both, presented in this publication at any time and without notice.
LIFE SUPPORT APPLICATIONS : comatlas products are not intended for use as critical components in life
support appliances, devices, or systems in which the failure of a comatlas product to perform could be expected
to result in personal injury.
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VES 1848 rev 1.2 / July 99 / p 2
1 GENERAL DESCRIPTION
FIGURE 1 : FUNCTIONAL BLOCK DIAGRAM
fixed
ADC
IF
DQPSK
demodulator
Out Of Band
channel processing
MAC
interface
MPEG2-TS
In Band
channel processing
application layers
interface
symbol clock
external
synchro
programmable
IF or I
DAC
Q
1.1
QPSK / 16QAM
burst modulator
Up Stream
channel encoding
ABREVIATIONS
AGC
BW
CRC
DS
HE
HEC
IB
IF
NIU
OOB
PWM
SL-ESF
STB
US
UW
1.2
Up Stream
synchronisation
Automatic Gain Control
Bandwidth
Cyclic Redundancy Checking (type of error correction code)
Down Stream (from the Headend to the set-top box)
Headend
Header Error Control (CRC of the ATM cell header)
In Band
Intermediate Frequency
Network Interface Unit (physical and MAC layers of the STB)
Out Of Band
Pulse Wave Modulation
Signalling Link Extended SuperFrame (name of the OOB frame)
Set-Top Box
Up Stream (from the set-top box to the headend)
Unique Word (=preamble)
NOTATION
References to programmation registers are done this way :
AD.7 = bit 7 (in decimal) of the register located at the address AD (in hexa).
AD.[7-5] = bits 7 down to 5 of the register located at the address AD.
1.3
FUNCTIONAL DESCRIPTION
½ ADC
The VES 1848 implements a 7-bit analog to digital converter. It directly samples the OOB IF signal. The IF value
can be chosen by the system designer.
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VES 1848 rev 1.2 / July 99 / p 3
½ DQPSK DEMODULATOR
Fully digital variable bitrate demodulator used for the OOB channel. It implements a digital down conversion to
base band, filtering and decimation, frequency and clock recoveries as well as equalization. It also provides an
AGC command to the OOB tuner.
½ OOB CHANNEL PROCESSING
After descrambling, deframing and deinterleaving, ATM cells are fed into the RS decoder and corrected. A filtering
on ATM headers and MAC headers is then done on valid cells to keep only those addressed to the STB. MAC cells
and application layers cells are stored in 2 different FIFOs. Up to 4 different VPI-VCI can be filtered for application
layers data.
(1)
Mbits and Rxbits are also output after integrity checking.
For US synchronization, 3ms markers are generated.
½ IB CHANNEL PROCESSING
This block is fed with the outputs of a cable FEC decoder. It implements the filtering of the MAC data addressed to
the STB as well as valid time references and valid Rxbits filtering.
Mbits, Rxbits (after integrity checking) and MAC data are stored in a FIFO.
For US synchronization, 3ms markers are generated.
No PID filtering is done for application layers data.
This block implements the filtering of ATM cells transported in MPEG2-TS packet as defined by DAVIC. These data
are stored in the application layers FIFO and up to 4 different VPI-VCI can be filtered.
½ INTERFACES
MAC messages and application layers data are stored in different FIFOs. They can then be read/write with the
same or 2 different micro processor interfaces.
The VES 1848 registers are programmed with the MAC interface.
½ US SYNCHRONIZATION
This block decides when to send an US burst.
When the VES 1848 is used in a DVB/DAVIC device, this block also does the propagation delay compensation and
the US slot numbering. It uses information from the DS channel (Mbits, 3ms markers) and some provided by the
MAC layer (time compensation, slot number where to send a burst).
When the US path is used in a MCNS device, the burst start information is provided by the toggle of the external
synchro pin.
½ US CHANNEL ENCODING
It is DVB/DAVIC and MCNS compliant thanks to its burst profile programmation (6 different profiles can be stored
in the VES 1848).
Data read in FIFOs are RS encoded, randomized and differential encoded before the addition of a programmable
preamble.
½ BURST MODULATOR
Data can be output either in base band after predistorsion and nyquist filtering or directly on a programmable IF. In
that case a programmable sinewave can also be generated if required.
½ DAC
Two 10-bit Digital to Analog Converters are built in the VES 1848. The modulated data are provided on both analog
and digital outputs.
(1)
refer to the DVB or DAVIC specification for the definition of Mbits and Rxbits.
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VES 1848 rev 1.2 / July 99 / p 4
TABLE 1: ABSOLUTE MAXIMUM RATINGS
Parameter
Min
Max
Unit
Ambient operating temperature : Ta
0
70
°C
DC supply voltage (VDD)
- 0.5
+ 4.1
V
DC Input voltage
- 0.5
VDD + 0.5
V
DC Input Current
± 20
mA
Lead Temperature
+300
°C
Junction Temperature
+150
°C
Stresses above the absolute maximum ratings may cause permanent damage to the device. Exposure to
absolute maximum ratings conditions for extended periods may affect device reliability.
TABLE 2 : RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Typ
Max
Unit
Notes
VDD
VD1, VD1IQ
VCC
Digital supply voltage
3.14
3.3
3.46
V
3.3V ±5%
5V supply
4.75
5
5.25
V
Ta
Operating temperature
0
70
°C
5V ± 5%
Ambient temperature
High-level input voltage
2
VCC + 0.3
V
TTL input
Low-level input voltage
-0.5
0.8
V
TTL input
V
@ IOH = -0.8 mA
@ IOH = + 2mA
@ IOL = 0.8 mA
@ IOL = + 2mA
@US_clk = 116MHz
(1)
VIH
VIL
VOH
(2)
VOL
(2)
(3)
0.1
0.4
300
V
IDD + ICC
Supply current
CIN
Input capacitance
15
pF
COUT
Output capacitance
15
pF
VD2
VD3, VD4
AVDDI, AVDDQ
VD0I, VD0Q
IFS
Analog supply voltage
RL
(1)
High-level output voltage VDD -0.1
2.4
Low-level output voltage
DAC full scale output
current range
DAC termination resistor
3.14
3.3
mA
3.46
V
25
mA
75
ohms
(3)
3.3V ± 5%
All inputs are 5V tolerant.
IOH, IOL = ± 4mA only for pins DATAA, DATAM, INTA, INTM, VAGC, PWM2, FCONTI, SDAOUT, SDAIN,
SCLOUT, WRNA, RDN_ENAA, CSA, US_SACLK.
with the US modulator working in continuous mode and with direct IF synthesys.
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VES 1848 rev 1.2 / July 99 / p 5
TABLE 3 : ANALOG CHARACTERISTICS
Symbol
Parameter
Min
VIP-VIM
ADC input signal range
-0.5
ADC Rin
ADC input Resistance
3
ADC Cin
ADC capacitance
(VIP or VIM)
OOB ADC input full
power bandwidth
DAC full scale output
current
(on Iana and Qana)
ADC BW
IFS147
Voc
SFRD
DAC output voltage
compliance
DAC spurious Free
Dynamic Range
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Typ
Max
Unit
0.5
V
Notes
kohms
5
40
50
17
18
0
1.0
10
pf
MHZ
0.1dB bandwith
19
mA
1.05
V
-50
DBc
VrefIQ=1.235V
IrefI and irefQ
connected to a
147Ω resistor,
US_clk = 60MHz
Vout ≤ 1.0V
RL ≤ 75 ohms
RL = 37.5 ohms
US_clk = 58 MHz
Input data
frequency
= 0.3 US_clk
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VES 1848 rev 1.2 / July 99 / p 6
FIGURE 2 : INPUT-OUTPUT BLOCK DIAGRAM
VDD VSS VCC
10
OOB_clk_in
OOB_clk_out
VIP
VIM
OOB_dig
Q
US_saclk
ctrl
DS_3ms
power supplies
hmuxmodeA
hstbmodeA
aleA
csA
wrnA
7
application layers
interface
OOB
rdn_enaA
intA
dataA
16
addA
5
IB
8
VES1848
EXT_SYNC
Fconti
Iconti
Qconti
on_off
PctrPWM
Iana
Qana
I_IF
5
OOB analog
Doob
clk_OOB
OOB_saclk
vagc
PWM2
IBsymbclk
IBclk
IB
Psync
US_clk_in
US_clk_out
15
MAC
interface
3
8
8
3
US
control
10
hmuxmodeM
hstbmodeM
aleM
csM
wrnM
rdn_enaM
intM
dataM
addM
utopia
nb_micro
Fmicro
RESET
10
4
start_slot_US
test
scan_en
IDDQ test
Tmode
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switch
SCLin
SDAin
SCLout
SDAout
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VES 1848 rev 1.2 / July 99 / p 7
vs1IQ
vd1IQ
vd0I
vs0I
irefQ
avssQ
Qana
compQ
vd0Q
vs0Q
avddQ
US_clk_out
US_clk_in
VDD
PctrPWM
OnOff
start_slot_us
DS_3ms
dataA[4]
dataA[3]
dataA[2]
dataA[1]
dataA[0]
addA[4]
addA[3]
addA[2]
addA[1]
addA[0]
VSS
VCC
csA
aleA
rdn_enaA
wrnA
intA
VDD
VSS
SCLin
SCLout
SDAin
SDAout
VSS
dataA[13]
dataA[12]
dataA[11]
dataA[10]
dataA[9]
dataA[8]
dataA[7]
dataA[6]
dataA[5]
dataA[14]
FIGURE 3 : PIN DIAGRAM
208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157
dataA[15]
1
156
hmuxmodeA
hstbmodeA
VCC
VSS
2
155
3
154
4
153
5
152
intM
wrnM
6
151
7
150
rdn_enaM
addM[0]
addM[1]
addM[2]
addM[3]
addM[4]
VDD
VSS
addM[5]
addM[6]
addM[7]
8
149
9
148
10
147
11
146
12
145
13
144
14
143
15
142
16
141
17
140
18
139
dataM[0]
dataM[1]
dataM[2]
dataM[3]
dataM[4]
VCC
VSS
19
138
20
137
21
136
22
135
23
134
dataM[5]
dataM[6]
dataM[7]
csM
aleM
26
24
133
VES1848
25
132
131
27
130
28
129
29
128
30
127
hmuxmodeM
hstbmodeM
utopia
31
126
32
125
33
124
VDD
VSS
nb_micro
Fmicro
IBsymbclk
IBclk
PSYNC
IB[0]
IB[1]
VCC
VSS
34
123
35
122
36
121
37
120
38
119
39
118
40
117
41
116
42
115
43
114
44
113
IB[2]
IB[3]
IB[4]
IB[5]
IB[6]
IB[7]
SCAN_EN
Tmode
45
112
46
111
47
110
48
109
49
108
50
107
51
106
52
105
avssI
vrefIQ
Iana
compI
irefI
avddI
I_IF[9]
I_IF[8]
I_IF[7]
I_IF[6]
VDD
VSS
I_IF[5]
I_IF[4]
I_IF[3]
I_IF[2]
VDD
VSS
I_IF[1]
I_IF[0]
US_SACLK
Q[9]
Q[8]
VDD
VSS
Q[7]
Q[6]
Q[5]
Q[4]
VDD
VSS
Q[3]
Q[2]
Q[1]
Q[0]
VD4
VD2
VS2
VIP
VIM
VS3
VD3
VREF
VREFP
VREFM
CMCAP
CMO
CMI
RBIAS
VD1
VS1
VS4
53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104
CTRL0
CTRL1
CTRL2
CTRL3
Iconti[2]
Iconti[1]
Iconti[0]
Qconti[2]
Qconti[1]
Qconti[0]
Fconti
EXT_SYNC
comatlas reserves the right to make any change at any time without notice.
OOB_dig[6]
OOB_dig[5]
OOB_dig[4]
OOB_dig[3]
OOB_dig[2]
OOB_dig[1]
OOB_dig[0]
OOB_SACLK
VSS
VCC
VAGC
PWM2
VDD
OOB_clk_out
OOB_clk_in
VSS
TEST
RESET
VSS
VDD
clk_oob
Doob
IDDQ
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VES 1848 rev 1.2 / July 99 / p 8
TABLE 4 : PIN DESCRIPTION
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
Pin Name
dataA[15]
hmuxmodeA
hstbmodeA
VCC
VSS
intM
wrnM
rdn_enaM
addM[0]
addM[1]
addM[2]
addM[3]
addM[4]
VDD
VSS
addM[5]
addM[6]
addM[7]
dataM[0]
dataM[1]
dataM[2]
dataM[3]
dataM[4]
VCC
VSS
dataM[5]
dataM[6]
dataM[7]
csM
aleM
hmuxmodeM
hstbmodeM
utopia
VDD
VSS
nb_micro
Fmicro
IBsymbclk
IBclk
PSYNC
IB[0]
IB[1]
Direction
I /O
I
I
O
I
I
I
I
I
I
I
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
I
I
I
I
I
Pin
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Pin Name
VCC
VSS
IB[2]
IB[3]
IB[4]
IB[5]
IB[6]
IB[7]
SCAN_EN
Tmode
IDDQ
Doob
clk_oob
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used
VDD
VSS
RESET
TEST
VSS
OOB_clk_in
OOB_clk_out
VDD
PWM2
VAGC
VCC
VSS
Direction
I
I
I
I
I
I
I
I
I
O
O
I
I
I
O
O
O
-
Pin
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
Pin Name
OOB_SACLK
OOB_dig[0]
OOB_dig[1]
OOB_dig[2]
OOB_dig[3]
OOB_dig[4]
OOB_dig[5]
OOB_dig[6]
EXT_SYNC
Fconti
Qconti[0]
Qconti[1]
Qconti[2]
Iconti[0]
Iconti[1]
Iconti[2]
CTRL3
CTRL2
CTRL1
CTRL0
VS4
VS1
VD1
RBIAS
CMI
CMO
CMCAP
VREFM
VREFP
VREF
VD3
VS3
VIM
VIP
VS2
VD2
VD4
Q[0]
Q[1]
Q[2]
Q[3]
VSS
Direction
O
I
I
I
I
I
I
I
I
O
I
I
I
I
I
I
O
O
O
O
I
O
O
I
O
O
O
I
I
O
O
O
O
-
Pins 56 to 72 as well as all input
pins not used must be grounded.
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VES 1848 rev 1.2 / July 99 / p 9
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
VDD
Q[4]
Q[5]
Q[6]
Q[7]
VSS
VDD
Q[8]
Q[9]
US_SACLK
I_IF[0]
I_IF[1]
VSS
VDD
I_IF[2]
I_IF[3]
I_IF[4]
I_IF[5]
VSS
VDD
I_IF[6]
I_IF[7]
I_IF[8]
I_IF[9]
avddI
irefI
compI
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
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154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
Iana
vrefIQ
avssI
vs0I
vd0I
vd1IQ
vs1IQ
avssQ
irefQ
compQ
Qana
avddQ
vs0Q
vd0Q
DS_3ms
start_slot_us
OnOff
PctrPWM
VDD
US_clk_in
US_clk_out
VSS
SDAout
SDAin
SCLout
SCLin
VSS
O
I
I
I
O
O
O
O
O
I
O
I /O
I/O
O
I
-
comatlas reserves the right to make any change at any time without notice.
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
VDD
intA
wrnA
rdn_enaA
aleA
csA
VCC
VSS
addA[0]
addA[1]
addA[2]
addA[3]
addA[4]
dataA[0]
dataA[1]
dataA[2]
dataA[3]
dataA[4]
dataA[5]
dataA[6]
dataA[7]
dataA[8]
dataA[9]
dataA[10]
dataA[11]
dataA[12]
dataA[13]
dataA[14]
O
I/O
I/O
I
I/O
I
I
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VES 1848 rev 1.2 / July 99 / p 10
2 INPUT - OUTPUT SIGNAL DESCRIPTION
SYMBOL
US_clk_in
PIN NUMBER
173
TYPE
I
US_clk_out
174
O
OOB_clk_in
78
I
OOB_clk_out
79
O
OOB_dig[6:0]
86,87,88,89
90,91,92
I
OOB_saclk
85
Doob
54
clk_oob
55
VAGC
82
PWM2
81
O
(5V)
O
(5V)
O
(5V)
O
(5V)
O
(5V)
IBsymbclk
38
I
IBclk
39
I
IB[7:0]
41,42,45,46
47,48,49,50
I
PSYNC
40
I
EXT_SYNC
93
I
Fconti
94
O
(5V)
Iconti[2:0]
98,99,100
I
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DESCRIPTION
XTAL oscillator input pin. Typically a fifth overtone XTAL oscillator is
connected between the US_clk_in and US_clk_out pins.
XTAL oscillator output pin. Typically a fifth overtone XTAL oscillator
is connected between the US_clk_in and US_clk_out pins.
XTAL oscillator input pin. Typically a fifth overtone XTAL oscillator is
connected between the OOB_clk_in and OOB_clk_out pins.
XTAL oscillator output pin. Typically a fifth overtone XTAL oscillator
is connected between the OOB_clk_in and OOB_clk_out pins.
IF digital OOB signal. OOB_dig[6:0] is connected to an external A/D
converter. OOB_dig[6] is the MSB. When not used, OOB_dig[6 :0]
must be tied to ground.
IF OOB Sampling ClocK. Can be used as the sampling clock of an
external 7-bit ADC that will generate OOB_dig signals.
Output of the OOB DQPSK demodulator. Data are output on the
falling edge of clk_oob.
Bit clock associated with Doob.
PWM encoded output signal for AGC. This signal is typically fed to
the AGC amplifier through a single RC network.
PWM encoded programmable signal. The encoded data is the
parameter PWM2 (C2[7-0]). This signal can be used to control a
second input of the AGC amplifier through a single RC network.
IB symbol clock. This clock is provided by the QAM demodulator.
Its polarity can be selected with parameter PsymbIB(AE.3).
IB byte clock associated with the data bus IB[7:0].
Its polarity can be selected with parameter PbyteIB(AE.2).
IB MPEG2-TS input. These 8-bit parallel data are the outputs of the
DS QAM FEC.
When the parallel interface is selected (Parameter serie = 0,
address 82.6) then IB[7:0] is the transport stream input (IB[7] is the
MSB).
When the serial interface is selected (Parameter serie = 1, address
82.6) then the serial input is on pin IB[0] (pin 41).
If parameter Ps_DE=0 (address 83.7) : Pulse SYNChro. This input
signal must be high when the sync byte (4716) is provided on IB[7:0],
then it must be low until the next sync byte. If the serial interface is
selected, then PSYNC is high only during the first bit of the sync
byte (4716).
If parameter Ps_DE=1 (address 83.7) : data enable. This input
signal must be high during the first 188 bytes of the MPEG2-TS
packet. It is then low during the redondancy bytes.
EXTernal SYNChro. Only used when parameter InExt=1 (88.1).
When not used, must be tied to ground.
This input signal toggles at each US burst start.
EXT_SYNC must be initiated to 0.
Programmable clock with the parameter contiCk (AF.[5-4]). This
clock must be used in continuous mode to generate Iconti[2:0] and
Qconti[2:0].
I input for the US modulator in continuous mode (parameter
contiMode=1 (AF.3), and contiMem=0 (AF.6)). This data bus is
clocked on the rising edge of Fconti clock.
comatlas reserves the right to make any change at any time without notice.
VES 1848 rev 1.2 / July 99 / p 11
SYMBOL
Qconti[2:0]
PIN NUMBER
95,96,97
TYPE
I
OnOff
170
O
(5V)
PctrPWM
171
O
(5V)
I_IF[9:0]
137,138,141,142
143,144,147,148
149,150
122,123,124,125
128,129,130,131
134,135
O
(3.3V)
US_SACLK
136
CTRL[3:0]
101,102,103,104
O
(3.3V)
O
(5V)
DS_3ms
168
start_slot_us
169
SCAN_EN
51
I
Tmode
IDDQ
TEST
SCLin
52
53
76
179
I
I
I
I
SCLout
178
O
(5V)
SDAin
177
I/O
(5V)
SDAout
176
I/O
(5V)
Q[9:0]
O
(3.3V)
O
(5V)
O
(5V)
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DESCRIPTION
Q input for the US modulator in continuous mode (parameter
contiMode=1 (AF.3), and contiMem=0 (AF.6)). This data bus is
clocked on the rising edge of Fconti clock.
On/off command for the US amplifier. It can be active high or low
depending on parameter Pampli (AE.6). It is activated just before
the start of a burst and desactivated just after the end of the burst.
PWM encoded output signal to control the US amplifier power level.
The encoded data is the parameter PwAmpli (95.[7-0]). This signal
is typically fed to the US amplifier through a single RC.
When parameter BB_IF=0 (AD.2) : I base band digital output.
When parameter BB_IF=1 (AD.2) : modulated IF digital output.
I_IF[9] is the MSB. I_IF is in offset binary.
When parameter BB_IF=0 (AD.2) : Q base band digital output.
When parameter BB_IF=1 (AD.2) : programmable sinewave
(B0.[7-0], B1.[7-0]) digital output.
Q[9] is the MSB. Q is in offset binary.
US Sampling ClocK for the external DACs connected to I_IF and Q.
Control pins. Their values are programmable through regCtrl[5:2]
(FE.[5-2]). RegCtrl[5] controls CTRL[3] (pin 101).
CTRL are open drain outputs and therefore require external pull up
resistors to VCC.
3ms markers received DS either IB or OOB. Mainly used for test.
Active high pulse that is one US_clk period long.
Start of US slot as defined in the DVB/DAVIC spec. Mainly used for
test.
Active high pulse that is one US_clk period long.
For normal operation of the VES 1848, SCAN_EN must be
grounded.
For normal operation of the VES 1848, Tmode must be grounded.
For normal operation of the VES 1848, IDDQ must be grounded.
For normal operation of the VES 1848, TEST must be grounded.
The VES1848 is only a switch between SCLin and SCLout. It is
used to isolate the OOB tuner (programmed by I2C) from the I2C
bus. When regCtrl[0]=0 (FE.0) SCLout is isolated from SCLin.
The VES1848 is only a switch between SCLin and SCLout. It is
used to isolate the OOB tuner (programmed by I2C) from the I2C
bus. When regCtrl[0]=0 (FE.0) SCLout is isolated from SCLin.
The VES1848 is only a switch between SDAin and SDAout. It is
used to isolate the OOB tuner (programmed by I2C) from the I2C
bus. When regCtrl[0]=0 (FE.0) SDAout is isolated from SDAin. SDA
is a bidirectional signal. When regCtrl[1]=0 (FE.1) SDAin is an input
else it is an output.
The VES1848 is only a switch between SDAin and SDAout. It is
used to isolate the OOB tuner (programmed by I2C) from the I2C
bus. When regCtrl[0]=0 (FE.0) SDAout is isolated from SDAin. SDA
is a bidirectional signal. When regCtrl[1]=1 (FE.1) SDAout is an
input else it is an output.
comatlas reserves the right to make any change at any time without notice.
VES 1848 rev 1.2 / July 99 / p 12
SYMBOL
RESET
PIN NUMBER
75
TYPE
I
Fmicro
37
I
nb_micro
36
I
utopia
33
I
AddM[7:0]
I
IntM
9,10,11,12
13,16,17,18
19,20,21,22
23,26,27,28
6
hstbmodeM
32
I
hmuxmodeM
31
I
rdn_enaM
8
I
wrnM
7
I
csM
aleM
29
30
I
I
addA[4:0]
I
IntA
189,190,191
192,193
194,195,196,197
198,199,200,201
202,203,204,205
206,207,208,1
182
hstbmodeA
3
I
hmuxmodeA
2
I
rdn_enaA
184
I
wrnA
183
I
csA
186
I
DataM[7:0]
dataA[15:0]
I/O
(5V)
O
(5V)
I/O
(5V)
O
(5V)
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DESCRIPTION
The RESET input is asynchronous, active low, and clears the VES
1848. When RESET goes low, the circuit immediately enters its
reset mode and normal operation will resume 4 OOB_clk falling
edges or 8 US_clk falling edges or 4 IBclk falling edges (depending
which delay is the bigger) later after RESET returned high. The
register contents are all initialized to their default values. The
minimum width of RESET at low level is the maximum of 4 OOB_clk
clock periods, 8 US_clk clock periods and 4 IBclk clock periods.
Controls the working frequency of the interface block.
If Fsysus > 65MHz then Fmicro must be set to Vdd.
If Fsysus ≤ 65MHz then Fmicro must be set to Vss.
If a single micro-processor is used to read the MAC data and the
application layers data then nb_micro must be set to Vdd.
If the application layers data are read by an other circuit then
nb_micro must be set to Vss.
Must be set to Vss.
Application layers data can only be read through a micro processor
interface.
MAC interface address bus.
AddM[7] is the MSB.
MAC interface data bus.
DataM[7] is the MSB.
MAC interface active low interrupt line.
IntM is an open drain output and therefore requires an external pull
up resistor to VCC.
Host interface STRobe mode (Intel=0, Motorola=1) for the MAC
interface.
Host interface MUX mode for the MAC interface : address and data
multiplexed (=1) or not (=0).
MAC interface active low read strobe (Intel mode) or active low data
valid (Motorola mode).
MAC interface active low write strobe (Intel mode) or
read(=1) /write(=0) qualifier (Motorola mode).
MAC interface active low Chip Select.
MAC interface Address Latch Enable (only for multiplexed microprocessor).
Application layers interface address bus.
addA[4] is the MSB.
Application layers interface data bus.
dataA[15] is the MSB.
Application layers interface active low interrupt line.
IntA is an open drain output and therefore requires an external pull
up resistor to VCC.
Host interface STRobe mode (Intel=0, Motorola=1) for the
application layers interface.
Host interface MUX mode for the application layers interface :
address and data multiplexed (=1) or not (=0).
application layers interface active low read strobe (Intel mode) or
active low data valid (Motorola mode).
application layers interface active low write strobe (Intel mode) or
read(=1) /write(=0) qualifier (Motorola mode).
application layers interface active low Chip Select.
comatlas reserves the right to make any change at any time without notice.
VES 1848 rev 1.2 / July 99 / p 13
SYMBOL
aleA
PIN NUMBER
185
TYPE
I
VIP
118
I
VIM
117
I
CMCAP
111
I
RBIAS
108
I
VREF
114
O
VREFP
113
O
VREFM
112
O
CMO
110
O
CMI
109
O
VD1
VS1
VD2
VS2
VD3
VS3
VD4
107
106
120
119
115
116
121
I
I
I
I
I
I
I
VS4
105
I
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DESCRIPTION
application layers interface Address Latch Enable (only for
multiplexed micro-processor).
IF analog OOB input signal. Positive input to the A/D converter. This
pin is DC biased to half-supply through an internal resistor divider (2
x 10kΩ resistors). In order to remain in the range of the ADC, the
voltage difference between pins VIP and VIM should be between
-0.5 and 0.5 volts.
IF analog OOB input signal. Negative input to the A/D converter.
This pin is DC biased to half-supply through an internal resistor
divider (2 x 10kΩ resistors). In order to remain in the range of the
ADC, the voltage difference between pins VIP and VIM should be
between -0.5 and 0.5 volts.
This pin is connected to a tap point on an internal resistor divider
used to create CMO and CMI. An external capacitor of value .1 µf
should be connected between this point and ground to provide good
power supply rejection from the positive supply at higher
frequencies.
An external resistor of value 3.3kΩ should be connected between
this pin and ground to provide good accurate bias currents for the
analog circuits on the ADC.
This is the output of an on-chip resistor divider. An external
capacitor of value .1µf should be connected between this point and
ground to provide good power supply rejection from the positive
supply at higher frequencies. Reference voltages VREFP and
VREFM are derived from the voltage on VREF.
This is a positive voltage reference for the A/D converter. It is
derived from the voltage on pin VREF through an on-chip fullydifferential amplifier. The voltage on this pin is nominally equal to
CMO + 0.25 volts.
This is the negative voltage reference for the A/D converter. It is
derived from the voltage on pin VREF through an on-chip fullydifferential amplifier. The voltage on this pin is nominally equal to
CMO - 0.25 volts.
This pin provides the common-mode out voltage for the analog
circuits on the ADC. It is the buffered version of a voltage derived
from an on-chip resistor devider, and has a nominal value of 0.5 x
VD3.
This pin provides the common-mode in voltage for the analog
circuits on the ADC. It is the buffered version of a voltage derived
from an on-chip resistor devider, and has a nominal value of 0.75 x
VD3.
Power supply input for the digital switching circuitry (3.3V typ).
Ground return for the digital switching circuitry.
Power supply input for the analog clock drivers (3.3V typ).
Ground return for the analog clock drivers.
Power supply input for the analog circuits (3.3V typ).
Ground return for analog circuits.
Power supply input connected to an n-well guard ring that surrounds
the ADC (3.3V typ).
Ground for a p+ guard ring that surrounds the ADC.
comatlas reserves the right to make any change at any time without notice.
VES 1848 rev 1.2 / July 99 / p 14
SYMBOL
Iana
PIN NUMBER
154
TYPE
O
Qana
164
O
CompI
153
I
CompQ
163
I
IrefI
152
I
IrefQ
162
I
VrefIQ
AVDDI
AVSSI
VS0I
155
151
156
157
I
I
I
I
VD0I
158
I
VD1IQ
VS1IQ
AVSSQ
AVDDQ
VS0Q
159
160
161
165
166
I
I
I
I
I
VD0Q
167
I
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DESCRIPTION
Analog output current for channel I. Iana is the output of the DAC
and can directly drive a single or double terminated 75Ω
transmission line.
When parameter BB_IF=0 (AD.2) : I base band analog output.
When parameter BB_IF=1 (AD.2) : modulated IF analog output.
Analog output current for channel Q. Qana is the output of the DAC
and can directly drive a single or double terminated 75Ω
transmission line.
When parameter BB_IF=0 (AD.2) : Q base band analog output.
When parameter BB_IF=1 (AD.2) : programmable sinewave
(B0.[7-0], B1.[7-0]) analog output.
An external .1µF bypass capacitor must be connected between this
pin and analog VDD to stabilize the internal current reference node
of the D/A converter of channel I.
An external .1µF bypass capacitor must be connected between this
pin and analog VDD to stabilize the internal current reference node
of the D/A converter of channel Q.
An external resistor of value 147Ω should be connected between
this pin and ground to provide good accurate bias currents for the
analog circuits on the DAC of channel I.
An external resistor of value 147Ω should be connected between
this pin and ground to provide good accurate bias currents for the
analog circuits on the DAC of channel Q.
Voltage reference of 1.235V for both DAC.
DAC analog core power supply (3.3V)
DAC analog core ground.
Ground for a P+ guard ring that surrounds the DAC (must be a clean
Vss)
Power supply for an N- guard ring that surrounds the DAC (must be
a clean 3.3V)
DAC digital core power supply (3.3V)
DAC digital core ground.
DAC analog core ground.
DAC analog core power supply (3.3V)
Ground for a P+ guard ring that surrounds the DAC (must be a clean
Vss).
Power supply for an N- guard ring that surrounds the DAC (must be
a clean 3.3V).
comatlas reserves the right to make any change at any time without notice.
VES 1848 rev 1.2 / July 99 / p 15
FIGURE 4 : APPLICATION EXAMPLE 1
only IB DS with a specific PID for
interactive application MPEG2-TS packets,
2 micro-processors interface
direct IF synthesys between 5 and 46MHz
LPF1
cable
broadcast
+ DS IB
tuner
diplexer
fixed
IF
VES1820
(QAM demod
+FEC)
MPEG2-TS
demux
MPEG
broadcast
I2C
symbol
clock
MAC data
interactive
application layers
micro-processor
16
VES1848
8
OnOff
analog power
command
LPF1
interactive
data
MAC
micro-processor
PctrPWM
Iana Qana
digital
command
or
LPF3
BB_IF(AD.2)=1, DStype(88.[7-6])=0, IB_ATM(83.6)=0, InExt(88.1)=0, utopia(pin33)=0, nb_micro(pin36)=0
FIGURE 5 : APPLICATION EXAMPLE 2
only OOB DS
2 micro-processors interface
base band outputs US
If the frequency range achieved by the direct IF synthesys (5 to 46 MHz) is not convenient,
an external modulator can be used. It is controled by the MAC micro-processor to set the desired IF.
LPF1
broadcast
cable
splitter
diplexer
tuner
fixed
IF
VES1820
(QAM demod
+FEC)
MPEG2-TS
demux
MPEG
broadcast
I2C
LPF1
DS OOB
tuner
fixed
IF
VAGC
16
VES1848
OnOff
analog power
command
or
LPF1
PctrPWM
Iana Qana
8
interactive
application layers
micro-processor
MAC
micro-processor
digital
command
modulator
LPF2
LPF2
BB_IF(AD.2)=0, DStype(88.[7-6])=1 or 2, InExt(88.1)=0, utopia(pin33)=0, nb_micro(pin36)=0
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comatlas reserves the right to make any change at any time without notice.
VES 1848 rev 1.2 / July 99 / p 16
FIGURE 6 : APPLICATION EXAMPLE 3
OOB (MAC and application data) and
IB (application data with a specific PID)
1 micro-processor interface
IF between 5 and 65MHz
An other solution to get an US frequency band larger than the direct IF synthesys range is to use the
sinewave generated on Q and mixed it with the modulated signal (output on I).
The carrier frequency on I and the sinewave frequency on Q are chosen equal to IF/2.
Thus after multiplication we get one spectrum centered on the IF frequency and the second centered on 0.
LPF1
broadcast
+ DS IB
cable
tuner
splitter
diplexer
fixed
IF
VES1820
(QAM demod
+FEC)
MPEG2-TS
demux
broadcast
MPEG
I2C
interactive
data
LPF1
DS OOB
tuner
fixed
IF
interactive
application layers
micro-processor
VAGC
VES1848
16
OnOff
analog power
command
LPF1
MAC
micro-processor
PctrPWM
Iana Qana
digital
command
or
IF
LPF4
PBF1
LPF4
IF/2
IF/2
BB_IF(AD.2)=1, DStype(88.[7-6])=1 or 2, IB_ATM(83.6)=0, InExt(88.1)=0, utopia(pin33)=0, nb_micro(pin36)=1
FIGURE 7 : APPLICATION EXAMPLE 4
DS MCNS
single micro-processor interface
direct IF synthesys between 5 and 46MHz
LPF1
cable
diplexer
broadcast
+ DS IB
tuner
fixed
IF
VES1900
(QAM demod
+FEC)
MPEG2-TS
demux
MPEG
broadcast
I2C
MCNS deframing
(FPGA)
MAC and application
data
EXT_SYNC
interactive
application layers
micro-processor
VES1848
OnOff
analog power
command
or
LPF1
16
PctrPWM
Iana Qana
MAC
micro-processor
digital
command
LPF3
BB_IF(AD.2)=1, InExt(88.1)=1, utopia(pin33)=0, nb_micro(pin36)=1
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comatlas reserves the right to make any change at any time without notice.
VES 1848 rev 1.2 / July 99 / p 17
comatlas S.A, 30 rue du Chêne Germain, BP 814, 35518 CESSON SEVIGNE CEDEX – France
Tel : +33 2 99 27 55 55, Fax : +33 2 99 27 55 27, Internet : www.comatlas.fr, e-mail : [email protected]
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comatlas reserves the right to make any change at any time without notice.
VES 1848 rev 1.2 / July 99 / p 18