ETC 5962-8757902XA

REVISIONS
LTR
DESCRIPTION
DATE (YR-MO-DA)
APPROVED
A
Changes in table I: Page 4, input offset voltage should read +VCC = 3.5 V,
-VCC = -32.5 V. Page 5, gain error, reference subgroups 4, 5, 6, as separate
tests. Temperature limits +VCC = 32.5 V should be .06 instead of .02.
Page 6, changes acquisition parameters. Page 10, add replacement military
specification part number. Inactivate drawing for new design.
Editorial changes throughout.
88-05-11
M. A. FRYE
B
Changes in accordance with N.O.R. 5962-R313-92.
92-10-08
M. A. FRYE
C
Add generic part number 5537 as device type 02. Add vendor CAGE 18324.
Add case outline letter P. Make changes to 1.2.1, 1.2.2, 1.3, TABLE I, and
FIGURE 1. Redrawn.
94-04-19
M. A. FRYE
D
Add device class level Q and V devices. Add case outline letter Z. Make
changes to 1.2.2, 1.3, figure 1, table II, and the gain error test as specified in
table I. - ro
01-05-25
R. MONNIN
THE ORIGINAL FIRST SHEET OF THIS DRAWING HAS BEEN REPLACED.
REV
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REV
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PMIC N/A
PREPARED BY
MARCIA B. KELLEHER
STANDARD
MICROCIRCUIT
DRAWING
THIS DRAWING IS AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
AMSC N/A
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216
http://www.dscc.dla.mil
CHECKED BY
RAY MONNIN
APPROVED BY
MICHAEL A. FRYE
MICROCIRCUIT, LINEAR, SAMPLE AND HOLD,
MONOLITHIC SILICON
DRAWING APPROVAL DATE
87-06-17
REVISION LEVEL
D
SIZE
CAGE CODE
A
67268
SHEET
DSCC FORM 2233
APR 97
DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.
1 OF
5962-87608
16
5962-E445-01
1. SCOPE
1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and
M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the
Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the
PIN.
1.2 PIN. The PIN is as shown in the following examples.
For device classes M and Q:
5962



Federal
stock class
designator
\



RHA
designator
(see 1.2.1)
87608
01



Device
type
(see 1.2.2)
G



Case
outline
(see 1.2.4)
X



Lead
finish
(see 1.2.5)
01



Device
type
(see 1.2.2)
V



Device
class
designator
(see 1.2.3)
Z



Case
outline
(see 1.2.4)
/
\/
Drawing number
For device class V:
5962



Federal
stock class
designator
\



RHA
designator
(see 1.2.1)
87608
/
X



Lead
finish
(see 1.2.5)
\/
Drawing number
1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and
are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A
specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device.
1.2.2 Device type(s). The device type(s) identify the circuit function as follows:
Device type
Generic number
01
02
Circuit function
LF198
5537
Sample and hold
Sample and hold
1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as listed
below. Since the device class designator has been added after the original issuance of this drawing for devices 01GA and
02PA, the device classes M and Q designators will not be included in the PIN and will not be marked on the device.
Device class
M
Q or V
Device requirements documentation
Vendor self-certification to the requirements for MIL-STD-883 compliant,
non-JAN class level B microcircuits in accordance with MIL-PRF-38535,
appendix A
Certification and qualification to MIL-PRF-38535
STANDARD
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REVISION LEVEL
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2
1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows:
Outline letter
G
P
Z
Descriptive designator
Terminals
MACY1-X8
GDIP1-T8 or CDIP2-T8
GDFP1-G14
8
8
14
Package style
Can
Dual-in-line
Flat pack with gullwing leads
1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535,
appendix A for device class M.
1.3 Absolute maximum ratings. 1/
Supply voltage (±VCC) ..................................................................... ±18 V
Power dissipation (PD) ..................................................................... 500 mW 2/
Input voltage (VIN) ............................................................................ ±18 V 3/
Logic to logic differential voltage ...................................................... +7 V, -30 V 4/
Output short circuit duration ............................................................. Indefinite
Hold capacitor short circuit duration ................................................. 10 seconds
Lead temperature (soldering, 10 seconds) ...................................... 300°C
Storage temperature range .............................................................. -65°C to +150°C
Junction temperature (TJ) ................................................................ +150°C
Thermal resistance, junction-to-case (θJC):
Case G .......................................................................................... 48°C/W
Case P .......................................................................................... See MIL-STD-1835
Case Z .......................................................................................... 20°C/W
Thermal resistance, junction-to-ambient (θJA):
Case G .......................................................................................... 160°C/W, still air at 0.5 W
84°C/W, 500 LFPM air flow 0.5 W
Case P .......................................................................................... 120°C/W
Case Z .......................................................................................... 140°C/W, still air at 0.5 W
95°C/W, 500 LFPM air flow 0.5 W
1.4 Recommended operating conditions.
Supply voltage (±VCC) ..................................................................... ±15 V
Ambient operating temperature range (TA) ...................................... -55°C to +125°C
2. APPLICABLE DOCUMENTS
2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a
part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those listed in
the issue of the Department of Defense Index of Specifications and Standards (DoDISS) and supplement thereto, cited in the
solicitation.
1/
2/
3/
4/
Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the
maximum levels may degrade performance and affect reliability.
The maximum power dissipation must be derated at elevated temperatures and is dicated by TJMAX, θJA and TA.
The maximum allowable power dissipation at any temperature is PDMAX – (TJMAX – TA) / θJA or the number given
in the absolute maximum ratings, whichever is lower.
The maximum input voltage shall not exceed the power supply voltage.
Although the differential voltage may not exceed the limits given, the common-mode voltage the logic pins may be equal
to the supply voltages without causing damage to the circuit. For proper logic operation, however, one of the logic pins
must always be at 2 V below the positive supply and 3 V above the negative supply.
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REVISION LEVEL
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SPECIFICATION
DEPARTMENT OF DEFENSE
MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.
STANDARDS
DEPARTMENT OF DEFENSE
MIL-STD-883 MIL-STD-1835 -
Test Method Standard Microcircuits.
Interface Standard Electronic Component Case Outlines.
HANDBOOKS
DEPARTMENT OF DEFENSE
MIL-HDBK-103 MIL-HDBK-780 -
List of Standard Microcircuit Drawings.
Standard Microcircuit Drawings.
(Unless otherwise indicated, copies of the specification, standards, and handbooks are available from the Standardization
Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text
of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a
specific exemption has been obtained.
3. REQUIREMENTS
3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with
MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The
modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for
device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified
herein.
3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified
in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M.
3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein.
3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1.
3.2.3 Logic diagrams. The logic diagrams shall be as specified on figure 2.
3.3 Electrical performance characteristics and post irradiation parameter limits. Unless otherwise specified herein, the
electrical performance characteristics and post irradiation parameter limits are as specified in table I and shall apply over the
full ambient operating temperature range.
3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical
tests for each subgroup are defined in table I.
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REVISION LEVEL
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3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be
marked as listed in MIL-HDBK-103. For packages where marking of the entire SMD PIN number is not feasible due to space
limitations, the manufacturer has the option of not marking the "5962-" on the device. For RHA product using this option, the
RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535.
Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A.
3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in
MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix A.
3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535
listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of
compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see
6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this
drawing shall affirm that the manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF-38535
and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein.
3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for
device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing.
3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2
herein) involving devices acquired to this drawing is required for any change as defined in MIL-PRF-38535, appendix A.
3.9 Verification and review for device class M. For device class M, DSCC, DSCC's agent, and the acquiring activity retain
the option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made
available onshore at the option of the reviewer.
3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in
microcircuit group number 60 (see MIL-PRF-38535, appendix A).
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REVISION LEVEL
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TABLE I. Electrical performance characteristics.
Test
Input offset voltage
Symbol
Conditions 1/
-55°C ≤ TA ≤ +125°C
unless otherwise specified
VOS
+VCC = 3 V, -VCC = -7 V
Group A
subgroups
Device
type
1
01
Max
3
2,3
-5
5
1
-3
3
2,3
-5
5
+VCC = 3.5 V,
1
-3
3
-VCC = -26.5 V
2,3
-5
5
±VCC = ±18 V
1
-3
3
2,3
-5
5
+VCC = 3.5 V,
1
-3
3
-VCC = -32.5 V
2,3
-5
5
+VCC = 26.5 V,
1
-3
3
2,3
-5
5
1
-3
3
2,3
-5
5
1
-3
3
2,3
-5
5
-3
3
-5
5
-VCC = -3.5 V
+VCC = 32.5 V,
-VCC = -3.5 V
+VCC = 7 V, -VCC = -3 V
1
±VCC = ±5 V to ±18 V
02
2,3
+ICC
Unit
Min
-3
±VCC = 15 V
Positive supply current
Limits 2/
1,2
VCC = ±15 V
01
5.5
3
1,2
VCC = ±18 V
1,2
mode = sample
mA
6.5
02
6.5
3
VCC = ±18 V,
mV
7.5
01
5.5
3
6.5
See footnotes at end of table.
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REVISION LEVEL
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TABLE I. Electrical performance characteristics – Continued.
Test
Symbol
Conditions 1/
-55°C ≤ TA ≤ +125°C
unless otherwise specified
+ICC
Group A
subgroups
Device
type
VCC = ±18 V,
1,2
01
mode = hold
3
VCC = ±15 V
1,2
Limits 2/
Min
Positive supply current
Negative supply current
-ICC
1,2
01
-5.5
1,2
mode = sample
Input bias current
IIB
02
mA
-6.5
-7.5
01
-5.5
3
-6.5
VCC = ±18 V,
1,2
-5.5
mode = hold
3
-6.5
+VCC = 3 V, -VCC = -7 V
1
-25
25
2,3
-75
75
1
-25
25
2,3
-75
75
+VCC = 3.5 V,
1
-25
25
-VCC = -32.5 V
2,3
-75
75
1
-25
25
2,3
-75
75
1
-25
25
2,3
-75
75
-25
25
-75
75
±VCC = 15 V
+VCC = +32.5 V,
-VCC = -3.5 V
+VCC = 7 V, -VCC = -3 V
1
±VCC = ±5 V to ±18 V
mA
-6.5
3
VCC = ±18 V,
Max
5.5
6.5
3
VCC = ±18 V
Unit
01
02
2,3
nA
See footnotes at end of table.
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TABLE I. Electrical performance characteristics – Continued.
Test
Leakage current into 3/
hold capacitor
Symbol
Conditions 1/
-55°C ≤ TA ≤ +125°C
unless otherwise specified
Group A
subgroups
Device
type
ILEAK
+VCC = 3 V, -VCC = -7 V,
1
01
Limits 2/
Unit
Min
-100
Max
100
-100
100
-100
100
-100
100
pA
TA = +25°C
+VCC = 3.5 V,
-VCC = -32.5 V,
TA = +25°C
+VCC = 32.5 V,
-VCC = -3.5 V,
TA = +25°C
+VCC = 7 V, -VCC = -3 V,
TA = +25°C
Hold mode
1
02
.05
2,3
Hold step 4/
VHS
1
25
-2
2
2,3
-5.6
5.6
+VCC = 3.5 V,
1
-2.5
2.5
-VCC = -26.5 V
2,3
-5.6
5.6
+VCC = 26.5 V,
1
-2.5
2.5
2,3
-5.6
5.6
±VCC = 15 V
-VCC = -3.5 V
VOUT = 0 V, TA = +25°C,
nA
01
1
02
1
01
mV
2.0
CH = 0.01 µF
Input impedance
ZIN
+VCC = 8 V, -VCC = -28 V
+VCC = 28 V, -VCC = -8 V
Output impedance
ZOUT
2,3
0.8
1
10
2,3
0.8
1
±VCC = ±18 V
10
01
GΩ
2
2,3
GΩ
4
See footnotes at end of table.
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TABLE I. Electrical performance characteristics – Continued.
Test
Symbol
Conditions 1/
-55°C ≤ TA ≤ +125°C
unless otherwise specified
ZOUT
Hold mode
Group A
subgroups
Device
type
1
02
Limits 2/
Min
Output impedance
2,3
Capacitor charging
current
ICHRG
+VCC = 8 V,
1
-VCC = -28 V
+VCC = 28 V,
-VCC = -8 V
Logic pin current
LOGIC
Max
2
Ω
4
-25
-4.5
2,3
-25
-3
1
4.5
25
2,3
3
25
1,2,3
±VCC = ±18 V,
Unit
01
01
mA
µA
10
mode = sample
±VCC = ±18 V,
mode = hold
Input offset voltage
1
2,3
0.5
VOS /
±VCC = ±15 V,
1
∆VOS
1Drive = +1 mA
±VCC = ±15 V,
1Drive = +1 mA to –1 mA
Output short circuit
current
1
+IOS
-3.5
3.5
2,3
-6
6
1
-1.1
1.1
2,3
-2
2
7
20
-25
7
-1
1
-0.5
5
1
±VCC = ±18 V,
01
01
mV
mA
TA = +25°C
-IOS
±VCC = ±18 V,
TA = +25°C
Logic reference pin
current
ILOG
±VCC = ±18 V,
1
mode = sample
2,3
±VCC = ±18 V,
1,2,3
01
µA
10
mode = hold
See footnotes at end of table.
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TABLE I. Electrical performance characteristics – Continued.
Test
Symbol
Conditions 1/
-55°C ≤ TA ≤ +125°C
unless otherwise specified
ILOG
VIN = 2.4 V
Group A
subgroups
Device
type
1
02
Limits 2/
Min
Logic and logic reference
input current
2,3
VIN = 0 V
Power supply rejection
ratio
PSRR
Max
10
µA
20
1
-10
2,3
-20
+VCC = 10 V,
1
-VCC = -15 V
2,3
74
+VCC = 15 V,
1
80
-VCC = -10 V
2,3
74
01
80
1,2,3
02
80
+VCC = 3.5 V,
1
01
86
-VCC = -32.5 V
2,3
74
+VCC = 32.5 V,
1
86
-VCC = -3.5 V
2,3
74
CH = 0.01 µF,
1
02
86
+VCC = 15 V, VOUT = 0 V,
Unit
dB
-VCC = -10 V
Feed through rejection
ratio
Feed through attenuation
ratio
FTRR
FTAR
dB
dB
TA = +25°C
Differential logic level 5/
VTH
TA = +25°C
1
All
0.8
2.4
V
Second stage VOS
VOS
+VCC = 3.5 V,
1
01
-35
35
mV
(2 nd
stage)
-VCC = -32.5 V
2,3
-50
50
+VCC = 3.0 V,
1
-35
35
2,3
-50
50
1
-35
35
2,3
-50
50
+VCC = 7 V,
1
-35
35
-VCC = -3 V
2,3
-50
50
-VCC = -7 V
+VCC = 32.5 V,
-VCC = -3.5 V
See footnotes at end of table.
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TABLE I. Electrical performance characteristics – Continued.
Test
Symbol
Conditions 1/
-55°C ≤ TA ≤ +125°C
unless otherwise specified
tAQ
∆VOUT = 10 V,
Group A
subgroups
Device
type
4
01
Limits 2/
Min
Acquisition time 6/
Unit
Max
6
µs
TA = +25°C,
CHOLD = 1000 pF
25
∆VOUT = 10 V,
TA = +25°C,
CHOLD = 0.01 µF
Gain error
AE
+VCC = 7 V,
1
-VCC = -3 V
2,3
.06
+VCC = 3.5 V,
1
.005
-VCC = -26.5 V
2,3
.02
+VCC = 32.5 V,
1
.005
2,3
.06
1
.005
2,3
.02
-VCC = -3.5 V
+VCC = 26.5 V,
-VCC = -3.5 V
1
VIN = -10 V to 10 V,
RL = 2 kΩ
VIN = -11.5 V to 11.5 V,
RL = 10 kΩ
01
.02
02
%
.007
2,3
.01
1
.007
2,3
.01
1/ Unless otherwise specified, VCC = ±15 V, CHOLD = 0.01 µF, and logic reference pin = 0 V. For device type 01,
RL = 10 kΩ and VIN = 0 V. For device type 02, RL = 2 kΩ, VIN = -11.5 V to +11.5 V and logic voltage = 2.5 V.
2/ The algebraic convention, whereby the most negative value is a minimum and the most positive is a maximum,
is used in this table. Negative current shall be defined as conventional current flow out of a device terminal.
3/ Leakage current is measured at a junction temperature of 25°C. The effects of junction temperature rise due to power
dissipation of elevated ambient can be calculated by doubling the 25°C value for each 11°C increase in chip temperature.
Leakage is guaranteed over full input signal range.
4/ Hold step is sensitive to stray capacitive coupling between input logic signals and the hold capacitor. One pF, for
instance, will create an additional 0.5 mV step with 5 V logic swing and a 0.01 µF hold capacitor. Magnitude of the
hold step is inversely proportional to hold capacitor value.
5/ Parameter tested go-no-go only.
6/ If not tested, shall be guaranteed to the limits specified in table I herein.
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Device types
01
Case outlines
G
Terminal
number
1
02
Z
P
Terminal symbol
+VCC
INPUT
+VCC
NC
3
OFFSET
ADJUST
+INPUT
-VCC
OFFSET
ADJUST
+INPUT
4
-VCC
NC
-VCC
5
OUTPUT
NC
OUTPUT
6
CH
NC
CH
7
OUTPUT
8
LOGIC
REFERENCE
LOGIC
CH
LOGIC
REFERENCE
LOGIC
9
---
NC
---
10
---
---
11
---
LOGIC
REFERENCE
LOGIC
---
12
---
+VCC
---
13
---
NC
---
14
---
OFFSET
ADJUST
---
2
NC = No connection
FIGURE 1. Terminal connections.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
DSCC FORM 2234
APR 97
SIZE
5962-87608
A
REVISION LEVEL
D
SHEET
12
FIGURE 2. Logic diagram.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
DSCC FORM 2234
APR 97
SIZE
5962-87608
A
REVISION LEVEL
D
SHEET
13
4. QUALITY ASSURANCE PROVISIONS
4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with
MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan
shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be
in accordance with MIL-PRF-38535, appendix A.
4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted
on all devices prior to qualification and technology conformance inspection. For device class M, screening shall be in
accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection.
4.2.1 Additional criteria for device class M.
a.
Burn-in test, method 1015 of MIL-STD-883.
(1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision
level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in
test method 1015.
(2) TA = +125°C, minimum.
b.
Interim and final electrical test parameters shall be as specified in table IIA herein.
4.2.2 Additional criteria for device classes Q and V.
a.
The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the
device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under
document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test
method 1015 of MIL-STD-883.
b.
Interim and final electrical test parameters shall be as specified in table IIA herein.
c.
Additional screening for device class V beyond the requirements of device class Q shall be as specified in
MIL-PRF-38535, appendix B.
4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in
accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for
groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.4).
4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with
MIL-PRF-38535 including groups A, B, C, D, and E inspections and as specified herein. Quality conformance inspection for
device class M shall be in accordance with MIL-PRF-38535, appendix A and as specified herein. Inspections to be performed
for device class M shall be those specified in method 5005 of MIL-STD-883 and herein for groups A, B, C, D, and E inspections
(see 4.4.1 through 4.4.4).
4.4.1 Group A inspection.
a.
Tests shall be as specified in table IIA herein.
b.
Subgroups 7, 8, 9, 10, and 11 in table I, method 5005 of MIL-STD-883 shall be omitted.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
DSCC FORM 2234
APR 97
SIZE
5962-87608
A
REVISION LEVEL
D
SHEET
14
TABLE IIA. Electrical test requirements.
Test requirements
Subgroups
(in accordance with
MIL-PRF-38535, table III)
Subgroups
(in accordance with
MIL-STD-883,
method 5005, table I)
Device
class M
Device
class Q
Device
class V
Interim electrical
parameters (see 4.2)
1
1
1
Final electrical
parameters (see 4.2)
1,2,3,4 1/
1,2,3,4 1/
1,2,3,4 1/
Group A test
requirements (see 4.4)
1,2,3,4
1,2,3,4
1,2,3,4
Group C end-point electrical
parameters (see 4.4)
1
1
1,2,3 2/
Group D end-point electrical
parameters (see 4.4)
1
1
1,2,3
Group E end-point electrical
parameters (see 4.4)
1
1
1
1/ PDA applies to subgroup 1.
2/ Delta limits as specified in table IIB shall be required where specified, and the delta limits
shall be computed with reference to the previous endpoint electrical parameters.
Table IIB. Group C end-point electrical parameters. TA = 25°C
Parameter
Device type 01
Delta limit
Conditions
Min
Max
VIO
+VCC = 15 V, -VCC = -15 V
-0.5 mV
0.5 mV
IIB
+VCC = 15 V, -VCC = -15 V
-2.5 nA
2.5 nA
4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table IIA herein.
4.4.2.1 Additional criteria for device class M. Steady-state life test conditions, method 1005 of MIL-STD-883:
a.
Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level
control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify
the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method
1005 of MIL-STD-883.
b.
TA = +125°C, minimum.
c.
Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
DSCC FORM 2234
APR 97
SIZE
5962-87608
A
REVISION LEVEL
D
SHEET
15
4.4.2.2 Additional criteria for device classes Q and V. The steady-state life test duration, test condition and test temperature,
or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The
test circuit shall be maintained under document revision level control by the device manufacturer's TRB in accordance with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify
the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1005 of
MIL-STD-883.
4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table IIA herein.
4.4.4 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness
assured (see 3.5 herein).
a.
End-point electrical parameters shall be as specified in table IIA herein.
b.
For device classes Q and V, the devices or test vehicle shall be subjected to radiation hardness assured tests as
specified in MIL-PRF-38535 for the RHA level being tested. For device class M, the devices shall be subjected to
radiation hardness assured tests as specified in MIL-PRF-38535, appendix A for the RHA level being tested. All
device classes must meet the post irradiation end-point electrical parameter limits as defined in table I at
TA = +25°C ±5°C, after exposure, to the subgroups specified in table IIA herein.
c.
When specified in the purchase order or contract, a copy of the RHA delta limits shall be supplied.
5. PACKAGING
5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device
classes Q and V or MIL-PRF-38535, appendix A for device class M.
6. NOTES
6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications
(original equipment), design applications, and logistics purposes.
6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a
contractor-prepared specification or drawing.
6.2 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for
the individual documents. This coordination will be accomplished DD Form 1692, Engineering Change Proposal.
6.3 Record of users. Military and industrial users should inform Defense Supply Center Columbus when a system
application requires configuration control and which SMD's are applicable to that system. DSCC will maintain a record of users
and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering
microelectronic devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0544.
6.4 Comments. Comments on this drawing should be directed to DSCC-VA, Columbus, Ohio 43216-5000, or telephone
(614) 692-0547.
6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in
MIL-PRF-38535 and MIL-HDBK-1331.
6.6 Sources of supply.
6.6.1 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in QML-38535.
The vendors listed in QML-38535 have submitted a certificate of compliance (see 3.6 herein) to DSCC-VA and have agreed to
this drawing.
6.6.2 Approved sources of supply for device class M. Approved sources of supply for class M are listed in MIL-HDBK-103.
The vendors listed in MIL-HDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been
submitted to and accepted by DSCC-VA.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
DSCC FORM 2234
APR 97
SIZE
5962-87608
A
REVISION LEVEL
D
SHEET
16
STANDARD MICROCIRCUIT DRAWING BULLETIN
DATE: 01-05-24
Approved sources of supply for SMD 5962-87608 are listed below for immediate acquisition information only and
shall be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be
revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a
certificate of compliance has been submitted to and accepted by DSCC-VA. This bulletin is superseded by the next
dated revision of MIL-HDBK-103 and QML-38535.
Standard
microcircuit drawing
PIN 1/
Vendor
CAGE
number
Vendor
similar
PIN 2/
Reference
military specification
PIN
5962-8760801GA
27014
LF198H/883
M38510/12501BGA
5962-8760802PA
3/
5537/BPA
M38510/12502BPA
5962-8760801QZA
27014
LF198WG/883
---
5962-8760801VZA
27104
LF198WG-QMLV
---
1/ The lead finish shown for each PIN representing a hermetic package is the most
readily available from the manufacturer listed for that part. If the desired lead
finish is not listed contact the vendor to determine its availability.
2/ Caution. Do not use this number for item acquisition. Items acquired to this
number may not satisfy the performance requirements of this drawing.
3/ Not available from an approved source of supply.
Vendor CAGE
number
27014
Vendor name
and address
National Semiconductor Corporation
2900 Semiconductor Drive
P.O. Box 58090
Santa Clara, CA 95052-8090
The information contained herein is disseminated for convenience only and the
Government assumes no liability whatsoever for any inaccuracies in the
information bulletin.