APPLICATION BULLETIN ® Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706 Tel: (602) 746-1111 • Twx: 910-952-111 • Telex: 066-6491 • FAX (602) 889-1510 • Immediate Product Info: (800) 548-6132 THE MPC100 ANALOG MULTIPLEXER IMPROVES RF SIGNAL DISTRIBUTION By Christian Henn When designing high-performance systems for RF and video applications requiring amplifiers, multiplexers, DC restoration circuits, switched and continuous multipliers, or programmable gain amplifiers, finding the right component to do the job is not easy. The new 4 to 1 video multiplexer MPC100 opens the door to high-speed signal distribution without the headaches. This component contains four wideband open-loop amplifiers connected together internally at the output with a bandwidth of 180MHz at 1.4Vpp signal swing. When the user selects one channel by applying a digital “1” to the corresponding SEL input (see Figure 1), the component acts as a buffer amplifier with a high input impedance of 0.88MΩ||1pF and a low output impedance of 11Ω. The MPC100 can be used to design a bus-controlled distribution field, as shown in Figure 3. In this application, a driver device, which is controlled by a memory and a parallel-to-serial converter, shifts the information about the field state into the output latches, U1, U2, and U3. When the strobe line is triggered the new latch information is stored in the output latches, which controls whether the buffers of the MPC100 (U4-U9) are in an “on” or “off” state. The MPC100 operates with a fast make-before-break switching action to keep the output switching transients small and short. As shown in Figure 2, the switching time from one channel to the next is less than 0.5µs, and the signal envelope during transition rises and falls symmetrically and shows practically no overshoot or DC settling effects. A transmission SWITCHING ENVELOPE 1 IN2 3 IN3 5 IN4 7 DB1 DB2 11 Output Voltage (V) IN1 VOUT DB3 DB4 14 13 9 8 SEL1 SEL2 SEL3 SEL4 Time (µs) FIGURE 1. MPC100 Wide Bandwidth 4 X 1 Video Multiplexer. MPC100 SEL Inputs SER IN 2 FIGURE 2. Switching Time from Channel to Channel of the MPC100. MPC100 SEL Inputs 3 3 5 7 7 1 3 5 7 4 5 6 7 14 13 12 11 4 5 6 7 14 13 12 11 Parallel Out HC4094 0 1 5 MPC100 SEL Inputs 1 3 1 MPC100 SEL Inputs SER 9 Out 15 2 1 3 Parallel Out HC4094 3 1 5 7 SER 9 Out 15 CLOCK STR OE FIGURE 3. Serial Bus-controlled Distribution Field Using the MPC100. © 1993 Burr-Brown Corporation AB-049 Printed in U.S.A. March, 1993 rate of up to several MHz ensures control during the vertical blanking line, even in huge crosspoint fields. table in Figure 4, a two-bit logic can vary the amplitude of the RF signal at the output of the subsequent OPA621 within less than 0.5µs from a gain of zero when all channels are off to gain of two when DBI is selected. The digital amplitude control can easily be combined with an AGC amplifier. The MPC100 sets the rough range and the AGC circuit the fine tuning. The MPC100 is available in a 14-pin plastic DIP or plastic SOIC package. Other performance highlights are low interchannel crosstalk (<60dB in SO package), a low differential gain of 0.05%, low phase errors of 0.01 degrees, a low quiescent current of ±230µA when no channel is selected. Figure 4 shows the MPC100 used in a digitally controlled amplitude control system. With one MPC100, it is possible to perform four amplitude steps. Two MPC100s will perform eight steps. The R/2R ladder network used in this application varies the output swing by a factor of two when switching from one channel to the other, the highest gain being G = 1. The BUF600 decouples the RF input and drives the resistor network, which is connected from the amplifier’s output to ground. The taps of the ladder network are tied to the channel inputs of the MPC100. A 74HC237 decoder controls the channel selection. As illustrated in the truth +5V 2.2µF +5V 0.1µF 470pF +5V In 150Ω 10 1 4 BUF600 +1 5 –5V 75Ω 8 150Ω 1 DB1 2 75Ω 150Ω 150Ω 3 R/2R Ladder Network 75Ω 75Ω 150Ω 75Ω 150Ω 13 14 9 13 8 12 4 8 5 LE GND CS2 Y1 2 74HC 237 3 Y2 5 Y3 150Ω 7 3 2 5 1 Y0 A0 A1 A2 CS1 +5V 11 75Ω 150Ω 15 DB2 4 150Ω 14 OPA621 DB3 75Ω 6 Out 4 6 –5V 7 150Ω DB4 150Ω MPC100 12 2.2µF 470pF –5V FIGURE 4. Digital Gain Control Circuit Using the MPC100. 2 CS A1 A0 GAIN SEL 2 3 4 0 0 0 0 1 0 0 1 1 X 0 1 0 1 X 2 1 0.5 0.25 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 0