a 2.5 V to 5.5 V, 400 A, 2-Wire Interface, Quad Voltage Output, 8-/10-/12-Bit DACs AD5306/AD5316/AD5326* GENERAL DESCRIPTION FEATURES AD5306: Four Buffered 8-Bit DACs in 16-Lead TSSOP AD5316: Four Buffered 10-Bit DACs in 16-Lead TSSOP AD5326: Four Buffered 12-Bit DACs in 16-Lead TSSOP Low Power Operation: 400 A @ 3 V, 500 A @ 5 V 2-Wire (I2C®-Compatible) Serial Interface 2.5 V to 5.5 V Power Supply Guaranteed Monotonic By Design over All Codes Power-Down to 90 nA @ 3 V, 300 nA @ 5 V (PD Pin or Bit) Double-Buffered Input Logic Buffered/Unbuffered Reference Input Options Output Range: 0–VREF or 0–2 V REF Power-On-Reset to Zero Volts Simultaneous Update of Outputs (LDAC Pin) Software Clear Facility Data Readback Facility On-Chip Rail-to-Rail Output Buffer Amplifiers Temperature Range –40ⴗC to +105ⴗC The AD5306/AD5316/AD5326 are quad 8-, 10-, and 12-bit buffered voltage output DACs, in a 16-lead TSSOP package, that operate from a single 2.5 V to 5.5 V supply, consuming 500 µA at 3 V. Their on-chip output amplifiers allow rail-to-rail output swing with a slew rate of 0.7 V/µs. A 2-wire serial interface that operates at clock rates up to 400 kHz is used. This interface is SMBus-compatible at VDD < 3.6 V. Multiple devices can be placed on the same bus. Each DAC has a separate reference input that can be configured as buffered or unbuffered. The outputs of all DACs may be updated simultaneously using the asynchronous LDAC input. The parts incorporate a power-on-reset circuit that ensures that the DAC outputs power-up to zero volts and remain there until a valid write to the device takes place. There is also a software clear function that clears all DACs to 0 V. The parts contain a powerdown feature that reduces the current consumption of the device to 300 nA @ 5 V (90 nA @ 3 V). All three parts are offered in the same pinout, which allows users to select the amount of resolution appropriate for their application without redesigning their circuit board. APPLICATIONS Portable Battery-Powered Instruments Digital Gain and Offset Adjustment Programmable Voltage and Current Sources Programmable Attenuators Industrial Process Control FUNCTIONAL BLOCK DIAGRAM VREFA VREFB VDD AD5306/AD5316/AD5326 GAIN-SELECT LOGIC LDAC SCL SDA A1 INPUT REGISTER DAC REGISTER STRING DAC A BUFFER VOUTA INPUT REGISTER DAC REGISTER STRING DAC B BUFFER VOUTB INPUT REGISTER DAC REGISTER STRING DAC C BUFFER VOUTC INPUT REGISTER DAC REGISTER STRING DAC D BUFFER VOUTD INTERFACE LOGIC A0 LDAC POWER-DOWN LOGIC POWER-ON RESET VREFD VREFC PD GND *Protected by U.S. Patent Numbers 5,969,657 and 5,684,481. I2C is a registered trademark of Philips Corporation. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001 AD5306/AD5316/AD5326–SPECIFICATIONS (V DD = 2.5 V to 5.5 V; VREF = 2 V; RL = 2 k⍀ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX unless otherwise noted.) B Version2 Typ Max Unit Conditions/Comments 8 ± 0.15 ± 0.02 ±1 ± 0.25 Bits LSB LSB Guaranteed Monotonic by Design over All Codes 10 ± 0.5 ± 0.05 ±4 ± 0.5 Bits LSB LSB Guaranteed Monotonic by Design over All Codes 12 ±2 ± 0.2 ±5 ± 0.3 10 ± 16 ±1 ± 60 ± 1.25 60 Bits LSB LSB mV % of FSR mV Upper Deadband5 10 60 mV Offset Error Drift6 Gain Error Drift6 DC Power Supply Rejection Ratio6 DC Crosstalk6 –12 –5 –60 200 Parameter1 Min 3, 4 DC PERFORMANCE AD5306 Resolution Relative Accuracy Differential Nonlinearity AD5316 Resolution Relative Accuracy Differential Nonlinearity AD5326 Resolution Relative Accuracy Differential Nonlinearity Offset Error Gain Error Lower Deadband5 DAC REFERENCE INPUTS6 VREF Input Range ppm of FSR/°C ppm of FSR/°C dB µV ∆VDD = ± 10% RL = 2 kΩ to GND or VDD >10 180 90 –90 –75 V V MΩ kΩ kΩ dB dB Buffered Reference Mode Unbuffered Reference Mode Buffered Reference Mode and Power-Down Mode Unbuffered Reference Mode. 0–VREF Output Range Unbuffered Reference Mode. 0–2 VREF Output Range Frequency = 10 kHz Frequency = 10 kHz 0.001 VDD – 0.001 0.5 25 16 2.5 5 V V Ω mA mA µs µs This is a measure of the minimum and maximum drive capability of the output amplifier. 1 0.25 VREF Input Impedance 148 74 Reference Feedthrough Channel-to-Channel Isolation OUTPUT CHARACTERISTICS6 Minimum Output Voltage7 Maximum Output Voltage7 DC Output Impedance Short Circuit Current Power-Up Time VDD VDD LOGIC INPUTS (Excl. SCL, SDA)6 Input Current VIL, Input Low Voltage VIH, Input High Voltage Pin Capacitance LOGIC INPUTS (SCL, SDA)6 VIH, Input High Voltage VIL, Input Low Voltage IIN, Input Leakage Current VHYST, Input Hysteresis CIN, Input Capacitance Glitch Rejection Guaranteed Monotonic by Design over All Codes VDD = 4.5 V, Gain = 2; See Figures 2 and 3 VDD = 4.5 V, Gain = 2; See Figures 2 and 3 See Figure 2; Lower Deadband Exists Only If Offset Error Is Negative See Figure 3; Upper Deadband Exists Only If VREF = VDD and Offset Plus Gain Error Is Positive ±1 0.8 0.6 0.5 µA V V V V pF VDD + 0.3 0.3 VDD ±1 V V µA V pF ns 1.7 3 0.7 VDD –0.3 0.05 VDD 8 50 VDD = 5 V VDD = 3 V Coming Out of Power-Down Mode. VDD = 5 V Coming Out of Power-Down Mode. VDD = 3 V VDD = 5 V ± 10% VDD = 3 V ± 10% VDD = 2.5 V VDD = 2.5 V to 5.5 V; TTL and 1.8 V CMOS-Compatible SMBus-Compatible at VDD < 3.6 V SMBus-Compatible at VDD < 3.6 V See TPC 15 Input Filtering Suppresses Noise Spikes of Less than 50 ns 6 LOGIC OUTPUT (SDA) VOL, Output Low Voltage Three-State Leakage Current Three-State Output Capacitance 0.4 0.6 ±1 8 V V µA pF –2– ISINK = 3 mA ISINK = 6 mA REV. B AD5306/AD5316/AD5326 2 Parameter1 POWER REQUIREMENTS VDD IDD (Normal Mode)8 VDD = 4.5 V to 5.5 V VDD = 2.5 V to 3.6 V IDD (Power-Down Mode) VDD = 4.5 V to 5.5 V VDD = 2.5 V to 3.6 V Min B Version Typ Max Unit 5.5 V 500 400 900 750 µA µA 0.3 0.09 1 1 µA µA 2.5 Conditions/Comments VIH = VDD and VIL = GND. Interface Inactive All DACs in Unbuffered Mode. In Buffered Mode extra current is typically x µA per DAC where x = 5 µA + VREF/RDAC. VIH = VDD and VIL = GND. Interface Inactive IDD = 3 µA (Max) During “0” Readback on SDA IDD = 1.5 µA (Max) During “0” Readback on SDA NOTES 1 See Terminology. 2 Temperature range: B Version: –40°C to +105°C; typical at 25°C. 3 DC specifications tested with the outputs unloaded. 4 Linearity is tested using a reduced code range: AD5306 (Code 8 to 255); AD5316 (Code 28 to 1023); AD5326 (Code 115 to 4095). 5 This corresponds to x codes. x = Deadband Voltage/LSB size. 6 Guaranteed by design and characterization; not production tested. 7 For the amplifier output to reach its minimum voltage, Offset Error must be negative; for the amplifier output to reach its maximum voltage, V REF = VDD and Offset plus Gain Error must be positive. 8 Interface inactive; all DACs active. DAC outputs unloaded. Specifications subject to change without notice. AC CHARACTERISTICS1 (VDD = 2.5 V to 5.5 V; RL = 2 k⍀ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX unless otherwise noted.) Parameter2 Output Voltage Settling Time AD5306 AD5316 AD5326 Slew Rate Major-Code Change Glitch Energy Digital Feedthrough Digital Crosstalk Analog Crosstalk DAC-to-DAC Crosstalk Multiplying Bandwidth Total Harmonic Distortion Min B Version3 Typ Max 6 7 8 0.7 12 0.5 0.5 1 3 200 –70 8 9 10 Unit µs µs µs V/µs nV sec nV sec nV sec nV sec nV sec kHz dB NOTES 1 Guaranteed by design and characterization; not production tested. 2 See Terminology. 3 Temperature range: B Version: –40°C to +105°C; typical at 25°C. Specifications subject to change without notice. REV. B –3– Conditions/Comments VREF = VDD = 5 V 1/4 Scale to 3/4 Scale Change (40 Hex to C0 Hex) 1/4 Scale to 3/4 Scale Change (100 Hex to 300 Hex) 1/4 Scale to 3/4 Scale Change (400 Hex to C00 Hex) 1 LSB Change Around Major Carry VREF = 2 V ± 0.1 V p-p. Unbuffered Mode VREF = 2.5 V ± 0.1 V p-p. Frequency = 10 kHz AD5306/AD5316/AD5326 TIMING CHARACTERISTICS1 Parameter2 fSCL t1 t2 t3 t4 t5 t6 3 t7 t8 t9 t10 t11 t12 t13 Cb (VDD = 2.5 V to 5.5 V; all specifications TMIN to TMAX unless otherwise noted.) B Version Limit at TMIN, TMAX Unit Conditions/Comments 400 2.5 0.6 1.3 0.6 100 0.9 0 0.6 0.6 1.3 300 0 250 0 300 20 + 0.1Cb4 20 400 400 kHz max µs min µs min µs min µs min ns min µs max µs min µs min µs min µs min ns max ns min ns max ns min ns max ns min ns min ns min pF max SCL Clock Frequency SCL Cycle Time tHIGH, SCL High Time tLOW, SCL Low Time tHD,STA, Start/Repeated Start Condition Hold Time tSU,DAT, Data Setup Time tHD,DAT, Data Hold Time tSU,STA, Setup Time for Repeated Start tSU,STO, Stop Condition Setup Time tBUF, Bus Free Time Between a STOP and a START Condition tR, Rise Time of SCL and SDA when Receiving tR, Rise Time of SCL and SDA when Receiving (CMOS-Compatible) tF, Fall Time of SDA when Transmitting tF, Fall Time of SDA when Receiving (CMOS-Compatible) tF, Fall Time of SCL and SDA when Receiving tF, Fall Time of SCL and SDA when Transmitting LDAC Pulsewidth SCL Rising Edge to LDAC Rising Edge Capacitive Load for Each Bus Line NOTES 1 See Figure 1. 2 Guaranteed by design and characterization; not production tested. 3 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the V IH min of the SCL signal) in order to bridge the undefined region of SCL’s falling edge. 4 Cb is the total capacitance of one bus line in pF. t R and tF measured between 0.3 V DD and 0.7 VDD. Specifications subject to change without notice. START CONDITION REPEATED START CONDITION STOP CONDITION SDA t9 t 10 t4 t 11 t3 SCL t4 t6 t2 t1 t5 t8 t7 LDAC1 t 12 t 13 t 12 LDAC2 NOTES 1ASYNCHRONOUS 2SYNCHRONOUS LDAC UPDATE MODE. LDAC UPDATE MODE. Figure 1. 2-Wire Serial Interface Timing Diagram –4– REV. B AD5306/AD5316/AD5326 ABSOLUTE MAXIMUM RATINGS1, 2 (TA = 25°C unless otherwise noted) VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V SCL, SDA to GND . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V A0, A1, LDAC, PD to GND . . . . . . . . –0.3 V to VDD + 0.3 V Reference Input Voltage to GND . . . . –0.3 V to VDD + 0.3 V VOUTA–D to GND . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V Operating Temperature Range Industrial (B Version) . . . . . . . . . . . . . . . –40°C to +105°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Junction Temperature (TJ max) . . . . . . . . . . . . . . . . . . 150°C 16-Lead TSSOP Package Power Dissipation . . . . . . . . . . . . . . . . . . (TJ max – TA)/θJA θJA Thermal Impedance . . . . . . . . . . . . . . . . . . 150.4°C/W Reflow Soldering Peak Temperature . . . . . . . . . . . . . . . . . . . . . 220 +5/–0°C Time at Peak Temperature . . . . . . . . . . . . 10 sec to 40 sec NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Transient currents of up to 100 mA will not cause SCR latch-up. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5306/AD5316/AD5326 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE ORDERING GUIDE Model Temperature Range Package Description Package Option AD5306BRU AD5316BRU AD5326BRU –40°C to +105°C –40°C to +105°C –40°C to +105°C Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) RU-16 RU-16 RU-16 REV. B –5– AD5306/AD5316/AD5326 PIN CONFIGURATION LDAC 1 VDD 2 VOUTA 3 16 A1 AD5306/ AD5316/ AD5326 15 A0 14 SCL 13 SDA TOP VIEW VOUTC 5 (Not to Scale) 12 GND VOUTB 4 11 V OUTD VREFA 6 VREFB 10 PD 7 VREFC 8 9 VREFD PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Function 1 LDAC 2 VDD 3 4 5 6 VOUTA VOUTB VOUTC VREFA 7 VREFB 8 VREFC 9 VREFD 10 PD 11 12 13 VOUTD GND SDA 14 SCL 15 16 A0 A1 Active low control input that transfers the contents of the input registers to their respective DAC registers. Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data. This allows simultaneous update of all DAC outputs. Alternatively, this pin can be tied permanently low. Power Supply Input. These parts can be operated from 2.5 V to 5.5 V and the supply should be decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND. Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. Buffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation. Reference Input Pin for DAC A. It may be configured as a buffered or an unbuffered input depending on the state of the BUF bit in the input word to DAC A. It has an input range from 0.25 V to VDD in unbuffered mode and from 1 V to VDD in buffered mode. Reference Input Pin for DAC B. It may be configured as a buffered or an unbuffered input depending on the state of the BUF bit in the input word to DAC B. It has an input range from 0.25 V to VDD in unbuffered mode and from 1 V to VDD in buffered mode. Reference Input Pin for DAC C. It may be configured as a buffered or an unbuffered input depending on the state of the BUF bit in the input word to DAC C. It has an input range from 0.25 V to VDD in unbuffered mode and from 1 V to VDD in buffered mode. Reference Input Pin for DAC D. It may be configured as a buffered or an unbuffered input depending on the state of the BUF bit in the input word to DAC D. It has an input range from 0.25 V to VDD in unbuffered mode and from 1 V to VDD in buffered mode. Active low control input that acts as a hardware Power-Down option. All DACs go into power-down mode when this pin is tied low. The DAC outputs go into a high-impedance state. The current consumption of the part drops to 300 nA @ 5 V (90 nA @ 3 V). Buffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation. Ground reference point for all circuitry on the part. Serial Data Line. This is used in conjunction with the SCL line to clock data into the 16-bit input shift register. It is a bidirectional open-drain data line that should be pulled to the supply with an external pull-up resistor. Serial Clock Line. This is used in conjunction with the SDA line to clock data into the 16-bit input shift register. Clock rates of up to 400 kbit/s can be accommodated in the I2C-compatible interface. Address Input. Sets the least significant bit of the 7-bit slave address. Address Input. Sets the second least significant bit of the 7-bit slave address. –6– REV. B AD5306/AD5316/AD5326 TERMINOLOGY RELATIVE ACCURACY For the DAC, relative accuracy or integral nonlinearity (INL) is a measure of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. Typical INL versus Code plots can be seen in TPCs 1, 2, and 3. MAJOR-CODE TRANSITION GLITCH ENERGY Major-code transition glitch energy is the energy of the impulse injected into the analog output when the code in the DAC register changes state. It is normally specified as the area of the glitch in nV secs and is measured when the digital code is changed by 1 LSB at the major carry transition (011 . . . 11 to 100 . . . 00 or 100 . . . 00 to 011 . . . 11). DIFFERENTIAL NONLINEARITY Differential Nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ± 1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. Typical DNL versus Code plots can be seen in TPCs 4, 5, and 6. DIGITAL FEEDTHROUGH OFFSET ERROR DIGITAL CROSSTALK This is a measure of the offset error of the DAC and the output amplifier. It can be positive or negative. See Figures 2 and 3. It is expressed in mV. This is the glitch impulse transferred to the output of one DAC at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) in the input register of another DAC. It is expressed in nV secs. Digital feedthrough is a measure of the impulse injected into the analog output of a DAC from the digital input pins of the device, when the DAC output is not being updated. It is specified in nV secs and is measured with a worst-case change on the digital input pins, i.e., from all 0s to all 1s or vice versa. GAIN ERROR This is a measure of the span error of the DAC. It is the deviation in slope of the actual DAC transfer characteristic from the ideal expressed as a percentage of the full-scale range. ANALOG CROSSTALK This is a measure of the change in offset error with changes in temperature. It is expressed in (ppm of full-scale range)/°C. This is the glitch impulse transferred to the output of one DAC due to a change in the output of another DAC. It is measured by loading one of the DACs with a full-scale code change (all 0s to all 1s and vice versa) while keeping LDAC high. Then pulse LDAC low and monitor the output of the DAC whose digital code was not changed. The energy of the glitch is expressed in nV secs. GAIN ERROR DRIFT DAC-TO-DAC CROSSTALK This is a measure of the change in gain error with changes in temperature. It is expressed in (ppm of full-scale range)/°C. This is the glitch impulse transferred to the output of one DAC due to a digital code change and subsequent output change of another DAC. This includes both digital and analog crosstalk. It is measured by loading one of the DACs with a full-scale code change (all 0s to all 1s and vice versa) with LDAC low and monitoring the output of another DAC. The energy of the glitch is expressed in nV secs. OFFSET ERROR DRIFT DC POWER-SUPPLY REJECTION RATIO (PSRR) This indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in VOUT to a change in VDD for full-scale output of the DAC. It is measured in dBs. VREF is held at 2 V and VDD is varied ± 10%. MULTIPLYING BANDWIDTH DC CROSSTALK This is the dc change in the output level of one DAC at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) and output change of another DAC. It is expressed in µV. The amplifiers within the DAC have a finite bandwidth. The multiplying bandwidth is a measure of this. A sine wave on the reference (with full-scale code loaded to the DAC) appears on the output. The multiplying bandwidth is the frequency at which the output amplitude falls to 3 dB below the input. REFERENCE FEEDTHROUGH This is the ratio of the amplitude of the signal at the DAC output to the reference input when the DAC output is not being updated (i.e., LDAC is high). It is expressed in dBs. CHANNEL-TO-CHANNEL ISOLATION TOTAL HARMONIC DISTORTION This is the difference between an ideal sine wave and its attenuated version using the DAC. The sine wave is used as the reference for the DAC, and the THD is a measure of the harmonics present on the DAC output. It is measured in dBs. This is the ratio of the amplitude of the signal at the output of one DAC to a sine wave on the reference input of another DAC. It is measured in dBs. REV. B –7– AD5306/AD5316/AD5326 GAIN ERROR + OFFSET ERROR GAIN ERROR + OFFSET ERROR OUTPUT VOLTAGE UPPER DEADBAND CODES OUTPUT VOLTAGE ACTUAL NEGATIVE OFFSET ERROR IDEAL DAC CODE POSITIVE OFFSET ERROR ACTUAL IDEAL DAC CODE FULL SCALE Figure 3. Transfer Function with Positive Offset (VREF = VDD) LOWER DEADBAND CODES AMPLIFIER FOOTROOM NEGATIVE OFFSET ERROR Figure 2. Transfer Function with Negative Offset –8– REV. B Typical Performance Characteristics–AD5306/AD5316/AD5326 TA = 25ⴗC VDD = 5V TA = 25ⴗC VDD = 5V INL ERROR – LSBs INL ERROR – LSBs 0 TA = 25ⴗC VDD = 5V 8 2 0.5 INL ERROR – LSBs 12 3 1.0 1 0 –1 4 0 –4 –0.5 –8 –2 –1.0 –3 100 150 CODE 200 250 –12 0 200 400 600 CODE 800 1000 TPC 1. AD5306 Typical INL Plot TPC 2. AD5316 Typical INL Plot 0.3 0.6 1000 2000 CODE 3000 4000 TPC 3. AD5326 Typical INL Plot 1 TA = 25ⴗC VDD = 5V 0.1 0 –0.1 DNL ERROR – LSBs DNL ERROR – LSBs 0.4 0.2 0 –0.2 0.5 0 –0.5 –0.4 –0.2 –0.3 –1 –0.6 0 50 100 150 CODE 200 0 250 TPC 4. AD5306 Typical DNL Plot 400 600 CODE 200 800 0 1000 TPC 5. AD5316 Typical DNL Plot TA = 25ⴗC VDD = 5V 0.4 2000 CODE 1000 3000 4000 TPC 6. AD5326 Typical DNL Plot 0.5 0.5 1 VDD = 5V VREF = 3V VDD = 5V VREF = 2V MAX INL 0.3 OFFSET ERROR 0.5 MAX DNL 0 MIN DNL 0.2 ERROR – % FSR MAX INL ERROR – LSBs 0.25 ERROR – LSBs 0 TA = 25ⴗC VDD = 5V TA = 25ⴗC VDD = 5V 0.2 DNL ERROR – LSBs 50 0 MAX DNL 0.1 0 –0.1 MIN DNL –0.2 0 GAIN ERROR –0.5 –0.25 –0.3 MIN INL MIN INL –0.5 0 1 2 3 VREF – V –0.4 4 TPC 7. AD5306 INL and DNL Error vs. VREF REV. B 5 –0.5 ⴚ40 0 80 TEMPERATURE – ⴰC 40 TPC 8. AD5306 INL and DNL Error vs. Temperature –9– 120 –1 ⴚ40 0 40 80 TEMPERATURE – ⴰC TPC 9. AD5306 Offset Error and Gain Error vs. Temperature 120 AD5306/AD5316/AD5326 600 5 0.2 TA = 25ⴗC VREF = 2V 0.1 4 5V SOURCE 500 3V SOURCE 400 –0.2 –0.3 3 IDD – A –0.1 2 300 200 OFFSET ERROR –0.4 1 5V SINK –0.5 –0.6 TA = 25ⴗC VDD = 5V VREF = 2V GAIN ERROR VOUT – Volts ERROR – % FSR 0 0 2 1 3 4 VDD – Volts 5 0 6 0 3V SINK 2 5 1 3 4 SINK/SOURCE CURRENT – mA 100 TPC 12. Supply Current vs. DAC Code 0.5 600 650 –40ⴗC +25ⴗC 500 FULL-SCALE CODE TPC 11. VOUT vs. Source and Sink Current Capability TPC 10. Offset Error and Gain Error vs. VDD 0 ZERO-SCALE 6 0.4 600 0.3 550 TA = 25ⴗC DECREASING INCREASING 300 IDD – A +105ⴗC IDD – A IDD – A 400 –40ⴗC 0.2 +25ⴗC 200 500 DECREASING INCREASING 0.1 100 450 VDD = 3V +105ⴗC 0 2.5 3.0 3.5 4.0 4.5 VDD – Volts 5.0 5.5 TPC 13. Supply Current vs. Supply Voltage CH1 TA = 25ⴗC VDD = 5V VREF = 5V 0 2.5 3.0 3.5 4.5 4.0 VDD – Volts 5.0 5.5 TPC 14. Power-Down Current vs. Supply Voltage CH1 VOUTA CH2 VDD = 5V TA = 25ⴗC VDD = 5V VREF = 2V 2 3 VLOGIC – Volts 4 5 TPC 15. Supply Current vs. Logic Input Voltage for SDA and SCL Voltage Increasing and Decreasing CH1 TA = 25ⴗC VDD = 5V VREF = 2V VOUTA CH2 CH2 TPC 16. Half-Scale Settling (1/4 to 3/4 Scale Code Change) 1 VDD SCL CH1 1V, CH2 5V, TIME BASE = 1s/DIV 400 0 VOUTA CH1 2.00V, CH2 200mV, TIME BASE = 200s/DIV TPC 17. Power-On Reset to 0 V –10– PD CH1 500mV, CH2 5.00V, TIME BASE = 1s/DIV TPC 18. Exiting Power-Down to Midscale REV. B AD5306/AD5316/AD5326 2.50 10 VDD = 3V 0 –10 2.49 –20 dB VOUT – Volts FREQUENCY VDD = 5V –30 2.48 –40 –50 2.47 350 450 500 IDD – A 400 550 600 –60 0.01 1s/DIV TPC 19. IDD Histogram with VDD = 3 V and VDD = 5 V 0.1 1 10 100 FREQUENCY – kHz 1k 10k TPC 21. Multiplying Bandwidth (Small-Signal Frequency Response) TPC 20. AD5326 Major-Code Transition Glitch Energy 0.02 0.01 1mV/DIV FULL-SCALE ERROR – V VDD = 5V TA = 25ⴗC 0 –0.01 –0.02 0 1 2 3 4 VREF – Volts 5 TPC 22. Full-Scale Error vs. VREF 6 150ns/DIV TPC 23. DAC-to-DAC Crosstalk FUNCTIONAL DESCRIPTION where The AD5306/AD5316/AD5326 are quad resistor-string DACs fabricated on a CMOS process with resolutions of 8, 10, and 12 bits respectively. Each contains four output buffer amplifiers and is written to via a 2-wire serial interface. They operate from single supplies of 2.5 V to 5.5 V and the output buffer amplifiers provide rail-to-rail output swing with a slew rate of 0.7 V/µs. Each DAC is provided with a separate reference input, which may be buffered to draw virtually no current from the reference source, or unbuffered to give a reference input range from 0.25 V to VDD. The devices have a power-down mode in which all DACs may be turned off completely with a high-impedance output. D = decimal equivalent of the binary code that is loaded to the DAC register; 0–255 for AD5306 (8 Bits) 0–1023 for AD5316 (10 Bits) 0–4095 for AD5326 (12 Bits) N = DAC resolution VREF A BUF REFERENCE BUFFER GAIN MODE (GAIN = 1 OR 2) Digital-to-Analog Section The architecture of one DAC channel consists of a resistor-string DAC followed by an output buffer amplifier. The voltage at the VREF pin provides the reference voltage for the corresponding DAC. Figure 4 shows a block diagram of the DAC architecture. Since the input coding to the DAC is straight binary, the ideal output voltage is given by: VREF × D VOUT = 2N REV. B INPUT REGISTER DAC REGISTER RESISTOR STRING VOUTA OUTPUT BUFFER AMPLIFIER Figure 4. Single DAC Channel Architecture –11– AD5306/AD5316/AD5326 Resistor String POWER-ON RESET The resistor string section is shown in Figure 5. It is simply a string of resistors, each of value R. The digital code loaded to the DAC register determines at which node on the string the voltage is tapped off to be fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. Because it is a string of resistors, it is guaranteed monotonic. The AD5306/AD5316/AD5326 are provided with a power-on reset function, so that they power up in a defined state. The power-on state is: DAC Reference Inputs There is a reference pin for each of the four DACs. The reference inputs are buffered but can also be individually configured as unbuffered. The advantage with the buffered input is the high impedance it presents to the voltage source driving it. However, if the unbuffered mode is used, the user can have a reference voltage as low as 0.25 V and as high as VDD since there is no restriction due to headroom and footroom of the reference amplifier. R R R TO OUTPUT AMPLIFIER • • • • Normal Operation Reference Inputs Unbuffered 0–VREF Output Range Output Voltage Set to 0 V Both input and DAC registers are filled with zeros and remain so until a valid write sequence is made to the device. This is particularly useful in applications where it is important to know the state of the DAC outputs while the device is powering up. SERIAL INTERFACE The AD5306/AD5316/AD5326 are controlled via an I2Ccompatible serial bus. These devices are connected to this bus as slave devices (i.e., no clock is generated by the AD5306/ AD5316/AD5326 DACs). This interface is SMBus-compatible at VDD < 3.6 V. The AD5306/AD5316/AD5326 has a 7-bit slave address. The five MSBs are 00011 and the two LSBs are determined by the state of the A0 and A1 pins. The facility to make hardwired changes to A0 and A1 allows the user to have up to four of these devices on one bus. The 2-wire serial bus protocol operates as follows: R R Figure 5. Resistor String 1. The master initiates data transfer by establishing a START condition which is when a high-to-low transition on the SDA line occurs while SCL is high. The following byte is the address byte which consists of the 7-bit slave address followed by an R/W bit (this bit determines whether data will be read from or written to the slave device). The slave whose address corresponds to the transmitted address responds by pulling SDA low during the 9th clock pulse (this is termed the Acknowledge bit). At this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its shift register. If there is a buffered reference in the circuit (e.g., REF192), there is no need to use the on-chip buffers of the AD5306/ AD5316/AD5326. In unbuffered mode the input impedance is still large at typically 180 kΩ per reference input for 0–VREF mode and 90 kΩ for 0–2 VREF mode. The buffered/unbuffered option is controlled by the BUF bit in the Control Byte. The BUF bit setting applies to whichever DAC is selected in the Pointer Byte. Output Amplifier The output buffer amplifier is capable of generating output voltages to within 1 mV of either rail. Its actual range depends on the value of VREF, GAIN, offset error, and gain error. If a gain of 1 is selected (GAIN = 0), the output range is 0.001 V to VREF. If a gain of 2 is selected (GAIN = 1), the output range is 0.001 V to 2 VREF. Because of clamping, however, the maximum output is limited to VDD – 0.001 V. 2. Data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an Acknowledge bit). The transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL. 3. When all data bits have been read or written to, a STOP condition is established. In Write mode, the master will pull the SDA line high during the 10th clock pulse to establish a STOP condition. In Read mode, the master will issue a No Acknowledge for the 9th clock pulse (i.e., the SDA line remains high). The master will then bring the SDA line low before the 10th clock pulse and then high during the 10th clock pulse to establish a STOP condition. The output amplifier is capable of driving a load of 2 kΩ to GND or VDD, in parallel with 500 pF to GND or VDD. The source and sink capabilities of the output amplifier can be seen in the plot in TPC 11. The slew rate is 0.7 V/µs with a half-scale settling time to ± 0.5 LSB (at 8 bits) of 6 µs. –12– REV. B AD5306/AD5316/AD5326 Read/Write Sequence Input Shift Register In the case of the AD5306/AD5316/AD5326, all write access sequences and most read sequences begin with the device address (with R/W = 0) followed by the pointer byte. This pointer byte specifies the data format and determines which DAC is being accessed in the subsequent read/write operation. See Figure 6. In a write operation, the data follows immediately. In a read operation, the address is resent with R/W = 1 and the data is then read back. However, it is also possible to perform a read operation by sending only the address with R/W = 1. The previously loaded pointer settings are then used for the readback operation. The input shift register is 16 bits wide. Data is loaded into the device as two data bytes on the serial data line, SDA, under the control of the serial clock input, SCL. The timing diagram for this operation is shown in Figure 1. The two data bytes consist of four control bits followed by 8, 10, or 12 bits of DAC data, depending on the device type. The first bits loaded are the control bits: GAIN, BUF, CLR, and PD. The remaining bits are left-justified DAC data bits, starting with the MSB. See Figure 7. MSB X LSB X DOUBLE = 0 LEFT = 0 DACD GAIN: 0: Output range for that DAC set at 0–VREF. 1: Output range for that DAC set at 0–2 VREF. BUF: 0: Reference Input for that DAC is unbuffered. 1: Reference Input for that DAC is buffered. CLR: 0: All DAC registers and input registers are filled with zeros on completion of the write sequence. 1: Normal operation. PD: 0: On completion of the write sequence all four DACs go into Power-Down mode. The DAC outputs enter a high-impedance state. 1: Normal operation. DACC DACB DACA Figure 6. Pointer Byte Pointer Byte Bits The following is an explanation of the individual bits that make up the Pointer Byte. X: Don’t Care Bits LEFT: 0: Data written to the device and read from the device is Left-Justified Default Readback Conditions DOUBLE: 0: Data Write and Readback are done as 2-byte write/read sequences All Pointer Byte bits power up to 0. Therefore, if the user initiates a readback without first writing to the pointer byte, no single DAC channel has been specified. In this case, the default readback bits are all 0 except for the CLR bit and the PD bit, which are 1. DACD: 1: The following data bytes are for DAC D Multiple-DAC Write Sequence DACC: 1: The following data bytes are for DAC C Because there are individual bits in the Pointer Byte for each DAC, it is possible to write the same data and control bits to 2, 3, or 4 DACs simultaneously by setting the relevant bits to 1. DACB: 1: The following data bytes are for DAC B DACA: 1: The following data bytes are for DAC A Multiple-DAC Readback Sequence If the user attempts to read back data from more than one DAC at a time, the part will read back the power-on condition of GAIN, BUF, and data bits (all 0), and the current state of CLR and PD. DATA BYTES (WRITE AND READBACK) MOST SIGNIFICANT DATA BYTE 8-BIT AD5306 MSB GAIN BUF CLR BUF CLR BUF CLR MSB GAIN D7 D6 D5 D8 D7 D10 D9 10-BIT AD5316 MSB GAIN PD PD D9 12-BIT AD5326 PD D11 LSB MSB D4 D3 LSB MSB D6 D5 LSB MSB D8 D7 LEAST SIGNIFICANT DATA BYTE 8-BIT AD5306 D2 D1 D4 D3 D6 D5 D0 –13– LSB X X D0 X D2 D1 10-BIT AD5316 D2 D1 D4 D3 X LSB 12-BIT AD5326 Figure 7. Data Formats for Write and Readback REV. B X X LSB D0 AD5306/AD5316/AD5326 WRITE OPERATION READ OPERATION When writing to the AD5306/AD5316/AD5326 DACs, the user must begin with an address byte (R/W = 0) after which the DAC will acknowledge that it is prepared to receive data by pulling SDA low. This address byte is followed by the pointer byte which is also acknowledged by the DAC. Two bytes of data are then written to the DAC as shown in Figure 8. A STOP condition follows. When reading data back from the AD5306/AD5316/AD5326 DACs, the user begins with an address byte (R/W = 0) after which the DAC will acknowledge that it is prepared to receive data by pulling SDA low. This address byte is usually followed by the pointer byte which is also acknowledged by the DAC. Following this there is a repeated start condition by the master and the address is resent with R/W = 1. This is acknowledged by the DAC indicating that it is prepared to transmit data. Two bytes of data are then read from the DAC as shown in Figure 9. A STOP condition follows. SCL 0 SDA 0 0 START COND BY MASTER 1 1 A1 A0 R/W X ACK BY AD53x6 ADDRESS BYTE X LSB ACK BY AD53x6 MSB POINTER BYTE SCL MSB SDA LSB MSB ACK BY AD53x6 MOST-SIGNIFICANT DATA BYTE LSB ACK BY AD53x6 LEAST-SIGNIFICANT DATA BYTE STOP COND BY MASTER Figure 8. Write Sequence SCL 0 SDA 0 0 START COND BY MASTER 1 A1 1 A0 X R/W ACK BY AD53x6 ADDRESS BYTE X LSB MSB POINTER BYTE ACK BY AD53x6 SCL 0 SDA 0 REPEATED START COND BY MASTER 0 1 1 A1 A0 MSB R/W ACK BY AD53x6 ADDRESS BYTE LSB MOST SIGNIFICANT DATA BYTE ACK BY MASTER SCL SDA LSB MSB LEAST SIGNIFICANT DATA BYTE NO ACK BY MASTER STOP COND BY MASTER *DATA BYTES ARE THE SAME AS THOSE IN THE WRITE SEQUENCE, EXCEPT THAT DON'T CARES ARE READ BACK AS 0s. Figure 9. Readback Sequence –14– REV. B AD5306/AD5316/AD5326 When the PD pin is high and the PD bit is set to 1, all DACs work normally with a typical power consumption of 500 µA at 5 V (400 µA at 3 V). In power-down mode, however, the supply current falls to 300 nA at 5 V (90 nA at 3 V) when all DACs are powered down. Not only does the supply current drop, but each output stage is also internally switched from the output of its amplifier, making it open-circuit. This has the advantage that the outputs are three-state while the part is in power-down mode and provides a defined input condition for whatever is connected to the output of the DAC amplifiers. The output stage is illustrated in Figure 10. However, if the master sends an ACK and continues clocking SCL (no STOP is sent), the DAC will retransmit the same two bytes of data on SDA. This allows continuous readback of data from the selected DAC register. Alternatively, the user may send a START followed by the address with R/W = 1. In this case the previously loaded pointer settings are used and readback of data can commence immediately. DOUBLE-BUFFERED INTERFACE The AD5306/AD5316/AD5326 DACs all have double-buffered interfaces consisting of two banks of registers: input registers and DAC registers. The input registers are connected directly to the input shift register and the digital code is transferred to the relevant input register on completion of a valid write sequence. The DAC registers contain the digital code used by the resistor strings. AMPLIFIER RESISTOR STRING DAC POWER-DOWN CIRCUITRY Access to the DAC registers is controlled by the LDAC pin. When LDAC is high, the DAC registers are latched and the input registers may change state without affecting the contents of the DAC registers. When LDAC is brought low, however, the DAC registers become transparent and the contents of the input registers are transferred to them. Figure 10. Output Stage During Power-Down Double-buffering is useful if the user requires simultaneous updating of all DAC outputs. The user may write to each of the input registers individually and then, by pulsing the LDAC input low, all outputs will update simultaneously. These parts contain an extra feature whereby a DAC register is not updated unless its input register has been updated since the last time that LDAC was low. Normally, when LDAC is low, the DAC registers are filled with the contents of the input registers. In the case of the AD5306/AD5316/AD5326, the part will only update the DAC register if the input register has been changed since the last time the DAC register was updated, thereby removing unnecessary digital crosstalk. Load DAC Input LDAC LDAC transfers data from the input registers to the DAC registers (and hence updates the outputs). Use of the LDAC function enables double-buffering of the DAC data, GAIN, and BUF. There are two LDAC modes: Synchronous Mode: In this mode the DAC registers are updated after new data is read in on the rising edge of the 8th SCL pulse. LDAC can be tied permanently low or pulsed as in Figure 2. The bias generator, the output amplifiers, the resistor strings, and all other associated linear circuitry are shut down when the power-down mode is activated. However, the contents of the registers are unaffected when in power-down. In fact it is possible to load new data to the input registers and DAC registers during power-down. The DAC outputs will update as soon as the PD pin goes high or the PD bit is reset to 1. The time to exit power-down is typically 2.5 s for VDD = 5 V and 5 s when VDD = 3 V. This is the time from the rising edge of the 8th SCL pulse, or from the rising edge of PD, to when the output voltage deviates from its power-down voltage. See TPC 18. APPLICATIONS Typical Application Circuit The AD5306/AD5316/AD5326 can be used with a wide range of reference voltages where the devices offer full, one-quadrant multiplying capability over a reference range of 0 V to VDD. More typically, these devices are used with a fixed, precision reference voltage. Suitable references for 5 V operation are the AD780 and REF192 (2.5 V references). For 2.5 V operation, a suitable external reference would be the AD589, a 1.23 V bandgap reference. Figure 11 shows a typical setup for the AD5306/AD5316/AD5326 when using an external reference. Note that A0 and A1 can be high or low. VDD = 2.5V TO 5.5V 0.1F VIN VOUT VREFA VREFB VREFC VREFD 1F EXT REF POWER-DOWN MODE REV. B 10F AD5306/AD5316/ AD5326 Asynchronous Mode: In this mode the outputs are not updated at the same time that the input registers are written to. When LDAC goes low, the DAC registers are updated with the contents of the input registers. The AD5306/AD5316/AD5326 have very low power consumption, dissipating typically 1.2 mW with a 3 V supply and 2.5 mW with a 5 V supply. Power consumption can be further reduced when the DACs are not in use by putting them into power-down mode, which is selected by setting the PD pin low or by setting Bit 12 (PD) of the data word to zero. VOUT VOUTA VOUTB VOUTC VOUTD SCL AD780/REF192 WITH VDD = 5V OR AD589 WITH VDD = 2.5V SDA A0 GND A1 SERIAL INTERFACE Figure 11. AD5306/AD5316/AD5326 Using a 2.5 V External Reference –15– AD5306/AD5316/AD5326 Driving VDD from the Reference Voltage Multiple Devices on One Bus If an output range of 0 V to VDD is required when the reference inputs are configured as unbuffered, the simplest solution is to connect the reference inputs to VDD. As this supply may be noisy and not very accurate, the AD5306/AD5316/AD5326 may be powered from the reference voltage; for example, using a 5 V reference such as the REF195. The REF195 will output a steady supply voltage for the AD5306/AD5316/AD5326. The typical current required from the REF195 is 500 µA supply current and approximately 112 µA to supply the reference inputs (if unbuffered). This is with no load on the DAC outputs. When the DAC outputs are loaded, the REF195 also needs to supply the current to the loads. The total current required (with a 10 kΩ load on each output) is: Figure 13 shows four AD5306 devices on the same serial bus. Each has a different slave address since the states of the A0 and A1 pins are different. This allows each of 16 DACs to be written to or read from independently. VDD VDD A1 PULL-UP RESISTORS SDA Bipolar Operation Using the AD5306/AD5316/AD5326 The AD5306/AD5316/AD5326 have been designed for singlesupply operation, but a bipolar output range is also possible using the circuit in Figure 12. This circuit will give an output voltage range of ± 5 V. Rail-to-rail operation at the amplifier output is achievable using an AD820 or an OP295 as the output amplifier. R2 10k⍀ 10F VDD VIN AD5306/AD5316/ AD5326 AD1585 VOUT GND VREFA VREFB VREFC VREFD 1F A1 A0 GND SCL VDD SDA SCL A1 AD5306 A0 AD5306 Figure 13. Multiple AD5306 Devices on One Bus A digitally programmable upper/lower limit detector using two of the DACs in the AD5306/AD5316/AD5326 is shown in Figure 14. The upper and lower limits for the test are loaded to DACs A and B which, in turn, set the limits on the CMP04. If the signal at the VIN input is not within the programmed window, a LED will indicate the fail condition. Similarly DACs C and D can be used for window detection on a second VIN signal. 5V 0.1F ⴞ5V VOUTA SCL AD5306/AD5316/AD5326 as a Digitally Programmable Window Detector +5V 0.1F SDA A1 R1 10k⍀ 6V TO 12V SCL SDA A0 The load regulation of the REF195 is typically 2 ppm/mA, which results in an error of 5.2 ppm (26 µV) for the 2.6 mA current drawn from it. This corresponds to a 0.0013 LSB error at 8 bits and 0.021 LSB error at 12 bits. AD5306 A0 MASTER 612 µA + 4(5 V/10 kΩ) = 2.6 mA 5V A1 AD5306 A0 VREF AD820/ OP295 10F VIN VOUTB VOUTC VOUTD DIN SDA SCL SCL 1k⍀ FAIL VDD VREFA VREFB PASS VOUTA 1/2 AD5306/AD5316/ AD5326* –5V 1k⍀ 1/2 CMP04 VOUTB GND PASS/FAIL 1/6 74HC05 SCL SDA *ADDITIONAL PINS OMITTED FOR CLARITY 2-WIRE SERIAL INTERFACE Figure 12. Bipolar Operation with the AD5306/ AD5316/AD5326 The output voltage for any input code can be calculated as follows: VOUT = [(REFIN × D/2N) × (R1+R2)/R1 – REFIN × (R2/R1)] where: D is the decimal equivalent of the code loaded to the DAC. N is the DAC resolution. REFIN is the reference voltage input. with: REFIN = 5 V, R1 = R2 = 10 kΩ: VOUT = (10 × D/2N) – 5 V Figure 14. Window Detection Coarse and Fine Adjustment Using the AD5306/AD5316/ AD5326 Two of the DACs in the AD5306/AD5316/AD5326 can be paired together to form a coarse and fine adjustment function, as shown in Figure 15. DAC A is used to provide the coarse adjustment while DAC B provides the fine adjustment. Varying the ratio of R1 and R2 will change the relative effect of the coarse and fine adjustments. With the resistor values and external reference shown the output amplifier has unity gain for the DAC A output, so the output range is 0 V to 2.5 V – 1 LSB. For DAC B the amplifier has a gain of 7.6 × 10–3, giving DAC B a range equal to 19 mV. Similarly DACs C and D can be paired together for coarse and fine adjustment. The circuit is shown with a 2.5 V reference, but reference voltages up to VDD may be used. The op amps indicated will allow a rail-to-rail output swing. –16– REV. B AD5306/AD5316/AD5326 R3 51.2k⍀ VDD = 5V R4 390⍀ 5V 0.1F 10F VDD V OUTA R1 390⍀ VOUT AD820/ OP295 VIN EXT REF VOUT GND AD780/REF192 WITH VDD = 5V 0.1F VREFA VREFB VOUTB 1/2 AD5306/AD5316/ AD5326 R2 51.2k⍀ GND Figure 15. Coarse/Fine Adjustment POWER SUPPLY DECOUPLING In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD5306/AD5316/AD5326 is mounted should be designed so that the analog and digital sections are separated, and confined to certain areas of the board. If the AD5306/AD5316/AD5326 is in a system where multiple devices require an AGND-to-DGND connection, the connection should be made at one point only. The star ground point should be established as close as possible to the device. The AD5306/ REV. B AD5316/AD5326 should have ample supply bypassing of 10 µF in parallel with 0.1 µF on the supply located as close to the package as possible, ideally right up against the device. The 10 µF capacitors are the tantalum bead type. The 0.1 µF capacitor should have low Effective Series Resistance (ESR) and Effective Series Inductance (ESI), like the common ceramic types that provide a low impedance path to ground at high frequencies, to handle transient currents due to internal logic switching. The power supply lines of the AD5306/AD5316/AD5326 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board, and should never be run near the reference inputs. A ground line routed between the SDA and SCL lines will help reduce crosstalk between them (not required on a multilayer board as there will be a separate ground plane, but separating the lines will help). Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far the best, but not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground plane while signal traces are placed on the solder side. –17– AD5306/AD5316/AD5326 Table I. Overview of AD53xx Serial Devices Resolution No. of DACs DNL Interface Settling Time Package Pins AD5300 AD5310 AD5320 8 10 12 1 1 1 ± 0.25 ± 0.5 ± 1.0 SPI SPI SPI 4 µs 6 µs 8 µs SOT-23, microSOIC SOT-23, microSOIC SOT-23, microSOIC 6, 8 6, 8 6, 8 AD5301 AD5311 AD5321 8 10 12 1 1 1 ± 0.25 ± 0.5 ± 1.0 2-Wire 2-Wire 2-Wire 6 µs 7 µs 8 µs SOT-23, microSOIC SOT-23, microSOIC SOT-23, microSOIC 6, 8 6, 8 6, 8 AD5302 AD5312 AD5322 8 10 12 2 2 2 ± 0.25 ± 0.5 ± 1.0 SPI SPI SPI 6 µs 7 µs 8 µs microSOIC microSOIC microSOIC 8 8 8 AD5303 AD5313 AD5323 8 10 12 2 2 2 ± 0.25 ± 0.5 ± 1.0 SPI SPI SPI 6 µs 7 µs 8 µs TSSOP TSSOP TSSOP 16 16 16 AD5304 AD5314 AD5324 8 10 12 4 4 4 ± 0.25 ± 0.5 ± 1.0 SPI SPI SPI 6 µs 7 µs 8 µs microSOIC microSOIC microSOIC 10 10 10 AD5305 AD5315 AD5325 8 10 12 4 4 4 ± 0.25 ± 0.5 ± 1.0 2-Wire 2-Wire 2-Wire 6 µs 7 µs 8 µs microSOIC microSOIC microSOIC 10 10 10 AD5306 AD5316 AD5326 8 10 12 4 4 4 ± 0.25 ± 0.5 ± 1.0 2-Wire 2-Wire 2-Wire 6 µs 7 µs 8 µs TSSOP TSSOP TSSOP 16 16 16 AD5307 AD5317 AD5327 8 10 12 4 4 4 ± 0.25 ± 0.5 ± 1.0 SPI SPI SPI 6 µs 7 µs 8 µs TSSOP TSSOP TSSOP 16 16 16 Part No. SINGLES DUALS QUADS Visit our web-page at www.analog.com/support/standard_linear/selection_guides/AD53xx.html. Table II. Overview of AD53xx Parallel Devices Part No. Resolution DNL VREF Pins Settling Time SINGLES AD5330 AD5331 AD5340 AD5341 8 10 12 12 ± 0.25 ± 0.5 ± 1.0 ± 1.0 1 1 1 1 6 µs 7 µs 8 µs 8 µs DUALS AD5332 AD5333 AD5342 AD5343 8 10 12 12 ± 0.25 ± 0.5 ± 1.0 ± 1.0 2 2 2 1 6 µs 7 µs 8 µs 8 µs QUADS AD5334 AD5335 AD5336 AD5344 8 10 10 12 ± 0.25 ± 0.5 ± 0.5 ± 1.0 2 2 4 4 6 µs 7 µs 7 µs 8 µs Additional Pin Functions BUF ✓ ✓ ✓ GAIN ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ –18– Package Pins ✓ CLR ✓ ✓ ✓ ✓ TSSOP TSSOP TSSOP TSSOP 20 20 24 20 ✓ ✓ ✓ ✓ ✓ TSSOP TSSOP TSSOP TSSOP 20 24 28 20 ✓ ✓ ✓ TSSOP TSSOP TSSOP TSSOP 24 24 28 28 HBEN ✓ REV. B AD5306/AD5316/AD5326 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 16-Lead Small Outline Package (TSSOP) (RU-16) 0.201 (5.10) 0.193 (4.90) 9 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) 16 1 8 PIN 1 0.006 (0.15) 0.002 (0.05) 0.0256 SEATING (0.65) PLANE BSC REV. B 0.0433 (1.10) MAX 0.0118 (0.30) 0.0075 (0.19) 8° 0° 0.0079 (0.20) 0.0035 (0.090) –19– 0.028 (0.70) 0.020 (0.50) AD5306/AD5316/AD5326–Revision History Location Page Data sheet changed from REV. A to REV. B. Edit to Figure 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Edits to RIGHT/LEFT section of Pointer Byte Bits section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Edits to Figure 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Edits to Figure 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Edits to Figure 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 PRINTED IN U.S.A. Edit to Figure 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 C02066–0–4/01(B) Edits to Input Shift Register section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 –20– REV. B