a ADSL Chipset AD6435 FEATURES Component in Analog Devices DMT ADSL Chipset— AD20msp910 Designed to ANSI/ETSI T1.413 Suitable for CO or Residence (ATU-R and ATU-C) Performs All Digital Interface Tasks: Elastic Store; Byte-Stuffing/Robbing Synchronization and EOC and AOC Insertion/Removal CRC Generation/Detection Scrambler and Descrambler Forward Error Correction/Detection Interleave/Deinterleave Absolute Maximum Data Rate: 12 Mbps Simplex/ 4 Mbps Duplex Simple Interface: Synchronous Simplex and Duplex Streams 128-Lead TQFP Operating Temperature Range: –408C to +858C 3.3 V Operation, 400 mW GENERAL DESCRIPTION The AD6435 is part of the Analog Devices ADSL chipset, the AD20msp910. It accompanies the AD6436 (DMT accelerator), AD6437 (single-chip analog front end) and ADTSP-2183 (control and DSP). Object code is also supplied. Offering a flexible, standard-based approach (designed to ANSI T1.413, Category 1) with low total bill of materials and high performance, the chipset offers a straightforward approach to realizing an ADSL modem. The AD6435 interfaces the ADSL modem to the external system, at either CO or RT modem. It implements all the bitstuffing/robbing and elastic store operations, and all digital processing (block and forward error correction, scrambling, interleaving, etc.). The AD6435 has four simple synchronous connections, duplex in and out, simplex in (only used at ATU-C) and simplex out (used at ATU-R), which may be treated as the AS0 Simplex and LS0 duplex stream of the standard. These have “clean” clock and data, and may operate asynchronously of one another, or of the modem itself. FUNCTIONAL BLOCK DIAGRAM BYPASS PORT DUPLEX_TX TRANSMIT DUPLEX_RX SIMPLEX_TX (ATU-C) ELASTIC STORE, FRAMING, BYTE–STUFF/ROB TO AD6436/AD6439 DIGITAL LOGIC, FEC, CRC INTERLEAVING RECEIVE CONTROL FROM AD6436/AD6439 SIMPLEX_RX (ATU-R) AD6435 TO ADTSP2183 INTERLEAVE RAM REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1997 AD6435–SPECIFICATIONS Parameter Units Comments ABSOLUTE MAXIMUM SIMPLEX DATA RATE 12.288 Mbps Absolute Maximum. May not be achieved under realistic conditions. Actual performance will depend on copper loop. ABSOLUTE MAXIMUM DUPLEX DATA RATE 4.096 Mbps Absolute Maximum. May not be achieved under realistic conditions. Actual performance will depend on copper loop. INTERNAL PLL FOR CLOCK REGENERATION 176.64 MHz Resolution is 172.5 Hz/Bit 0.076 Unit Intervals. VDD SUPPLY VOLTAGE 3.3 V ± 10% POWER DISSIPATION 400 mW TA OPERATING TEMPERATURE –40°C to +85°C Typical Specifications are subject to change without notice. ABSOLUTE MAXIMUM RATINGS * ELECTRICAL SPECIFICATIONS Parameter Typ Value Comments* VOH VOL VIH VIL IIH IIL VDD–0.4 V dc 0.4 V dc 2.0 V dc 1.0 V dc ± 500 nA ± 500 nA At IOH = –0.5 mA At IOL = +1.0 mA Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +4.6 V Input Voltage . . . . . . . . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V Output Voltage Swing . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V Operating Temperature Range (Ambient) . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Lead Temperature (5 sec) TQFP . . . . . . . . . . . . . . . . +280°C VIN = VDD = 3.6 V VIN = 0 V, VDD = 3.6 V *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. *VDD = 3.3 V dc ± 10%. ORDERING GUIDE Model Temperature Range Package Description Package Option AD6435 –40°C to +85°C 128-Lead Plastic Thin Quad Flatpack ST-128 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD6435 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –2– WARNING! ESD SENSITIVE DEVICE REV. 0 AD6435 1 D0 2 TEST4 104 A0 103 A1 105 VDD12 106 GND12 108 NRD 107 NCS 109 NWR 111 D15 110 NRESET 112 D14 114 D12 102 A2 PIN 1 IDENTIFIER 101 A3 3 100 A4 SIMPLX_TX 4 99 A5 SIMPLX_CLKI 5 98 A6 SIMPLX_CLKO 6 97 VDD1 7 96 A7 VDD11 GND1 8 95 GND11 SIMPLX_RX 9 94 DSP_CLK DUPLX_TX 10 93 A8 DUPLX_CLKI 11 92 A9 DUPLX_CLKO 12 91 A10 DUPLX_RX 13 90 A11 RX_BUF 14 89 A12 VDD2 15 88 VDD10 GND2 16 87 GND10 RFS 17 86 A13 RX_FR 18 85 RX_FRM RX_SPFR 19 84 RX_SDATA RX_SPFRI 20 83 RX_DREQ TX_BUF 21 82 RX_BS TFS 22 81 TX_RX_SCLK GND3 23 80 GND9 VDD3 24 79 VDD9 TX_FR 25 78 TX_FRM TX_SPFR 26 77 TX_SDATA MCLK_OUT 27 76 TX_BS TEST0 28 75 TX_DREQ TEST1 29 74 MCLK RT_NCO 30 73 NM_OE GND4 31 72 GND8 VDD4 32 71 VDD8 NC 33 70 NM_WE NC 34 69 M_A14 PLL_GND 35 68 M_A13 PLL_VDD 36 67 M_A12 PLL_RBIAS 37 66 M_A11 NC 38 65 M_A10 AD6435 DTIR 128 TQFP –3– M_A9 64 M_A8 63 VDD7 62 GND7 61 M_A7 60 M_A6 59 M_A5 58 M_A3 56 M_A4 57 M_A2 55 M_A1 54 M_A0 53 VDD6 51 GND6 52 M_D0 50 M_D1 49 M_D2 48 M_D3 47 M_D4 46 M_D6 44 M_D5 45 M_D7 43 VDD5 41 GND5 42 TEST3 40 TEST2 39 TOP VIEW (Not to Scale) NC = NO CONNECT REV. 0 113 D13 115 VDD13 116 GND13 117 D11 118 D10 119 D9 121 D7 120 D8 122 D6 124 D4 123 D5 126 VDD14 125 GND14 128 D2 D1 127 D3 PIN CONFIGURATION AD6435 PIN DESCRIPTION The AD6435 contains 91 signal pins, 33 output pins, 35 input pins, and 24 bidirectional pins. There are also 5 test pins and 28 digital supply pins, 2 analog supply pins, and 1 PLL bias pin for the PLL. PIN FUNCTION DESCRIPTIONS Pin No. Pin Name Type Description 1–2 3 4 5 6 7 8 9 10 11 12 13 14 D1, D0 TEST4 SIMPLX_TX SIMPLX_CLKI SIMPLX_CLKO VDD1 GND1 SIMPLX_RX DUPLX_TX DUPLX_CLKI DUPLX_CLKO DUPLX_RX RX_BUF I/O Input Input Input Output Supply Supply Output Input Input Output Output Output 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33, 34 35 36 37 38 39 40 41 42 43–50 51 52 53–60 VDD2 GND2 RFS RX_FR RX_SPFR RX_SPFRI TX_BUF TFS GND3 VDD3 TX_FR TX_SPFR MCLK_OUT TEST0 TEST1 RT_NCO GND4 VDD4 NC PLL_GND PLL_VDD PLL_RBIAS NC TEST2 TEST3 VDD5 GND5 M_D7–0 VDD6 GND6 M_A0–7 Supply Supply Output Output Output Output Input Output Supply Supply Output Output Output 16-Bit Data Bus for DSP Port. See also 111:114, 117:124, 127:128. Tie to Ground Through a 10 kΩ Resistor. Input Downstream Data at CO. Pin not used at RT. Input Clock at CO for Downstream Data. Pin is not used at RT. Recovered Downstream Clock at RT. Pin not used at CO. 3.3 V. Ground. Received Downstream Data at RT. Pin not used at CO. Input Duplex Data. Input Duplex Clock. Recovered Duplex Clock. Received Duplex Data Stream. TICL Bypass—RX Data Buffer. If TCIL is not used, this pin must have a pull-up resistor. 3.3 V. Ground. TICL Bypass—RX Byte Sync. TICL Bypass—RX Frame Sync. 10 kΩ to Ground. TICL Bypass—TICL Superframe Sync. TICL Bypass—RX Interleaved Superframe Sync. TICL Bypass—TX Data Buffer. TICL Bypass—TX Byte Sync. Ground. 3.3 V. TICL Bypass—TX Frame Sync. TICL Bypass—TX Superframe Sync. TICL Bypass—Output MCLK. No Connection. No Connection. Mode Pin, 1 = RT Mode, 0 = CO Mode. Ground. 3.3 V. No Connect. PLL Analog Ground. PLL Analog Power. Tie to Ground Through a 30 kΩ Resistor. No Connect. Tie to Ground Through a 10 kΩ Resistor. No Connection. 3.3 V. Ground. Data for Interleave Ram. 3.3 V. Ground. Address Bus for Interleave Ram. See also Pins 60–66. Supply Supply Input Three-State Supply Supply I/O Supply Supply Output –4– REV. 0 AD6435 PIN FUNCTION DESCRIPTIONS (Continued) Pin No. Pin Name Type Description 61 62 63–69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89–93 94 95 96 97–104 105 106 107 108 109 110 111–114 115 116 117–124 125 126 127, 128 GND7 VDD6 M_A8–14 NM_WE VDD8 GND8 NM_OE MCLK TX _DREQ TX _BS TX _SDATA TX _FRM VDD9 GND9 TX _RX_SCLK RX_BS RX_DREQ RX_SDATA RX_FRM A13 GND10 VDD10 A12–A8 DSP_CLK GND11 VDD11 A7–0 VDD12 GND12 NCS NRD NWR NRESET D15–D12 VDD13 GND13 D11–D4 GND14 VDD14 D3–D2 Supply Supply Output Output Supply Supply Output Input Input Output Output Input Supply Supply Input Input Output Input Input Input Supply Supply Input Input Supply Supply Supply Supply Supply Input Input Input Input I/O Supply Supply I/O Supply Supply I/O Ground. 3.3 V. Address Bus for Interleave Ram. See also Pins 50–57. Write Enable for Interleave Ram. 3.3 V. Ground. Output Enable for Interleave Ram. The AD6435 Master Clk (35.328 MHz). Data Request Provided by the AD6436. Transmit Byte Strobe Provided by the AD6435. Transmit Serial Data Provided by the AD6435. Transmit Frame Strobe Provided by the AD6436. 3.3 V. Ground. Transmit and Receive Serial Clock. Receive Byte Strobe Provided by the AD6436. Receive Data Request Provided by the AD6435. Receive Serial Data Provided by the AD6436. Receive Frame Strobe Provided by the AD6436. 14-Bit Address Bus for DSP Port. See also 86–90 and 94–101. Ground. 3.3 V. 14-Bit Address Bus for DSP Port. See also 83 and 94–101. DSP Output Clock. Ground. 3.3 V. 14-Bit Address Bus for DSP Port. See also 83 and 86–90. 3.3 V. Ground. DSP Memory Select. Active Low. DSP Memory Read Enable, Active Low. DSP Write Enable, Active Low. Reset Pin, Active Low. 16-Bit Data Bus for DSP Port. See also 1–2, 117–124, 127–128. 3.3 V. Ground. 16-Bit Data Bus for DSP Port. See also 1–2, 111–114, 127–128. Ground. 3.3 V. 16-Bit Data Bus for DSP Port. See also 1–2, 111–114, 117–124. REV. 0 –5– AD6435 INTRODUCTION The AD6435 is the interface chip in the AD20msp910 ADSL chipset, connecting the core transceiver functions to the external system. The other portions within the AD20msp910 chipset are the AD6436 (which connects to the AD6435 and is responsible for the core DMT signal processing), the AD6437 analog frontend IC, the AD816 driver/receiver and ADTSP2183, which is used as the system control processor. An object code licence for all modem software is supplied with the AD20msp910 chipset. The AD6435 implements a generic interface, with straightforward synchronous clock and data streams corresponding to simplex and duplex bearer channels. These can be considered as the AS0 (simplex) and LS0 (duplex) streams as per the standard, but can run at any rate; the “duplex” channel can be treated as two independent streams, one up and one down. This implementation is a simplified variant of that described in ANSI T1.413. It is easy to use this structure to connect to the rest of the system, or to external devices, such as framers or dedicated ICs for particular protocols. Variants of the AD6435 with support for specific functions or interfaces (e.g., ATM, Ethernet) are under development. When used as part of the AD20msp910 ADSL chipset, the internal functionality is under the control of the firmware supplied with the ADTSP2183, and the Messaging Protocol (MP) implemented there. This protocol supplies a hardware-neutral method of controlling the operation of the ADSL chipset, which will be compatible between different hardware implementations. The AD6435 can implement rate adaptive ADSL (RADSL). This is under the control of the MP, and several different modes are supported. The absolute maximum data rate of the AD6435 is 12 Mbps downstream, and 4 Mbps upstream. However, the rate depends primarily on the channel conditions, and these rates will not be achieved on real loops, with attenuation and crosstalk. a. One codeword per frame in the fact and/or interleaved data portion of a frame. A(13:0) D(15:0) DSP_CLK NRD NWR NCS c. Multiple frames per codeword on the interleaved portion of the frame only, up to 20 frames per codeword. The number of checkbytes must be an integer multiple of the number of frames in the codeword. RX_FRM RX_BS RX_SDATA RX_DREQ DUPLX_RX DUPLX_CLKO DUPLX_CLKI DUPLX_TX SIMPLX_CLKI SIMPLX_TX SIMPLX_CLKO SIMPLX_RX M_A(14:0) M_D(7:0) NM_WE NM_OE DME INTERFACE TX_SDATA DTIR MCLK RT_NCO b. Multiple codewords per frame in the fast and/or interleaved data portion, providing the codeword length evenly divides into the output (DME) frame length. TX_DREQ TX_FRM TX_BS TX_BUF TX_FR TFS TX_SPFR MCLK_OUT INTERLEAVE RAM DATA INTERFACE • The digital processing section (Digital Interface Area or “DIA”), which is responsible for error correction, scrambling, interleaving, AOC and control operations. This is based on the earlier AD6442 device. This is a highly programmable system, whose operation is not restricted to the operating modes as defined in ANSI T1.413, but which could be used in variety of systems. The DIA supports the following codeword cases: TX_RX_SCLK TEST(4:0) There are two main blocks within the AD6435: RX_BUF RFS RX_FR RX_SPFR RX_SPFRI NRESET TICL BYPASS INTERFACE ADTSP2183 INTERFACE CONTROL INTERFACE Figure 1. Functional Diagram d. Codewords may span superframes. • The interface block (Transceiver Interface and Control Logic or “TICL”), which handles the framing, signal buffering and data retiming functions required to support clean synchronous data streams. (This essentially corresponds to the transmission convergence layer of a stack.) As some designs may not require the TICL block, there is a bypass mode, in which this block is powered down and there is access to the unformatted/unframed data stream from the DIA. This data sheet gives a user’s description of the AD6435. It describes functionality and interfacing, but does not give any details of the internal structure. For details of the internal structure, see the AD6435 User’s Manual, available on request. INTERFACES The standard interface is a very straightforward buffered and demultiplexed synchronous connection. It is physically the same at both ATU-R and ATU-C, and presents four channels— simplex in and out, duplex in and out—with just two signals per connection, clock and data (obviously, only three of these channels can be used at an end; with the ATU-C using simplex_in and the ATU-R simplex_out). These streams are independent and can be used asynchronously of one another. No framing signals are provided. The “duplex” stream can be used as a true duplex carrier (same rates upstream and downstream) or the two may be independent (i.e., the chipset has two simplex downstream paths, one fast and one slower, and one simplex upstream). –6– REV. 0 AD6435 Table I. Interface Descriptions Name Description duplex_rx Duplex data output from the AD6435 (i.e., data received). Clock associated with duplex_rx (output). Duplex data input to the AD6435 (i.e., data to be transmitted). Clock associated with duplex_tx input. Simplex data output from the AD6435. ATU-R: downstream data received. ATU-C: not used. Clock associated with simplex_rx (output). Simplex data input to the AD6435. ATU-R: not used. ATU-C: downstream data to be sent. Clock associated with simplex_tx (input). duplex_clko duplex_tx duplex_clki simplex_rx simplex_clko simplex_tx simplex_clki PAYLOAD DATA IN In general tx clock signals (i.e., duplex_clcki, simplex_clki) are input to the AD6435, while the received data clock signals (duplex_clko, simplex_clko) are outputs. In other words, the sending modem (at ATU-C or ATU-R) supplies the clock to the AD6435, and the receiving modem’s AD6435 recovers it (using a digital phase locked loop) and supplies it to the external system. The channels all have separate—independent—clocks. There are two exceptions; the duplex streams can be “locked” with a single clock or, in a “one down/one up” system typical for data applications, the unused DPLL can be programmed to be a clock source at the desired data rate for the tx channel. To avoid overflow/underflow of internal buffers, the clock rate of the streams should be held roughly constant. As such, although a degree of jitter or rate variation is supported, pure burst-mode is not, and idle cell insertion (deletion) is necessary and must be implemented by an external device. Alternatively, the buffering multiplex/demultiplex and bit-stuff/ rob operations may be bypassed (TICL bypass operation). These blocks are then powered down, reducing the AD6435’s power consumption. The interface presented is then a “raw” stream of upstream and downstream data. As the elastic store has been disabled, these have the relic of the ADSL line superframe structure, and will show an irregular clock (with a pause for every 69th frame). This mode is compatible with the AD6442 DIA interface and is suited to packet (e.g., ATM) operation. It results in a slight power saving. PAYLOAD DATA OUT ELASTIC STORE EOC REMOVE EOC INSERT SYNC FRAMER AD6435 CRC CRC DETECT RAM ARBITRATION SCRAMBLER FEC ENCODE INTERLEAVER FRAMER NB: Although the AD6435 can implement the T1.413 standard, and includes the required framing/interfacing (e.g., elastic store, bit-stuffing/robbing), it does not support the full optional suite of seven bearer streams (ASx and LSx) and associated multiplexing/demultiplexing as defined in T1.413. Instead, simple synchronous data streams are provided. These are essentially AS0 (simplex) and LS0 (duplex) but with variable rate or rate adaptive (not merely fixed multiples of standard PDH rates, as per Chapter 5 of T1.413). Additionally, the “duplex” stream can be treated as two independent streams, one up and one down. Indeed, in many applications, only one stream in each direction is required; in this case, the downstream duplex path is not used. UNSCRAMBLE DE-INTERLEAVER FEC DECODE RAM TONE SHUFFLE TONE REORDER CONSTELLATION ENCODE CONSTELLATION DECODE AD6436 INVERSE FFT FFT INTERPOLATE DECIMATE & TDQ Further TC-layer operations can be defined by the system for their requirements (e.g., for V.35, ATM or 10BaseT), and simply interfaced to the AD6435 serial ports. INTERFACE TIMING DAC SERIAL DAC (TO VCXO) CONTROL The DTIR contains simplex (AS) and duplex (LS) channels that interface with the Central Office (CO) and Remote Terminal (RT). The DTIR contains a transmit serial port in which the DTIR transmits a bit stream to the DME and a receive serial port in which DTIR receives a serial bit stream from the DME. Since the DIA is being treated as a black box, the TICL-DIA interface will be defined here. This interface is similar to the DIA-DME transmit and receive interfaces. The DTIR also interfaces with a 32k × 8 Interleave RAM. The DTIR also has a DSP host port that allows a DSP to monitor the DTIR and control the data through the device. ADC AD6437 FILTER PGA FILTER HYBRID POTS SPLITTER RECEIVER DRIVER AD816 DRIVER/RECEIVER Figure 2. AD20msp910 System Block Diagram REV. 0 –7– AD6435 and DUPLX_CLKI. The serial clock rate is completely variable between 8 kbps and 4.096 Mbps. The interface operates identically at the CO and RT locations. The input interface can accept a continuous stream of data at a fixed frequency within the duplex rate. The output interface on the other end transmits the same continuous stream of data at the same fixed frequency. This frequency is established and programmed into the registers by the DSP during reset. CO/RT INTERFACE TIMING Simplex Serial Port The simplex serial port consists of four pins, two outputs, SIMPLX_RX and SIMPLX_CLKO, and two inputs, SIMPLX_ TX and SIMPLX_CLKI. The serial clock rate is completely variable between 8 kbps and 12.288 Mbps. The interface operates differently at the CO and RT locations. DTIR XMT RT RECEIVE For the Duplex Rx channel, data is driven out of the AD6435 on the positive edge of the respective CLKO signal and should be sampled by the external circuit on the negative edge. SIMPLX_CLKO SIMPLX_RX For the Duplex Tx channel, the data is sampled by the AD6435 on the positive edge of the respective CLKO signal and should be driven by the external circuit on the negative edge. VALID DATA tSRX-S tSRX-H DTIR XMT SIMPLX_CLKI DUPLX_CLKO SIMPLX_TX VALID DATA tSTX-S DUPLX_RX tDRX-S CO/RT XMT Parameter Description tSRX-S Setup Time of SIMPLX_RX from Falling Edge of SIMPLX_CLKO Hold Time of SIMPLX_RX from Falling Edge of SIMPLX_CLKO Setup Time of SIMPLX_TX from Rising Edge of SIMPLX_CLKI Hold Time of SIMPLX_TX from Rising Edge of SIMPLX_CLKI tSTX-H tDRX-H DTIR RECEIVE DUPLX_CLKI Table II. TX Serial I/F Timing tSTX-S VALID DATA tSTX-H Figure 3. Simplex Serial Port tSRX-H CO/RT RECEIVE DTIR RECEIVE CO XMT Typ DUPLX_TX VALID DATA tDTX-S 5 ns tDTX-H Figure 4. Duplex Serial Port 5 ns Table III. TX Serial I/F Timing 5 ns 5 ns At the CO, the two input pins SIMPLX_TX and SIMPLX_CLKI are used while the two output pins SIMPLX_RX and SIMPLX_ CLKO are not functionally connected. The interface can operate at a continuous data stream into SIMPLX_RX at a fixed frequency between 8 kbps and 12.288 Mbps. The data rate is set while the DTIR is in reset and does not change without going into the reset state again. Parameter Description tDRX-S Setup Time of DUPLX_RX from Falling Edge of DUPLX_CLKO Hold Time of DUPLX_RX from Falling Edge of DUPLX_CLKO Setup Time of DUPLX_TX from Rising Edge of DUPLX_CLKI Hold Time of DUPLX_TX from Rising Edge of DUPLX_CLKI tDRX-H tDTX-S tDTX-H At the RT, the two output pins SIMPLX_RX and SIMPLX_ CLKO are used while the two input pins SIMPLX_TX and SIMPLX_CLKI are not functionally connected. The interface can operate at a continuous data stream out of SIMPLX_RX at a fixed frequency between 8 kbps and 12.288 Mbps. The data rate is set while the DTIR is in reset and does not change without going into the reset state again. Typ 5 ns 5 ns 5 ns 5 ns INTERLEAVE RAM INTERFACE The DTIR (DIA) Interfaces an external 32k × 8 Interleave RAM. The interleave RAM interface consists of M_A(14:0), M_D(7:0), NM_WE, and NM_OE. When operating at 3.3 V RAM must have access time less than 50 ns. For further information concerning the operation of the RAM access, consult the DIA specification. For the Simplex Rx channel, data is driven out of the AD6435 on the positive edge of the respective CLKO signal and should be sampled by the external circuit on the negative edge. DME INTERFACE TIMING All signals transmitted by the DME to the DTIR are transmitted on the rising edge and sampled on the falling edge except for the TX_DREQ signal that is transmitted by the DME on the falling edge and sampled by the DTIR on the rising edge. All output signals from the DTIR to the DME are transmitted by the DTIR on the rising edge and received by the DME on the rising edge. For the Simplex Tx channel, the data is sampled by the AD6435 on the positive edge of the respective CLKO signal and should be driven by the external circuit on the negative edge. Duplex Serial Port The duplex serial port consists of four pins, two outputs, DUPLX_RX and DUPLX_CLKO, and two inputs, DUPLX_TX –8– REV. 0 AD6435 Parameter Description Typ Units TX Serial I/F Timing tTFRM-S tTFRM-H tTDREQ-S tTDREQ-H tTBS-S tTBS-H tTD_S tTD_H Setup Time of TX_FRM from Falling Edge of TX_RX_SCLK Hold Time of TX_FRM from Falling Edge of TX_RX_SCLK Setup Time of TX_DREQ from Rising Edge of TX_RX_SCLK Hold Time of TX_DREQ from Rising Edge of TX_RX_SCLK Setup Time of TX_BS from Rising Edge of TX_RX_SCLK Hold Time of TX_BS from Rising Edge of TX_RX_SCLK Setup Time of TX_SDATA from Rising Edge of TX_RX_SCLK Hold Time of TX_SDATA from Rising Edge of TX_RX_SCLK 5 15 5 15 10 0 5 0 ns ns ns ns ns ns ns ns TX_RX_SCLK TX_FRM tTFRM-S tTFRM-H TX_DREQ tTDREQ-S tTDREQ-H TX_BS tTBS-S TX_SDATA tTBS-H VALID DATA tTD-S tTD-H Figure 5. TX Serial I/F Timing Parameter Description Typ Units RX Serial I/F Timing tRFRM-S tRFRM-H tRDREQ-S tRDREQ-H tRBS-S tRBS-H tRD-S tRD-H Setup Time of RX_FRM from Falling Edge of TX_RX_SCLK Hold Time of RX_FRM from Falling Edge of TX_RX_SCLK Setup Time of RX_DREQ from Rising Edge of TX_RX_SCLK Hold Time of RX_DREQ from Rising Edge of TX_RX_SCLK Setup Time of RX_BS from Falling Edge of TX_RX_SCLK Hold Time of RX_BS from Falling Edge of TX_RX_SCLK Setup Time of RX_SDATA from Falling Edge of TX_RX_SCLK Hold Time of RX_SDATA from Falling Edge of TX_RX_SCLK 5 15 5 0 5 15 5 15 ns ns ns ns ns ns ns ns TX_RX_SCLK RX_FRM tRFRM-S tRFRM-H RX_DREQ tRDREQ-S tRDREQ-H RX_BS tRBS-S tRBS-H RX_SDATA VALID DATA tRD-S tRD-H Figure 6. RX Serial I/F Timing REV. 0 –9– AD6435 TX_RX_SCLK: RX_FRMRX_FRM: RX_BS: RX_SDATA: RX_DREQ: TX Serial Port The TX serial interface between the DME and DTIR uses five (5) signals: TX_RX_SCLK: TX_DREQ: TX_FRM: TX_BS: TX_SDATA: Serial clock provided by DME. Data request provided by DME. Frame strobe provided by DME. Byte strobe provided by DTIR. Serial data provided by DTIR. Serial clock provided by DME. Frame strobe provided by DME. Byte strobe provided by DME. Serial data provided by DME. Data request provided by DTIR. DSP PORT The DSP port consists of a 14-bit address bus, A[13:0], a 16-bit data bus, D[15:0], DSP_CLK and three bus control pins, NRD, NWR, NCS. RX Serial Interface The RX serial interface between the DME and DTIR uses five (5) signals: Parameter Min Max Unit 8 14 ns ns ns Read Operation Timing Requirements: NRD Low to Data Valid tRDD tAA A0–A13, NCS to Data Valid tRDH Data Hold from NRD High 0 Switching Characteristics: NRD Pulsewidth tRP tCRD DSP_CLK High to NRD Low tASR A0–A13, NCS Setup before NRD Low tRDA A0–A13, NCS Hold after NRD Deasserted tRWR NRD High to NRD or NWR Low 12 3 2 5 12 16 ns ns ns ns ns NOTE: DSP clock 28 MHz (35.7 ns) DSP_CLK A0–A13 NCS tRDA NRD tASR tRP tCRD tRWR D tAA tRDD tRDH NWR Figure 7. Read Operation –10– REV. 0 AD6435 Parameter Min Max Unit Write Operation Switching Characteristics: Data Setup before NWR High tDW tDH Data Hold after NWR High tWP NWR Pulsewidth tWDE NWR Low to Data Enabled tASW A0–A13, NCS Setup before NWR Low tDDR Data Disable before NWR or NRD Low tCWR DSP_CLK High to NWR Low tAW A0–A13, NCS, Setup before NWR Deasserted tWRA A0–A13, NCS Hold after NWR Deasserted tWWR NWR High to NRD or NWR Low 10 6 12 0 2 1 3 17 5 12 16 NOTE: DSP clock 28 MHz (35.7 ns) DSP_CLK A0–A13 NCS tWRA NWR tASW tWWR tWP tAW tDH tCWR D tWDE tDW NRD Figure 8. Write Operation REV. 0 –11– tDDR ns ns ns ns ns ns ns ns ns ns AD6435 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 0.063 (1.60) TYP C3227–3–10/97 128-Lead Plastic Thin Quad Flatpack (ST-128) 0.630 (16.00) BSC 0.551 (14.00) BSC 0.030 (0.75) 0.024 (0.60) 0.018 (0.45) 103 102 128 1 SEATING PLANE TOP VIEW 0.787 0.866 (20.00) (22.00) BSC BSC (PINS DOWN) 0.003 (0.08) MAX 38 65 64 39 0.057 (1.45) 0.053 (1.40) 0.018 (1.35) 0.020 (0.50) BSC 0.011 (0.27) 0.009 (0.22) 0.007 (0.17) PRINTED IN U.S.A. 0.006 (0.15) 0.002 (0.05) –12– REV. 0