ETC AT49BV4096A-90TC

Features
•
•
•
•
•
•
•
•
•
•
Single-voltage Read/Write Operation: 2.7V to 3.6V (BV), 3.0V to 3.6V (LV)
Fast Read Access Time – 70 ns
Internal Erase/Program Control
Sector Architecture
– One 8K Word (16K Bytes) Boot Block with Programming Lockout
– Two 4K Word (8K Bytes) Parameter Blocks
– One 240K Word (480K Bytes) Main Memory Array Block
Fast Sector Erase Time – 10 Seconds
Byte-by-byte or Word-by-word Programming – 30 µs Typical
Hardware Data Protection
Data Polling for End of Program Detection
Low Power Dissipation
– 25 mA Active Current
– 50 µA CMOS Standby Current
Typical 10,000 Write Cycles
Description
The AT49BV/LV4096A is a 3-volt, 4-megabit Flash memory organized as 524,288
words of 8 bits each or 256K words of 16 bits each. Manufactured with Atmel’s
advanced nonvolatile CMOS technology, the device offers access times to 70 ns with
power dissipation of just 67 mV at 2.7V read. When deselected, the CMOS standby
current is less than 50 µA.
Th e device co nt ain s a us e r-e n a ble d “ bo o t blo ck ” pr ot ec tio n fe a tu re. Th e
AT49BV/LV4096A locates the boot block at lowest order addresses (“bottom boot”).
To allow for simple in-system reprogrammability, the AT49BV/LV4096A does not
require high input voltages for programming. Reading data out of the device is similar
to reading from an EPROM; it has standard CE, OE and WE inputs to avoid bus contention. Reprogramming the AT49BV/LV4096A is performed by first erasing a block of
data and then programming on a byte-by-byte or word-by-word basis.
4-megabit
(512K x 8/
256K x 16)
Single 2.7-volt
Battery-Voltage™
Flash Memory
AT49BV4096A
AT49LV4096A
Pin Configurations
Pin Name
Function
A0 - A17
Addresses
CE
Chip Enable
OE
Output Enable
WE
Write Enable
RESET
Reset
VPP
VPP can be left unconnected or connected to VCC, GND, 5V or
12V. The input has no effect on the operation of the device.
I/O0 - I/O15
Data Inputs/Outputs
I/O15(A-1)
I/O15 (Data Input/Output, Word Mode)
A-1 (LSB Address Input, Byte Mode)
BYTE
Selects Byte or Word Mode
NC
No Connect
Rev. 1618E–FLASH–07/02
1
AT49BV/LV4096A SOIC (SOP)
VPP
NC
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE
GND
OE
I/O0
I/O8
I/O1
I/O9
I/O2
I/O10
I/O3
I/O11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
AT49BV/LV4096A TSOP Top View
Type 1
RESET
WE
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE
GND
I/O15/A-1
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
VCC
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE
RESET
VPP
NC
NC
NC
A17
A7
A6
A5
A4
A3
A2
A1
AT49BV/LV4096A
CBGA 7 x 7 mm Top View (Ball Down)
1
2
3
4
5
6
7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE
GND
I/O15/A-1
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
VCC
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
OE
GND
CE
A0
AT49LV4096A
CBGA 6 x 8 mm Top View (Ball Down)
1
2
A3
3
4
5
6
A7 RDY/BUSY WE
A9
A13
A4
A17
NC
RESET
A8
A12
A2
A6
NC
VPP
A10
A14
A1
A5
NC
NC
A11
A15
A0
I/O0
I/O2
I/O5
I/O7
A16
CE
I/O8
I/O10
I/O12
I/O14
BYTE
OE
I/O9
I/O11
VCC
I/O13
I/O15
/A-1
VSS
I/O1
I/O3
I/O4
I/O6
VSS
8
A
A
A13 A11
A8 VPP NC
NC
A7
A4
B
A14 A10 WE RST NC A17
A5
A2
C
B
C
A15 A12
A9
NC
NC
A6
A3
A1
D
A16 I/O14 I/O5 I/O11 I/O2 I/O8 CE
A0
E
D
E
BYTE I/O15 I/O6 I/O12 I/O3 I/O9 I/O0 GND
F
F
GND I/O7 I/O13 I/O4 VCC I/O10 I/O1 OE
Note:
2
“•” denotes a white dot on the package.
G
H
AT49BV/LV4096A
1618E–FLASH–07/02
AT49BV/LV4096A
Description
(Continued)
The device is erased by executing the Erase command sequence; the device internally
controls the erase operation. The memory is divided into four blocks for erase operations. There are two 4K word parameter block sections, the boot block, and the main
memory array block. The typical number of program and erase cycles is in excess of
10,000 cycles.
The 8K word boot block section includes a reprogramming lock out feature to provide
data integrity. This feature is enabled by a command sequence. Once the boot block
programming lockout feature is enabled, the data in the boot block cannot be changed
when input levels of 5.5 volts or less are used. The boot sector is designed to contain
user secure code.
The BYTE pin controls whether the device data I/O pins operate in the byte or word configuration. If the BYTE pin is set at a logic “1” or left open, the device is in word
configuration, I/O0 - I/O15 are active and controlled by CE and OE.
If the BYTE pin is set at logic “0”, the device is in byte configuration, and only data I/O
pins I/O0 - I/O7 are active and controlled by CE and OE. The data I/O pins I/O8 - I/O14
are tri-stated and the I/O15 pin is used as an input for the LSB (A-1) address function.
Block Diagram
VCC
DATA INPUTS/OUTPUTS
I/O0 - I/O15
GND
OE
WE
CE
RESET
CONTROL
LOGIC
Y DECODER
ADDRESS
INPUTS
X DECODER
INPUT/OUTPUT
BUFFERS
PROGRAM DATA
LATCHES
Y-GATING
MAIN MEMORY
(240K WORDS)
PARAMETER
BLOCK 2
4K WORDS
PARAMETER
BLOCK 1
4K WORDS
BOOT BLOCK
8K WORDS
Device Operation
3FFFF
04000
03FFF
03000
02FFF
02000
01FFF
00000
READ: The AT49BV/LV4096A is accessed like an EPROM. When CE and OE are low
and WE is high, the data stored at the memory location determined by the address pins
is asserted on the outputs. The outputs are put in the high-impedance state whenever
CE or OE is high. This dual-line control gives designers flexibility in preventing bus
contention.
COMMAND SEQUENCES: When the device is first powered on, it will be reset to the
read or standby mode, depending upon the state of the control line inputs. In order to
perform other device functions, a series of command sequences are entered into the
device. The command sequences are shown in the Command Definitions table (I/O8 I/O15 are don’t care inputs for the command codes). The command sequences are written by applying a low pulse on the WE or CE input with CE or WE low (respectively) and
OE high. The address is latched on the falling edge of CE or WE, whichever occurs last.
The data is latched by the first rising edge of CE or WE. Standard microprocessor write
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1618E–FLASH–07/02
timings are used. The address locations used in the command sequences are not
affected by entering the command sequences.
RESET: A RESET input pin is provided to ease some system applications. When
RESET is at a logic high level, the device is in its standard operating mode. A low level
on the RESET input halts the present device operation and puts the outputs of the
device in a high-impedance state. When a high level is reasserted on the RESET pin,
the device returns to the read or standby mode, depending upon the state of the control
inputs. By applying a 12V ± 0.5V input signal to the RESET pin, the boot block array can
be reprogrammed even if the boot block program lockout feature has been enabled (see
“Boot Block Programming Lockout Override” section).
ERASURE: Before a byte or word can be reprogrammed, it must be erased. The erased
state of memory bits is a logic “1”. The entire device can be erased by using the Chip
Erase command or individual sectors can be erased by using the Sector Erase
commands.
CHIP ERASE: The entire device can be erased at one time by using the 6-byte chip
erase software code. After the chip erase has been initiated, the device will internally
time the erase operation so that no external clocks are required. The maximum time to
erase the chip is tEC.
If the boot block lockout has been enabled, the chip erase will not erase the data in the
boot block; it will erase the main memory block and the parameter blocks only. After the
chip erase, the device will return to the read or standby mode.
SECTOR ERASE: As an alternative to a full chip erase, the device is organized into four
sectors that can be individually erased. There are two 4K word parameter block sections, one boot block, and the main memory array block. The Sector Erase command is
a six-bus cycle operation. The sector address is latched on the falling WE edge of the
sixth cycle while the 30H data input command is latched at the rising edge of WE. The
sector erase starts after the rising edge of WE of the sixth cycle. The erase operation is
internally controlled; it will automatically time to completion. Whenever the main memory
block is erased and reprogrammed, the two parameter blocks should be erased and
reprogrammed before the main memory block is erased again. Whenever a parameter
block is erased and reprogrammed, the other parameter block should be erased and
reprogrammed before the first parameter block is erased again. Whenever the boot
block is erased and reprogrammed, the main memory block and the parameter blocks
should be erased and reprogrammed before the boot block is erased again.
BYTE/WORD PROGRAMMING: Once a memory block is erased, it is programmed (to
a logic “0”) on a byte-by-byte or word-by-word basis. Programming is accomplished via
the internal device command register and is a four-bus cycle operation. The device will
automatically generate the required internal program pulses.
Any commands written to the chip during the embedded programming cycle will be
ignored. If a hardware reset happens during programming, the data at the location being
programmed will be corrupted. Please note that a data “0” cannot be programmed back
to a “1”; only erase operations can convert “0”s to “1”s. Programming is completed after
the specified tBP cycle time. The Data Polling feature may also be used to indicate the
end of a program cycle.
BOOT BLOCK PROGRAMMING LOCKOUT: The device has one designated block
that has a programming lockout feature. This feature prevents programming of data in
the designated block once the feature has been enabled. The size of the block is 8K
words. This block, referred to as the boot block, can contain secure code that is used to
bring up the system. Enabling the lockout feature will allow the boot code to stay in the
device while data in the rest of the device is updated. This feature does not have to be
4
AT49BV/LV4096A
1618E–FLASH–07/02
AT49BV/LV4096A
activated; the boot block’s usage as a write-protected region is optional to the user. The
address range of the boot block is 00000H to 01FFFH.
Once the feature is enabled, the data in the boot block can no longer be erased or programmed when input levels of 5.5V or less are used. Data in the main memory block
can still be changed through the regular programming method. To activate the lockout
feature, a series of six program commands to specific addresses with specific data must
be performed. Please refer to the Command Definitions table.
BOOT BLOCK LOCKOUT DETECTION: A software method is available to determine if
programming of the boot block section is locked out. When the device is in the software
product identification mode (see Software Product Identification Entry and Exit sections)
a read from the following address location will show if programming the boot block is
locked out – 00002H. If the data on I/O0 is low, the boot block can be programmed; if
the data on I/O0 is high, the program lockout feature has been enabled and the block
cannot be programmed. The software product identification exit code should be used to
return to standard operation.
BOOT BLOCK PROGRAMMING LOCKOUT OVERRIDE: The user can override the
boot block programming lockout by taking the RESET pin to 12 volts during the entire
chip erase, sector erase or word programming operation. When the RESET pin is
brought back to TTL levels, the boot block programming lockout feature is again active.
PRODUCT IDENTIFICATION: The product identification mode identifies the device and
manufacturer as Atmel. It may be accessed by hardware or software operation. The
hardware operation mode can be used by an external programmer to identify the correct
programming algorithm for the Atmel product.
For details, see “Operating Modes” (for hardware operation) or “Software Product Identification Entry/Exit” on page 12. The manufacturer and device codes are the same for
both modes.
DATA POLLING: The AT49BV/LV4096A features Data Polling to indicate the end of a
program cycle. During a program cycle an attempted read of the last byte loaded will
result in the complement of the loaded data on I/O7. Once the program cycle has been
completed, true data is valid on all outputs and the next cycle may begin. During a chip
or sector erase operation, an attempt to read the device will give a “0” on I/O7. Once the
program or erase cycle has completed, true data will be read from the device. Data Polling may begin at any time during the program cycle.
TOGGLE BIT: In addition to Data Polling, the AT49BV/LV4096A provides another
method for determining the end of a program or erase cycle. During a program or erase
operation, successive attempts to read data from the device will result in I/O6 toggling
between one and zero. Once the program cycle has completed, I/O6 will stop toggling
and valid data will be read. Examining the toggle bit may begin at any time during a program cycle.
HARDWARE DATA PROTECTION: Hardware features protect against inadvertent programs to the AT49BV/LV4096A in the following ways: (a) VCC sense: if V CC is below
1.8V (typical), the program function is inhibited. (b) VCC power on delay: once VCC has
reached the VCC sense level, the device will automatically time out 10 ms (typical)
before programming. (c) Program inhibit: holding any one of OE low, CE high or WE
high inhibits program cycles. (d) Noise filter: pulses of less than 15 ns (typical) on the
WE or CE inputs will not initiate a program cycle.
INPUT LEVELS: While operating with a 2.7V to 3.6V power supply, the address and
control inputs (OE, CE and WE) may be driven from 0 to 5.5V without adversely affecting the operation of the device. The I/O lines can only be driven from 0 to VCC + 0.6V.
5
1618E–FLASH–07/02
Command Definition (in Hex)(1)
Command
Sequence
1st Bus
Cycle
Bus
Cycles
Addr
Data
Read
1
Addr
DOUT
Chip Erase
6
5555
AA
2nd Bus
Cycle
3rd Bus
Cycle
4th Bus
Cycle
6th Bus
Cycle
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
2AAA
55
5555
80
5555
AA
2AAA
55
5555
10
2AAA
55
(4)
SA
30
2AAA
55
5555
40
Sector Erase
6
5555
AA
2AAA
55
5555
80
5555
AA
Byte/Word Program
4
5555
AA
2AAA
55
5555
A0
Addr
DIN
Boot Block Lockout(2)
6
5555
AA
2AAA
55
5555
80
5555
AA
Product ID Entry
3
5555
AA
2AAA
55
5555
90
Product ID Exit
(3)
3
5555
AA
2AAA
55
5555
F0
Product ID Exit
(3)
1
xxxx
F0
Notes:
5th Bus
Cycle
1. The DATA FORMAT in each bus cycle is as follows: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex).
The ADDRESS FORMAT in each bus cycle is as follows: A15 - A0 (Hex), A-1, and A15 - A17 (Don’t Care).
2. The boot sector has the address range 00000H to 01FFFH.
3. Either one of the Product ID Exit commands can be used.
4. SA = sector addresses: (A17 - A0)
SA = 01XXX for BOOT BLOCK
SA = 02XXX for PARAMETER BLOCK 1
SA = 03XXX for PARAMETER BLOCK 2
SA = 3FXXX for MAIN MEMORY ARRAY
Absolute Maximum Ratings*
Temperature under Bias ................................ -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to VCC + 0.6V
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Voltage on RESET
with Respect to Ground ...................................-0.6V to +13.5V
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AT49BV/LV4096A
1618E–FLASH–07/02
AT49BV/LV4096A
DC and AC Operating Range
Operating
Temperature (Case)
Com.
Ind.
VCC Power Supply
AT49LV4096A-70
AT49BV4096A-90
AT49BV4096A-12
0°C - 70°C
0°C - 70°C
0°C - 70°C
N/A
-40°C - 85°C
-40°C - 85°C
3.0V - 3.6V
2.7V - 3.6V
2.7V - 3.6V
Operating Modes
Mode
CE
OE
WE
RESET
Ai
I/O
Read
VIL
VIL
VIH
VIH
Ai
DOUT
Program/Erase(2)
VIL
VIH
VIL
VIH
Ai
DIN
Standby/Program
Inhibit
VIH
X(1)
X
VIH
X
High-Z
X
X
VIH
VIH
X
VIL
X
VIH
Output Disable
X
VIH
X
VIH
Reset
X
X
X
VIL
X
VIL
VIL
VIH
VIH
A1 - A17 = VIL, A9 = VH(3)
A0 = VIL
Manufacturer Code(4)
A1 - A17 = VIL, A9 = VH(3)
A0 = VIH
Device Code(4)
Program Inhibit
High-Z
High-Z
Product Identification
Hardware
Software(5)
Notes:
VIH
A0 = VIL, A1 - A17 = VIL
Manufacturer Code(4)
A0 = VIH, A1 - A17 = VIL
Device Code(4)
1.
2.
3.
4.
X can be VIL or VIH.
Refer to AC programming waveforms.
VH = 12.0V ± 0.5V.
Manufacturer Code: 161FH
Device Code: 1692H
5. See details under “Software Product Identification Entry/Exit” on page 12.
DC Characteristics
Symbol
Parameter
Condition
ILI
Input Load Current
ILO
Max
Units
VIN = 0V to VCC
10.0
µA
Output Leakage Current
VI/O = 0V to VCC
10.0
µA
ISB1
VCC Standby Current CMOS
CE = V CC - 0.3V to VCC
50.0
µA
ISB2
VCC Standby Current TTL
CE = 2.0V to VCC
0.5
mA
VCC Active Current
f = 5 MHz; IOUT = 0 mA
25.0
mA
0.6
V
ICC
(1)
VIL
Input Low Voltage
VIH
Input High Voltage
VOL
Output Low Voltage
IOL = 2.1 mA
VOH
Output High Voltage
IOH = -400 µA
Note:
Min
2.0
V
0.45
2.4
V
V
In the erase mode, ICC is 50 mA.
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1618E–FLASH–07/02
AC Read Characteristics
AT49LV4096A-70
Symbol
Parameter
tACC
Address to Output Delay
70
tCE(1)
CE to Output Delay
70
tOE(2)
OE to Output Delay
0
35
0
40
CE or OE to Output Float
0
25
0
25
tOH
Output Hold from OE, CE or
Address, whichever occurred first
0
tRO
RESET to Output Delay
tDF
(3)(4)
Min
AT49BV4096A-90
Max
Min
Max
AT49BV4096A-12
Max
Units
90
120
ns
90
120
ns
0
50
ns
0
30
ns
0
Min
0
800
800
ns
800
ns
AC Read Waveforms(1)(2)(3)(4)
ADDRESS
ADDRESS VALID
CE
t
OE
CE
t
OE
t
DF
t
ACC
t
RO
RESET
OUTPUT
Notes:
t
OH
HIGH Z
OUTPUT
VALID
1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC.
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC.
3. tDF is specified from OE or CE, whichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
Input Test Waveforms and Measurement Level
2.4V
0.4V
tR, tF < 5 ns
Output Test Load
3.3V
1.8K
OUTPUT
PIN
1.3K
8
100 pF
AT49BV/LV4096A
1618E–FLASH–07/02
AT49BV/LV4096A
Pin Capacitance
f = 1 MHz, T = 25°C(1)
Symbol
Typ
Max
Units
Conditions
CIN
4
6
pF
VIN = 0V
COUT
8
12
pF
VOUT = 0V
Note:
1. This parameter is characterized and is not 100% tested.
AC Word Load Characteristics
Symbol
Parameter
Min
Max
Units
tAS, tOES
Address, OE Setup Time
0
ns
tAH
Address Hold Time
70
ns
tCS
Chip Select Setup Time
0
ns
tCH
Chip Select Hold Time
0
ns
tWP
Write Pulse Width (WE or CE)
70
ns
tDS
Data Setup Time
70
ns
tDH, tOEH
Data, OE Hold Time
0
ns
tWPH
Write Pulse Width High
50
ns
AC Byte/Word Load Waveforms
WE Controlled
CE Controlled
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1618E–FLASH–07/02
Program Cycle Characteristics
Symbol
Parameter
Min
Typ
Max
Units
tBP
Byte/Word Programming Time
tAS
Address Setup Time
0
ns
tAH
Address Hold Time
70
ns
tDS
Data Setup Time
70
ns
tDH
Data Hold Time
0
ns
tWP
Write Pulse Width
70
ns
tWPH
Write Pulse Width High
50
ns
tEC
Erase Cycle Time
30
µs
10
seconds
Program Cycle Waveforms
PROGRAM CYCLE
OE
CE
t WP
t BP
t WPH
WE
t
AS
A0-A17
t DH
t AH
5555
5555
2AAA
5555
ADDRESS
t DS
55
AA
DATA
A0
AA
INPUT DATA
Sector or Chip Erase Cycle Waveforms
OE
(1)
CE
t WP
t WPH
WE
t AS
A0-A17
t DH
t AH
5555
5555
2AAA
5555
Note 2
2AAA
t EC
t DS
DATA
AA
WORD 0
Notes:
10
55
WORD 1
80
AA
55
Note 3
WORD 2
WORD 3
WORD 4
WORD 5
1. OE must be high only when WE and CE are both low.
2. For chip erase, the address should be 5555. For sector erase, the address depends on what sector is to be erased.
(See note 4 under Command Definitions.)
3. For chip erase, the data should be 10H, and for sector erase, the data should be 30H.
AT49BV/LV4096A
1618E–FLASH–07/02
AT49BV/LV4096A
Data Polling Characteristics(1)
Symbol
Parameter
Min
tDH
Data Hold Time
tOEH
OE Hold Time
Max
OE to Output Delay
tWR
Write Recovery Time
Units
10
ns
10
ns
(2)
tOE
Notes:
Typ
ns
0
ns
1. These parameters are characterized and not 100% tested.
2. See tOE spec in “AC Read Characteristics” on page 8.
Data Polling Waveforms
WE
CE
tOEH
OE
tDH
tOE
I/O7
A0-A17
An
tWR
HIGH Z
An
An
An
An
Toggle Bit Characteristics(1)
Symbol
Parameter
tDH
Data Hold Time
10
ns
tOEH
OE Hold Time
10
ns
tOE
OE to Output Delay(2)
tOEHP
OE High Pulse
tWR
Write Recovery Time
Notes:
Min
Typ
Max
Units
ns
150
ns
0
ns
1. These parameters are characterized and not 100% tested.
2. See tOE spec in “AC Read Characteristics” on page 8.
Toggle Bit Waveforms(1)(2)(3)
WE
CE
tOEHP
tOEH
OE
tDH
I/O6
Notes:
tOE
HIGH Z
tWR
1. Toggling either OE or CE or both OE and CE will operate toggle bit. The tOEHP specification must be met by the toggling
input(s).
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.
11
1618E–FLASH–07/02
Software Product Identification Entry(1)
LOAD DATA AA
TO
ADDRESS 5555
Boot Block Lockout Enable
Algorithm(1)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 90
TO
ADDRESS 5555
LOAD DATA 80
TO
ADDRESS 5555
ENTER PRODUCT
IDENTIFICATION
MODE(2)(3)(5)
LOAD DATA AA
TO
ADDRESS 5555
Software Product Identification Exit(1)(6)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
OR
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA F0
TO
ANY ADDRESS
LOAD DATA 40
TO
ADDRESS 5555
EXIT PRODUCT
IDENTIFICATION
MODE(4)
LOAD DATA F0
TO
ADDRESS 5555
PAUSE 1 second(2)
Notes:
EXIT PRODUCT
IDENTIFICATION
MODE(4)
Notes:
12
1. Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex)
Address Format: A15 - A0 (Hex), A-1, and A15 - A17
(Don’t Care).
2. Boot Block Lockout feature enabled.
1. Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex)
Address Format: A15 - A0 (Hex), A-1, and A15 - A17 (Don’t
Care).
2. A1 - A17 = VIL.
Manufacturer Code is read for A0 = VIL;
Device Code is read for A0 = VIH.
3. The device does not remain in identification mode if powered
down.
4. The device returns to standard operation mode.
5. Manufacturer Code: 161FH
Device Code: 1692H
6. Either one of the Product ID Exit commands can be used.
AT49BV/LV4096A
1618E–FLASH–07/02
AT49BV/LV4096A
Ordering Information
ICC (mA)
tACC
(ns)
Active
Standby
Ordering Code
(1)
Package
Operation Range
70
25
0.05
AT49LV4096A-70C1C
AT49LV4096A-70C5C(2)
AT49LV4096A-70RC
AT49LV4096A-70TC
48C1
48C5
44R
48T
Commercial
(0° to 70°C)
90
25
0.05
AT49BV4096A-90C1C(3)
AT49BV4096A-90C5C(4)
AT49BV4096A-90TC
48C1
48C5
48T
Commercial
(0° to 70°C)
48T
Industrial
(-40° to 85°C)
48C1
Industrial
(-40° to 85°C)
AT49BV4096A-90TI
110
25
0.05
AT49BV4096A-11C1I(3)
120
25
0.05
AT49BV4096A-12TC
48T
Commercial
(0° to 70°C)
AT49BV4096A-12TI
48T
Industrial
(-40° to 85°C)
Notes:
1.
2.
3.
4.
The topside marking
The topside marking
The topside marking
The topside marking
will be AT49LV4096A1.
will be AT49LV4096A5.
will be AT49BV4096A1.
will be AT49BV4096A5.
Package Type
48C1
48-ball, 7 x 7 mm, Chip-size Ball Grid Array Package (CBGA)
48C5
48-ball, 6 x 8 mm, Chip-size Ball Grid Array Package (CBGA)
44R
44-lead, 0.525" Wide, Plastic Gull Wing Small Outline (SOIC)
48T
48-lead, 12 x 20 mm, Plastic Thin Small Outline Package (TSOP)
13
1618E–FLASH–07/02
Packaging Information
48C1 – CBGA
Dimensions in Millimeters and (Inches).
Controlling dimension: millimeters.
7.10(0.280)
6.90(0.272)
A1 ID
7.10(0.280)
6.90(0.272)
SIDE VIEW
0.15 (0.006)MIN
TOP VIEW
1.20(0.047) MAX
0.875 (0.034) REF
5.25 (0.207)
8
7
6
5
4
3
2
1
1.625 (0.064)REF
A
B
C
0.75 (0.0295) BSC
NON-ACCUMULATIVE
3.75 (0.148)
D
E
F
0.30 (0.012)
DIA BALL TYP
0.75 (0.0295) BSC
NON-ACCUMULATIVE
BOTTOM VIEW
04/11/01
R
14
2325 Orchard Parkway
San Jose, CA 95131
TITLE
48C1, 48-ball (8 x 6 Array) 0.75 mm Pitch, 7 x 7 x 1.2 mm
Chip-scale Ball Grid Array Package (CBGA)
DRAWING NO.
48C1
REV.
A
AT49BV/LV4096A
1618E–FLASH–07/02
AT49BV/LV4096A
48C5 – CBGA
Dimensions in Millimeters and (Inches).
Controlling dimension: millimeters.
6.10 (0.240)
5.90 (0.232)
A1 ID
8.10 (0.319)
7.90 (0.311)
0.25 (0.010)MIN
1.20 (0.047) MAX
TOP VIEW
SIDE VIEW
1.00(0.039) REF
4.00(0.157)
6
5
4
3
2
1
1.20 (0.047) REF
A
B
C
0.80 (0.0315) BSC
NON-ACCUMULATIVE
D
5.60 (0.220)
E
F
G
H
0.40 (0.016)
DIA BALL TYP
0.80 (0.0315) BSC
NON-ACCUMULATIVE
BOTTOM VIEW
10/18/01
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
48C5, 48-ball (6 x 8 Array), 0.80 mm Pitch, 6 x 8 x 1.2 mm
Chip-scale Ball Grid Array Package (CBGA)
DRAWING NO.
48C5
REV.
A
15
1618E–FLASH–07/02
44R – SOIC
Dimensions in Millimeters and (Inches).
Controlling dimension: Inches.
0.508(0.020)
0.356(0.014)
13.46(0.530)
13.21(0.520)
16.18(0.637)
15.82(0.623)
PIN 1
1.27(0.050) BSC
28.32(1.115)
28.07(1.105)
2.67(0.105)
2.41(0.095)
0.33(0.130)
1.27(0.050)
0.250(0.010)
0.100(0.004)
0º ~ 8º
1.00(0.039)
0.60(0.024)
04/11/01
R
16
2325 Orchard Parkway
San Jose, CA 95131
TITLE
44R, 44-lead (0.525" Body) Plastic Gull Wing Small Outline (SOIC)
DRAWING NO.
REV.
44R
A
AT49BV/LV4096A
1618E–FLASH–07/02
AT49BV/LV4096A
48T – TSOP
PIN 1
0º ~ 8º
c
Pin 1 Identifier
D1 D
L
b
e
L1
A2
E
A
GAGE PLANE
SEATING PLANE
COMMON DIMENSIONS
(Unit of Measure = mm)
A1
MIN
NOM
MAX
A
–
–
1.20
A1
0.05
–
0.15
A2
0.95
1.00
1.05
D
19.80
20.00
20.20
D1
18.30
18.40
18.50
Note 2
E
11.90
12.00
12.10
Note 2
L
0.50
0.60
0.70
SYMBOL
Notes:
1. This package conforms to JEDEC reference MO-142, Variation DD.
2. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.
3. Lead coplanarity is 0.10 mm maximum.
L1
0.25 BASIC
b
0.17
0.22
0.27
c
0.10
–
0.21
e
NOTE
0.50 BASIC
10/18/01
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
48T, 48-lead (12 x 20 mm Package) Plastic Thin Small Outline
Package, Type I (TSOP)
DRAWING NO.
REV.
48T
B
17
1618E–FLASH–07/02
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Atmel Operations
Corporate Headquarters
Memory
2325 Orchard Parkway
San Jose, CA 95131
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e-mail
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Web Site
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© Atmel Corporation 2002.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
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Printed on recycled paper.
1618E–FLASH–07/02
/xM